A constant current source drive control system for digital tubes

Abstract

The present invention discloses a digital tube constant current source drive control system, which belongs to the field of LED control bias, and includes a current source generation module, an output driver module, and a segment control module. The bias current source generation module generates a mirror bias constant current source for use by subsequent segment drive constant current sources; the output driver module uses the bias constant current source as a bias reference to generate a segment constant current source drive, and implements segment current limit control when this segment constant current source drive is turned on and off; in addition, when the segment constant current source drive is turned off, a bit scan switch drive is generated according to the segment control signal; when writing display data, the segment control module outputs a bit scan and segment display control signal based on relevant instruction control and clock input, and writes it into the output driver module to implement segment multiplexing control. The present invention can achieve high stability and high precision for the digital tube display drive constant current source, and save the cost and power consumption of the digital tube display.

Description

Technical Field

[0001] The present invention relates to the technical field of LED control, and in particular to a digital tube constant current source drive control system. Background Art

[0002] A digital tube is a semiconductor light-emitting device whose basic unit is a light-emitting diode (LED). It is generally configured as an 8-segment, N-bit display system. The dynamic drive system for a common cathode digital tube involves connecting the cathodes of all LEDs together to form a common cathode (COM), which is then connected to the bit line. This common cathode (COM) is then dynamically driven by the persistence of vision phenomenon, which alternates between the bit scanning switches of each digital tube. The anodes of these LEDs are illuminated according to the segment code using the high voltage level of the segment drive circuit. Because LEDs are primarily current-sensitive devices, their forward voltage drop varies widely and is highly temperature-dependent. Furthermore, short-term current overloads can permanently damage the LEDs. Therefore, to ensure excellent brightness uniformity and safety, segment constant current sources are generally used. Common cathode LED drivers currently on the market are striving for higher cost-performance and flexibility. This has led to the development of segment multiplexing technology, which significantly reduces chip area and cost. However, segment multiplexing can induce reverse voltage spikes at the output, significantly reducing the lifespan and output brightness uniformity of the digital tube. Therefore, there is an urgent need for a constant current source drive control circuit that can eliminate electromagnetic interference at the output end without affecting the transient response of segment multiplexing, ensure high stability and high precision of the driving constant current source, and save the cost and power consumption of the digital tube display. Summary of the Invention

[0003] The object of the present invention is to provide a digital tube constant current source drive control system to solve the problems in the background technology.

[0004] In order to solve the above technical problems, the present invention provides a digital tube constant current source drive control system, comprising:

[0005] The bias current source generation module includes a voltage reference generation circuit and a current control circuit, which generates a mirror bias constant current source for use by the subsequent segment drive constant current source;

[0006] The output drive module includes a segment constant current source feedback control circuit, a segment current slew rate limiting circuit, a bit scanning switch control circuit and a segment position control feedback circuit. The bias constant current source is used as a bias reference to generate a segment constant current source drive, and when the segment constant current source drive is turned on and off, the segment current limit control is realized; in addition, when the segment constant current source drive is turned off, a bit scanning switch drive is generated according to the segment position control signal;

[0007] The segment control module includes a bit scanning and segment display circuit. When writing display data, based on relevant instruction control and clock input, it outputs bit scanning and segment display control signals, writes them into the output drive module, and realizes segment multiplexing control.

[0008] In one embodiment, the segment constant current source feedback control circuit includes PMOS transistors MP1 to MP10 and NMOS transistors MN2 to MN13; PMOS transistors MP9 and MP10 are connected to the bias current source generation module, and the bias current sources I2 and I3 generated by them are used as current references, and I3=2*I2;

[0009] The bias current source I3 is controlled by the PMOS transistor MP10, and the enable signal is the output signal ENN_B of the bit scanning and segment display circuit. When ENN_B is at a low level, I3 is shunted by the NMOS transistors MN5, MN6 and the NMOS transistors MN9, MN10, and the currents are IN1 and IN2 respectively. The bias current source I2 is controlled by the PMOS transistor MP9, and the enable signal is the output signal ENN_B of the bit scanning and segment display circuit. When ENN_B is at a low level, I2 is shunted by the NMOS transistors MN3, MN4 and the NMOS transistors MN7, MN8, and the currents are IN3 and IN4 respectively.

[0010] NMOS transistors MN12 and MN13 form a 1:1 mirror current mirror with NMOS transistors MN9 and MN10. The branch current of NMOS transistors MN12 and MN13 is IN2. PMOS transistors MP4 and MP3 form a 1:1 mirror current branch. The branch current of PMOS transistor MP3 is equal to that of PMOS transistor MP4, also IN2, that is, IN3 = IN2. NMOS transistors MN5 and MN6 form a 1:1 mirror current mirror with NMOS transistors MN3 and MN4. IN1 = IN2, so IN2 = 1 / 2 * I3 = I2. NMOS transistors MN9 and MN12, PMOS transistors MP4 and MP3, and NMOS transistor MN4 form a negative feedback path to achieve precise current control.

[0011] The PMOS tube MP2 branch is connected to the segment current slew rate limiting circuit, and the segment current slew rate limiting circuit forms a current mirror with the NMOS tubes MN9 and MN10 branches, with a current of 6*IN2. The current of the PMOS tube MP2 branch is 6*IN2; the PMOS tube MP2 branch forms a 1:N current mirror with the PMOS tube MP1 branch, and the PMOS tube MP1 is the driving tube of the segment constant current source, and the current of the segment constant current source is 6N*IN2; the PMOS tube MP5 and the PMOS tube MP6 form a 1:M current mirror, and the NMOS tube MN2 and the NMOS tube MN3 also form a 1:M current mirror, so the PMOS tube MP5 and the NMOS tube MN2 form a micro current branch of the nA level, and the current of this branch is IN=1 / M*IN2. This micro current branch is the output voltage detection branch;

[0012] When the normal segment is displayed, the output pin OUT drawn from the drain end of the PMOS tube MP1 and the source end of the PMOS tube MP5 is electrically connected to the external display device. When the segment is switched, the output voltage VOUT will fluctuate. When the voltage difference of the PMOS tube MP1 is insufficient, it will affect the constant current source characteristics and cause the output current to drop sharply. At this time, the branch detects the output voltage through the PMOS tube MP5, and the output voltage is fed back to the drain end of the PMOS tube MP3 through the feedback loop formed by the PMOS tube MP5, MP6, NMOS tubes MN2, MN3, MN4 and PMOS tube MP6. The PMOS transistor MP3 serves as the induction transistor for the output constant current source drive transistor. At this time, the current in the PMOS transistor MP3 branch decreases, while the current IN1 in the NMOS transistors MN5 and MN6 branches decreases. Then, IN2 increases, and the gate voltage of the PMOS transistor MP2 decreases accordingly, so that the output current does not decrease instantaneously. At this time, the gate voltage of the PMOS transistor MP4 decreases accordingly. The negative feedback loop formed by the NMOS transistors MN9, MN12, the PMOS transistors MP4, MP3, and the NMOS transistor MN4 maintains the current in the PMOS transistor MP3 branch relatively stable, so that the current IN2 remains unchanged.

[0013] In one embodiment, the segment current slew rate limiting circuit includes NMOS transistors MN14 to MN31;

[0014] The segment current slew rate limiting circuit is connected to the current branch IN2 in the segment constant current source feedback control circuit. The NMOS tubes MN14 and MN15 form the first segment current branch, and form a common source and common gate current mirror with a ratio of 1:1 with the NMOS tubes MN9 and MN10 in the current branch IN2. The on-off of this branch is controlled by the NMOS tube MN26, and its enable signal is the output signal SEG_EN0 of the segment control feedback circuit; the NMOS tubes MN16 and MN17 form the second segment current branch, the NMOS tubes MN18 and MN19 form the third segment current branch, the NMOS tubes MN20 and MN21 form the fourth segment current branch, the NMOS tubes MN22 and MN23 form the fifth segment current branch, and the NMOS tubes MN24 and MN25 form the fifth segment current branch. Transistors MN24 and MN25 form the sixth current branch, each forming a 1:1 mirror image ratio with the NMOS transistors MN9 and MN10 in the current branch IN2. The on / off of the second, third, fourth, fifth, and sixth current branches are controlled by NMOS transistors MN27, MN28, MN29, MN30, and MN31, respectively, whose enable signals are the output signals SEG_EN1, SEG_EN2, SEG_EN3, SEG_EN4, and SEG_EN5 of the segment control feedback circuit, respectively. These six current branches are electrically connected together to form a 6*IN2 current sink, which is connected to the PMOS transistor MP2 in the segment constant current source feedback control circuit as a mirror current of the output segment constant current source.

[0015] When the segment scan signal EN_SEG is valid, the enable signal SEG_EN0 will first become high, turning on the first current sink branch, and then the bias current source control signals ENN_B and ENP_B will become low and high respectively, selecting the segment constant current source feedback control circuit to form a mirror path, and outputting a segment constant current source of N*IN2; the control signal SEG_EN0 passes through five identical delay units in series to form control signals SEG_EN1, SEG_EN2, SEG_EN3, SEG_EN4 and SEG_EN5 respectively. After each identical time interval, the control signal SE G_EN1~SEG_EN5 become high level in turn, and the five groups of current sink branches are turned on in turn. The output current increases in steps of N*IN2 until it becomes the set value 6N*IN2. At this time, the current rise time is 5 time units; similarly, when the segment is closed, the control signals SEG_EN0, SEG_EN1, SEG_EN2, SEG_EN3, SEG_EN4, and SEG_EN5 first turn off the corresponding switch tubes in turn, and finally the bias current source control signals ENN_B and ENP_B turn off the segment constant current source feedback control circuit, so that the output constant current source is reduced to 0 in steps of N*IN2.

[0016] In one embodiment, the bit scanning switch control circuit includes an NMOS transistor MN1 and a resistor R1; the bit scanning switch control circuit is connected to the output pin OUT of the segment constant current source feedback control circuit, the NMOS transistor MN1 is a bit scanning switch, and its gate end is connected to one end of the resistor R1. The function of the resistor R1 is to slow down the switch switching to reduce the electromagnetic interference of the segment switching; the other end of the resistor R1 is connected to the control signal ENB_DIG, which is output by the segment control feedback circuit and controlled by the bit scanning signal EN_DIG; when the bit scanning signal EN_DIG is valid, ENB_DIG becomes a high level, the segment constant current source feedback control circuit is turned off, and the output OUT is pulled down to a low level by the NMOS transistor MN1, and the bit scanning is turned on.

[0017] In one embodiment, the segment control feedback circuit has an output connected to the segment constant current source feedback control circuit, the bit scanning switch control circuit and the segment current slew rate limiting circuit, for providing the required control signals to the corresponding circuits, and an input connected to the segment control module for receiving signals for bit scanning and segment display;

[0018] The inverse of the bit scan signal EN_DIG and the segment slew rate control signal SEG_EN5 is used as the input signal of the AND gate A1. The output signal of the AND gate A1 passes through the buffer unit BUF1 to generate the control signal ENB_DIG of the bit scan switch. After ENB_DIG is inverted, it is combined with the segment display signal EN_SEG as the input signal of the AND gate A2. The output signal of the AND gate A2 passes through the buffer unit BUF2 to generate the first segment slew rate control signal SEG_EN0. SEG_EN0 passes through a delay unit delay and a buffer unit BUF2 to generate the second segment slew rate control signal SEG_EN1. SEG_EN1 passes through the same delay unit delay and a buffer unit BUF2 to generate the third segment slew rate control signal SEG_EN2. And so on, the fourth, fifth and sixth segment slew rate control signals SEG_EN3, SEG_EN4 and SEG_EN5 are generated respectively.

[0019] The sixth segment slew rate control signal SEG_EN5 and the first segment slew rate control signal SEG_EN0 pass through an OR gate to generate the enable signals ENN_B and ENP_B of the segment constant current source feedback control circuit; when a segment display signal driven by an output is enabled, that is, EN_SEG = 1, EN_DIG = 0, then ENB_DIG = 0, the bit scan switch is not turned on, at this time SEG_EN0 = 1, the first segment current branch is turned on, and ENN_B = 0, ENP_B = 1, so that the output generates an N*IN2 segment constant current source. At this time, SEG_EN0 passes through five identical delay networks to generate SEG_EN1, SEG_EN2, SEG_EN3, SEG_EN4, SEG_EN5, Enable the second to sixth segment current branches respectively, so that the output is finally a 6N*IN2 segment constant current source; when the segment display signal is not enabled and the bit scan signal is enabled, that is, EN_SEG=0, EN_DIG=1, the enable signal ENB_DIG of the bit scan switch cannot be immediately changed to 1, because SEG_EN5 cannot immediately become a low level. When the segment is turned off, SEG_EN0 first becomes 0, turning off the first segment current branch. After five delays, SEG_EN1, SEG_EN2, SEG_EN3, SEG_EN4, and SEG_EN5 successively become 0. At this time, the segment constant current source output is 0, and the constant current source feedback control circuit is also turned off at this time. At this time, ENB_DIG=1, and the bit scan switch is turned on.

[0020] In one embodiment, the delay unit delay is formed by two identical inverters INV1 and a capacitor C1 connected in series, wherein the inverter INV1 is an inverse ratio transistor, and the sizes of the inverter INV1 and the capacitor C1 are selected according to the delay time requirement.

[0021] In one embodiment, in the bias current source generation module, the reference voltage generation circuit is electrically connected to the current control circuit and is configured to generate a low-temperature drift voltage VR as a voltage reference for the external resistor R;

[0022] The current control circuit includes an operational amplifier AMP1, PMOS transistors MP11 to MP16, and an NMOS transistor MN0. A voltage VR generated by a reference voltage generation circuit serves as the positive input voltage of the operational amplifier AMP1. The negative input of the operational amplifier AMP1 is connected to a pin ISET, which is used to connect to an external resistor R. The output of the operational amplifier AMP1 is connected to the gate of the NMOS transistor MN0. The operational amplifier AMP1 and the NMOS transistor MN0 form a negative feedback loop. At this time, the current I1 of the NMOS transistor MN0 branch is equal to VR / R, where I1 is the first mirror current branch generated by the external resistor.

[0023] The PMOS transistors MP13 and MP14 form a cascode current mirror with a mirror ratio of 1:A with the PMOS transistors MP11 and MP12, and the branch current I2 = VR / R*A; the PMOS transistors MP15 and MP16 form a cascode current mirror with a mirror ratio of 1:2A with the PMOS transistors MP11 and MP12, and the branch current I3 = VR / R*2A; the current sources I2 and I3 are electrically connected to a constant current source feedback control circuit to serve as bias current sources for the constant current source.

[0024] In one embodiment, in the bit scanning and segment display control circuit, nine diodes respectively represent the eight-segment lamps of the digital tube; output drivers 1 to 8 are simplified into a segment constant current source, a switch controlled by a segment display signal, and a bit scanning switch controlled by a bit scanning signal, respectively. In addition, there is an output driver module DP, which only has a segment constant current source and a switch controlled by a segment display signal, which are the same as output driver 1; the digital tube device has a total of 8 bits, each bit corresponds to the eight-segment lamps of the digital tube, and is driven by a common cathode, so when the segment display control of the output driver module is enabled, the segment constant current source is electrically connected to the anode of the corresponding diode, providing high-precision current as a constant current source, and when the bit scanning control of a certain output driver module is enabled, the cathode of the eight-segment diode is connected to the bit scanning switch of this output driver module.

[0025] In one embodiment, when the first bit is displayed and all eight segments are bright, the bit scan control EN_DIG1 of output driver 1 becomes high, and output driver 1 is connected to the cathodes of the eight-segment diodes as a bit scan switch. At this time, EN_SEG1 must be low, and the constant current function of output driver 1 cannot be turned on. The segment display control signals EN_SEG2~EN_SEG8 of output driver 2~output driver 8 and the segment display control signal EN_SEGDP of output driver DP all become high, and the segment constant current sources of output driver 2~output driver 8 and output driver DP are respectively connected to the anodes of the corresponding diodes, and the bit scan signals EN_DIG2~EN_DIG8 of the corresponding drive modules must be low, and the bit scan switch cannot be turned on;

[0026] In one embodiment, when the second digit is displayed and all eight segments are bright, the bit scan control EN_DIG2 of output driver 2 becomes high, and output driver 2 is connected to the cathode of the eight-segment diode as a bit scan switch. At this time, EN_SEG2 must be low, and the constant current function of output driver 1 cannot be turned on. The segment display control signals EN_SEG1, EN_SEG3~EN_SEG8, and EN_SEGDP of output driver 1, output driver 3~output driver 8, and output driver DP all become high, and the segment constant current sources of output driver 1, output driver 3~output driver 8, and output driver DP are respectively connected to the anode of the corresponding diode, and the bit scan signals EN_DIG1, ​​EN_DIG3~EN_DIG8 of the corresponding drive modules must be low, and the bit scan switch cannot be turned on.

[0027] In a digital tube constant current source drive control system provided by the present invention, it includes a current source generation module, an output drive module and a segment control module. The bias current source generation module generates a mirror bias constant current source for use by subsequent segment drive constant current sources; the output drive module uses the bias constant current source as a bias reference to generate a segment constant current source drive, and when this segment constant current source drive is turned on and off, it realizes the control of the segment current limit; in addition, when the segment constant current source drive is turned off, a bit scan switch drive is generated according to the segment control signal; when the segment control module writes display data, based on the relevant instruction control and clock input, it outputs the bit scan and segment display control signal, writes it into the output drive module, and realizes segment multiplexing control. The present invention can achieve high stability and high precision for the digital tube display drive constant current source, and save the cost and power consumption of the digital tube display. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 The present invention provides a structural diagram of a digital tube constant current source drive control system.

[0029] Figure 2 It is a structural diagram of the output driver module.

[0030] Figure 3 It is a structural diagram of the segment control feedback circuit.

[0031] Figure 4 It is a structural diagram of the current control circuit.

[0032] Figure 5 It is a structural diagram of the position scanning and segment display circuit when the first digit is displayed and all eight segments are bright.

[0033] Figure 6 It is a structural diagram of the position scanning and segment display circuit when the second digit is displayed and all eight segments are bright. DETAILED DESCRIPTION

[0034] The following is a further detailed description of a constant current source drive control system for a digital tube according to the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0035] The present invention provides a digital tube constant current source drive control system, the structure of which is as follows Figure 1 As shown, it includes a bias current source generation module, an output driver module, and a segment control module. The bias current source generation module includes a voltage reference generation circuit and a current control circuit to generate a mirror bias constant current source for use by subsequent segment drive constant current sources; the output driver module includes a segment constant current source feedback control circuit, a segment current slew rate limiting circuit, a bit scan switch control circuit, and a segment control feedback circuit. It uses the bias constant current source as a bias reference to generate a segment constant current source drive and implements segment current limit control when the segment constant current source drive is turned on and off; in addition, when the segment constant current source drive is turned off, a bit scan switch drive is generated according to the segment control signal; the segment control module includes a bit scan and segment display circuit. When writing display data, based on relevant instruction control and clock input, it outputs bit scan and segment display control signals, which are written into the output driver module to implement segment multiplexing control.

[0036] like Figure 2As shown, the segment constant current source feedback control circuit includes PMOS transistors MP1-MP10 and NMOS transistors MN2-MN13. PMOS transistors MP9 and MP10 are connected to the bias current source generation module, using bias current sources I2 and I3 generated by the bias current source generation module as current references, with I3 = 2*I2. Bias current source I3 is controlled by a PMOS transistor MP10. The enable signal is the output signal ENN_B of the bit scan and segment display circuit. When ENN_B is low, I3 is shunted by NMOS transistors MN5 and MN6 and NMOS transistors MN9 and MN10, with currents IN1 and IN2, respectively. Bias current source I2 is controlled by a PMOS transistor MP9. The enable signal is the output signal ENN_B of the bit scan and segment display circuit. When ENN_B is low, I2 is shunted by NMOS transistors MN3 and MN4 and NMOS transistors MN7 and MN8, with currents IN3 and IN4, respectively. Furthermore, NMOS transistors MN12 and MN13 form a 1:1 mirror current with NMOS transistors MN9 and MN10. The branch current of NMOS transistors MN12 and MN13 is IN2. PMOS transistors MP4 and MP3 form a 1:1 mirror current branch. The current in the branch of PMOS transistor MP3 is equal to that of PMOS transistor MP4, also IN2, so IN3 = IN2. Furthermore, NMOS transistors MN5 and MN6 form a 1:1 mirror current with NMOS transistors MN3 and MN4. Therefore, IN1 = IN2, and IN2 = 1 / 2 * I3 = I2. The NMOS transistors MN9 and MN12, PMOS transistors MP4 and MP3, and NMOS transistor MN4 form a negative feedback path, enabling precise current control.

[0037] The PMOS transistor MP2 branch connects to the segment current slew rate limiting circuit. This current mirror forms with the NMOS transistors MN9 and MN10 branches, resulting in a current of 6*IN2. Therefore, the current in the PMOS transistor MP2 branch is 6*IN2. Furthermore, the PMOS transistor MP2 branch forms a 1:N current mirror with the PMOS transistor MP1 branch. Since PMOS transistor MP1 is the driver of the segment constant current source, the current in the segment constant current source is 6N*IN2. PMOS transistors MP5 and MP6 form a 1:M current mirror, while NMOS transistors MN2 and MN3 also form a 1:M current mirror. Therefore, PMOS transistors MP5 and MN2 form a nanoamp-level micro-current branch. The current in this branch is IN = 1 / M*IN2. This micro-current branch serves as the output voltage detection branch. When displaying in the normal segment, the output pin OUT is electrically connected to an external display device. When switching between segments, the output voltage VOUT fluctuates. When the voltage drop across the PMOS transistor MP1 is insufficient, the constant current source characteristics are easily affected, causing the output current to drop sharply. At this point, this branch detects the output voltage through the PMOS transistor MP5. The feedback loop formed by the PMOS transistors MP5, MP6, NMOS transistors MN2, MN3, MN4, and PMOS transistor MP6 feeds the output voltage back to the drain of the PMOS transistor MP3, making the PMOS transistor MP3 serve as the sensing transistor for the output constant current source drive transistor. At this point, the current in the PMOS transistor MP3 branch decreases, and the current IN1 in the NMOS transistors MN5 and MN6 branches also decreases. Consequently, IN2 increases, and the gate voltage of the PMOS transistor MP2 decreases accordingly, preventing the output current from dropping instantly. At this time, the gate voltage of PMOS transistor MP4 will also decrease accordingly. The negative feedback loop formed by NMOS transistors MN9, MN12, PMOS transistor MP4, MP3 and NMOS transistor MN4 maintains the current of PMOS transistor MP3 branch relatively stable, so that current IN2 remains unchanged. Therefore, PMOS transistor MP3 is a precise detection transistor for the output of PMOS transistor MP1. It detects changes in the voltage at the OUT terminal (whether caused by changes in the external environment or internal chip mismatch offset caused by the large mirror ratio N) and makes rapid adjustments through the dual feedback system to maintain the high precision of the constant current source.

[0038] Please continue reading Figure 2The segment current slew rate limiting circuit includes NMOS transistors MN14 to MN31; the segment current slew rate limiting circuit is connected to the current branch IN2 in the segment constant current source feedback control circuit, NMOS transistors MN14 and MN15 form a first segment current branch, and form a 1:1 cascode current mirror with the NMOS transistors MN9 and MN10 in the current branch IN2. The on-off of this branch is controlled by the NMOS transistor MN26, and its enable signal is the output signal SEG_EN0 of the segment control feedback circuit; in addition, NMOS transistors MN16 and MN17 form a second segment current branch, NMOS transistors MN18 and MN19 form a third segment current branch, NMOS transistors MN20 and MN21 form a fourth segment current branch, and NMOS transistors MN22 and MN2 form a fourth segment current branch. 3 forms the fifth current branch, and NMOS transistors MN24 and MN25 form the sixth current branch, each of which forms a 1:1 mirror image ratio with the NMOS transistors MN9 and MN10 in the current branch IN2. The on / off of the second, third, fourth, fifth, and sixth current branches are controlled by NMOS transistors MN27, MN28, MN29, MN30, and MN31, respectively, and their enable signals are the output signals SEG_EN1, SEG_EN2, SEG_EN3, SEG_EN4, and SEG_EN5 of the segment control feedback circuit, respectively. These six current branches are electrically connected together to form a current sink of 6*IN2, which is connected to the PMOS transistor MP2 in the segment constant current source feedback control circuit as the mirror current of the output segment constant current source. When the segment scan signal EN_SEG is valid, the enable signal SEG_EN0 will first become a high level, turning on the first current sink branch, and then the bias current source control signals ENN_B and ENP_B will become low and high levels respectively, selecting the segment constant current source feedback control circuit to form a mirror path, and outputting an N*IN2 segment constant current source; the control signal SEG_EN0 passes through five identical delay units in series to form control signals SEG_EN1, SEG_EN2, SEG_EN3, SEG_EN4 and SEG_EN5 respectively. After each identical time interval, the control signals SEG_EN1~SEG_EN5 become high levels in turn, and the five groups of current sink branches are turned on in turn , the output current increases in steps of N*IN2 until it becomes the set value 6N*IN2. At this time, the current rise time is 5 time units, which limits the slew rate of the output current. This can effectively reduce the influence of the electromagnetic effect caused by frequent segment switching, making the stability and accuracy of the constant current source higher, and at the same time increasing the life of the digital tube device; similarly, when the segment is closed, the control signals SEG_EN0, SEG_EN1, SEG_EN2, SEG_EN3, SEG_EN4, and SEG_EN5 first turn off the corresponding switch tubes in sequence, and finally the bias current source control signals ENN_B and ENP_B turn off the segment constant current source feedback control circuit, so that the output constant current source is reduced to 0 in steps of N*IN2.

[0039] The bit scanning switch control circuit includes an NMOS transistor MN1 and a resistor R1. The bit scanning switch control circuit is connected to the output pin OUT of the segment constant current source feedback control circuit. The NMOS transistor MN1 functions as the bit scanning switch, with its gate connected to one end of resistor R1. Resistor R1 slows down switching and reduces electromagnetic interference caused by segment switching. The other end of resistor R1 is connected to a control signal ENB_DIG, which is output by the segment control feedback circuit and controlled by the bit scanning signal EN_DIG. When the bit scanning signal EN_DIG is valid, ENB_DIG goes high, shutting down the segment constant current source feedback control circuit. Output OUT is pulled low by the NMOS transistor MN1, enabling the bit scanning operation.

[0040] The output of the segment control feedback circuit is connected to the segment constant current source feedback control circuit, the bit scanning switch control circuit and the segment current slew rate limiting circuit, and is used to provide the required control signals to the corresponding circuits. The input is connected to the segment control module, and is used to receive the bit scanning and segment display signals. Figure 3 As shown, the inverse of the bit scan signal EN_DIG and the segment slew rate control signal SEG_EN5 serves as the input signal of AND gate A1. The output signal of AND gate A1 passes through buffer unit BUF1 to generate the bit scan switch control signal ENB_DIG. After ENB_DIG is inverted, it is combined with the segment display signal EN_SEG as the input signal of AND gate A2. The output signal of AND gate A2 passes through buffer unit BUF2 to generate the first segment slew rate control signal SEG_EN0. SEG_EN0 passes through a delay unit delay and a buffer unit BUF2 to generate the second segment slew rate control signal SEG_EN1. SEG_EN1 passes through the same delay unit delay and a buffer unit BUF2 to generate the third segment slew rate control signal SEG_EN2. And so on, the fourth, fifth, and sixth segment slew rate control signals SEG_EN3, SEG_EN4, and SEG_EN5 are generated respectively. The difference between buffer unit BUF1 and BUF2 is that they have different buffer delays. The delay of buffer unit BUF2 is greater than that of buffer unit BUF1. Please continue to refer to Figure 3The delay unit, delay, consists of two identical inverters INV1 and capacitor C1 connected in series. Inverter INV1 is an inverse ratio transistor. The sizes of inverter INV1 and capacitor C1 can be selected based on the delay time requirement. The sixth segment slew rate control signal SEG_EN5 and the first segment slew rate control signal SEG_EN0 are combined through a NOR gate to generate the enable signals ENN_B and ENP_B for the segment constant current source feedback control circuit. When the segment display signal of a certain output driver is enabled, that is, EN_SEG = 1, EN_DIG = 0, then ENB_DIG = 0, the bit scan switch is not turned on, at this time SEG_EN0 = 1, the first segment current branch is turned on, and ENN_B = 0, ENP_B = 1, so that the output generates an N*IN2 segment constant current source. At this time, SEG_EN0 passes through five identical delay networks to generate SEG_EN1, SEG_EN2, SEG_EN3, SEG_EN4, SEG_EN5, which enable the second to sixth segment current branches respectively, so that the output is finally a 6N*IN2 segment constant current source. ;When the segment display signal is not enabled and the bit scan signal is enabled, that is, EN_SEG=0, EN_DIG=1, the enable signal ENB_DIG of the bit scan switch cannot change to 1 immediately because SEG_EN5 cannot change to a low level immediately. When the segment is turned off, SEG_EN0 first changes to 0, turning off the first segment current branch. After five delays, SEG_EN1, SEG_EN2, SEG_EN3, SEG_EN4, and SEG_EN5 change to 0 successively. At this time, the segment constant current source output is 0, and the constant current source feedback control circuit is also turned off at this time. At this time, ENB_DIG=1, and the bit scan switch is turned on.

[0041] The bias current source generation module includes a reference voltage generation circuit and a current control circuit. The reference voltage generation circuit is electrically connected to the current control circuit and is used to generate a low-temperature drift voltage VR as a voltage reference for the external resistor R. This reference voltage generation circuit can be any type of voltage reference source, and the voltage range of VR is 0 <VR<VDD。

[0042] like Figure 4As shown, the current control circuit includes an op amp AMP1, PMOS transistors MP11-MP16, and an NMOS transistor MN0. A voltage VR generated by a reference voltage generation circuit serves as the positive input voltage of op amp AMP1. The negative input of op amp AMP1 is connected to pin ISET, which is used to connect to an external resistor R. The output of op amp AMP1 is connected to the gate of NMOS transistor MN0. Op amp AMP1 and NMOS transistor MN0 form a negative feedback loop. At this point, the current I1 in the NMOS transistor MN0 branch equals VR / R. As the first mirror current branch generated by the external resistor, I1 has high accuracy. This is because the external resistor R does not change with temperature or process changes, with an accuracy deviation of only 0.1%. The PMOS transistors MP13 and MP14 form a cascode current mirror with a mirror ratio of 1:A with the PMOS transistors MP11 and MP12, and the branch current I2 = VR / R*A; the PMOS transistors MP15 and MP16 form a cascode current mirror with a mirror ratio of 1:2A with the PMOS transistors MP11 and MP12, and the branch current I3 = VR / R*2A; the current sources I2 and I3 are electrically connected to a constant current source feedback control circuit to serve as bias current sources for the constant current source.

[0043] The segment control module includes a bit scan and segment display control module, such as Figure 5 As shown, the nine diodes represent the eight-segment lamps (the number 8 and the decimal point) of the digital tube respectively; the eight identical output drive modules are simplified into a segment constant current source, a switch controlled by a segment display signal, and a bit-scanning switch controlled by a bit-scanning signal; there is also an output drive module DP, which only has a segment constant current source and a switch controlled by a segment display signal that are the same as output drive 1. The digital tube device in the present invention has a total of 8 bits, each bit corresponds to the eight-segment lamps of the digital tube, and is driven by a common cathode. Therefore, when the segment display control of the output drive module is enabled, the segment constant current source is electrically connected to the anode of the corresponding diode, and acts as a constant current source to provide high-precision current. When the bit-scanning control of a certain output drive module is enabled, the cathode of the eight-segment diode is connected to the bit-scanning switch of this output drive module. Utilizing Figure 5 and Figure 6 For example: Figure 5When the first bit is displayed and all eight segments are bright, the bit scan control EN_DIG1 of output driver 1 becomes high, and output driver 1 is connected to the cathode of the eight-segment diode as a bit scan switch. At this time, EN_SEG1 must be low, and the constant current function of output driver 1 must not be turned on. The segment display control signals EN_SEG2~EN_SEG8 of output driver 2~output driver 8 and the segment display control signal EN_SEGDP of output driver DP all become high, and the segment constant current sources of output driver 2~output driver 8 and output driver DP are respectively connected to the anode of the corresponding diode, and the bit scan signals EN_DIG2~EN_DIG8 of the corresponding drive modules must be low, and the bit scan switch must not be turned on. Figure 6 When the second digit is displayed and all eight segments are bright, the bit scan control EN_DIG2 of output driver 2 becomes high, and output driver 2 is connected to the cathode of the eight-segment diode as a bit scan switch. At this time, EN_SEG2 must be low, and the constant current function of output driver 1 must not be turned on. The segment display control signals EN_SEG1, EN_SEG3~EN_SEG8, and EN_SEGDP of output driver 1, output driver 3~output driver 8, and output driver DP all become high, and the segment constant current sources of output driver 1, output driver 3~output driver 8, and output driver DP are respectively connected to the anode of the corresponding diode, and the bit scan signals EN_DIG1, ​​EN_DIG3~EN_DIG8 of the corresponding drive modules must be low, and the bit scan switch must not be turned on.

[0044] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A digital tube constant current source drive control system, characterized in that: include: The bias current source generation module includes a reference voltage generation circuit and a current control circuit, which generates a mirror bias constant current source for use by the subsequent segment drive constant current source; The output drive module includes a segment constant current source feedback control circuit, a segment current slew rate limiting circuit, a bit scanning switch control circuit and a segment position control feedback circuit. The bias constant current source is used as a bias reference to generate a segment constant current source drive, and when the segment constant current source drive is turned on and off, the segment current limit control is realized; in addition, when the segment constant current source drive is turned off, a bit scanning switch drive is generated according to the segment position control signal; The segment control module includes a bit scanning and segment display circuit. When writing display data, based on relevant instruction control and clock input, it outputs bit scanning and segment display control signals and writes them into the output driver module to realize segment multiplexing control; The segment constant current source feedback control circuit includes PMOS transistors MP1 to MP10 and NMOS transistors MN2 to MN13; PMOS transistors MP9 and MP10 are connected to the bias current source generation module, and the bias current sources I2 and I3 generated by them are used as current references, and I3=2*I2; The bias current source I3 is controlled by the PMOS transistor MP10, and the enable signal is the output signal ENN_B of the bit scanning and segment display circuit. When ENN_B is at a low level, I3 is shunted by the NMOS transistors MN5, MN6 and the NMOS transistors MN9, MN10, and the currents are IN1 and IN2 respectively. The bias current source I2 is controlled by the PMOS transistor MP9, and the enable signal is the output signal ENN_B of the bit scanning and segment display circuit. When ENN_B is at a low level, I2 is shunted by the NMOS transistors MN3, MN4 and the NMOS transistors MN7, MN8, and the currents are IN3 and IN4 respectively. NMOS transistors MN12 and MN13 form a 1:1 mirror current mirror with NMOS transistors MN9 and MN10. The branch current of NMOS transistors MN12 and MN13 is IN2. PMOS transistors MP4 and MP3 form a 1:1 mirror current branch. The branch current of PMOS transistor MP3 is equal to that of PMOS transistor MP4, also IN2, that is, IN3=IN2. NMOS transistors MN5 and MN6 form a 1:1 mirror current mirror with NMOS transistors MN3 and MN4. IN1=IN2, so IN2=1 / 2*I3=I2. NMOS transistors MN9 and MN12, PMOS transistors MP4 and MP3, and NMOS transistor MN4 form a negative feedback path to achieve precise current control. The PMOS tube MP2 branch is connected to the segment current slew rate limiting circuit, and the segment current slew rate limiting circuit forms a current mirror with the NMOS tubes MN9 and MN10 branches, with a current of 6*IN2. The current of the PMOS tube MP2 branch is 6*IN2; the PMOS tube MP2 branch forms a 1:N current mirror with the PMOS tube MP1 branch. The PMOS tube MP1 is the driving tube of the segment constant current source, and the current of the segment constant current source is 6N*IN2; the PMOS tube MP5 and the PMOS tube MP6 form a 1:M current mirror, and the NMOS tube MN2 and the NMOS tube MN3 also form a 1:M current mirror. Therefore, the PMOS tube MP5 and the NMOS tube MN2 form a micro current branch at the nA level. The current of this branch is IN=1 / M*IN2. This micro current branch is the output voltage detection branch; When the normal segment is displayed, the output pin OUT drawn from the drain end of the PMOS tube MP1 and the source end of the PMOS tube MP5 is electrically connected to the external display device. When the segment is switched, the output voltage VOUT will fluctuate. When the voltage difference of the PMOS tube MP1 is insufficient, it will affect the constant current source characteristics and cause the output current to drop sharply. At this time, the branch detects the output voltage through the PMOS tube MP5, and the output voltage is fed back to the drain end of the PMOS tube MP3 through the feedback loop formed by the PMOS tube MP5, MP6, NMOS tubes MN2, MN3, MN4 and PMOS tube MP6. The PMOS tube MP3 serves as the induction tube of the output constant current source driving transistor. At this time, the current of the PMOS tube MP3 branch decreases, while the current IN1 of the NMOS tube MN5 and MN6 branches decreases, then IN2 increases, and the gate voltage of the PMOS tube MP2 decreases accordingly, so that the output current does not decrease instantly; at this time, the gate voltage of the PMOS tube MP4 decreases accordingly, and the negative feedback loop formed by the NMOS tubes MN9, MN12, PMOS tubes MP4, MP3 and NMOS tube MN4 maintains the current of the PMOS tube MP3 branch relatively stable, so that the current IN2 remains unchanged; The segment current slew rate limiting circuit includes NMOS tubes MN14 to MN31; The segment current slew rate limiting circuit is connected to the current branch IN2 in the segment constant current source feedback control circuit. The NMOS tubes MN14 and MN15 form the first segment current branch, and form a common source and common gate current mirror with a ratio of 1:1 with the NMOS tubes MN9 and MN10 in the current branch IN2. The on-off of this branch is controlled by the NMOS tube MN26, and its enable signal is the output signal SEG_EN0 of the segment control feedback circuit; the NMOS tubes MN16 and MN17 form the second segment current branch, the NMOS tubes MN18 and MN19 form the third segment current branch, the NMOS tubes MN20 and MN21 form the fourth segment current branch, the NMOS tubes MN22 and MN23 form the fifth segment current branch, and the NMOS tubes MN24 and MN25 form the fifth segment current branch. Transistors MN24 and MN25 form the sixth current branch, each forming a 1:1 mirror image ratio with the NMOS transistors MN9 and MN10 in the current branch IN2. The on / off of the second, third, fourth, fifth, and sixth current branches are controlled by NMOS transistors MN27, MN28, MN29, MN30, and MN31, respectively, whose enable signals are the output signals SEG_EN1, SEG_EN2, SEG_EN3, SEG_EN4, and SEG_EN5 of the segment control feedback circuit, respectively. These six current branches are electrically connected together to form a 6*IN2 current sink, which is connected to the PMOS transistor MP2 in the segment constant current source feedback control circuit as a mirror current of the output segment constant current source. When the segment scan signal EN_SEG is valid, the enable signal SEG_EN0 will first become high, turning on the first current sink branch, and then the bias current source control signals ENN_B and ENP_B will become low and high respectively, selecting the segment constant current source feedback control circuit to form a mirror path, and outputting a segment constant current source of N*IN2; the control signal SEG_EN0 passes through five identical delay units in series to form control signals SEG_EN1, SEG_EN2, SEG_EN3, SEG_EN4 and SEG_EN5 respectively. After each identical time interval, the control signal SE G_EN1~SEG_EN5 become high levels in turn, and the five current sink branches are turned on in turn. The output current increases in steps of N*IN2 until it reaches the set value 6N*IN2. At this time, the current rise time is 5 time units; similarly, when the segment is closed, the control signals SEG_EN0, SEG_EN1, SEG_EN2, SEG_EN3, SEG_EN4, and SEG_EN5 first turn off the corresponding switch tubes in turn, and finally the bias current source control signals ENN_B and ENP_B turn off the segment constant current source feedback control circuit, so that the output constant current source is reduced to 0 in steps of N*IN2.

2. The digital tube constant current source drive control system according to claim 1, characterized in that: The bit scanning switch control circuit includes an NMOS transistor MN1 and a resistor R1; the bit scanning switch control circuit is connected to the output pin OUT of the segment constant current source feedback control circuit. The NMOS transistor MN1 is a bit scanning switch, and its gate end is connected to one end of the resistor R1. The function of the resistor R1 is to slow down the switch switching to reduce the electromagnetic interference of the segment switching; the other end of the resistor R1 is connected to the control signal ENB_DIG, which is output by the segment control feedback circuit and controlled by the bit scanning signal EN_DIG; when the bit scanning signal EN_DIG is valid, ENB_DIG becomes a high level, the segment constant current source feedback control circuit is turned off, and the output OUT is pulled down to a low level by the NMOS transistor MN1, at which time the bit scanning is turned on.

3. The digital tube constant current source drive control system according to claim 1, characterized in that: The segment control feedback circuit has an output connected to the segment constant current source feedback control circuit, the bit scanning switch control circuit and the segment current slew rate limiting circuit, and is used to provide the required control signals to the corresponding circuits. The input of the segment control circuit is connected to the segment control module, and is used to receive the bit scanning and segment display signals. The inverse of the segment slew rate control signal SEG_EN5 and the bit scan signal EN_DIG are used as the input signals of the AND gate A1. The output signal of the AND gate A1 passes through the buffer unit BUF1 to generate the control signal ENB_DIG of the bit scan switch. The inverse of ENB_DIG and the segment display signal EN_SEG are used as the input signals of the AND gate A2. The output signal of the AND gate A2 passes through the buffer unit BUF2 to generate the first segment slew rate control signal SEG_EN0. SEG_EN0 passes through a delay unit delay and a buffer unit BUF2 to generate the second segment slew rate control signal SEG_EN1. SEG_EN1 passes through the same delay unit delay and a buffer unit BUF2 to generate the third segment slew rate control signal SEG_EN2. And so on, the fourth, fifth and sixth segment slew rate control signals SEG_EN3, SEG_EN4 and SEG_EN5 are generated respectively. The sixth segment slew rate control signal SEG_EN5 and the first segment slew rate control signal SEG_EN0 pass through an OR gate to generate the enable signals ENN_B and ENP_B of the segment constant current source feedback control circuit; when a segment display signal of an output drive is enabled, that is, EN_SEG=1, EN_DIG=0, then ENB_DIG=0, the bit scan switch is not turned on, at this time SEG_EN0=1, the first segment current branch is turned on, and ENN_B=0, ENP_B=1, so that the output generates an N*IN2 segment constant current source. At this time, SEG_EN0 passes through five identical delay networks to generate SEG_EN1, SEG_EN2, SEG_EN3, SEG_EN4, SEG_EN5, Enable the second to sixth segment current branches respectively, so that the output is finally a 6N*IN2 segment constant current source; when the segment display signal is not enabled and the bit scan signal is enabled, that is, EN_SEG=0, EN_DIG=1, the enable signal ENB_DIG of the bit scan switch cannot be immediately changed to 1, because SEG_EN5 cannot immediately become a low level. When the segment is turned off, SEG_EN0 first becomes 0, turning off the first segment current branch. After five delays, SEG_EN1, SEG_EN2, SEG_EN3, SEG_EN4, and SEG_EN5 successively become 0. At this time, the segment constant current source output is 0, and the constant current source feedback control circuit is also turned off at this time. At this time, ENB_DIG=1, and the bit scan switch is turned on.

4. The digital tube constant current source drive control system according to claim 3, characterized in that: The delay unit delay is composed of two identical inverters INV1 and capacitor C1 connected in series, wherein the inverter INV1 is an inverse ratio transistor, and the sizes of the inverter INV1 and the capacitor C1 are selected according to the delay time requirement.

5. The digital tube constant current source drive control system according to claim 1, characterized in that: In the bias current source generation module, the reference voltage generation circuit is electrically connected to the current control circuit and is used to generate a low-temperature drift voltage VR as a voltage reference for the external resistor R; The current control circuit includes an operational amplifier AMP1, PMOS transistors MP11 to MP16, and an NMOS transistor MN0. A voltage VR generated by a reference voltage generation circuit serves as the positive input voltage of the operational amplifier AMP1. The negative input of the operational amplifier AMP1 is connected to a pin ISET, which is used to connect to an external resistor R. The output of the operational amplifier AMP1 is connected to the gate of the NMOS transistor MN0. The operational amplifier AMP1 and the NMOS transistor MN0 form a negative feedback loop. At this time, the current I1 of the NMOS transistor MN0 branch is equal to VR / R, where I1 is the first mirror current branch generated by the external resistor. The PMOS transistors MP13 and MP14 form a cascode current mirror with a mirror ratio of 1:A with the PMOS transistors MP11 and MP12, and the branch current I2 = VR / R*A; the PMOS transistors MP15 and MP16 form a cascode current mirror with a mirror ratio of 1:2A with the PMOS transistors MP11 and MP12, and the branch current I3 = VR / R*2A; the current sources I2 and I3 are electrically connected to a constant current source feedback control circuit to serve as bias current sources for the constant current source.

6. The digital tube constant current source drive control system according to claim 1, characterized in that: In the bit scanning and segment display control circuit, nine diodes represent the eight-segment lamps of the digital tube respectively; output drivers 1~8 are simplified into a segment constant current source, a switch controlled by a segment display signal, and a bit scanning switch controlled by a bit scanning signal. In addition, there is an output driver module DP, which only has a segment constant current source and a switch controlled by a segment display signal, which are the same as output driver 1; the digital tube device has a total of 8 bits, each bit corresponds to the eight-segment lamps of the digital tube, and is driven by a common cathode, so when the segment display control of the output driver module is enabled, the segment constant current source is electrically connected to the anode of the corresponding diode, providing high-precision current as a constant current source, and when the bit scanning control of a certain output driver module is enabled, the cathode of the eight-segment diode is connected to the bit scanning switch of this output driver module.

7. The digital tube constant current source drive control system according to claim 6, characterized in that: When the first bit is displayed and all eight segments are bright, the bit scan control EN_DIG1 of output driver 1 becomes high, and output driver 1 is connected to the cathode of the eight-segment diode as a bit scan switch. At this time, EN_SEG1 must be low, and the constant current function of output driver 1 cannot be turned on. The segment display control signals EN_SEG2~EN_SEG8 of output driver 2~output driver 8 and the segment display control signal EN_SEGDP of output driver DP all become high, and the segment constant current sources of output driver 2~output driver 8 and output driver DP are respectively connected to the anode of the corresponding diode, and the bit scan signals EN_DIG2~EN_DIG8 of the corresponding drive modules must be low, and the bit scan switch cannot be turned on; When the second digit is displayed and all eight segments are bright, the bit scan control EN_DIG2 of output driver 2 becomes high, and output driver 2 is connected to the cathode of the eight-segment diode as a bit scan switch. At this time, EN_SEG2 must be low, and the constant current function of output driver 1 cannot be turned on. The segment display control signals EN_SEG1, EN_SEG3~EN_SEG8, and EN_SEGDP of output driver 1, output driver 3~output driver 8, and output driver DP all become high, and the segment constant current sources of output driver 1, output driver 3~output driver 8, and output driver DP are respectively connected to the anode of the corresponding diode, and the bit scan signals EN_DIG1, ​​EN_DIG3~EN_DIG8 of the corresponding drive modules must be low, and the bit scan switch cannot be turned on.

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