Display panel and display device

Abstract

The application discloses a display panel and a display device, the display panel comprising a plurality of sub-pixel units, a plurality of data lines corresponding to the plurality of sub-pixel units, a plurality of first switch modules and a plurality of first connection lines, the plurality of first connection lines being electrically connected with the plurality of data lines through the plurality of first switch modules; the resistance values of at least part of the first connection lines are different, the plurality of first switch modules are used for enabling at least part of the data lines to be in communication with the first connection lines with different resistance values in the same time period and transmitting data signals to the data lines, and enabling at least part of the data lines to exchange the first connection lines with different resistance values in communication in different time periods. The scheme can improve the display quality problem caused by the load difference on adjacent first connection lines and effectively solve the phenomenon of display vertical lines.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the development of display technology, display panels are playing an increasingly important role in people's daily lives, and people's demands for screen-to-body ratio are also increasing. To improve the screen-to-body ratio, the bottom bezel is usually compressed.

[0003] However, existing narrow bottom bezel panels suffer from poor display quality. Summary of the Invention

[0004] The present invention provides a display panel and a display device to improve display quality.

[0005] According to one aspect of the present invention, a display panel is provided, comprising:

[0006] Multiple sub-pixel units, and multiple data lines connected to the corresponding sub-pixel units;

[0007] Multiple first switch modules;

[0008] Multiple first connection lines are electrically connected to multiple data lines via multiple first switch modules; at least some of the first connection lines have different resistance values; the multiple first switch modules are used to enable at least some data lines to be connected to first connection lines with different resistance values ​​at the same time and transmit data signals to the data lines, and to enable at least some data lines to switch the connected first connection lines with different resistance values ​​at different time periods.

[0009] Optionally, the first switch module includes a first terminal, a second terminal, and a third terminal. The first terminals of different first switch modules are connected to different first connection lines, and the second and third terminals of the same first switch module are connected to different data lines. The second terminals of at least two first switch modules are electrically connected, and the third terminals of at least two first switch modules are electrically connected.

[0010] The first switch module is used to transmit data signals on the first connection line to the data line via the first terminal from its second or third terminal when the circuit is turned on.

[0011] Optionally, the first end of each first switch module is connected to a first connecting line, the second end of the first switch module is connected to a second connecting line, and the third end of the first switch module is connected to a third connecting line.

[0012] One end of the second connecting line is connected to the corresponding data line, and the other end is connected to the second end of at least two first switch modules; one end of the third connecting line is connected to the corresponding data line, and the other end is connected to the third end of at least two first switch modules; the second connecting line and the third connecting line are connected to different data lines.

[0013] Among them, the resistance values ​​of the first connecting lines connected to adjacent first switch modules are different, and the second ends of multiple first switch modules connected to the same second connecting line are not simultaneously turned on, and the third ends of multiple first switch modules connected to the same third connecting line are not simultaneously turned on.

[0014] Optionally, the first connection lines connecting adjacent first switch modules are arranged on different layers;

[0015] Optionally, the line width of the first connection line located on different layers may be different.

[0016] Optionally, a second connecting line is connected to the second terminals of the (2n-1)th and the 2nth first switch modules respectively, and a third connecting line is connected to the third terminals of the (2n-1)th and the 2nth first switch modules respectively; wherein, n≥1 and n is an integer;

[0017] The first switch module includes a first switch unit and a second switch unit. The first switch unit is connected between a first connecting line and a second connecting line, and the second switch unit is connected between the first connecting line and a third connecting line. The first switch unit and the second switch unit in the same first switch module are not simultaneously turned on.

[0018] Optionally, the first switch modules with adjacent serial numbers are positioned adjacent to each other, and the arrangement direction of the multiple first switch modules is perpendicular to the extension direction of the data line.

[0019] Optionally, the display panel may also include a first switch signal line and a second switch signal line;

[0020] The first switch signal line is connected to the control terminal of the first switch unit in the 2n-1 first switch module and the control terminal of the second switch unit in the 2n first switch module, respectively; the second switch signal line is connected to the control terminal of the second switch unit in the 2n-1 first switch module and the control terminal of the first switch unit in the 2n second switch module, respectively.

[0021] Specifically, the first switch unit in the (2n-1)th first switch module and the second switch unit in the 2nth first switch module are configured to be turned on in the Nth frame and turned off in the N+1th frame; the second switch unit in the (2n-1)th first switch module and the first switch unit in the 2nth first switch module are configured to be turned on in the N+1th frame and turned off in the Nth frame; N≥1 and N is an odd number;

[0022] Optionally, the first switching unit includes a first transistor, the gate of the first transistor is the control terminal of the first switching unit, the first terminal of the first transistor is connected to the first connection line, and the second terminal of the first transistor is connected to the second connection line.

[0023] The second switching unit includes a second transistor, the gate of which is the control terminal of the second switching unit, the first terminal of which is connected to the first connection line, and the second terminal of which is connected to the third connection line.

[0024] Optionally, the first switch signal line is multiplexed as the second switch signal line. In the same first switch module, the channel type of the first transistor is opposite to that of the second transistor, and the channel type of the first transistor in the (2n-1)th first switch module is opposite to that of the first transistor in the 2nth first switch module.

[0025] Optionally, the data line includes a first data line and a second data line arranged alternately along the row direction, and a second switch module is also provided on the connection path between the data line and the corresponding first switch module, with the second switch module corresponding to the first switch module one by one;

[0026] The first end of the m-th second switch module is connected to the second connecting line, and the first end of the (m+1)-th second switch module is connected to the third connecting line; where m is an odd number greater than or equal to 1.

[0027] The second terminal of the second switch module is connected to the first data line, and the third terminal of the second switch module is connected to the second data line.

[0028] Optionally, the second switch modules with adjacent serial numbers are positioned adjacently, and the arrangement direction of multiple second switch modules is perpendicular to the extension direction of the data line;

[0029] The multiple sub-pixel units include a first sub-pixel unit and a second sub-pixel unit, the first sub-pixel unit being connected to a first data line and the second sub-pixel unit being connected to a second data line;

[0030] The first sub-pixel unit includes a first sub-pixel and a second sub-pixel arranged along the column direction, and the second sub-pixel unit includes a third sub-pixel. The first sub-pixel, the second sub-pixel, and the third sub-pixel emit different colors.

[0031] Optionally, the display panel further includes a first selection signal line and a second selection signal line, and the second switch module includes a third switch unit and a fourth switch unit. The first selection signal line is connected to the control terminal of the third switch unit, and the second selection signal line is connected to the control terminal of the fourth switch unit.

[0032] For the m-th second switch module, the first end of the third switch unit is connected to the second connection line, the second end of the third switch unit is connected to the first data line, the first end of the fourth switch unit is connected to the second connection line, and the second end of the fourth switch unit is connected to the second data line.

[0033] For the (m+1)th second switch module, the first end of the third switch unit is connected to the third connection line, the second end of the third switch unit is connected to the first data line, the first end of the fourth switch unit is connected to the third connection line, and the second end of the fourth switch unit is connected to the second data line.

[0034] Optionally, the third switching unit includes a third transistor, the fourth switching unit includes a fourth transistor, the gate of the third transistor is connected to the first selection signal line, the gate of the fourth transistor is connected to the second selection signal line, the first terminal of the third transistor and the first terminal of the fourth transistor are connected together as the first terminal of the second switching module, the second terminal of the third transistor is connected to the first data line, and the second terminal of the fourth transistor is connected to the second data line.

[0035] Optionally, the display panel includes a display area and a non-display area, with sub-pixel units disposed in the display area; the first connecting line, the second connecting line, and the third connecting line are all located in the non-display area.

[0036] Optionally, the non-display area also includes a fan-out area, with the first connection line located in the fan-out area; wherein, the first switch module is located between the fan-out area and the display area.

[0037] Optionally, the second connecting line and the third connecting line are set on the same layer.

[0038] Optionally, the display panel also includes a driver chip, which is electrically connected to the data line via a first connection line and a first switch module.

[0039] According to another aspect of the present invention, a display device is provided, including the display panel provided in any embodiment of the present invention.

[0040] The technical solution provided by this invention, by setting a first switching module, allows data signals to be transmitted through first connecting lines with different resistance values ​​at different time periods. This results in the sub-pixel units connected to the same data line in the display panel being in a bright (or dark) state during the first time period and in a dark (or bright) state during the second time period. This allows the luminous brightness of the second time period to compensate for the luminous brightness of the first time period, making the luminous brightness of adjacent columns of sub-pixel units consistent. This can improve the display quality problem caused by the load difference on adjacent first connecting lines and effectively solve the phenomenon of vertical lines on the display.

[0041] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of the structure of a display panel in related technologies;

[0044] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0045] Figure 3 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention;

[0046] Figure 4 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0047] Figure 5 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0048] Figure 6 A timing waveform diagram on a switch signal line provided in an embodiment of the present invention;

[0049] Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0050] Figure 8 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0051] Figure 9 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0052] Figure 10 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0053] Figure 11 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0054] Figure 12 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0055] Figure 13 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0056] Figure 14 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0057] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0058] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0059] As described in the background section, existing narrow-bezel panels suffer from poor display quality. The inventors' research revealed that the cause of this problem is: Figure 1 This is a schematic diagram of the structure of a display panel in related technologies, such as... Figure 1 As shown, the display panel is divided into a display area AA and a non-display area NA. To achieve a narrow bottom bezel, the connection lines LI (i.e., source-fanout signal lines) located in the non-display area NA typically use two different metal layers running alternately. Because different metal layers are etched separately, the linewidth loss (CD loss) of the two metal layers fluctuates during the etching process. This can easily lead to significant differences in the linewidth of the connection lines LI located on different metal layers, resulting in large differences in the load on adjacent data lines and consequently, differences in the data voltage written to the pixels. Specifically, the data lines with higher loads may experience insufficient charging, leading to higher data voltages written to the pixels and dimmer pixel brightness. This results in inconsistent brightness between adjacent columns of pixels, causing vertical stripes and affecting display quality.

[0060] To address the above problems, embodiments of the present invention provide a display panel. Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, wherein, Figure 2 Only a portion of the sub-pixel units PX are shown. (Example) Figure 2 As shown, the display panel includes: multiple sub-pixel units PX, multiple data lines DL connected to the multiple sub-pixel units PX, multiple first switch modules 10, and multiple first connection lines LI1. The multiple first connection lines LI1 are electrically connected to the multiple data lines DL via the multiple first switch modules 10. At least some of the first connection lines LI1 have different resistance values. The multiple first switch modules 10 are used to enable at least some of the data lines DL to be connected to the first connection lines LI1 with different resistance values ​​in the same time period and transmit data signals to the data lines DL. They also enable at least some of the data lines DL to switch between being connected to the first connection lines LI1 with different resistance values ​​in different time periods, so that each data line DL in the at least some of the data lines DL is alternately connected to the first connection line LI1 with a larger resistance value and the first connection line LI1 with a smaller resistance value in different time periods.

[0061] Specifically, each sub-pixel unit PX is connected to a corresponding data line DL. The first connection line LI1 is used to transmit data signals to the corresponding data line DL, so as to write the corresponding data voltage into the sub-pixel unit PX. The resistance values ​​of two adjacent first connection lines LI1 are different; for example, two adjacent first connection lines LI1 can be located in different film layers of the display panel. Figure 3 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention, specifically... Figure 2 The cross-sectional structure of the display panel shown is obtained along the cutting line AA', for reference. Figure 3 Along the thickness direction Z of the display panel, a substrate 40, a first metal layer M1, a first insulating layer 41, a second metal layer M2, and a second insulating layer 42 are sequentially disposed. Figure 2 and Figure 3 For example, the first connecting lines LI1 are arranged in an alternating manner with the first metal layer M1 and the second metal layer M2. That is, an odd number of first connecting lines LI1 are located in the first metal layer M1, and an even number of first connecting lines LI1 are located in the second metal layer M2. The resistivity of lines located in the same metal layer is the same. The linewidth of the first connecting lines located in different layers is different. For example, the linewidth of the first connecting line LI1 located in the first metal layer M1 is greater than the linewidth of the first connecting line LI1 located in the second metal layer M2 (e.g., ...). Figure 2 (As shown by the thick and thin lines), therefore, the load (or resistance) of the first connection line LI1 located on the first metal layer M1 is less than the load (or resistance) of the first connection line LI1 located on the second metal layer M2. Optionally, multiple data lines DL are arranged along the first direction X and extend along the second direction Y.

[0062] In this embodiment, a first switch module 10 is provided on the connection path between the first connection line LI1 and the corresponding data line DL. Within the same time period (e.g., the same frame), the first switch module 10 is configured to connect the data line DL to first connection lines LI1 with different resistance values, enabling data signals to be transmitted to the corresponding data line DL. Furthermore, within different time periods, the first switch module 10 is controlled to switch the first connection lines LI1 connected to the data line DL, thereby allowing the same data line DL to alternately connect to first connection lines LI1 with different resistance values ​​in different time periods (e.g., different frames). For example, it connects to a first connection line LI1 with a higher resistance value in the first time period, to a first connection line LI1 with a lower resistance value in the second time period, and then connects to a first connection line LI1 with a higher resistance value again in the third time period, and so on. Therefore, the sub-pixel unit PX connected to the same data line DL transmits data signals through first connection lines LI1 with different resistance values ​​in different time periods, thus neutralizing the brightness of the sub-pixel unit PX and improving the vertical stripe phenomenon caused by the difference in the trace load of the first connection line LI1.

[0063] Optionally, the first switch module 10 includes a first terminal a, a second terminal b, and a third terminal c. The first terminal c of different first switch modules 10 is connected to different first connection lines LI1, and the second terminal b and the third terminal c of the same first switch module 10 are connected to different data lines DL. The second terminals b of at least two first switch modules 10 are electrically connected, and the third terminals c of at least two first switch modules 10 are electrically connected, so as to exchange the first connection lines LI1 between the data lines DL at different time periods.

[0064] Optionally, the first switch module 10 is used to transmit the data signal on the first connection line LI1 to the data line DL via its second terminal b or third terminal c through its first terminal a when it is turned on. The first terminal a of the first switch module 10 may be connected to one of the second terminal b and the third terminal c at the same time period (e.g., within one frame); at different time periods (e.g., within different frames), the second terminal b and the third terminal c may be connected to the first terminal a alternately. The first terminal a of the first switch module 10 may not be connected to both the second terminal b and the third terminal c simultaneously.

[0065] Optionally, the multiple first switch modules 10 can be divided into multiple groups of first switch modules 10. Each group of first switch modules 10 may include at least two first switch modules 10, or more, such as three first switch modules 10, four first switch modules 10, etc. Each pair of adjacent first switch modules 10 can be grouped together. The number of first switch modules 10 in each group can be equal to the number of output terminals of each first switch module 10. Different output terminals of each first switch module 10 can be connected to different data lines DL. First switch modules 10 in the same group can be connected to the same at least two data lines DL. First switch modules 10 in different groups can be connected to different data lines DL. The first terminal a of the first switch module 10 in the same group can be connected to first connection lines LI1 with different resistance values. The data lines DL connected to each group of first switch modules 10 can be switched to the first connection lines LI1 connected to that group of first switch modules 10 at different time periods. The number of first switch modules 10 and the number of first connection lines LI1 can be equal.

[0066] Continue to refer to Figure 2 A second connecting line LI2 is connected to the second end of the (2n-1)th and 2nth first switch modules 10 respectively, and a third connecting line LI3 is connected to the third end of the (2n-1)th and 2nth first switch modules 10 respectively; where n≥1 and n is an integer. Optionally, the first switch modules 10 with adjacent serial numbers are positioned adjacently, and the arrangement direction of the multiple first switch modules 10 is perpendicular to the extension direction of the data line DL.

[0067] Specifically, each first switch module 10 has its first terminal a connected to a first connecting line LI1, its second terminal b connected to a second connecting line LI2, and its third terminal c connected to a third connecting line LI3. One end of the second connecting line LI2 is connected to a corresponding data line DL, and the other end is connected to the second terminals b of at least two first switch modules 10. One end of the third connecting line LI3 is connected to a corresponding data line DL, and the other end is connected to the third terminals c of at least two first switch modules 10. The data lines DL connected to the second connecting line LI2 and the third connecting line LI3 are different. The first switch module 10 is used to transmit the data signal on the first connecting line LI1 from its second terminal b or third terminal c to the data line DL when it is turned on. The first connecting lines LI1 connected to adjacent first switch modules 10 are arranged on different layers. Furthermore, the second terminals b of multiple first switch modules 10 connected to the same second connecting line LI2 are not turned on simultaneously, and the third terminals c of multiple first switch modules 10 connected to the same third connecting line LI3 are not turned on simultaneously.

[0068] In this circuit, the first terminal a of the first switch module 10 can be an input terminal, and the second terminal b and the third terminal c are different output terminals. The first terminal a of the first switch module 10 is connected to the first connecting line LI1, the second terminal b is connected to the second connecting line LI2, and the third terminal c is connected to the third connecting line LI3. For each second connecting line LI2 and the third connecting line LI3, the same second connecting line LI2 is connected to the second terminal b of at least two first switch modules 10, and the same third connecting line LI3 is connected to the third terminal c of at least two first switch modules 10. The number of first switch modules 10 connected to the same second connecting line LI2 and the number of first switch modules 10 connected to the same third connecting line LI3 can be the same.

[0069] It should be noted that the number of first switch modules 10 connected to the second connection line LI2 or the third connection line LI3 can be related to the film layer configuration of the first connection line LI1. The number of first switch modules 10 connected to the second connection line LI2 or the third connection line LI3 can correspond to the number of film layers arranged in the first connection line LI1.

[0070] The first switch module 10 is configured such that the second terminal b of each first switch module 10 connected to the same second connection line LI2 is not simultaneously turned on, and the third terminal c of each first switch module 10 connected to the same third connection line LI3 is not simultaneously turned on. For the same first switch module 10, its second terminal b and third terminal c cannot be turned on at the same time, otherwise it will lead to data signal transmission errors.

[0071] by Figure 2 Taking the structure shown as an example, the multiple first switch modules 10 are numbered (1), (2), (3), and (4) in sequence. The first connection line LI1 connected to the first first switch module 10 is located in the first metal layer, the first connection line LI1 connected to the second first switch module 10 is located in the second metal layer, the first connection line LI1 connected to the third first switch module 10 is located in the first metal layer, the first connection line LI1 connected to the fourth first switch module 10 is located in the second metal layer, and so on.

[0072] During the first time period, the first terminal a and the second terminal b of the odd-numbered first switch module 10 are connected, while the first terminal a and the third terminal c are disconnected. Each first connection line LI1 located in the first metal layer transmits data signals to the corresponding data line DL via the first switch module 10 and the second connection line LI2. Simultaneously, the first terminal a and the third terminal c of the even-numbered first switch module 10 are connected, while the first terminal a and the second terminal b are disconnected. Each first connection line LI1 located in the second metal layer transmits data signals to the corresponding data line DL via the first switch module 10 and the third connection line LI3. Because the linewidths of the first connection lines LI1 connected to the odd-numbered and even-numbered first switch modules 10 differ, the trace loads of the first connection lines LI1 connected to the odd-numbered and even-numbered first switch modules 10 differ, resulting in different illumination levels of the sub-pixel units PX connected to the odd-numbered and even-numbered first switch modules 10. For example, if the trace load of the first connection line LI1 located in the second metal layer is large, the light emission brightness of the sub-pixel unit PX corresponding to the odd-numbered first switch module 10 will be brighter, and the light emission brightness of the sub-pixel unit PX corresponding to the even-numbered first switch module 10 will be dimmer.

[0073] During the second time period, the first terminal a and the second terminal b of the odd-numbered first switch module 10 are turned off, while the first terminal a and the third terminal c are connected. Each first connection line LI1 located in the first metal layer transmits data signals to the corresponding data line DL via the first switch module 10 and the third connection line LI3. Simultaneously, the first terminal a and the third terminal c of the even-numbered first switch module 10 are turned off, while the first terminal a and the second terminal b are connected. Each first connection line LI1 located in the second metal layer transmits data signals to the corresponding data line DL via the first switch module 10 and the second connection line LI2. Since the sub-pixel unit PX corresponding to the odd-numbered first switch module 10 receives its data signal from the first connection line LI1 located in the second metal layer, the brightness of the sub-pixel unit PX corresponding to the odd-numbered first switch module 10 is dimmer, while the brightness of the sub-pixel unit PX corresponding to the even-numbered first switch module 10 is brighter.

[0074] Therefore, the sub-pixel unit PX connected by the same data line DL transmits data signals through the first connection line LI1 located in two different film layers at two different time periods, so that the brightness of the sub-pixel unit PX can be neutralized, thereby improving the phenomenon of vertical stripes caused by the difference in the wiring load of the first connection line LI1.

[0075] In this embodiment, the first time period and the second time period can be two different display frames or display subframes. To ensure the accuracy of data signal transmission, image data processing is required within the driver IC to exchange the odd and even column data signals between the first and second time periods.

[0076] The technical solution provided by this invention addresses the architecture of a first connecting line with alternating wiring of different film layers. By controlling the first switching module to alternately conduct its second and third terminals in a time-division manner, data signals are transmitted by the first connecting lines of different film layers in different time periods. This results in the sub-pixel units connected to the same data line in the display panel being in a bright (or dark) state in the first time period and in a dark (or bright) state in the second time period. This allows the luminous brightness of the second time period to compensate for the luminous brightness of the first time period, ensuring consistent luminous brightness between adjacent columns of sub-pixel units. This improves the display quality caused by load differences on adjacent first connecting lines and effectively solves the problem of vertical stripes on the display.

[0077] It should be noted that the "bright state" and "dark state" mentioned in this embodiment refer to the brightness of the sub-pixel unit being brighter or darker than the normal brightness.

[0078] Figure 4 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, with reference to... Figure 4 Based on the above technical solution, optionally, the first switch module 10 includes a first switch unit 101 and a second switch unit 102. The first switch unit 101 is connected between the first connecting line LI1 and the second connecting line LI2, and the second switch unit 102 is connected between the first connecting line LI1 and the third connecting line LI3. The first switch unit 101 and the second switch unit 102 in the same first switch module 10 are not simultaneously turned on. The first switch unit 101 and the second switch unit 102 in the same first switch module 10 are turned on in a time-sharing manner.

[0079] Specifically, the first switch unit 101 is connected between the first terminal a and the second terminal b of the first switch module 10, and is used to control the on / off state of the path between the first terminal a and the second terminal b; the second switch unit 102 is connected between the first terminal a and the third terminal c of the first switch module 10, and is used to control the on / off state of the path between the first terminal a and the third terminal c. During a first time period, the first switch unit 101 in the odd-numbered first switch module 10 is turned on, and the second switch unit 102 is turned off; the second switch unit 102 in the even-numbered first switch module 10 is turned on, and the first switch unit 101 is turned off. The first switch module 10 is connected one-to-one with the first connection line LI1. Data signals on the first connection line LI1 located on the first metal layer are transmitted to the corresponding data line DL via the turned-on first switch unit 101, and data signals on the first connection line LI1 located on the second metal layer are transmitted to the corresponding data line DL via the turned-on second switch unit 102. Assuming the load on the first connection line LI1 of the second metal layer is greater than the load on the first connection line LI1 of the first metal layer, the data signal on the first connection line LI1 of the second metal layer experiences a significant delay during transitions. During charging, there is insufficient time for the data voltage on the data line DL to reach the target voltage. Therefore, the voltage on the data line DL connected to the first connection line LI1 with the larger load is higher than the voltage on the data line DL connected to the first connection line LI1 with the smaller load. Consequently, the data voltage written to the sub-pixel unit PX corresponding to the even-numbered first switch module 10 is too high, resulting in a darker brightness for that column of sub-pixel units, while the brightness of the sub-pixel units PX corresponding to the odd-numbered first switch module 10 is too high.

[0080] During the second time period, the first switch unit 101 in the even-numbered first switch module 10 is turned on, and the second switch unit 102 is turned off; the second switch unit 102 in the odd-numbered first switch module 10 is turned on, and the first switch unit 101 is turned off. Data signals on the first connection line LI1 of the second metal layer are transmitted to the corresponding data line DL via the turned-on first switch unit 101, and data signals on the first connection line LI1 of the first metal layer are transmitted to the corresponding data line DL via the turned-on second switch unit 102. Assuming the load on the first connection line LI1 of the second metal layer is greater than the load on the first connection line LI1 of the first metal layer, the data voltage written to the sub-pixel unit PX corresponding to the odd-numbered first switch module 10 is higher, resulting in a darker brightness for that column of sub-pixel units, while the brightness of the sub-pixel unit PX corresponding to the even-numbered first switch module 10 is brighter.

[0081] In summary, the sub-pixel units PX connected by the same data line DL transmit data signals through the first connection line LI1 of different film layers at different time periods, so as to cancel out the brightness difference caused by the load difference of the first connection line LI1 of different film layers. As a result, no vertical lines will appear during the display panel display process, which is beneficial to improving display quality.

[0082] Figure 5 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, with reference to... Figure 5 Based on the above technical solution, optionally, the first switching unit 101 includes a first transistor T1, the gate of the first transistor T1 is the control terminal of the first switching unit 101, the first electrode of the first transistor T1 is connected to the first connection line LI1, and the second electrode of the first transistor T1 is connected to the second connection line LI2; the second switching unit 102 includes a second transistor T2, the gate of the second transistor T2 is the control terminal of the second switching unit 102, the first electrode of the second transistor T2 is connected to the first connection line LI1, and the second electrode of the second transistor T2 is connected to the third connection line LI3.

[0083] Furthermore, the display panel also includes a first switch signal line SW1 and a second switch signal line SW2. The first switch signal line SW1 is connected to the control terminal of the first switch unit 101 in the (2n-1)th first switch module 10 and the control terminal of the second switch unit 102 in the (2n-1)th first switch module 10, respectively. The second switch signal line SW2 is connected to the control terminal of the second switch unit 102 in the (2n-1)th first switch module 10 and the control terminal of the first switch unit 101 in the (2n-1)th second switch module 10, respectively. Wherein, n ≥ 1 and n is an integer. That is, the first switch unit 101 in the odd-numbered first switch module 10 and the second switch unit 102 in the even-numbered first switch module 10 are connected to the same first switch signal line SW1; the first switch unit 101 in the even-numbered first switch module 10 and the second switch unit 102 in the odd-numbered first switch module 10 are connected to the same second switch signal line SW2. Here, the channel type of the first transistor T1 and the channel type of the second transistor T2 are the same, for example, both are N-type transistors or P-type transistors. The first transistor T1 can be an N-type transistor or a P-type transistor. The second transistor T2 can be an N-type transistor or a P-type transistor.

[0084] The timing of the control signals transmitted on the first switch signal line SW1 and the second switch signal line SW2 is different. Optionally, data signal exchange and transmission can be performed in one display frame as a time interval. Figure 6 A timing waveform diagram on a switch signal line provided in an embodiment of the present invention, with reference to... Figure 5 and Figure 6The first switch unit 101 in the (2n-1)th first switch module 10 and the second switch unit 102 in the 2nth first switch module 10 are configured to be turned on in the Nth frame and turned off in the N+1th frame; the second switch unit 102 in the (2n-1)th first switch module 101 and the first switch unit 101 in the 2nth first switch module 10 are configured to be turned on in the N+1th frame and turned off in the Nth frame; N≥1 and N is an odd number. For example, in odd-numbered frames, such as the first frame, the first switch unit 101 in the odd-numbered first switch module 10 is turned on and the second switch unit 102 is turned off; the second switch unit 102 in the even-numbered first switch module 10 is turned on and the first switch unit 101 is turned off. In even-numbered frames, such as the second frame, the second switch unit 102 in the odd-numbered first switch module 10 is turned on, and the first switch unit 101 is turned off; in even-numbered first switch modules 10, the first switch unit 101 is turned on, and the second switch unit 102 is turned off. This configuration averages out the load difference of the first connection line LI1 across the two frames, resulting in even brightness across odd and even frames and preventing vertical lines from appearing.

[0085] Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, with reference to... Figure 7 Based on the above technical solution, optionally, a second switch module 20 with demultiplexing function is provided between the data line DL and the first switch module 10. The second switch module 20 can be used to connect the first connection line LI1 to different data lines DL in a time-division multiplexing manner within one frame. Different second switch modules 20 are connected to different data lines DL. The second and third ends of the same second switch module 20 are connected to different data lines DL. The first end of the second switch module 20 is connected to the second ends b of at least two first switch modules 10, or the first end of the second switch module 20 is connected to the third ends c of at least two first switch modules 10. The number of second switch modules 20 and first switch modules 10 can be equal.

[0086] Optionally, the data line DL includes a first data line DL1 and a second data line DL2 arranged alternately along the row direction (which may be parallel to direction X). A second switch module 20 is also provided on the connection path between the data line and the corresponding first switch module, with each second switch module 20 corresponding to a first switch module 10. The first end of the m-th second switch module 20 is connected to the second connecting line LI2, and the first end of the (m+1)-th second switch module 20 is connected to the third connecting line LI3, where m is an odd number greater than or equal to 1. The second end of the second switch module 20 is connected to the first data line DL1, and the third end of the second switch module is connected to the second data line DL2. Optionally, adjacent second switch modules 20 are positioned adjacently, and the arrangement direction of multiple second switch modules 20 is perpendicular to the extension direction of the data line DL. Optionally, the first end of the second switch module 20 is time-divisionally connected to its second and third ends within one frame. Optionally, the first end of the second switch module 20 is not simultaneously connected to its second and third ends.

[0087] In this embodiment, the sub-pixel unit PX includes a first sub-pixel unit PX1 and a second sub-pixel unit PX2. The first sub-pixel unit PX1 is connected to the first data line DL1, and the second sub-pixel unit PX2 is connected to the second data line DL2. The first sub-pixel unit PX1 includes a first sub-pixel R and a second sub-pixel B arranged along the column direction (which may be parallel to the Y direction). The second sub-pixel unit PX2 includes a third sub-pixel G. The first sub-pixel R, the second sub-pixel B, and the third sub-pixel G emit different colors. The first sub-pixel R can be a red sub-pixel, the second sub-pixel B can be a blue sub-pixel, and the third sub-pixel G can be a green sub-pixel. The pixel column containing the first sub-pixel unit PX1 forms a column of sub-pixels where the first sub-pixels R and the second sub-pixels B are alternately arranged along the column direction. The pixel column containing the second sub-pixel unit PX2 forms a column of sub-pixels where the third sub-pixels G are arranged along the column direction.

[0088] For the same second switch unit 20, it is used to select the path between the first data line DL1, the second data line DL2 and the corresponding connecting line. Specifically, the first end a of the first first switch module 10 is connected to the first first connecting line LI1 (located in the first metal layer), the second end b of the first first switch module 10 is connected to the first end of the first second switch module 20 through the first second connecting line LI2 (1), the second end of the first second switch module 20 is connected to the first first data line DL1 (1), the third end of the first second switch module 20 is connected to the first second data line DL2 (1), and the third end c of the first first switch module 10 is connected to the first third connecting line LI3 (1).

[0089] The first end a of the second first switch module 10 is connected to the second first connection line LI1 (located in the second metal layer), the second end b of the second first switch module 10 is connected to the first end of the first second switch module 20 through the first second connection line LI2 (1), the third end c of the second first switch module 10 is connected to the first end of the second second switch module 20 through the first third connection line LI3 (1), the second end of the second second switch module 20 is connected to the second first data line DL1 (2), and the third end of the second second switch module 20 is connected to the second second data line DL2 (2).

[0090] The first end a of the third first switch module 10 is connected to the third first connection line LI1 (located in the first metal layer), the second end b of the third first switch module 10 is connected to the first end of the third second switch module 20 through the second second connection line LI2 (2), the second end of the third second switch module 20 is connected to the third first data line DL1 (3), the third end of the third second switch module 20 is connected to the third second data line DL2 (3), and the third end c of the third first switch module 10 is connected to the second third connection line LI3 (2).

[0091] The first end a of the fourth first switch module 10 is connected to the fourth first connection line LI1 (located in the second metal layer), the second end b of the fourth first switch module 10 is connected to the first end of the third second switch module 20 through the second second connection line LI2 (2), the third end c of the fourth first switch module 10 is connected to the first end of the fourth second switch module 20 through the second third connection line LI3 (2), the second end of the fourth second switch module 20 is connected to the fourth first data line DL1 (4), and the third end of the fourth second switch module 20 is connected to the fourth second data line DL2 (4).

[0092] The connection methods of the subsequent first switch modules 10 and second switch modules 20 are similar and will not be described in detail here.

[0093] Continue to refer to Figure 7Optionally, the display panel further includes a first selection signal line D_MUX1 and a second selection signal line D_MUX2. The second switch module 20 includes a third switch unit 201 and a fourth switch unit 202. The first selection signal line D_MUX1 is connected to the control terminal of the third switch unit 201, and the second selection signal line D_MUX2 is connected to the control terminal of the fourth switch unit 202. The first selection signal line D_MUX1 is used to control the third switch unit 201 to be on or off, and the second selection signal line D_MUX2 is used to control the fourth switch unit 202 to be on or off. The connecting lines of the third switch unit 201 and the fourth switch unit 202 are different. Here, for different second switch modules, the paths between the data line DL used for control by the third switch unit 201 and the fourth switch unit 202 and the connecting lines are different.

[0094] Specifically, for the m-th second switch module 20, the first end of the third switch unit 201 is connected to the second connection line LI2, the second end of the third switch unit 201 is connected to the first data line DL1, the first end of the fourth switch unit 202 is connected to the second connection line LI2, and the second end of the fourth switch unit 202 is connected to the second data line DL2; m is an odd number greater than or equal to 1.

[0095] For the (m+1)th second switch module 20, the first end of the third switch unit 201 is connected to the third connection line LI3, the second end of the third switch unit 201 is connected to the first data line DL1, the first end of the fourth switch unit 202 is connected to the third connection line LI3, and the second end of the fourth switch unit 202 is connected to the second data line DL2.

[0096] The working principle of the second switch module 20 can be found in the description in the relevant technology, and will not be repeated here.

[0097] Optionally, the third switching unit 201 may include a third transistor T3, and the fourth switching unit 202 may include a fourth transistor T4. The gate of the third transistor T3 is connected to the first selection signal line D_MUX1, and the gate of the fourth transistor T4 is connected to the second selection signal line D_MUX2. The first terminal of the third transistor T3 and the first terminal of the fourth transistor T4 are connected together as the first terminal of the second switching module 20. The second terminal of the third transistor T3 is connected to the first data line DL1, and the second terminal of the fourth transistor T4 is connected to the second data line DL2.

[0098] Figure 8 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, with reference to... Figure 8Based on the above technical solutions, optionally, the first switch signal line SW1 is multiplexed as the second switch signal line SW2. In the same first switch module 10, the channel type of the first transistor T1 is opposite to the channel type of the second transistor T2, and the channel type of the first transistor T1 in the (2n-1)th first switch module 10 is opposite to the channel type of the first transistor T1 in the 2nth first switch module 10.

[0099] The following example illustrates the situation where the load on an odd number of first connection lines LI1 is less than the load on an even number of first connection lines LI1. Figure 9 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 10 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, specifically illustrating the on / off status of each transistor in odd-numbered frames. Switches marked with an "X" indicate they are in the off state, while switches without an "X" indicate they are in the on state. (See reference...) Figure 9 When the first sub-pixel R and the second sub-pixel B are lit, the signal transmitted on the first selection signal line D_MUX1 controls the third transistor T3 to turn on. In odd-numbered frames (such as the first frame), the first transistor T1 in the odd-numbered first switch module 10 is turned on, and the second transistor T2 is turned off; in even-numbered first switch modules 10, the second transistor T2 is turned on, and the first transistor T1 is turned off. The data signal on the odd-numbered first connection line LI1 is transmitted to the corresponding odd-numbered first data line DL1 via the first transistor T1 in the odd-numbered first switch module 10, and the data signal on the even-numbered first connection line LI1 is transmitted to the corresponding even-numbered first data line DL1 via the second transistor T2 in the even-numbered first switch module 10. The load of the odd-numbered first connection line LI1 is less than the load of the even-numbered first connection line LI1. Therefore, the brightness of the first sub-pixel R and the second sub-pixel B (e.g., the sub-pixel connected to data line DL1(1)) corresponding to the odd-numbered first connection line LI1 is brighter, while the brightness of the first sub-pixel R and the second sub-pixel B (e.g., the sub-pixel connected to data line DL1(2)) corresponding to the even-numbered first connection line LI1 is darker. See also Figure 10 When the third sub-pixel G is lit, the signal transmitted on the first selection signal line D_MUX1 controls the fourth transistor T4 to turn on. The brightness of the third sub-pixel G corresponding to the odd-numbered first connection line LI1 (e.g., the sub-pixel connected to the data line DL1(1)) is brighter, while the brightness of the third sub-pixel G corresponding to the even-numbered first connection line LI1 (e.g., the sub-pixel connected to the data line DL1(2)) is darker.

[0100] Figure 11 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 12This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, specifically illustrating the on / off state of each transistor in even-numbered frames. (Refer to...) Figure 11 In even-numbered frames (e.g., the second frame), the first transistor T1 in the odd-numbered first switch module 10 turns off in response to the signal on the first switch signal line SW1, and the second transistor T2 turns on; the second transistor T2 in the even-numbered first switch module 10 turns off, and the first transistor T1 turns on. The data signal on the odd-numbered first connection line LI1 is transmitted to the corresponding even-numbered first data line DL1 via the second transistor T2 in the odd-numbered first switch module 10, and the data signal on the even-numbered first connection line LI1 is transmitted to the corresponding odd-numbered first data line DL1 via the first transistor T1 in the even-numbered first switch module 10. The load of the odd-numbered first connection line LI1 is less than the load of the even-numbered first connection line LI1. Therefore, the brightness of the first sub-pixel R and the second sub-pixel B (e.g., the sub-pixel connected to the data line DL1(2)) corresponding to the odd-numbered first connection line LI1 is brighter, while the brightness of the first sub-pixel R and the second sub-pixel B (e.g., the sub-pixel connected to the data line DL1(1)) corresponding to the even-numbered first connection line LI1 is darker. See also Figure 12 When the third sub-pixel G is lit, the signal transmitted on the first selection signal line D_MUX1 controls the fourth transistor T4 to turn on. The brightness of the third sub-pixel G corresponding to the odd-numbered first connection line LI1 (e.g., the sub-pixel connected to the data line DL1(2)) is brighter, while the brightness of the third sub-pixel G corresponding to the even-numbered first connection line LI1 (e.g., the sub-pixel connected to the data line DL1(1)) is darker.

[0101] The first switching module 10 exchanges the data signals transmitted on the first connection line LI1 of two different film layers in the odd and even frames, so that the light emission brightness of the corresponding sub-pixels can be mutually compensated in the odd and even frames, thereby making the light emission brightness of the sub-pixels in different columns consistent, improving the phenomenon of vertical stripes and improving the display quality.

[0102] It should be understood that the above technical solution is not limited to odd and even frames, but can also be multiple frames. This is equivalent to exchanging the first connection line LI1 every multiple frames, which can be achieved by configuring the first switch module 10 and the corresponding connection line.

[0103] Figure 13 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, with reference to... Figure 8 and Figure 13 The display panel includes a display area AA and a non-display area NA, and the sub-pixel unit PX is located in the display area AA; the first connecting line LI1, the second connecting line LI2 and the third connecting line LI3 are all located in the non-display area NA.

[0104] The non-display area NA also includes a fan-out area C, with the first connecting line LI1 located in fan-out area C. The first switch module 10 is located between fan-out area C and display area AA. For example, the first switch module 10 can be located in area B, and the second switch module 20 can also be located in area B. Area B is also located within the non-display area NA.

[0105] Optionally, the display panel further includes a driver chip 50, which is electrically connected to the data line DL via a first connection line LI1 and a first switch module 10. The driver chip 50 can be used to provide data signals to the data line DL and control signals to the first scan drive circuit 61 and the second scan drive circuit 62, wherein the first scan drive circuit 61 and the second scan drive circuit 62 are used to provide scan drive signals to the sub-pixel units PX.

[0106] Optionally, the second connecting line LI2 and the third connecting line LI3 are arranged on the same layer, which helps to reduce the load difference on the connection path between the first connecting line LI1 and the corresponding data line DL, and facilitates wiring.

[0107] Optionally, embodiments of the present invention also provide a display device, including the display panel provided in the above embodiments, and thus the display device also possesses the beneficial effects described in any of the above embodiments. Figure 14 This is a schematic diagram of a display device provided in an embodiment of the present invention. In this embodiment, the display device can be as follows: Figure 14 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, in-vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on this.

[0108] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0109] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Multiple sub-pixel units, and multiple data lines connected to the multiple sub-pixel units; Multiple first switch modules; Multiple first connection lines are electrically connected to multiple data lines via multiple first switch modules; at least some of the first connection lines have different resistance values, and the multiple first switch modules are used to enable at least some of the data lines to be connected to first connection lines with different resistance values ​​at the same time period and transmit data signals to the data lines, and to enable at least some of the data lines to switch the first connection lines with different resistance values ​​connected at different time periods.

2. The display panel according to claim 1, characterized in that, The first switch module includes a first terminal, a second terminal, and a third terminal. The first terminals of different first switch modules are connected to different first connection lines, and the second and third terminals of the same first switch module are connected to different data lines. The second terminals of at least two first switch modules are electrically connected, and the third terminals of at least two first switch modules are electrically connected. The first switch module is used to transmit the data signal on the first connection line to the data line via its second or third end through its first end when the connection is turned on.

3. The display panel according to claim 2, characterized in that, Each of the first switch modules has its first end connected to a first connection line, its second end connected to a second connection line, and its third end connected to a third connection line. One end of the second connecting line is connected to the corresponding data line, and the other end is connected to the second end of at least two of the first switch modules; one end of the third connecting line is connected to the corresponding data line, and the other end is connected to the third end of at least two of the first switch modules; the second connecting line and the third connecting line are connected to different data lines; Among them, the resistance values ​​of the first connecting lines connected to adjacent first switch modules are different, and the second ends of multiple first switch modules connected to the same second connecting line are not simultaneously turned on, and the third ends of multiple first switch modules connected to the same third connecting line are not simultaneously turned on. Preferably, the first connecting lines connected to adjacent first switch modules are arranged on different layers; Preferably, the line width of the first connecting line located on different layers is different.

4. The display panel according to claim 3, characterized in that, The second connecting line is connected to the second terminals of the (2n-1)th and (2n)th first switch modules respectively, and the third connecting line is connected to the third terminals of the (2n-1)th and (2n)th first switch modules respectively; wherein, n≥1 and n is an integer; The first switch module includes a first switch unit and a second switch unit, wherein the first switch unit is connected between the first connecting line and the second connecting line, and the second switch unit is connected between the first connecting line and the third connecting line; The first switch unit and the second switch unit in the same first switch module are not simultaneously turned on; Preferably, the first switch modules with adjacent serial numbers are located adjacent to each other, and the arrangement direction of the plurality of first switch modules is perpendicular to the extension direction of the data line.

5. The display panel according to claim 4, characterized in that, The display panel also includes a first switch signal line and a second switch signal line; The first switch signal line is connected to the control terminal of the first switch unit in the 2n-1th first switch module and the control terminal of the second switch unit in the 2nth first switch module, respectively; the second switch signal line is connected to the control terminal of the second switch unit in the 2n-1th first switch module and the control terminal of the first switch unit in the 2nth second switch module, respectively. Wherein, the first switch unit in the (2n-1)th first switch module and the second switch unit in the 2nth first switch module are configured to be turned on in the Nth frame and turned off in the N+1th frame; the second switch unit in the (2n-1)th first switch module and the first switch unit in the 2nth first switch module are configured to be turned on in the N+1th frame and turned off in the Nth frame; N≥1 and N is an odd number; Preferably, the first switching unit includes a first transistor, the gate of the first transistor is the control terminal of the first switching unit, the first electrode of the first transistor is connected to the first connection line, and the second electrode of the first transistor is connected to the second connection line; The second switching unit includes a second transistor, the gate of the second transistor is the control terminal of the second switching unit, the first terminal of the second transistor is connected to the first connection line, and the second terminal of the second transistor is connected to the third connection line.

6. The display panel according to claim 5, characterized in that, The first switch signal line is multiplexed as the second switch signal line. In the same first switch module, the channel type of the first transistor is opposite to that of the second transistor, and the channel type of the first transistor in the (2n-1)th first switch module is opposite to that of the first transistor in the 2nth first switch module.

7. The display panel according to claim 3, characterized in that, The data line includes a first data line and a second data line arranged alternately along the row direction. A second switch module is also provided on the connection path between the data line and the corresponding first switch module. The second switch module is provided in a one-to-one correspondence with the first switch module. The first end of the m-th second switch module is connected to the second connecting line, and the first end of the (m+1)-th second switch module is connected to the third connecting line; where m is an odd number greater than or equal to 1. The second end of the second switch module is connected to the first data line, and the third end of the second switch module is connected to the second data line. Preferably, the second switch modules with adjacent serial numbers are positioned adjacent to each other, and the arrangement direction of the plurality of second switch modules is perpendicular to the extension direction of the data line; Preferably, the plurality of sub-pixel units include a first sub-pixel unit and a second sub-pixel unit, wherein the first sub-pixel unit is connected to the first data line and the second sub-pixel unit is connected to the second data line; The first sub-pixel unit includes a first sub-pixel and a second sub-pixel arranged along the column direction, and the second sub-pixel unit includes a third sub-pixel. The first sub-pixel, the second sub-pixel, and the third sub-pixel emit different colors. Preferably, the display panel further includes a first selection signal line and a second selection signal line, and the second switch module includes a third switch unit and a fourth switch unit. The first selection signal line is connected to the control terminal of the third switch unit, and the second selection signal line is connected to the control terminal of the fourth switch unit. For the m-th second switch module, the first end of the third switch unit is connected to the second connection line, the second end of the third switch unit is connected to the first data line, the first end of the fourth switch unit is connected to the second connection line, and the second end of the fourth switch unit is connected to the second data line; For the (m+1)th second switch module, the first end of the third switch unit is connected to the third connecting line, the second end of the third switch unit is connected to the first data line, the first end of the fourth switch unit is connected to the third connecting line, and the second end of the fourth switch unit is connected to the second data line; Preferably, the third switching unit includes a third transistor, the fourth switching unit includes a fourth transistor, the gate of the third transistor is connected to the first selection signal line, the gate of the fourth transistor is connected to the second selection signal line, the first terminal of the third transistor and the first terminal of the fourth transistor are connected together as the first terminal of the second switching module, the second terminal of the third transistor is connected to the first data line, and the second terminal of the fourth transistor is connected to the second data line.

8. The display panel according to claim 3, characterized in that, The display panel includes a display area and a non-display area, and the sub-pixel unit is disposed in the display area; the first connecting line, the second connecting line and the third connecting line are all located in the non-display area; Preferably, the non-display area further includes a fan-out area, and the first connecting line is located in the fan-out area; The first switch module is located between the fan-out area and the display area; Preferably, the second connecting line and the third connecting line are arranged on the same layer.

9. The display panel according to claim 1, characterized in that, The display panel also includes a driver chip, which is electrically connected to the data line via the first connection line and the first switch module.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

Images