Pixel Circuit, Driving Method Thereof, Display Substrate, and Display Device

Abstract

The present disclosure provides a pixel circuit, a driving method thereof, a display substrate, and a display device. The pixel circuit includes: a first transistor for providing a driving current to a light-emitting element; a reset circuit for providing a reset voltage to a control electrode of the first transistor; a threshold compensation circuit for compensating a threshold voltage of the first transistor to the control electrode of the first transistor; a first light-emitting control circuit for controlling on / off between a first pole of the first transistor and a power supply terminal; a second light-emitting control circuit for controlling on / off between a second pole of the first transistor and the light-emitting element; and a data writing circuit for superimposing a voltage variation amount on a control electrode voltage of the first transistor according to a data voltage.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a pixel circuit, a driving method thereof, a display substrate, and a display device. Background Art

[0002] This section aims to provide background or context for the embodiments described in the claims. The description herein is not admitted to be prior art merely by virtue of being included in this section.

[0003] In a display panel, the drift and uneven distribution of the threshold voltage of the transistors in the pixel circuit will have a great impact on the driving current of the pixel circuit, and further result in poor uniformity and stability of the emission brightness of the light-emitting elements. Summary of the Invention

[0004] The present disclosure provides a pixel circuit, a driving method thereof, a display substrate, and a display device.

[0005] The present disclosure adopts the following technical solutions: A pixel circuit includes:

[0006] A first transistor for providing a driving current to a light-emitting element;

[0007] A reset circuit for providing a reset voltage to the control electrode of the first transistor;

[0008] A threshold compensation circuit for compensating the threshold voltage of the first transistor to the control electrode of the first transistor;

[0009] A first light-emitting control circuit for controlling the on / off between the first pole of the first transistor and the power supply terminal;

[0010] A second light-emitting control circuit for controlling the on / off between the second pole of the first transistor and the light-emitting element;

[0011] A data writing circuit for superimposing a voltage variation amount on the control electrode voltage of the first transistor according to a data voltage.

[0012] In some embodiments, the data writing circuit includes a second transistor, a third transistor, a ninth transistor, a first capacitor, a second capacitor, and a third capacitor;

[0013] The control electrode of the second transistor receives a fourth control signal, the first pole of the second transistor receives the data voltage, and the second pole of the second transistor is connected to the first end of the first capacitor;

[0014] The control electrode of the third transistor receives a fifth control signal, the first pole of the third transistor is connected to the power supply terminal, and the second pole of the third transistor is connected to the first end of the first capacitor;

[0015] The control electrode of the ninth transistor receives a sixth control signal. The first electrode of the ninth transistor is connected to the second end of the first capacitor and the first electrode of the first transistor. The second electrode of the ninth transistor is connected to the first end of the second capacitor;

[0016] The second end of the second capacitor is connected to the control electrode of the first transistor and the first end of the third capacitor;

[0017] The second end of the third capacitor receives a fixed voltage.

[0018] In some embodiments, the second end of the third capacitor is connected to the power supply terminal to receive a fixed voltage.

[0019] In some embodiments, the second light-emitting control circuit includes a sixth transistor. The control electrode of the sixth transistor receives a second light-emitting control signal. The first electrode of the sixth transistor is connected to the second electrode of the first transistor. The second electrode of the sixth transistor is connected to the light-emitting element.

[0020] In some embodiments, the first light-emitting control circuit includes a fifth transistor. The control electrode of the fifth transistor receives a first light-emitting control signal. The first electrode of the fifth transistor is connected to the power supply terminal. The second electrode of the fifth transistor is connected to the first electrode of the first transistor;

[0021] The threshold compensation circuit includes a seventh transistor. The control electrode of the seventh transistor receives a third control signal. The first electrode of the seventh transistor is connected to the second electrode of the first transistor. The second electrode of the seventh transistor is connected to the control electrode of the first transistor.

[0022] In some embodiments, the data writing circuit includes a second capacitor, a second transistor, and a third transistor;

[0023] The first end of the second capacitor is connected to the control electrode of the first transistor. The second end of the second capacitor is connected to the first electrode of the second transistor and the first electrode of the third transistor;

[0024] The control electrode of the second transistor receives a first control signal. The second electrode of the second transistor receives the data voltage;

[0025] The control electrode of the third transistor receives the third control signal. The second electrode of the third transistor is connected to the power supply terminal.

[0026] In some embodiments, the first light-emitting control circuit includes a fifth transistor. The control electrode of the fifth transistor receives a first light-emitting control signal. The first electrode of the fifth transistor is connected to the power supply terminal, and the second electrode of the fifth transistor is connected to the first electrode of the first transistor.

[0027] The threshold compensation circuit includes a seventh transistor. The control electrode of the seventh transistor receives a third control signal. The first electrode of the seventh transistor is connected to the second electrode of the first transistor, and the second electrode of the seventh transistor is connected to the control electrode of the first transistor.

[0028] The second light-emitting control circuit includes a sixth transistor. The control electrode of the sixth transistor receives a second light-emitting control signal, and the second electrode of the sixth transistor is connected to the light-emitting element.

[0029] In some embodiments, the data writing circuit further includes a first capacitor. The first end of the first capacitor receives a fixed voltage, and the second end of the first capacitor is connected to the control electrode of the first transistor.

[0030] In some embodiments, the reset circuit includes a fourth transistor. The control electrode of the fourth transistor receives a second control signal. The first electrode of the fourth transistor receives the reset voltage, and the second electrode of the fourth transistor is connected to the control electrode of the first transistor.

[0031] In some embodiments, the reset circuit includes a fourth transistor and an eighth transistor;

[0032] The control electrode of the fourth transistor receives a second control signal. The first electrode of the fourth transistor receives the reset voltage, and the second electrode of the fourth transistor is connected to the control electrode of the first transistor;

[0033] The control electrode of the eighth transistor receives a second control signal. The first electrode of the eighth transistor receives the reset voltage, and the second electrode of the eighth transistor is connected to the second electrode of the sixth transistor.

[0034] In some embodiments, the fixed voltage received by the first end of the first capacitor is the reset voltage, or the first end of the first capacitor is connected to a power supply terminal to receive a fixed voltage.

[0035] In some embodiments, the data writing circuit is specifically configured to superimpose a voltage variation on the control electrode voltage of the first transistor in a capacitive coupling manner.

[0036] The present disclosure adopts the following technical solution: a display substrate including the foregoing pixel circuit.

[0037] The present disclosure adopts the following technical solution: a display device including the foregoing display substrate.

[0038] The present disclosure adopts the following technical solutions: A driving method for a pixel circuit as described above, comprising:

[0039] In the reset stage, setting the control gate voltage of the first transistor to a reset voltage;

[0040] In the threshold compensation stage, the first light emission control circuit and the threshold compensation circuit set the control gate voltage of the first transistor to the sum of the power supply voltage of the power supply terminal and the threshold voltage of the first transistor, obtaining the threshold compensation gate voltage of the first transistor;

[0041] In the data writing stage, the data writing circuit superimposes the voltage change amount on the threshold compensation gate voltage of the first transistor, obtaining the light emission control voltage of the first transistor;

[0042] In the light emission stage, the first light emission control circuit and the second light emission control circuit control the first pole of the first transistor to conduct with the power supply terminal, and the second pole of the first transistor to conduct with the light emitting element, so that the first transistor drives the light emitting element to emit light. Description of the Drawings

[0043] Figure 1 is a block diagram of the pixel circuit according to an embodiment of the present disclosure.

[0044] Figure 2 is a circuit diagram of the pixel circuit according to some embodiments of the present disclosure.

[0045] Figure 3 is Figure 2 the driving timing diagram of the pixel circuit shown.

[0046] Figure 4a is Figure 2 the state diagram of the pixel circuit shown in the reset stage.

[0047] Figure 4b is Figure 2 the state diagram of the pixel circuit shown in the threshold compensation stage.

[0048] Figure 4c is Figure 2 the state diagram of the pixel circuit shown in the data writing stage.

[0049] Figure 4d is Figure 2 the state diagram of the pixel circuit shown in the light emission stage.

[0050] Figure 5 is a circuit diagram of the pixel circuit according to other embodiments of the present disclosure.

[0051] Figure 6 isFigure 5 The driving timing diagram of the pixel circuit shown.

[0052] Figure 7a is Figure 5 The state diagram of the pixel circuit shown in the reset stage.

[0053] Figure 7b is Figure 5 The state diagram of the pixel circuit shown in the threshold compensation stage.

[0054] Figure 7c is Figure 5 The state diagram of the pixel circuit shown in the data writing stage.

[0055] Figure 7d is Figure 5 The state diagram of the pixel circuit shown in the light emitting stage.

[0056] Figure 8 It is the circuit diagram of the pixel circuit of some other embodiments of the present disclosure.

[0057] Figure 9 It is the circuit diagram of the pixel circuit of some other embodiments of the present disclosure.

[0058] Wherein the reference numerals are: 1. Threshold compensation circuit; 2. First light emission control circuit; 3. Second light emission control circuit; 4. Data writing circuit; 5. Reset circuit; M1. First transistor; M2. Second transistor; M3. Third transistor; M4. Fourth transistor; M5. Fifth transistor; M6. Sixth transistor; M7. Seventh transistor; C1. First capacitor; C2. Second capacitor; C3. Third capacitor; VDD. Power supply terminal; VSS. Power supply terminal; Vini. Reset voltage; Vdata. Data voltage; N1. First node; N2. Second node; N3. Third node; En1. First light emission control signal; En2. Second light emission control signal; S1n. First control signal; S2n. Second control signal; S3n. Third control signal; S4n. Fourth control signal; S5n. Fifth control signal; S6n. Sixth control signal. Detailed implementation manners

[0059] The present disclosure will be further described below in conjunction with the embodiments shown in the drawings.

[0060] Figure 1 It is the block diagram of the pixel circuit of the embodiment of the present disclosure. Referring to Figure 1 , the embodiment of the present disclosure provides a pixel circuit, including: a first transistor M1 for providing a driving current to a light emitting element D;

[0061] A reset circuit 5 for providing a reset voltage to the control electrode of the first transistor M1;

[0062] A threshold compensation circuit 1 for compensating the threshold voltage of the first transistor M1 to the control electrode of the first transistor M1;

[0063] A first light-emitting control circuit 2 for controlling the on / off between the first electrode of the first transistor M1 and the power supply terminal VDD;

[0064] A second light-emitting control circuit 3 for controlling the on / off between the second electrode of the first transistor M1 and the light-emitting element D;

[0065] A data writing circuit 4 for superimposing a voltage variation amount on the control electrode voltage of the first transistor M1 according to the data voltage Vdata.

[0066] A reset circuit 5 sets the control electrode voltage of the first transistor M1 to an effective reset voltage, which causes the first transistor M1 to conduct.

[0067] Specifically, the threshold compensation circuit 1 is used to set the control electrode voltage of the first transistor M1 to the sum of a fixed voltage value and the threshold voltage V of the first transistor M1 to obtain the threshold compensation gate voltage of the first transistor M1. The threshold compensation voltage contains the threshold voltage information of the first transistor M1. th The data writing circuit 4 then superimposes a voltage variation amount on the control electrode voltage (i.e., the threshold compensation voltage) of the first transistor M1 according to the data voltage Vdata. At this time, the control electrode voltage of the first transistor M1 contains both the information of its threshold voltage and the information of the data voltage Vdata, and the two pieces of information are independent of each other.

[0068] Specifically, the data writing circuit 4 superimposes a voltage variation amount on the control electrode voltage of the first transistor M1 according to the data voltage Vdata in a capacitive coupling manner.

[0069] The first electrode of the first transistor M1 is its source electrode, for example, receiving the power supply voltage provided by the power supply terminal VDD. The current of the transistor in the saturation region is: I = k(V

[0070] - V gs - V th ) 2 , where I is the current of the transistor, k is a coefficient, V gs is the gate-source voltage difference of the transistor, and V th is the threshold voltage. The source electrode voltage of the transistor is a fixed value. The information of the threshold voltage in the control electrode voltage in this current formula is removed, and only the information of the data voltage is retained, so that the saturation region current of the transistor is regulated by the data voltage and is independent of the threshold voltage of the transistor.

[0071] Specifically, the light-emitting element D includes: an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro light-emitting diode (Micro-LED), etc.

[0072] Figure 2 is a circuit diagram of a pixel circuit according to some embodiments of the present disclosure. Figure 3 is Figure 2 the driving timing diagram of the pixel circuit shown. Figure 4a is Figure 2 the state diagram of the pixel circuit shown in the reset stage. Figure 4b is Figure 2 the state diagram of the pixel circuit shown in the threshold compensation stage. Figure 4c is Figure 2 the state diagram of the pixel circuit shown in the data writing stage. Figure 4d is Figure 2 the state diagram of the pixel circuit shown in the light-emitting stage.

[0073] In some embodiments, referring to Figure 2 , the data writing circuit 4 includes a second transistor M2, a third transistor M3, a ninth transistor M9, a first capacitor C1, a second capacitor C2, and a third capacitor C3;

[0074] The control electrode of the second transistor M2 receives a fourth control signal S4n, the first electrode of the second transistor M2 receives the data voltage Vdata, and the second electrode of the second transistor M2 is connected to the first end of the first capacitor C1;

[0075] The control electrode of the third transistor M3 receives a fifth control signal S5n, the first electrode of the third transistor M3 is connected to the power supply terminal VDD, and the second electrode of the third transistor M3 is connected to the first end of the first capacitor C1;

[0076] The control electrode of the ninth transistor M9 receives a sixth control signal S6n, the first electrode of the ninth transistor M9 is connected to the second end of the first capacitor C1 and the first electrode of the first transistor M1, and the second electrode of the ninth transistor M9 is connected to the first end of the second capacitor C2;

[0077] The second end of the second capacitor C2 is connected to the control electrode of the first transistor M1 and the first end of the third capacitor C3;

[0078] The second end of the third capacitor C3 receives a fixed voltage.

[0079] When the ninth transistor M9 is turned on, the voltage fluctuation at the third node N3 (the connection node of the third transistor M3, the second transistor M2, and the first capacitor C1) will be coupled to the first node N1 (connected to the control electrode of the first transistor M1).

[0080] Specifically, when the third transistor M3 is turned on and the second transistor M2 is turned off, the voltage of the third node N3 is the voltage of the power supply terminal VDD. When the third transistor M3 is turned off and the second transistor M2 is turned on, the voltage of the third node N3 is the data voltage Vdata. The variation of the voltage of the third node N3 contains the information of the data voltage Vdata, so that the variation of the voltage of the first node N1 contains the information of the data voltage Vdata.

[0081] In some embodiments, referring to Figure 2 , the second end of the third capacitor C3 is connected to the power supply terminal VDD to receive a fixed voltage.

[0082] In other embodiments, in combination with Figure 2 , the second end of the third capacitor C3 is connected to the power supply terminal VSS. The power supply terminal VSS is, for example, a ground terminal.

[0083] The second end of the third capacitor C3 receives a fixed voltage, and its function is to keep the voltage of the first node N1 stable. If the third capacitor C3 is removed, the first end of the second capacitor C2 is floating in some periods, which is likely to cause fluctuations in the voltage of the first node N1.

[0084] In some embodiments, referring to Figure 2 , the second light-emitting control circuit 3 includes a sixth transistor M6. The control electrode of the sixth transistor M6 receives a second light-emitting control signal En2. The first electrode of the sixth transistor M6 is connected to the second electrode of the first transistor M1, and the second electrode of the sixth transistor M2 is connected to the light-emitting element D.

[0085] In some embodiments, referring to Figure 2 , the pixel circuit further includes a reset circuit 5 for setting the control electrode voltage of the first transistor M1 to a reset voltage Vini and setting the voltage of the connection node between the light-emitting element D and the second light-emitting control circuit 3 to the reset voltage Vini.

[0086] Specifically, the reset circuit 5 includes: a fourth transistor M4 and an eighth transistor M8;

[0087] The control electrode of the fourth transistor M4 receives a second control signal S2n. The first electrode of the fourth transistor M4 receives the reset voltage Vini. The second electrode of the fourth transistor M4 is connected to the control electrode of the first transistor M1 (i.e., connected to the first node N1);

[0088] The control electrode of the eighth transistor M8 receives a second control signal S2n, the first electrode of the eighth transistor M8 receives the reset voltage Vini, and the second electrode of the eighth transistor M8 is connected to the second electrode of the sixth transistor M6 (i.e., connected to the light-emitting element D).

[0089] When the fourth transistor M4 is turned on, the voltage of the first node N1 can be reset to the reset voltage Vini. When the eighth transistor M8 is turned on, the voltage of one end of the light-emitting element D can be reset to the reset voltage Vini.

[0090] Figure 2 In the illustrated embodiment, the reset voltage Vini is a low-level voltage so that the light-emitting element D does not emit light and the control electrode voltage of the first transistor M1 is an effective voltage.

[0091] In some embodiments, referring to Figure 2 , the first light-emitting control circuit 2 includes a fifth transistor M5. The control electrode of the fifth transistor M5 receives a first light-emitting control signal En1. The first electrode of the fifth transistor M5 is connected to the power supply terminal VDD, and the second electrode of the fifth transistor M5 is connected to the first electrode of the first transistor M1;

[0092] The threshold compensation circuit 1 includes a seventh transistor M7. The control electrode of the seventh transistor M7 receives a third control signal S3n. The first electrode of the seventh transistor M7 is connected to the second electrode of the first transistor M1, and the second electrode of the seventh transistor M7 is connected to the control electrode of the first transistor M1.

[0093] The threshold compensation circuit 1 and the first light-emitting control circuit 2 cooperate to perform threshold compensation on the control electrode voltage of the first transistor M1.

[0094] The following combines Figure 3 and Figures 4a to 4b to introduce the driving method of this pixel circuit. Since each transistor in the pixel circuit is a P-type field-effect transistor, the voltage of its control electrode (also called the gate) is effective at a low level.

[0095] Referring to Figure 3 and Figure 4a , in the reset stage t1, the reset module 5 sets the control electrode voltage of the first transistor M1 and the voltage of the connection node between the light-emitting element D and the second light-emitting control circuit 3 to the reset voltage Vini.

[0096] Specifically, when the first control signal S1n is valid, the fourth transistor M4 is turned on. When the second control signal S2n is valid, the eighth transistor M8 is turned on. The remaining control signals are invalid, and the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the ninth transistor M9 are turned off. The voltage of the first node N1 is set to the reset voltage Vini, and the anode voltage of the light-emitting element D is set to the reset voltage Vini.

[0097] In this embodiment, the reset voltage Vini is a low-level voltage, which enables the control electrode voltage of the first transistor M1 (specifically, it can also be a P-type thin-film transistor) to be valid, and makes the light-emitting element D in a non-light-emitting state.

[0098] In the threshold compensation stage t2, the first light-emitting control circuit 2 and the threshold compensation circuit 1 set the control electrode voltage of the control electrode of the first transistor M1 to the sum of the power supply voltage of the power supply terminal VDD and the threshold voltage of the first transistor M1, so as to obtain the threshold compensation gate voltage of the control electrode of the first transistor M1.

[0099] Reference Figure 3 and Figure 4b , in the threshold compensation stage t2, the second control signal S2n is valid, the eighth transistor M8 is turned on, and the anode voltage of the light-emitting element D continues to be maintained at the reset voltage Vini. The light-emitting element D remains in a non-light-emitting state. The third control signal S3n is valid, and the seventh transistor M7 is turned on. The fifth control signal S5n is valid, and the fifth transistor M5 is turned on. At the initial moment of the threshold compensation stage, the voltage of the first node N1 is the reset voltage Vini, the first transistor M1 is turned on, and the power supply terminal VDD charges the voltage of the first node N1 in sequence through the fifth transistor M5, the first transistor M1, and the seventh transistor M7. When the voltage of the first node N1 rises to the sum of the power supply voltage of the power supply terminal VDD and its threshold voltage V th (usually a negative value), the first transistor M1 is turned off. At this time, the voltage VN1 of the first node N1 is called the threshold compensation voltage, and its calculation formula is: VN1 = VDD + V th .

[0100] In the data writing stage t3, the data writing circuit 4 superimposes the voltage change amount on the threshold compensation gate voltage of the control electrode of the first transistor M1 to obtain the light-emitting control voltage of the control electrode of the first transistor M1.

[0101] Reference Figure 3 and Figure 4c, during the data writing stage t3, the second control signal S2n is valid, the eighth transistor M8 is turned on, and the anode voltage of the light-emitting element D is maintained at the reset voltage Vini. The fourth control signal S4n is valid, and the second transistor M2 is turned on. The sixth control signal S5n is valid, and the ninth transistor M9 is turned on. The first control signal S1n is invalid, and the fourth transistor is turned off. The third control signal S3n is invalid, and the seventh transistor is turned off. The fifth control signal S5n is invalid, and the third transistor M3 is turned off. The first light-emitting control signal En1 is invalid, and the fifth transistor M5 is turned off. The second light-emitting control signal En2 is invalid, and the sixth transistor M6 is turned off.

[0102] During the threshold compensation stage t2, the voltage of the third node N3 is the supply voltage of the power supply terminal VDD. During the data writing stage t3, the voltage of the third node N3 jumps to the data voltage Vdata. The voltage jump amount of the third node N3 is Vdata - VDD, and this voltage jump amount is coupled to the first node N1 through the first capacitor C1 and the second capacitor C2. That is, a voltage change amount is superimposed on the threshold compensation voltage of the control electrode of the first transistor M1. This voltage change amount contains the information of the data voltage Vdata. The voltage VN1 of the control electrode of the first transistor M1 in this stage is the light-emitting control voltage, and its calculation formula is:

[0103] VN1 = VDD + V th +(Vdata - VDD)*(C1C2 / (C1C2 + C1C3 + C2C3)).

[0104] During the light-emitting stage t4, the first light-emitting control circuit 2 and the second light-emitting control circuit 3 control the first pole of the first transistor M1 to be conducted with the power supply terminal VDD, and the second pole of the first transistor M1 is conducted with the light-emitting element D, so that the first transistor M1 drives the light-emitting element D to emit light.

[0105] Reference Figure 3 and Figure 4d , during this stage, the first light-emitting control signal En1 is valid, and the fifth transistor M5 is turned on. The second light-emitting control signal En2 is valid, and the sixth transistor M6 is turned on. The first control signal S1n is invalid, and the fourth transistor M4 is turned off. The second control signal S2 is invalid, and the eighth transistor M8 is turned off. The third control signal S3n is invalid, and the seventh transistor M7 is turned off. The fourth control signal S4n is invalid, and the second transistor M2 is turned off. The fifth control signal S5n is invalid, and the third transistor M3 is turned off. The sixth control signal S6n is invalid, and the ninth transistor M9 is turned off.

[0106] The source voltage of the first transistor M1 is the supply voltage of the power supply terminal VDD, and the calculation formula of the gate-source voltage difference Vgs is as follows:

[0107] Vgs = VN1 - VN2 = VDD + Vth +(Vdata - VDD)(C1C2 / (C1C2 + C1C3 + C2C3)) - VDD =

[0108] (Vdata - VDD)(C1C2 / (C1C2 + C1C3 + C2C3)) + V th ;

[0109] Wherein, VN1 is the voltage of the first node N1, VN2 is the voltage of the second node N2, VDD is the power supply voltage of the power supply terminal VDD, C1 is the capacitance value of the first capacitor C1, C2 is the capacitance value of the second capacitor C2, C3 is the capacitance value of the third capacitor C3, and V th is the threshold voltage of the first transistor M1.

[0110] The source-drain current I DS of the first transistor M1 is calculated as follows:

[0111]

[0112] Wherein, μ is the carrier mobility of the channel inversion layer, C ox is the gate capacitance per unit area, W is the channel width, L is the channel length, Vdata is the data voltage, VDD is the power supply voltage of the power supply terminal VDD, C1 is the capacitance value of the first capacitor C1, C2 is the capacitance value of the second capacitor C2, and C3 is the capacitance value of the third capacitor C3.

[0113] The current flowing through the light-emitting element D circuit is related to the data voltage Vdata and is th independent of the threshold voltage V

[0114] Figure 5 is the circuit diagram of the pixel circuit in some other embodiments of the present disclosure. Figure 6 is Figure 5 the driving timing diagram of the pixel circuit shown. Figure 7a is Figure 5 the state diagram of the pixel circuit shown in the reset stage. Figure 7b is Figure 5 the state diagram of the pixel circuit shown in the threshold compensation stage. Figure 7c is Figure 5 the state diagram of the pixel circuit shown in the data writing stage. Figure 7d is Figure 5 the state diagram of the pixel circuit shown in the light-emitting stage.

[0115] In some embodiments, referring to Figure 5 , the data writing circuit 4 includes a first capacitor C1, a second capacitor C2, a second transistor M2, and a third transistor M3;

[0116] The first end of the first capacitor C1 receives a fixed voltage, and the second end of the first capacitor C1 is connected to the control electrode of the first transistor M1;

[0117] The first end of the second capacitor C2 is connected to the control electrode of the first transistor M1, and the second end of the second capacitor C2 is connected to the first pole of the second transistor M2 and the first pole of the third transistor M3;

[0118] The control electrode of the second transistor M2 receives a first control signal, and the second pole of the second transistor M2 receives the data voltage Vdata;

[0119] The control electrode of the third transistor M3 receives the third control signal S3n, and the second pole of the third transistor M3 is connected to the power supply terminal VDD.

[0120] When the third transistor M3 is turned on and the second transistor M2 is turned off, the voltage of the second node N2 (the connection node of the second capacitor C2, the second transistor M2, and the third transistor M3) is the power supply voltage of the power supply terminal VDD. When the third transistor M3 is turned off and the second transistor M2 is turned on, the voltage of the second node N2 jumps to the data voltage Vdata (ignoring the source-drain voltage difference of the second transistor M2). The jump of the voltage of the second node N2 will cause the voltage of the first node N1 (connected to the control electrode of the first transistor M1) to jump, and the jump amount is related to the data voltage Vdata. This makes the voltage value of the first node N1 contain the information of the data voltage Vdata.

[0121] The function of the first capacitor C1 is to maintain the stability of the voltage of the first node N1 and avoid the first node being floatingly set in some periods.

[0122] In some embodiments, referring to Figure 5 , the first light-emitting control circuit 2 includes a fifth transistor M5. The control electrode of the fifth transistor M5 receives a first light-emitting control signal En1. The first pole of the fifth transistor M5 is connected to the power supply terminal VDD, and the second pole of the fifth transistor M5 is connected to the first pole of the first transistor M1;

[0123] The threshold compensation circuit 1 includes a seventh transistor M7. The control electrode of the seventh transistor M7 receives the third control signal S3n. The first pole of the seventh transistor M7 is connected to the second pole of the first transistor M1, and the second pole of the seventh transistor M7 is connected to the control electrode of the first transistor M1;

[0124] The second light-emitting control circuit 3 includes a sixth transistor M6. The control electrode of the sixth transistor M6 receives a second light-emitting control signal En2, and the second pole of the sixth transistor M6 is connected to the light-emitting element D.

[0125] In some embodiments, the pixel circuit further includes a reset circuit 5 for setting the voltage of the first transistor M1 to a reset voltage Vini.

[0126] Specifically, the control electrode of the fourth transistor M4 receives a second control signal S2n, the first electrode of the fourth transistor M4 receives the reset voltage Vini, and the second electrode of the fourth transistor M4 is connected to the control electrode of the first transistor M1.

[0127] It should be noted that Figure 2 and Figure 5 the reset circuit 5 in

[0128] In some embodiments, referring to Figure 5 , the fixed voltage received by the first end of the first capacitor C1 is the reset voltage. In some other embodiments, referring to Figure 8 , the first end of the first capacitor C1 is connected to the power supply terminal VDD. In some other embodiments, the first end of the first capacitor C1 is connected to the power supply terminal VSS. In some other embodiments, the first end of the first capacitor C1 receives other fixed voltages.

[0129] The following combines Figure 6 and Figures 7a to 7b to introduce Figure 5 the driving process of the pixel circuit shown in

[0130] In the reset stage t1, the reset circuit 5 sets the control electrode voltage of the first transistor M1 to the reset voltage Vini. In Figure 5 the embodiment shown, the reset voltage Vini is a low-level voltage.

[0131] Combining Figure 6 and Figure 7a , the second control signal S2n is valid, the fourth transistor M4 is turned on, and the voltages across both ends of the first capacitor C1 and the control electrode of the first transistor M1 are both set to the reset voltage Vini. The first control signal S1n is invalid, and the second transistor M2 is turned off. The third control signal S3n is invalid, and the third transistor M3 and the seventh transistor M7 are both turned off. The first light emission control signal En1 is invalid, and the fifth transistor M5 is turned off. The second light emission control signal En2 is invalid, and the sixth transistor is turned off.

[0132] In the threshold compensation stage t2, the first light emission control circuit 2 and the threshold compensation circuit 1 set the control electrode voltage of the first transistor M1 to the sum of the power supply voltage of the power supply terminal VDD and the threshold voltage of the first transistor, obtaining the threshold compensation gate voltage of the first transistor M1.

[0133] Combining Figure 6 and Figure 7b, the third control signal S3n is valid, the third transistor M3 is turned on, the seventh transistor M7 is turned on, and the voltage of the second node N2 is set to the supply voltage of the power supply terminal VDD. The first light emission control signal En1 is valid, and the fifth transistor M5 is turned on. The power supply terminal VDD charges the control electrode of the first transistor M1 through the fifth transistor M5 and the seventh transistor M7. The control electrode voltage VN1 of the first transistor M1 when the charging stops is denoted as the threshold compensation voltage of the first transistor M1, and satisfies: VN1 = VDD + V th .

[0134] In the data writing stage t3, the data writing circuit 4 superimposes the voltage change amount on the threshold compensation gate voltage of the first transistor M1 to obtain the light emission control voltage of the first transistor M1.

[0135] Combined Figure 6 and Figure 7c , the first control signal S1n is valid, the second transistor M2 is turned on, and the voltage of the second node N2 is changed from the supply voltage of the power supply terminal VDD to the data voltage Vdata. The second control signal S2n is invalid, and the fourth transistor M4 is turned off. The third control signal S3n is invalid, and the third transistor M3 and the seventh transistor M7 are invalid. The first light emission control signal En1 is invalid, and the fifth transistor M5 is turned off. The second light emission control signal En2 is invalid, and the sixth transistor M6 is turned off.

[0136] The voltage jump amount of the second node N2 is coupled to the first node N1. At this time, the voltage VN1 of the first node N1 is its light emission control voltage, and the calculation formula is:

[0137] VN1 = VDD + V th +(C2 / (C1 + C2)(Vdata - VDD).

[0138] In the light emission stage t4, the first light emission control circuit 2 and the second light emission control circuit 3 control the first pole of the first transistor M1 to be turned on with the power supply terminal VDD, and the second pole of the first transistor M1 to be turned on with the light emitting element D, so that the first transistor M1 drives the light emitting element D to emit light.

[0139] In the light emission stage t4, the first pole of the first transistor M1 is specifically its source electrode, and the source electrode voltage is the voltage VDD. The gate-source voltage difference V gs of the first transistor M1 is:

[0140] Vgs = VN1 - VN3 = V th +((C2 / (C1 + C2))(Vdata - VDD);

[0141] Among them, VN1 is the voltage of the first node N1, VN3 is the voltage of the dot node N3, Vdata is the data voltage, VDD is the power supply voltage, C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0142] The current I of the first transistor M1 DS is:

[0143]

[0144] Among them, μ is the carrier mobility, C ox is the gate capacitance per unit area, W is the channel width, L is the channel length, Vdata is the data voltage, VDD is the power supply voltage, C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0145] The current I DS 's calculation formula is applicable to Figure 5 the embodiment shown and Figure 8 the embodiment shown.

[0146] In the light-emitting stage t4, the current flowing through the light-emitting element D is independent of the threshold voltage of the first transistor M1 and is related to the data voltage.

[0147] Continue to refer to Figure 6 and in combination with Figure 5 , in the transition period from the reset stage t1 to the threshold compensation stage t2, the second control signal S2n first jumps to the invalid voltage, and the fourth transistor M4 first turns off. Subsequently, the first light-emitting control signal En1 jumps to the effective voltage, and the fifth transistor M5 turns on. Subsequently, the third control signal S3n jumps to the effective voltage, and the seventh transistor M7 and the third transistor M3 turn on.

[0148] In the transition period from the threshold compensation stage t2 to the data writing stage t3, the third control signal S3n first jumps to the invalid voltage, and the seventh transistor M7 and the third transistor M3 turn off. Subsequently, the first light-emitting control signal En1 jumps to the invalid voltage, and the fifth transistor M5 turns off. Subsequently, the first control signal S1n jumps to the effective voltage, and the second transistor M2 turns on.

[0149] In the transition period from the data writing stage t3 to the light-emitting stage t4, the first control signal S1n first jumps to the invalid voltage, and the second transistor M2 turns off. Subsequently, the first light-emitting control signal En1 and the second light-emitting control signal En2 synchronously jump to the effective voltage, and the fifth transistor M5 and the sixth transistor M6 turn on.

[0150] Continue to refer to Figure 9 , compared with the embodiment shown in Figure 5 , the first capacitor C1 is omitted. Figure 9The pixel circuit shown and Figure 5 the driving timings of the pixel circuit shown can be the same. The following, in conjunction with Figure 9 and Figure 6 introduces the driving timings of the pixel circuit.

[0151] In the reset stage t1, the reset circuit 5 sets the control - gate voltage of the first transistor M1 to the reset voltage Vini. In Figure 9 the embodiment shown, the reset voltage Vini is a low - level voltage.

[0152] In conjunction with Figure 6 and Figure 9 , the second control signal S2n is valid, the fourth transistor M4 is turned on, and the voltages across both ends of the first capacitor C1 and the control - gate voltage of the first transistor M1 are both set to the reset voltage Vini. The first control signal S1n is invalid, and the second transistor M2 is turned off. The third control signal S3n is invalid, and the third transistor M3 and the seventh transistor M7 are both turned off. The first light - emitting control signal En1 is invalid, and the fifth transistor M5 is turned off. The second light - emitting control signal En2 is invalid, and the sixth transistor is turned off.

[0153] In the threshold - compensation stage t2, the first light - emitting control circuit 2 and the threshold - compensation circuit 1 set the control - gate voltage of the first transistor M1 to the sum of the power - supply voltage of the power - supply terminal VDD and the threshold voltage of the first transistor, obtaining the threshold - compensation gate voltage of the first transistor M1.

[0154] In conjunction with Figure 6 and Figure 9 , the third control signal S3n is valid, the third transistor M3 is turned on, the seventh transistor M7 is turned on, the voltage of the second node N2 is set to the power - supply voltage of the power - supply terminal VDD. The first light - emitting control signal En1 is valid, and the fifth transistor M5 is turned on. The power - supply terminal VDD charges the control - gate of the first transistor M1 through the fifth transistor M5 and the seventh transistor M7. The control - gate voltage VN1 of the first transistor M1 when the charging stops is denoted as the threshold - compensation voltage of the first transistor M1, and satisfies: VN1 = VDD + V th .

[0155] In the data - writing stage t3, the data - writing circuit 4 superimposes the voltage change amount on the threshold - compensation gate voltage of the first transistor M1, obtaining the light - emitting control voltage of the first transistor M1.

[0156] In conjunction with Figure 6 and Figure 9, the first control signal S1n is valid, the second transistor M2 is turned on, and the voltage of the second node N2 is changed from the power supply voltage of the power supply terminal VDD to the data voltage Vdata. The second control signal S2n is invalid, and the fourth transistor M4 is turned off. The third control signal S3n is invalid, and the third transistor M3 and the seventh transistor M7 are invalid. The first light emission control signal En1 is invalid, and the fifth transistor M5 is turned off. The second light emission control signal En2 is invalid, and the sixth transistor M6 is turned off.

[0157] The voltage jump amount of the second node N2 is coupled to the first node N1. At this time, the voltage VN1 of the first node N1 is its light emission control voltage, and the calculation formula is:

[0158] VN1 = VDD + V th + Vdata - VDD.

[0159] In the light emission stage t4, the first light emission control circuit 2 and the second light emission control circuit 3 control the first pole of the first transistor M1 to be conducted with the power supply terminal VDD, and the second pole of the first transistor M1 is conducted with the light emitting element D, so that the first transistor M1 drives the light emitting element D to emit light.

[0160] In the light emission stage t4, the first pole of the first transistor M1 is specifically its source electrode, and the source electrode voltage is the voltage VDD. The gate-source voltage difference V gs is:

[0161] Vgs = VN1 - VN3 = V th + Vdata - VDD;

[0162] wherein, VN1 is the voltage of the first node N1, VN3 is the voltage of the dot node N3, Vdata is the data voltage, and VDD is the power supply voltage.

[0163] The current I of the first transistor M1 DS is:

[0164]

[0165] wherein, μ is the carrier mobility, C ox is the gate capacitance per unit area, W is the channel width, L is the channel length, Vdata is the data voltage, and VDD is the power supply voltage.

[0166] The current I DS The calculation formula of Figure 5 is applicable to the embodiments shown in Figure 8 and the embodiments shown in

[0167] In the light emission stage t4, the current flowing through the light emitting element D has nothing to do with the threshold voltage of the first transistor M1 and is related to the data voltage.

[0168] Comparison Figure 5 With Figure 9 In the illustrated embodiment, the smaller the capacitance value of the first capacitor C1 (the limit case is 0), the greater the influence of the fluctuation of the data voltage Vdata on the current value of the first transistor M1 during the light-emitting stage. The larger the capacitance value of the first capacitor C1, the smaller the influence of the fluctuation of the data voltage Vdata on the current value of the first transistor M1 during the light-emitting stage, but the stability of the voltage of the first node N1 is stronger.

[0169] Based on the same inventive concept, an embodiment of the present disclosure further provides a display substrate, including the foregoing pixel circuit.

[0170] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, including the foregoing display substrate.

[0171] The display device includes, for example: a display panel, a display module, a mobile phone, a tablet computer, a navigator, an in-vehicle interaction terminal, a billboard, a television, a monitor, and any other product or component with a display function.

[0172] The display type of the display device includes, for example: organic light-emitting diode (OLED) display, quantum dot light-emitting diode (QLED) display, micro light-emitting diode (Micro-LED) display, etc.

[0173] Each embodiment in the present disclosure is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the key point of each embodiment is to illustrate the differences from other embodiments.

[0174] The protection scope of the present disclosure is not limited to the above embodiments. Obviously, those skilled in the art can make various changes and deformations to the present disclosure without departing from the scope and spirit of the present disclosure. If these changes and deformations fall within the scope of the claims of the present disclosure and their equivalent technologies, the intention of the present disclosure also includes these changes and deformations.

Claims

1. A pixel circuit, characterized in that, Comprising: A first transistor for supplying a drive current to a light-emitting element; A reset circuit for supplying a reset voltage to a control electrode of the first transistor; A threshold compensation circuit for compensating a threshold voltage of the first transistor to the control electrode of the first transistor; A first light emission control circuit for controlling conduction and cutoff between a first electrode of the first transistor and a power supply terminal; A second light emission control circuit for controlling conduction and cutoff between a second electrode of the first transistor and the light-emitting element; A data writing circuit for superimposing a voltage variation amount on a control electrode voltage of the first transistor according to a data voltage; The data writing circuit includes a second transistor, a third transistor, a ninth transistor, a first capacitor, a second capacitor, and a third capacitor; A control electrode of the second transistor receives a fourth control signal, a first electrode of the second transistor receives the data voltage, and a second electrode of the second transistor is connected to a first end of the first capacitor; A control electrode of the third transistor receives a fifth control signal, a first electrode of the third transistor is connected to the power supply terminal, and a second electrode of the third transistor is connected to the first end of the first capacitor; A control electrode of the ninth transistor receives a sixth control signal, a first electrode of the ninth transistor is connected to a second end of the first capacitor and a first electrode of the first transistor, and a second electrode of the ninth transistor is connected to a first end of the second capacitor; A second end of the second capacitor is connected to the control electrode of the first transistor and a first end of the third capacitor; A second end of the third capacitor receives a fixed voltage.

2. The pixel circuit according to claim 1, characterized in that The second end of the third capacitor is connected to the power supply terminal to receive the fixed voltage.

3. The pixel circuit according to claim 1, characterized in that, The second light emission control circuit includes a sixth transistor, a control electrode of the sixth transistor receives a second light emission control signal, a first electrode of the sixth transistor is connected to the second electrode of the first transistor, and a second electrode of the sixth transistor is connected to the light-emitting element.

4. The pixel circuit according to claim 1, wherein The first light emission control circuit includes a fifth transistor, a control electrode of the fifth transistor receives a first light emission control signal, a first electrode of the fifth transistor is connected to the power supply terminal, and a second electrode of the fifth transistor is connected to the first electrode of the first transistor; The threshold compensation circuit includes a seventh transistor, a control electrode of the seventh transistor receives a third control signal, a first electrode of the seventh transistor is connected to the second electrode of the first transistor, and a second electrode of the seventh transistor is connected to the control electrode of the first transistor.

5. The pixel circuit according to claim 4, wherein The data writing circuit includes a second capacitor, a second transistor, and a third transistor; A first end of the second capacitor is connected to the control electrode of the first transistor, and a second end of the second capacitor is connected to a first electrode of the second transistor and a first electrode of the third transistor; A control electrode of the second transistor receives a first control signal, and a second electrode of the second transistor receives the data voltage; A control electrode of the third transistor receives the third control signal, and a second electrode of the third transistor is connected to the power supply terminal.

6. The pixel circuit according to claim 5, wherein The first light-emitting control circuit includes a fifth transistor. The control electrode of the fifth transistor receives a first light-emitting control signal. The first electrode of the fifth transistor is connected to the power supply terminal, and the second electrode of the fifth transistor is connected to the first electrode of the first transistor. The threshold compensation circuit includes a seventh transistor. The control electrode of the seventh transistor receives a third control signal. The first electrode of the seventh transistor is connected to the second electrode of the first transistor, and the second electrode of the seventh transistor is connected to the control electrode of the first transistor. The second light-emitting control circuit includes a sixth transistor. The control electrode of the sixth transistor receives a second light-emitting control signal. The second electrode of the sixth transistor is connected to the light-emitting element.

7. The pixel circuit according to claim 5, characterized in that, The data writing circuit further includes a first capacitor. The first terminal of the first capacitor receives a fixed voltage, and the second terminal of the first capacitor is connected to the control electrode of the first transistor.

8. The pixel circuit according to claim 7, wherein The fixed voltage received by the first terminal of the first capacitor is the reset voltage, or the first terminal of the first capacitor is connected to a power supply terminal to receive a fixed voltage.

9. The pixel circuit according to claim 1, wherein The reset circuit includes a fourth transistor. The control electrode of the fourth transistor receives a second control signal. The first electrode of the fourth transistor receives the reset voltage, and the second electrode of the fourth transistor is connected to the control electrode of the first transistor.

10. The pixel circuit according to claim 6, wherein The reset circuit includes: a fourth transistor and an eighth transistor; The control electrode of the fourth transistor receives a second control signal. The first electrode of the fourth transistor receives the reset voltage, and the second electrode of the fourth transistor is connected to the control electrode of the first transistor. The control electrode of the eighth transistor receives a second control signal. The first electrode of the eighth transistor receives the reset voltage, and the second electrode of the eighth transistor is connected to the second electrode of the sixth transistor.

11. The pixel circuit according to claim 1, wherein The data writing circuit is specifically configured to superimpose a voltage variation on the control electrode voltage of the first transistor in a capacitive coupling manner.

12. A display substrate, characterized in that, It includes the pixel circuit according to any one of claims 1 to 11.

13. A display device, characterized in that, It includes the display substrate according to claim 12.

14. A driving method for a pixel circuit according to any one of claims 1 to 11, characterized in that, It includes: In the reset stage, the control electrode voltage of the first transistor is set to the reset voltage. In the threshold compensation stage, the first light-emitting control circuit and the threshold compensation circuit set the control electrode voltage of the first transistor to the sum of the power supply voltage of the power supply terminal and the threshold voltage of the first transistor, obtaining the threshold compensation gate voltage of the first transistor. In the data writing stage, the data writing circuit superimposes the voltage variation on the threshold compensation gate voltage of the first transistor to obtain the light-emitting control voltage of the first transistor. In the light-emitting stage, the first light-emitting control circuit and the second light-emitting control circuit control the conduction between the first electrode of the first transistor and the power supply terminal, and the conduction between the second electrode of the first transistor and the light-emitting element, so that the first transistor drives the light-emitting element to emit light.

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