Address refresh circuit, method, memory and electronic device

Abstract

The embodiment of the present disclosure discloses an address refreshing circuit, method, memory and electronic device. The address refreshing circuit comprises a selection circuit and a decoding circuit. The selection circuit is used for obtaining a strobe signal, a redundant address signal and a normal address signal, and is used for selecting one of the redundant address signal and the normal address signal as a target address signal based on the strobe signal at a first pulse time and a second pulse time. The first pulse time and the second pulse time belong to the same refreshing period, and the second pulse time is later than the first pulse time. The decoding circuit is used for decoding the target address signal to obtain and output a decoding signal. The present disclosure can save consumption and improve performance.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more particularly to an address refresh circuit, method, memory, and electronic device. Background Technology

[0002] As the capacity and speed of semiconductor memory devices, which are widely used in electronic devices, rapidly increase, the power consumption of semiconductor memory devices continues to rise.

[0003] Dynamic Random Access Memory (DRAM) is a volatile semiconductor memory device that stores data using the charge stored in capacitors. Because the charge stored in the capacitors can leak out in various ways over time, DRAM has limited data retention. To address this limited data retention, DRAM typically requires periodic refreshing to charge or discharge the capacitors based on the data stored in the DRAM.

[0004] However, the addresses that need to be refreshed include normal addresses and redundant addresses. How to refresh these two types of addresses affects the performance of DRAM. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide an address refresh circuit, method, memory, and electronic device that can refresh the address according to at least two address signals in one refresh cycle, thereby completing the unified processing of regular addresses and redundant addresses, thus saving power and improving performance.

[0006] The technical solution of this disclosure embodiment is implemented as follows:

[0007] This disclosure provides an address refresh circuit, the circuit comprising: a selection circuit and a decoding circuit; wherein...

[0008] The selection circuit is used to acquire a strobe signal, a redundant address signal, and a regular address signal, and is used to select one of the redundant address signal and the regular address signal as the target address signal based on the strobe signal during a first pulse time and a second pulse time, respectively; the first pulse time and the second pulse time belong to the same refresh cycle, and the second pulse time is later than the first pulse time;

[0009] The decoding circuit is used to decode the target address signal to obtain and output the decoded signal.

[0010] In the above scheme, the selection circuit includes:

[0011] The first selection module is used to receive the redundant address signal and the strobe signal, and if the strobe signal has a first level, it outputs the redundant address signal.

[0012] The second selection module is used to receive the conventional address signal and the strobe signal, and if the strobe signal has a second level, it outputs the conventional address signal.

[0013] In the above scheme, the first selection module includes a first AND gate and a first inverter. The first input terminal of the first AND gate is connected to the output terminal of the first inverter. The input terminal of the first inverter is used to receive the gating signal. The second input terminal of the first AND gate is used to receive the redundant address signal.

[0014] The second selection module includes a second AND gate for receiving the conventional address signal and the strobe signal;

[0015] The selection circuit further includes a third selection module; the input terminal of the third selection module is connected to the output terminal of the first AND gate and the output terminal of the second AND gate respectively, and the output terminal of the third selection module is connected to the input terminal of the decoding circuit.

[0016] In the above scheme, the third selection module includes: a NOR gate and a second inverter;

[0017] The output of the NOR gate is connected to the input of the second inverter.

[0018] The input terminal of the NOR gate serves as the input terminal of the third selection module, and the output terminal of the second inverter serves as the output terminal of the third selection module.

[0019] In the above scheme, the decoding circuit includes:

[0020] An enable module is connected to the output of the selection circuit and is used to receive an enable signal. If the enable signal is at the second level, the received target address signal is output.

[0021] A decoder, connected to the output of the enable module, is used to decode the target address signal to obtain and output the decoded signal.

[0022] In the above scheme, the enabling module includes: a NAND gate and a third inverter;

[0023] The first input terminal of the NAND gate serves as the first input terminal of the enable module, receiving the enable signal; the second input terminal of the NAND gate serves as the second input terminal of the enable module, connected to the output terminal of the selection circuit.

[0024] The output of the NAND gate is connected to the input of the third inverter.

[0025] The output of the third inverter serves as the output of the enable module and is connected to the decoder.

[0026] In the above scheme, the refresh cycle also includes: a third pulse time;

[0027] The selection circuit is further configured to, during the third pulse time, select one of the redundant address signal and the regular address signal as the target address signal based on the strobe signal.

[0028] This disclosure also provides an address refresh method, the method comprising:

[0029] Obtain the strobe signal, redundant address signal, and normal address signal respectively;

[0030] During the first pulse time and the second pulse time, based on the strobe signal, one of the redundant address signal and the regular address signal is selected as the target address signal, respectively; the first pulse time and the second pulse time belong to the same refresh cycle, and the second pulse time is later than the first pulse time;

[0031] The target address signal is decoded to obtain and output the decoded signal.

[0032] In the above scheme, decoding the target address signal to obtain and output the decoded signal includes:

[0033] If the acquired enable signal is at the second level, the target address signal is decoded to obtain and output the decoded signal.

[0034] In the above scheme, the refresh cycle further includes: a third pulse time; the method further includes:

[0035] During the third pulse time, based on the strobe signal, one of the redundant address signal and the regular address signal is selected as the target address signal.

[0036] In the above scheme, the step of selecting one of the redundant address signal and the regular address signal as the target address signal based on the strobe signal includes:

[0037] If the strobe signal has a first level, then the redundant address signal is output as the target address signal; or,

[0038] If the strobe signal has a second level, then the regular address signal is output as the target address signal.

[0039] In the above scheme, the first level represents logic 0; the step of outputting the redundant address signal as the target address signal if the strobe signal has the first level includes:

[0040] The first level of the strobe signal is inverted and ANDed with the redundant address signal to obtain a first intermediate signal that represents the redundant address signal;

[0041] Perform an AND operation between the first level of the strobe signal and the conventional address signal to obtain a second intermediate signal set to the first level;

[0042] The target address signal, which is characterized as the redundant address signal, is obtained by performing an OR operation on the first intermediate signal and the second intermediate signal set to the first level.

[0043] In the above scheme, the second level represents logic 1; the step of outputting the conventional address signal as the target address signal if the strobe signal has the second level includes:

[0044] The second level of the strobe signal is inverted and ANDed with the redundant address signal to obtain a first intermediate signal set to the first level;

[0045] A bitwise AND operation is performed between the second level of the strobe signal and the conventional address signal to obtain a second intermediate signal that represents the conventional address signal.

[0046] The first intermediate signal, which is set to a first level, and the second intermediate signal, which represents the conventional address signal, are subjected to an OR operation to obtain the target address signal, which represents the conventional address signal.

[0047] In the above scheme, the second level represents logic 1; the step of decoding the target address signal to obtain and output the decoded signal if the acquired enable signal is the second level includes:

[0048] Perform an AND operation on the target address signal and the acquired enable signal. If the enable signal is at the second level, then output the target address signal to the decoder.

[0049] The decoder decodes the target address signal to obtain and output the decoded signal.

[0050] This disclosure also provides a memory, which includes the address refresh circuit described above.

[0051] In the above scheme, the memory includes at least: dynamic random access memory (DRAM).

[0052] This disclosure also provides an electronic device, which includes the memory described above.

[0053] Therefore, this disclosure provides an address refresh circuit, method, memory, and electronic device, including a selection circuit and a decoding circuit. The selection circuit acquires a strobe signal, a redundant address signal, and a regular address signal, and selects one of the redundant address signal and the regular address signal as the target address signal based on the strobe signal during a first pulse time and a second pulse time. The first pulse time and the second pulse time belong to the same refresh cycle, with the second pulse time being later than the first pulse time. The decoding circuit decodes the target address signal to obtain and output a decoded signal. Since the first pulse time and the second pulse time belong to the same refresh cycle, one pulse time can perform one address refresh. Therefore, the address refresh circuit provided by this disclosure can complete the refresh of both the regular and redundant row addresses within one refresh cycle, i.e., a single circuit can complete the refresh of both types of row addresses, thereby saving power and improving performance. Attached Figure Description

[0054] Figure 1 This is a schematic diagram of the structure of an address refresh circuit provided in an embodiment of this disclosure. Figure 1 ;

[0055] Figure 2 This is a schematic diagram of an address refresh circuit provided in an embodiment of this disclosure;

[0056] Figure 3 This is a schematic diagram of the structure of an address refresh circuit provided in an embodiment of this disclosure. Figure 2 ;

[0057] Figure 4 This is a schematic diagram of the structure of an address refresh circuit provided in an embodiment of this disclosure. Figure 3 ;

[0058] Figure 5 This is a schematic diagram of the structure of an address refresh circuit provided in an embodiment of this disclosure. Figure 4 ;

[0059] Figure 6 This is a schematic diagram of the structure of an address refresh circuit provided in an embodiment of this disclosure. Figure 5 ;

[0060] Figure 7 This is a schematic diagram of the structure of an address refresh circuit provided in an embodiment of this disclosure. Figure 6 ;

[0061] Figure 8 This is a schematic diagram of the structure of an address refresh circuit provided in an embodiment of this disclosure. Figure 7 ;

[0062] Figure 9 This is a flowchart of an address refresh method provided in an embodiment of the present disclosure. Figure 1 ;

[0063] Figure 10 This is a flowchart of an address refresh method provided in an embodiment of the present disclosure. Figure 2 ;

[0064] Figure 11 This is a flowchart of an address refresh method provided in an embodiment of the present disclosure. Figure 3 ;

[0065] Figure 12 This is a flowchart of an address refresh method provided in an embodiment of the present disclosure. Figure 4 ;

[0066] Figure 13 This is a flowchart of an address refresh method provided in an embodiment of the present disclosure. Figure 5 ;

[0067] Figure 14 This is a schematic diagram of the structure of a memory provided in an embodiment of this disclosure;

[0068] Figure 15 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0070] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0071] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0072] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0073] When DRAM performs a refresh operation, it refreshes several word lines simultaneously. For example, in a decoding circuit, if R15, R15B, R14, and R14B are all set to 1, four word lines can be refreshed at once. These word lines may contain regular addresses and redundant addresses; that is, some addresses in the word lines are replaced with redundant addresses.

[0074] In related technologies, regular addresses and redundant addresses are usually refreshed separately. This requires an additional refresh command signal (Command, CMD), which consumes bandwidth resources and reduces cell retention time. Alternatively, regular addresses and redundant addresses can be refreshed together, which requires separate decoding of regular addresses and redundant addresses, increasing the chip area and reducing chip integration.

[0075] Figure 1 This is a schematic diagram of the structure of an address refresh circuit provided in an embodiment of this disclosure, as shown below. Figure 1 As shown, this embodiment of the disclosure provides an address refresh circuit 10, including: a selection circuit 101 and a decoding circuit 102; wherein:

[0076] The selection circuit 101 is used to acquire a strobe signal, a redundant address signal, and a regular address signal, and is used to select one of the redundant address signal and the regular address signal as the target address signal based on the strobe signal during the first pulse time and the second pulse time, respectively; the first pulse time and the second pulse time belong to the same refresh cycle, and the second pulse time is later than the first pulse time;

[0077] The decoding circuit 102 is used to decode the target address signal to obtain and output the decoded signal.

[0078] In this embodiment of the disclosure, the redundant address signal can correspond to the redundant row address (RedRa), the normal address signal can correspond to the normal row address (Ra), and the strobe signal can be represented as RedEn (Redundancy Enable).

[0079] In this embodiment of the disclosure, such as Figure 2As shown, a refresh cycle occurs between the refresh command (REFCmd) and the active command (Active), and the word line address needs to be refreshed within one refresh cycle. The first pulse (1 st pulse) time and second pulse (2 nd The pulse times belong to the same refresh cycle, with the second pulse time being later than the first pulse time. The pulse time represents the refresh state, and one address refresh can be performed corresponding to each pulse time.

[0080] In this embodiment, the regular row address and the redundant row address can share a single address refresh circuit 10, inputting both the regular address signal and the redundant address signal into the selection circuit 101. When all row addresses in a refresh cycle are regular row addresses, the selection circuit 101 selects the regular address signal as the target address signal in both the first pulse time and the second pulse time, i.e., performing regular row address refresh in one refresh cycle. When all row addresses in a refresh cycle are redundant row addresses, the selection circuit 101 selects the redundant address signal as the target address signal in both the first pulse time and the second pulse time, i.e., performing redundant row address refresh in one refresh cycle. When both redundant and regular row addresses exist in a refresh cycle, the selection circuit 101 can select the redundant address signal as the target address signal in one pulse time and the regular address signal as the target address signal in another pulse time, i.e., performing both regular and redundant row address refresh in one refresh cycle.

[0081] It should be noted that, in this embodiment, a refresh cycle may include more pulse times (such as a third pulse time). Correspondingly, the selection circuit 101 may, during the third pulse time, select one of the redundant address signal and the regular address signal as the target address signal based on the strobe signal. If a refresh cycle includes only two pulse times, the corresponding refresh mode is two-pulse refresh; if a refresh cycle includes more than two pulse times, the corresponding refresh mode is multi-pulse refresh.

[0082] Understandably, the address refresh circuit 10 can select one of the redundant address signal and the normal address signal as the target address signal based on the strobe signal during the first pulse time and the second pulse time, respectively, for decoding. Since the first pulse time and the second pulse time belong to the same refresh cycle, and one pulse time can perform one address refresh, the address refresh circuit 10 can complete the refresh of the normal row address and the redundant row address within one refresh cycle. That is, a single circuit can complete the refresh of both types of row addresses, thereby saving power and improving performance.

[0083] In some embodiments of this disclosure, such as Figure 3 As shown, the selection circuit 101 includes: a first selection module 201, a second selection module 202, and a third selection module 203; wherein: the first selection module 201 is used to receive a redundant address signal and a strobe signal, and if the strobe signal has a first level, it outputs a redundant address signal; the second selection module 202 is used to receive a normal address signal and a strobe signal, and if the strobe signal has a second level, it outputs a normal address signal; the input terminal of the third selection module 203 is connected to the output terminal of the first selection module 201 and the output terminal of the second selection module 202 respectively, and the output terminal of the third selection module is connected to the input terminal of the decoding circuit 102.

[0084] In this embodiment of the disclosure, a high level represents logic 1, a low level represents logic 0, and the first level and the second level are respectively a high level or a low level; specifically, if the first level is a high level, then the second level is a low level; if the first level is a low level, then the second level is a high level.

[0085] In this embodiment of the present disclosure, when all row addresses in a refresh cycle are regular row addresses, the strobe signal is at the second level in both the first and second pulse times. Thus, the selection circuit 101 selects the regular address signal as the target address signal in both the first and second pulse times, meaning that regular row address refresh is performed in one refresh cycle. When all row addresses in a refresh cycle are redundant row addresses, the strobe signal is at the first level in both the first and second pulse times. Thus, the selection circuit 101 selects the redundant address signal as the target address signal in both the first and second pulse times, meaning that redundant row address refresh is performed in one refresh cycle. When both redundant and regular row addresses exist in a refresh cycle, the strobe signal can be at the first level in one pulse time and the second level in another pulse time. For example, if it is at the first level in the first pulse time and the second level in the second pulse time, the selection circuit 101 selects the redundant address signal as the target address signal in the first pulse time and the regular address signal as the target address signal in the second pulse time, meaning that both regular and redundant row address refresh are performed in one refresh cycle.

[0086] It is understandable that the first selection module 201 can output a redundant address signal based on the first level of the strobe signal; the second selection module 202 can output a normal address signal based on the second level of the strobe signal. In other words, the selection circuit 101 can output the corresponding address signal based on the level state of the strobe signal. Thus, one of the redundant address signal and the normal address signal can be output in each pulse time to complete the refresh. Therefore, within a refresh cycle including the first and second pulse times, the redundant address signal and the normal address signal can be refreshed respectively, thereby saving power and improving performance.

[0087] In some embodiments of this disclosure, such as Figure 4 As shown, the first selection module 201 includes a first AND gate 401 and a first inverter 402. The first input terminal of the first AND gate 401 is connected to the output terminal of the first inverter 402. The input terminal of the first inverter 402 is used to receive a strobe signal, and the second input terminal of the first AND gate 401 is used to receive a redundant address signal. The second selection module 202 includes a second AND gate 403, which is used to receive a regular address signal and a strobe signal. The input terminal of the third selection module 203 is connected to the output terminal of the first AND gate 401 and the output terminal of the second AND gate 402, respectively. The output terminal of the third selection module 203 is connected to the input terminal of the decoding circuit 102.

[0088] In this embodiment, the first level of the strobe signal is low, i.e., logic 0; the second level of the strobe signal is high, i.e., logic 1. If the strobe signal is logic 0, the first inverter 402 inverts the logic 0 of the strobe signal to logic 1, the first AND gate 401 performs an AND operation on logic 1 and the redundant address signal to obtain a first intermediate signal a representing the redundant address signal; the second AND gate 403 performs an AND operation on the logic 0 of the strobe signal and the normal address signal to obtain a second intermediate signal b set to logic 0, i.e., the normal address signal is masked. If the strobe signal is logic 1, the first inverter 402 inverts the logic 1 of the strobe signal to logic 0, the first AND gate 401 performs an AND operation on logic 0 and the redundant address signal to obtain a first intermediate signal a set to logic 0, i.e., the redundant address signal is masked; the second AND gate 403 performs an AND operation on the logic 1 of the strobe signal and the normal address signal to obtain a second intermediate signal b representing the normal address signal.

[0089] In this embodiment of the present disclosure, the input terminal of the second AND gate 403 may also receive other signals to adjust the output result of the second AND gate 403.

[0090] It should be noted that the output of the first inverter 402 can be replaced with the input of the second AND gate 403. In this case, if the strobe signal is logic 0, a normal address signal is output; if the strobe signal is logic 1, a redundant address signal is output. Alternatively, the first AND gate 401 and the second AND gate 403 can be replaced with OR gates. All of the above modifications should be covered within the scope of this disclosure.

[0091] Understandably, by using the first AND gate 401, the first inverter 402, and the second AND gate 403, when the strobe signal is logic 0, the normal address signal can be masked, and a redundant address signal can be output; when the strobe signal is logic 1, the redundant address signal can be masked, and a normal address signal can be output. In this way, the corresponding address signal is output based on the level state of the strobe signal. Therefore, the redundant address signal and the normal address signal can be refreshed separately within a refresh cycle that includes the first pulse time and the second pulse time, saving power and improving performance.

[0092] In some embodiments of this disclosure, such as Figure 5 As shown, the third selection module 203 includes: a NOR gate 404 and a second inverter 405; wherein, the output terminal of the NOR gate 404 is connected to the input terminal of the second inverter 405; the input terminal of the NOR gate 404 serves as the input terminal of the third selection module 203, and the output terminal of the second inverter 405 serves as the output terminal of the third selection module 203.

[0093] In this embodiment of the disclosure, if the strobe signal is logic 0, then the first intermediate signal a represents the redundant address signal, and the second intermediate signal b is set to logic 0, that is, the regular address signal is masked. At this time, the NOR gate 404 and the second inverter 405 perform an OR operation on the first intermediate signal a and the second intermediate signal b to obtain and output the redundant address signal as the target address signal.

[0094] If the strobe signal is logic 1, then the first intermediate signal a is set to logic 0, that is, the redundant address signal is masked, and the second intermediate signal b represents the normal address signal. At this time, the NOR gate 404 and the second inverter 405 perform an OR operation on the first intermediate signal a and the second intermediate signal b to obtain and output the normal address signal as the target address signal.

[0095] In this embodiment of the present disclosure, the second inverter 405 can drive the output target address signal to reduce the attenuation of the target address signal during transmission.

[0096] It should be noted that if the first AND gate 401 and the second AND gate 403 are replaced with OR gates, then the NOR gate 404 needs to be replaced with a NAND gate accordingly. The transformed circuit can still select one of the redundant address signal and the conventional address signal as the target address signal for output based on the level state of the strobe signal. All the above transformations should be covered within the protection scope of this disclosure.

[0097] It is understandable that by using the first AND gate 401, the first inverter 402, the second AND gate 403, the NOR gate 404, and the second inverter 405, one of the redundant address signal and the regular address signal can be selected as the target address signal for output based on the level state of the strobe signal. This allows the redundant address signal and the regular address signal to be refreshed within a refresh cycle that includes the first pulse time and the second pulse time, saving power and improving performance.

[0098] In some embodiments of this disclosure, such as Figure 6 As shown, the decoding circuit 102 includes: an enable module 204, which is connected to the output terminal of the selection circuit 101 and is used to receive an enable signal. If the enable signal is at the second level, the received target address signal is output; and a decoder 301, which is connected to the output terminal of the enable module 204 and is used to decode the target address signal to obtain and output a decoded signal.

[0099] In this embodiment, the first input terminal of the enable module 204 is connected to the output terminal of the selection circuit 101 to receive the target address signal; the second input terminal of the enable module 204 receives an enable signal, and if the enable signal is at a second level, the received target address signal is output. That is, the enable module 204 can control the output of the target address signal according to the level of the enable signal.

[0100] In this embodiment of the disclosure, the decoding signal output by the decoder 301 can characterize the position information of the row address to be refreshed. Based on the decoding signal, the refresh module can determine and refresh the corresponding row address.

[0101] Understandably, the enable module 204 can control the output of the target address signal based on the level of the enable signal, thereby adjusting the timing of the target address signal and improving the timing status of the signal.

[0102] In some embodiments of this disclosure, such as Figure 7As shown, the enable module 204 includes: a NAND gate 406 and a third inverter 407; wherein, the first input terminal of the NAND gate 406 serves as the first input terminal of the enable module 204 and receives an enable signal; the second input terminal of the NAND gate 406 serves as the second input terminal of the enable module 204 and is connected to the output terminal of the selection circuit 101; the output terminal of the NAND gate 406 is connected to the input terminal of the third inverter 407; the output terminal of the third inverter 407 serves as the output terminal of the enable module 204 and is connected to the decoder 301.

[0103] In this embodiment, the input of the NAND gate 406 receives an enable signal and a target address signal. The second level of the enable signal is high, i.e., logic 1. The NAND gate 406 and the third inverter 407 perform an AND operation on the enable signal and the target address signal. If the enable signal is at the second level, i.e., logic 1, the third inverter 407 outputs the target address signal after the AND operation; if the enable signal is logic 0, the third inverter 407 outputs logic 0, i.e., the target address signal is masked.

[0104] In this embodiment of the present disclosure, the third inverter 407 can drive the output target address signal to reduce the attenuation of the target address signal during transmission.

[0105] It should be noted that the NAND gate 406 can be replaced with a NOR gate. After replacement, when the enable signal is logic 0, the received target address signal is output. Thus, the output of the target address signal can also be controlled based on the level of the enable signal. Correspondingly, subsequent modules can identify the target address signal. If the target address signal is consistently logic 1, it is determined to be an invalid signal, and the address refresh operation is not performed. All the above transformations should be covered within the scope of this disclosure.

[0106] Understandably, the NAND gate 406 and the third inverter 407 can perform an AND operation on the enable signal and the target address signal. When the enable signal is logic 1, the target address signal is output; when the enable signal is logic 0, the target address signal is masked. In this way, the output of the target address signal is controlled based on the level of the enable signal, thereby adjusting the timing of the target address signal and improving its timing state.

[0107] In some embodiments of this disclosure, such as Figure 8 As shown, the output of the second inverter 405 serves as the output of the selection circuit 101 and is connected to the second input of the NAND gate 406.

[0108] In this embodiment, the input of the first AND gate 401 receives the inverted signals of the redundant address signal and the strobe signal, and the second AND gate 403 receives the normal address signal and the strobe signal. The outputs of the first AND gate 401 and the second AND gate 403 are respectively connected to the two inputs of the NOR gate 404. When the strobe signal is logic 0, the second inverter 405 outputs the redundant address signal as the target address signal to the first input of the NOR gate 406; when the strobe signal is logic 1, the second inverter 405 outputs the normal address signal as the target address signal to the first input of the NOR gate 406. Thus, in each pulse time of a refresh cycle, the refresh of the redundant row address or the normal row address can be achieved by controlling the level of the strobe signal.

[0109] The first input of NAND gate 406 receives the target address signal, and the second input receives the enable signal. When the enable signal is logic 1, the third inverter 407 outputs the target address signal to decoder 301 for decoding. Thus, the timing of the target address signal can be adjusted using the enable signal, improving the signal's timing state.

[0110] Figure 9 This is an optional flowchart illustrating an address refresh method provided in an embodiment of this disclosure, which will be combined with... Figure 9 The steps shown are explained.

[0111] S101. Obtain the strobe signal, redundant address signal, and normal address signal respectively.

[0112] In this embodiment of the disclosure, the selection circuit 101 can acquire the strobe signal, the redundant address signal, and the regular address signal, respectively. The redundant address signal can correspond to a redundant row address, and the regular address signal can correspond to a regular row address.

[0113] S102. During the first pulse time and the second pulse time, based on the strobe signal, one of the redundant address signal and the regular address signal is selected as the target address signal, respectively; the first pulse time and the second pulse time belong to the same refresh cycle, and the second pulse time is later than the first pulse time.

[0114] In this embodiment of the disclosure, the pulse time represents the refresh state, and one address refresh can be performed corresponding to the pulse time. That is, the selection circuit 101 can refresh one of the redundant row address and the regular row address at the first pulse time and the second pulse time, respectively. In this way, the refresh of the redundant address signal and the regular address signal can be completed within one refresh cycle.

[0115] S103. Decode the target address signal to obtain and output the decoded signal.

[0116] In this embodiment of the disclosure, the decoding circuit 102 can decode the target address signal to obtain and output a decoded signal. The decoded signal represents the location information of the row address to be refreshed. Based on the decoded signal, the corresponding row address can be determined and refreshed.

[0117] It is understood that, in the embodiments of this disclosure, one of the redundant address signal and the regular address signal can be selected as the target address signal based on the strobe signal during the first pulse time and the second pulse time, respectively, for decoding. Since the first pulse time and the second pulse time belong to the same refresh cycle, and one address refresh can be performed once per pulse time, the embodiments of this disclosure can complete the refresh of the regular row address and the redundant row address within one refresh cycle. That is, a single circuit is used to complete the refresh of both types of row addresses, thereby saving power and improving performance.

[0118] In some embodiments of this disclosure, it can be implemented via S1031. Figure 9 S103, shown below, will be explained in conjunction with each step.

[0119] S1031. If the acquired enable signal is the second level, then the target address signal is decoded to obtain and output the decoded signal.

[0120] In this embodiment of the disclosure, the enable module 204 can control the output of the target address signal according to the level of the enable signal. (See reference...) Figure 6 The second input terminal of the enable module 204 receives the enable signal. If the enable signal is at the second level, the enable module 204 outputs the received target address signal to the decoder 301. The decoder 301 decodes the target address signal and outputs the decoded signal.

[0121] It is understandable that the output of the target address signal is controlled based on the level of the enable signal, thereby adjusting the timing of the target address signal and improving the timing status of the signal.

[0122] In some embodiments of this disclosure, the refresh cycle further includes: a third pulse time; Figure 9 S104 is also included after S101 shown, and will be explained in conjunction with each step.

[0123] S104. During the third pulse time, based on the strobe signal, select one of the redundant address signal and the regular address signal as the target address signal.

[0124] In this embodiment of the disclosure, a refresh cycle may also include more pulse times (such as a third pulse time). Correspondingly, the selection circuit 101 may, during the third pulse time, select one of the redundant address signal and the regular address signal as the target address signal based on the strobe signal.

[0125] It is understood that a refresh cycle in the embodiments of this disclosure may include two or more pulse times, and the corresponding refresh mode is multi-pulse refresh.

[0126] In some embodiments of this disclosure, it is possible to... Figure 10 The shown S1021 to S1022 are implemented to achieve this. Figure 9 S102, shown below, will be explained in conjunction with each step.

[0127] S1021. If the strobe signal has a first level, then the redundant address signal is output as the target address signal.

[0128] In this embodiment of the disclosure, the selection circuit 101 can output a redundant address signal as a target address signal when the strobe signal has a first level.

[0129] S1022. If the strobe signal has a second level, then the output regular address signal is used as the target address signal.

[0130] In this embodiment of the disclosure, the selection circuit 101 can output a conventional address signal as a target address signal when the strobe signal has a second level.

[0131] It should be noted that the first level and the second level are either high or low, respectively. The selection circuit 101 can use AND gates or OR gates to select the target address signal based on the level state of the strobe signal; no restrictions are imposed here.

[0132] Understandably, the corresponding address signal is output based on the level state of the strobe signal. In this way, one of the redundant address signal and the regular address signal can be output in each pulse time to complete the refresh. Therefore, within a refresh cycle including the first and second pulse times, the redundant address signal and the regular address signal can be refreshed respectively, thus saving power and improving performance.

[0133] In some embodiments of this disclosure, the first level represents logic 0; it can be... Figure 11 The shown S201 to S203 are implemented to achieve this. Figure 10 The step 1021 shown will be explained in conjunction with each step.

[0134] S201. Invert the first level of the strobe signal and perform an AND operation with the redundant address signal to obtain the first intermediate signal, which is characterized as the redundant address signal.

[0135] In this embodiment of the disclosure, reference is made to Figure 5The selection circuit 101 can invert the logic 0 of the selection signal to logic 1 through the first inverter 402; then, it performs an AND operation on logic 1 and the redundant address signal through the first AND gate 401 to obtain the first intermediate signal a, which is characterized as the redundant address signal.

[0136] S202. Perform an AND operation on the first level of the strobe signal and the normal address signal to obtain the second intermediate signal set to the first level.

[0137] In this embodiment of the disclosure, reference is made to Figure 5 The selection circuit 101 can perform an AND operation between the logic 0 of the strobe signal and the normal address signal through the second AND gate 403 to obtain the second intermediate signal b set to logic 0, that is, to shield the normal address signal.

[0138] S203. Perform an OR operation on the first intermediate signal, which is characterized as a redundant address signal, and the second intermediate signal, which is set to the first level, to obtain the target address signal, which is characterized as a redundant address signal.

[0139] In this embodiment of the disclosure, reference is made to Figure 5 The selection circuit 101 can perform an OR operation on the first intermediate signal a and the second intermediate signal b through the OR gate 404 and the second inverter 405 to obtain and output a redundant address signal as the target address signal.

[0140] In some embodiments of this disclosure, the second level represents logic 1; it can be... Figure 12 The shown S301 to S303 are implemented to achieve this. Figure 10 The step 1022 shown will be explained in conjunction with each step.

[0141] S301. Invert the second level of the strobe signal and perform a bitwise AND operation with the redundant address signal to obtain the first intermediate signal set to the first level.

[0142] In this embodiment of the disclosure, reference is made to Figure 5 The selection circuit 101 can invert the logic 1 of the selection signal to logic 0 through the first inverter 402. The first AND gate 401 performs an AND operation on logic 0 and the redundant address signal to obtain the first intermediate signal a set to logic 0, that is, the redundant address signal is masked.

[0143] S302. Perform an AND operation on the second level of the strobe signal and the conventional address signal to obtain the second intermediate signal, which is characterized as the conventional address signal.

[0144] In this embodiment of the disclosure, reference is made to Figure 5 The selection circuit 101 can perform an AND operation on the logic 1 of the strobe signal and the normal address signal through the second AND gate 403 to obtain the second intermediate signal b, which is represented as the normal address signal.

[0145] S303. Perform an OR operation on the first intermediate signal set to the first level and the second intermediate signal representing a conventional address signal to obtain the target address signal representing a conventional address signal.

[0146] In this embodiment of the disclosure, reference is made to Figure 5 The selection circuit 101 can perform an OR operation on the first intermediate signal a and the second intermediate signal b through the NOR gate 404 and the second inverter 405 to obtain and output a conventional address signal as the target address signal.

[0147] It is understandable that by using the first AND gate 401, the first inverter 402, the second AND gate 403, the NOR gate 404, and the second inverter 405, one of the redundant address signal and the regular address signal can be selected as the target address signal for output based on the level state of the strobe signal. This allows the redundant address signal and the regular address signal to be refreshed within a refresh cycle that includes the first pulse time and the second pulse time, saving power and improving performance.

[0148] In some embodiments of this disclosure, the second level represents logic 1; it can be... Figure 13 The steps S401 to S403 shown implement 1031 in the above embodiment, and will be explained in conjunction with each step.

[0149] S401. Perform an AND operation on the target address signal and the acquired enable signal. If the enable signal is at the second level, output the target address signal to the decoder.

[0150] In this embodiment of the disclosure, reference is made to Figure 7 When the enable signal is logic 1, the enable module 204 can perform an AND operation on the enable signal and the target address signal using the NAND gate 406 and the third inverter 407. If the enable signal is at the second level, i.e., logic 1, the third inverter 407 outputs the target address signal after the AND operation; if the enable signal is logic 0, the third inverter 407 outputs logic 0, i.e., the target address signal is masked.

[0151] S402. The target address signal is decoded by a decoder to obtain and output the decoded signal.

[0152] In this embodiment of the present disclosure, the decoder 301 can decode the target address signal to obtain and output the decoded signal.

[0153] It is understandable that the enable signal and the target address signal can be ANDed by the NAND gate 406 and the third inverter 407. In this way, the target address signal can be output when the enable signal is logic 1, and the target address signal can be masked when the enable signal is logic 0. This realizes the control of the output of the target address signal based on the level of the enable signal, thereby adjusting the timing of the target address signal and improving the timing state of the signal.

[0154] This disclosure also provides a memory 80, such as... Figure 14 As shown, the memory 80 includes the address refresh circuit 10 of the aforementioned embodiment, thereby saving power and improving performance.

[0155] In some embodiments of this disclosure, Figure 14 The memory 80 shown includes at least dynamic random access memory (DRAM).

[0156] This disclosure also provides an electronic device 90, such as... Figure 15 As shown, the electronic device 90 includes a memory 80.

[0157] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0158] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0159] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An address refresh circuit, characterized in that, The circuit includes: a selection circuit and a decoding circuit; wherein... The selection circuit is used to acquire a strobe signal, a redundant address signal, and a regular address signal, and is used to select one of the redundant address signal and the regular address signal as the target address signal based on the strobe signal during a first pulse time and a second pulse time, respectively; the first pulse time and the second pulse time belong to the same refresh cycle, and the second pulse time is later than the first pulse time; wherein, the refresh cycle refers to the duration between a refresh command and an adjacent activation command, and the strobe signal is generated based on whether the address to be refreshed is replaced by a redundant row address within the refresh cycle; The decoding circuit is used to decode the target address signal to obtain and output the decoded signal.

2. The address refresh circuit according to claim 1, characterized in that, The selection circuit includes: The first selection module is used to receive the redundant address signal and the strobe signal, and if the strobe signal has a first level, it outputs the redundant address signal. The second selection module is used to receive the conventional address signal and the strobe signal, and if the strobe signal has a second level, it outputs the conventional address signal.

3. The address refresh circuit according to claim 2, characterized in that, The first selection module includes a first AND gate and a first inverter. The first input of the first AND gate is connected to the output of the first inverter. The input of the first inverter is used to receive the gating signal. The second input of the first AND gate is used to receive the redundant address signal. The second selection module includes a second AND gate for receiving the conventional address signal and the strobe signal; The selection circuit further includes: a third selection module; The input terminal of the third selection module is connected to the output terminal of the first AND gate and the output terminal of the second AND gate, respectively, and the output terminal of the third selection module is connected to the input terminal of the decoding circuit.

4. The address refresh circuit according to claim 3, characterized in that, The third selection module includes: a NOR gate and a second inverter; The output of the NOR gate is connected to the input of the second inverter. The input terminal of the NOR gate serves as the input terminal of the third selection module, and the output terminal of the second inverter serves as the output terminal of the third selection module.

5. The address refresh circuit according to claim 1, characterized in that, The decoding circuit includes: An enable module is connected to the output of the selection circuit and is used to receive an enable signal. If the enable signal is at the second level, the received target address signal is output. A decoder, connected to the output of the enable module, is used to decode the target address signal to obtain and output the decoded signal.

6. The address refresh circuit according to claim 5, characterized in that, The enabling module includes: a NAND gate and a third inverter; The first input terminal of the NAND gate serves as the first input terminal of the enable module, receiving the enable signal; the second input terminal of the NAND gate serves as the second input terminal of the enable module, connected to the output terminal of the selection circuit. The output of the NAND gate is connected to the input of the third inverter. The output of the third inverter serves as the output of the enable module and is connected to the decoder.

7. The address refresh circuit according to any one of claims 1 to 6, characterized in that, The refresh cycle also includes: the third pulse time; The selection circuit is further configured to, during the third pulse time, select one of the redundant address signal and the regular address signal as the target address signal based on the strobe signal.

8. An address refresh method, characterized in that, The method includes: Obtain the strobe signal, redundant address signal, and normal address signal respectively; During the first pulse time and the second pulse time, based on the strobe signal, one of the redundant address signal and the regular address signal is selected as the target address signal, respectively; the first pulse time and the second pulse time belong to the same refresh cycle, and the second pulse time is later than the first pulse time; wherein, the refresh cycle refers to the duration between the refresh command and the subsequent adjacent activation command, and the strobe signal is generated based on whether the address to be refreshed is replaced by the redundant row address within the refresh cycle; The target address signal is decoded to obtain and output the decoded signal.

9. The address refresh method according to claim 8, characterized in that, The process of decoding the target address signal to obtain and output the decoded signal includes: If the acquired enable signal is at the second level, the target address signal is decoded to obtain and output the decoded signal.

10. The address refresh method according to claim 8, characterized in that, The refresh cycle further includes: a third pulse time; the method further includes: During the third pulse time, based on the strobe signal, one of the redundant address signal and the regular address signal is selected as the target address signal.

11. The address refresh method according to claim 8, characterized in that, The step of selecting one of the redundant address signal and the regular address signal as the target address signal based on the strobe signal includes: If the strobe signal has a first level, then the redundant address signal is output as the target address signal; or, If the strobe signal has a second level, then the regular address signal is output as the target address signal.

12. The address refresh method according to claim 11, characterized in that, The first level represents logic 0; the step of outputting the redundant address signal as the target address signal if the strobe signal has the first level includes: The first level of the strobe signal is inverted and ANDed with the redundant address signal to obtain a first intermediate signal that represents the redundant address signal; Perform an AND operation between the first level of the strobe signal and the conventional address signal to obtain a second intermediate signal set to the first level; The target address signal, which is characterized as the redundant address signal, is obtained by performing an OR operation on the first intermediate signal and the second intermediate signal set to the first level.

13. The address refresh method according to claim 11, characterized in that, The second level characterization logic 1; the step of outputting the conventional address signal as the target address signal if the strobe signal has the second level includes: The second level of the strobe signal is inverted and ANDed with the redundant address signal to obtain a first intermediate signal set to the first level; A bitwise AND operation is performed between the second level of the strobe signal and the conventional address signal to obtain a second intermediate signal that represents the conventional address signal. The first intermediate signal, which is set to a first level, and the second intermediate signal, which represents the conventional address signal, are subjected to an OR operation to obtain the target address signal, which represents the conventional address signal.

14. The address refresh method according to claim 9, characterized in that, The second level represents logic 1; If the acquired enable signal is at the second level, then the target address signal is decoded to obtain and output the decoded signal, including: Perform an AND operation on the target address signal and the acquired enable signal. If the enable signal is at the second level, then output the target address signal to the decoder. The decoder decodes the target address signal to obtain and output the decoded signal.

15. A memory, characterized in that, The memory includes the address refresh circuit as described in any one of claims 1 to 7.

16. The memory according to claim 15, characterized in that, The memory includes at least: Dynamic Random Access Memory (DRAM).

17. An electronic device, characterized in that, The electronic device includes the memory as described in claim 15 or 16.

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