Integrated circuit including sampling circuit and storage device

Abstract

An integrated circuit includes: first and second pattern generation circuits for generating first and second pattern signals for a sampling segment; a first segment control unit for generating a coarse segment signal for a first segment of the sampling segment based on the first pattern signal; a first filtering unit for generating a first segment extraction signal by filtering a second pattern signal based on the coarse segment signal; a second segment control unit for generating a fine segment signal for a second segment of the sampling segment based on the first segment extraction signal; a second filtering unit for generating a second segment extraction signal by filtering the second pattern signal based on the fine segment signal; an output control circuit for generating a sampling enable signal based on the first and second segment extraction signals; and a sampling circuit adapted to sample an input signal based on the sampling enable signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0172410, filed on December 3, 2021, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a memory device including a sampling circuit for randomly sampling an input signal. Background Art

[0004] Recently, in addition to normal refresh operations, an additional refresh operation, hereinafter referred to as a "targeted refresh operation," is performed on memory cells of a specific word line that may have lost data due to row hammering. Row hammering is a phenomenon in which data in memory cells coupled to a specific word line or adjacent word lines located adjacent to the specific word line is damaged due to a large number of activations of the specific word line. To prevent row hammering, a targeted refresh operation is performed on a word line that has been activated more than a predetermined number of times, as well as on adjacent word lines located adjacent to the word line.

[0005] In a target refresh operation, a word line on which the target refresh operation is to be performed can be selected by randomly sampling addresses based on probability. Therefore, research has been conducted on a sampling circuit for randomly sampling addresses. Summary of the Invention

[0006] Embodiments of the present invention relate to an integrated circuit and a memory device including a sampling circuit capable of randomly sampling addresses.

[0007] According to one embodiment of the present invention, an integrated circuit includes a first pattern generation circuit, adapted to generate a first pattern signal that randomly generates pulses for a sampling segment; a second pattern generation circuit, adapted to generate a second pattern signal that randomly generates pulses for the sampling segment; a first segment control unit, adapted to generate a coarse segment signal that enables a first segment of the sampling segment based on the first pattern signal; a first filtering unit, adapted to generate a first segment extraction signal by filtering the second pattern signal based on the coarse segment signal; a second segment control unit, adapted to generate a fine segment signal that enables a second segment of the sampling segment based on the first segment extraction signal; a second filtering unit, adapted to generate a second segment extraction signal by filtering the second pattern signal based on the fine segment signal; an output control circuit, adapted to generate a sampling enable signal based on the first segment extraction signal and the second segment extraction signal; and a sampling circuit, adapted to sample an input signal based on the sampling enable signal.

[0008] According to one embodiment of the present invention, a method for operating an integrated circuit includes: dividing a sampling segment into a plurality of coarse segments; generating a first pattern signal that randomly generates pulses for each of the coarse segments; dividing the sampling segment into a plurality of fine segments; generating a second pattern signal that randomly generates pulses for each of the fine segments; randomly selecting one of the coarse segments; randomly selecting one of the fine segments for the selected coarse segment; generating a sampling enable signal based on the second pattern signal that generates pulses for the selected fine segment; and sampling an input signal based on the sampling enable signal.

[0009] According to one embodiment of the present invention, a storage device includes: a first pattern generation circuit, which is suitable for dividing a target refresh segment into multiple coarse segments and generating a first pattern signal of randomly occurring pulses for each of the coarse segments; a second pattern generation circuit, which is suitable for dividing the target refresh segment into multiple fine segments and generating a second pattern signal of randomly occurring pulses for each of the fine segments; a first segment extraction circuit, which is suitable for generating a first segment extraction signal by extracting the second pattern signal for a coarse segment randomly selected from the coarse segments according to the first pattern signal; a second segment extraction circuit, which is suitable for generating a second segment extraction signal by extracting the second pattern signal for a fine segment randomly selected from the fine segments according to the first segment extraction signal; an output control circuit, which is suitable for generating a sampling enable signal based on the first segment extraction signal and the second segment extraction signal; and a sampling circuit, which is suitable for outputting a target address by sampling an active address according to the sampling enable signal.

[0010] According to one embodiment of the present invention, a method for operating an integrated circuit includes: generating a sampling enable signal according to a pattern signal, the pattern signal generating a pulse during a selected fine segment among a plurality of fine segments, the selected fine segment being included in a selected coarse segment among a plurality of coarse segments; and sampling an address according to the sampling enable signal, wherein the coarse segment and the fine segment have random periods, and wherein the period of the fine segment is shorter than the period of the coarse segment.

[0011] Furthermore, according to embodiments of the present invention, the integrated circuit can address the periodicity of the sampling circuit and maximize randomization by performing sampling using dual pattern generation circuits operating at different periods. Furthermore, according to embodiments of the present invention, the integrated circuit can maximize the accuracy of address sampling and improve the efficiency of the targeted refresh operation by applying the sampling circuit to a memory device that performs a targeted refresh operation by sampling addresses based on probability. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram illustrating an integrated circuit according to one embodiment of the present invention.

[0013] Figure 2 is a diagram illustrating an embodiment of the present invention Figure 1 The detailed configuration diagram of the first section control circuit is shown.

[0014] Figure 3 is a diagram illustrating an embodiment of the present invention Figure 2 Detailed circuit diagram of the first comparator is shown.

[0015] Figure 4 is a diagram illustrating an embodiment of the present invention Figure 1 Detailed configuration diagram of the first filtering circuit shown.

[0016] Figure 5 is a diagram illustrating an embodiment of the present invention Figure 1 The detailed configuration diagram of the second section control circuit is shown.

[0017] Figure 6 is a diagram illustrating an embodiment of the present invention Figure 1 Detailed configuration diagram of the output control circuit shown.

[0018] Figure 7 is a timing diagram for depicting the operation of an integrated circuit according to one embodiment of the present invention.

[0019] Figure 8 is a block diagram illustrating a storage device according to one embodiment of the present invention.

[0020] Figure 9 is a diagram illustrating an embodiment of the present invention Figure 8 Detailed configuration diagram of the sampling circuit.

[0021] Figure 10A and Figure 10B FIG. 1 is a timing diagram for describing the tendency of a sampling circuit according to the prior art and one embodiment of the present invention. DETAILED DESCRIPTION

[0022] The various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make this disclosure thorough and complete and to fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, the same reference numerals refer to the same components in the various figures and embodiments of the present invention.

[0023] It should be understood that when an element is referred to as being "coupled" or "connected" to another element, this may mean that the two are directly coupled, or that the two are electrically connected to each other with another circuit interposed therebetween. It will be further understood that when used in this specification, the terms "comprising," "including," "having," and the like specify the presence of the stated features, quantities, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, and / or combinations thereof. In this disclosure, the singular is intended to include the plural, unless the context clearly indicates otherwise.

[0024] Figure 1 is a block diagram illustrating an integrated circuit 10 according to one embodiment of the present invention.

[0025] Reference Figure 1 , the integrated circuit 10 may include a sampling control circuit 100 and a sampling circuit 200 .

[0026] The sampling control circuit 100 can generate a sampling enable signal SAM_EN that is randomly enabled for each sampling section. The sampling control circuit 100 can include at least two pattern generation circuits 120 and 130 with different periods, and can generate a first pattern signal SOUT1 and a second pattern signal SOUT2 that randomly pulse with different periods for each sampling section. The sampling control circuit 100 can generate the sampling enable signal SAM_EN based on the first pattern signal SOUT1 and the second pattern signal SOUT2. For reference, a sampling section can be determined by a sampling section signal SP, and a sampling section can be demarcated by two adjacent sampling section signals SP.

[0027] The sampling circuit 200 may generate an output signal OUT by sampling the input signal IN according to the sampling enable signal SAM_EN.

[0028] In detail, the sampling control circuit 100 may include a first pattern generation circuit 120 , a second pattern generation circuit 130 , a first section extraction circuit 140 , a second section extraction circuit 150 , and an output control circuit 160 .

[0029] The first pattern generation circuit 120 can generate a first pattern signal SOUT1 that randomly generates pulses for each sampling segment. The first pattern generation circuit 120 can be activated in response to a rising edge of the sampling segment signal SP. The first pattern generation circuit 120 can divide the sampling segment into a plurality of coarse segments and generate a first pattern signal SOUT1 that randomly generates pulses for each coarse segment. In this case, each of the plurality of coarse segments can have a random period or length. The first pattern generation circuit 120 can be defined as a coarse pattern generation circuit.

[0030] The second pattern generation circuit 130 can generate a second pattern signal SOUT2 that randomly pulses for the sampling segment. The second pattern generation circuit 130 can be activated in response to the rising edge of the sampling segment signal SP. The second pattern generation circuit 130 can divide the sampling segment into a plurality of fine segments and generate a second pattern signal SOUT2 that randomly pulses for each fine segment. In this case, each of the plurality of fine segments can have a random period or length and can have a shorter period than any coarse segment. In other words, the second pattern generation circuit 130 can operate with a shorter period than the first pattern generation circuit 120, and therefore, the second pattern generation circuit 130 can generate the second pattern signal SOUT2 that randomly pulses with a period shorter than the period of the first pattern signal SOUT1. The second pattern generation circuit 130 can be defined as a fine pattern generation circuit.

[0031] Each of the first pattern generation circuit 120 and the second pattern generation circuit 130 can be implemented using a random pattern generator based on a pseudo-random binary sequence (PRBS) or a random pattern generator based on a linear feedback shift register (LFSR). For example, the first pattern generation circuit 120 and the second pattern generation circuit 130 can be implemented using a random pattern generator based on a PRBS. In this case, the first pattern generation circuit 120 and the second pattern generation circuit 130 can be implemented as a uniform random number sequence generator, which can generate a pattern signal in which pulses are randomly generated the same number of times within a specific period (rather than a cyclic method).

[0032] The first segment extraction circuit 140 may select one of the coarse segments according to the first pattern signal SOUT1 and generate a first segment extraction signal SOUT2_M1 by extracting the second pattern signal SOUT2 for the selected coarse segment.

[0033] The first segment control section 142 may generate a coarse segment signal MATCH1 enabled for a first segment of the sampling segment according to the first pattern signal SOUT1. The first segment control section 142 may randomly select one of the coarse segments based on the sampling segment signal SP and the first pattern signal SOUT1, and generate a coarse segment signal MATCH1 enabled for the selected coarse segment corresponding to the first segment.

[0034] The first filter unit 144 can generate a first segment extraction signal SOUT2_M1 by filtering the second pattern signal SOUT2 according to the coarse segment signal MATCH1. The first filter unit 144 can output the second pattern signal SOUT2 as the first segment extraction signal SOUT2_M1 during the active segment of the coarse segment signal MATCH1. Therefore, during the active segment of the coarse segment signal MATCH1, some fine segments can be extracted from the fine segments.

[0035] The second segment extraction circuit 150 may select one of the fine segments according to the first segment extraction signal SOUT2_M1 and generate a second segment extraction signal SOUT2_M2 by extracting the second pattern signal SOUT2 from the selected fine segment. For example, the second segment extraction circuit 150 may include a second segment control unit 152 and a second filtering unit 154.

[0036] The second segment control unit 152 may generate a fine segment signal MATCH2 enabled for the second segment of the sampling segment based on the first segment extraction signal SOUT2_M1. The second segment control unit 152 may randomly select one of the fine segments extracted from the fine segments based on the sampling segment signal SP and the first segment extraction signal SOUT2_M1, and generate a fine segment signal MATCH2 enabled for the selected fine segment corresponding to the second segment.

[0037] The second filter unit 154 can generate a second segment extraction signal SOUT2_M2 by filtering the second pattern signal SOUT2 according to the fine segment signal MATCH2. The second filter unit 154 can output the second pattern signal SOUT2 as the second segment extraction signal SOUT2_M2 for the active segment of the fine segment signal MATCH2. According to one embodiment, the second filter unit 154 can output the second pattern signal SOUT2 by filtering the second segment extraction signal SOUT2_M2 according to the fine segment signal MATCH2.

[0038] The output control circuit 160 can generate a sampling enable signal SAM_EN according to the first segment extraction signal SOUT2_M1 and the second segment extraction signal SOUT2_M2. The output control circuit 160 can set the final segment signal ( Figure 6 and generates a sampling enable signal SAM_EN by filtering the first section extraction signal SOUT2_M1 according to the final section signal FINAL_S.

[0039] Figure 2 is a diagram illustrating an embodiment of the present invention Figure 1Detailed configuration diagram of the first segment control unit 142 is shown. Figure 3 is a diagram illustrating an embodiment of the present invention Figure 2 Detailed circuit diagram of the first comparator 1426 is shown.

[0040] Reference Figure 2 , the first segment control unit 142 may include a first random counter 1422 , a first reference counter 1424 and a first comparator 1426 .

[0041] The first random counter 1422 may count the number of times the first pattern signal SOUT1 is triggered to generate a first sampling count signal S_CNT1. The first reference counter 1424 may count the number of times the sampling segment signal SP is input to generate a first reference count signal R_CNT1. For example, when the sampling segment signal SP is input, the first reference counter 1424 may increase the value of the first reference count signal R_CNT1 by "+1". The first comparator 1426 may output a coarse segment signal MATCH1 by comparing the first sampling count signal S_CNT1 with the first reference count signal R_CNT1. The first comparator 1426 may enable the coarse segment signal MATCH1 when the bits of the first sampling count signal S_CNT1 are the same as the bits of the first reference count signal R_CNT1.

[0042] For example, refer to Figure 3 When the first sampling count signal S_CNT1 and the first reference count signal R_CNT1 each consist of three bits, the first comparator 1426 may include first through third XOR gates XR1 through XR3, and a NOR gate NR1. The first through third XOR gates XR1 through XR3 may perform a logical exclusive-OR operation on each bit of the first sampling count signal S_CNT1 and each bit of the first reference count signal R_CNT1, respectively. The NOR gate NR1 may perform a logically negative-OR operation on the outputs of the first through third XOR gates XR1 through XR3 to output the coarse segment signal MATCH1. With the above configuration, the first comparator 1426 may generate the coarse segment signal MATCH1 enabled at a logic high level when each bit of the first reference count signal R_CNT1 matches each bit of the first sampling count signal S_CNT1.

[0043] Figure 4 is a diagram illustrating an embodiment of the present invention Figure 1 Detailed configuration diagram of the first filter circuit 144 is shown.

[0044] Reference Figure 4The first filter section 144 may include a NAND gate ND1 and an inverter INV1. The NAND gate ND1 may perform a logical AND operation on the second pattern signal SOUT2 and the coarse segment signal MATCH1. The inverter INV1 may invert the output of the NAND gate ND1 to output the first segment extraction signal SOUT2_M1. With the above configuration, the first filter section 144 may perform a logical AND operation on the second pattern signal SOUT2 and the coarse segment signal MATCH1 and, when both the second pattern signal SOUT2 and the coarse segment signal MATCH1 are enabled, output the first segment extraction signal SOUT2_M1 enabled at a logic high level.

[0045] In addition, the second filter unit 154 may have Figure 4 That is, the second filtering section 154 may include a NAND gate and an inverter, and output the second segment extraction signal SOUT2_M2 by performing a logic AND operation on the fine segment signal MATCH2 and the second pattern signal SOUT2.

[0046] Figure 5 is a diagram illustrating an embodiment of the present invention Figure 1 Detailed configuration diagram of the second segment control circuit 152 is shown.

[0047] Reference Figure 5 The second segment control circuit 152 may include a second random counter 1522 , a second reference counter 1524 , and a second comparator 1526 .

[0048] The second random counter 1522 can count the number of times the first segment extraction signal SOUT2_M1 is triggered to generate a second sampling count signal S_CNT2. The second reference counter 1524 can count the number of times the sampling segment signal SP is input to generate a second reference count signal R_CNT2. For example, when the sampling segment signal is input, the second reference counter 1524 can increase the value of the second reference count signal R_CNT2 by "+2." In other words, the first reference counter 1424 and the second reference counter 1524 can generate the first reference count signal R_CNT1 and the second reference count signal R_CNT2 that increase to different values, thereby maximizing randomization of the sampling circuit. According to one embodiment, the first reference counter 1424 and the second reference counter 1524 can set the first reference count signal R_CNT1 and the second reference count signal R_CNT2 to different initial values. The second comparator 1526 can output the fine segment signal MATCH2 by comparing the second sampling count signal S_CNT2 with the second reference count signal R_CNT2. The second comparator 1526 may be composed of a plurality of gates for performing a logic exclusive-OR (XNOR) operation on each bit of the second sampling count signal S_CNT2 and the second reference count signal R_CNT2, and when each bit of the second reference count signal R_CNT2 matches each bit of the second sampling count signal S_CNT2, the fine segment signal MATCH2 is enabled to a logic high level. For example, the second comparator 1526 may have a gate with Figure 3 The first comparator 1426 is shown with substantially the same configuration.

[0049] Figure 6 is a diagram illustrating an embodiment of the present invention Figure 1 Detailed configuration diagram of the output control circuit 160 is shown.

[0050] Reference Figure 6 , the output control circuit 160 may include a set-reset (SR) latch 162 and a third filtering circuit 164 .

[0051] The SR latch 162 may generate a final segment signal FINAL_S that is set according to the sampling segment signal SP and reset according to the second segment extraction signal SOUT2_M2. The third filtering circuit 164 may output a sampling enable signal SAM_EN by filtering the first segment extraction signal SOUT2_M1 according to the final segment signal FINAL_S. The third filtering circuit 164 may output the first segment extraction signal SOUT2_M1 as the sampling enable signal SAM_EN for an active segment of the final segment signal FINAL_S. For example, the third filtering circuit 164 may have a Figure 4That is, the third filtering circuit 164 may include a NAND gate and an inverter, and output the sampling enable signal SAM_EN by performing a logic AND operation on the final section signal FINAL_S and the first section extraction signal SOUT2_M1.

[0052] In the following, reference is made to Figures 1 to 7 , a sampling operation of the integrated circuit 10 according to an embodiment of the present invention will be described.

[0053] Figure 7 is a timing diagram for depicting the operation of integrated circuit 10 according to one embodiment of the present invention.

[0054] Reference Figure 7 , the sampling section signal SP is enabled to define the sampling section tSP. The first reference count signal R_CNT1<2:0> and the second reference count signal R_CNT2<2:0> may be initialized to “000”.

[0055] The first pattern generation circuit 120 may output a first pattern signal SOUT1 having randomly generated pulses for a sampling section tSP. The first pattern generation circuit 120 may divide the sampling section tSP into a plurality of coarse sections tCOARSE and generate a first pattern signal SOUT1 having randomly generated pulses for each coarse section tCOARSE, wherein each coarse section tCOARSE has a random period or length.

[0056] The second pattern generation circuit 130 can output a second pattern signal SOUT2 that randomly generates pulses for the sampling section tSP. The second pattern generation circuit 130 can divide the sampling section tSP into a plurality of fine sections tFINE and generate a second pattern signal SOUT2 that randomly generates pulses for each fine section tFINE, where each fine section tFINE has a random period or length that is shorter than the period or length of the coarse section tCOARSE. Therefore, the second pattern generation circuit 130 can generate a second pattern signal SOUT2 that randomly generates pulses with a period shorter than the period of the first pattern signal SOUT1.

[0057] The first segment extraction circuit 140 can randomly select one of the coarse segments tCOARSE based on the first pattern signal SOUT1 and generate a first segment extraction signal SOUT2_M1 by extracting the second pattern signal SOUT2 for the selected coarse segment tCOARSE. Specifically, the first segment control unit 142 can generate a first sampling count signal S_CNT1<2:0> by counting the number of times the first pattern signal SOUT1 is toggled, and generate a first reference count signal R_CNT1<2:0> by counting the number of times the sampling segment signal SP is input. At this time, the first reference count signal R_CNT1<2:0> can increase from "000" to "001" based on the sampling segment signal. The first segment control unit 142 can enable the coarse segment signal MATCH1 when the corresponding bits of the first sampling count signal S_CNT1<2:0> and the first reference count signal R_CNT1<2:0> are identical. The first filter unit 144 may filter the second pattern signal SOUT2 according to the coarse segment signal MATCH1 and generate a first segment extraction signal SOUT2_M1. The first filter unit 144 may output the second pattern signal SOUT2 as the first segment extraction signal SOUT2_M1 for an active segment of the coarse segment signal MATCH1.

[0058] The second segment extraction circuit 150 can select one of the fine segments tFINE based on the first segment extraction signal SOUT2_M1 and generate a second segment extraction signal SOUT2_M2 by extracting the second pattern signal SOUT2 for the selected fine segment tFINE. Specifically, the second segment control unit 152 can generate a second sampling count signal S_CNT2<2:0> by counting the number of times the first segment extraction signal SOUT2_M1 is toggled, and generate a second reference count signal R_CNT2<2:0> by counting the number of times the sampling segment signal SP is input. At this time, the second reference count signal R_CNT2<2:0> can increase from "000" to "010" based on the sampling segment signal. The second segment control unit 152 can enable the fine segment signal MATCH2 when the bits of the second sampling count signal S_CNT2<2:0> and the second reference count signal R_CNT2<2:0> are identical. That is, the active segment of the fine segment signal MATCH2 may be sampled during the active segment of the coarse segment signal MATCH1 . The second filter unit 154 may output the second pattern signal SOUT2 as the second segment extraction signal SOUT2_M2 for the active segment of the fine segment signal MATCH2 .

[0059] The output control circuit 160 can generate a final segment signal FINAL_S that is set according to the sampling segment signal SP and reset according to the second segment extraction signal SOUT2_M2. The output control circuit 160 can output the sampling enable signal SAM_EN by filtering the first segment extraction signal SOUT2_M1 according to the final segment signal FINAL_S. Therefore, the sampling enable signal SAM_EN can be generated based on the second pattern signal SOUT2 that pulses during the selected fine segment tFINE, that is, generated in response to the second segment extraction signal SOUT2_M2.

[0060] Finally, the sampling circuit 200 may generate an output signal OUT by sampling the input signal IN according to the sampling enable signal SAM_EN.

[0061] As described above, the integrated circuit 10 according to one embodiment may include a pattern generation circuit 120 having a longer random sampling section and a pattern generation circuit 130 having a shorter random sampling section. The integrated circuit 10 can perform random sampling by dividing a sampling section tSP into a plurality of coarse sections tCOARSE, selecting one of the coarse sections tCOARSE, and then performing random sampling by dividing the selected coarse section tCOARSE into a plurality of fine sections tFINE. The integrated circuit 10 can sample the input signal based on the sampling results, thereby resolving the periodicity problem of the sampling circuit and maximizing the randomness of the sampling circuit.

[0062] Hereinafter, a memory device will be described as an example of an integrated circuit including a sampling circuit. However, the present invention is not limited thereto and can be applied to any integrated circuit including a sampling circuit for randomly sampling an input address or signal. Furthermore, in the following embodiments, descriptions of configurations related to data input / output operations will be omitted to focus on refresh operations.

[0063] Figure 8 is a block diagram illustrating a storage device 300 according to one embodiment of the present invention. Figure 9 is a diagram illustrating an embodiment of the present invention Figure 8 Detailed configuration diagram of the sampling circuit 336.

[0064] Reference Figure 8 , the memory device 300 may include a memory cell array 310 , a row control circuit 320 , a refresh control circuit 330 , a command input circuit 372 , an address input circuit 374 , a command decoder 376 , and a target command generation circuit 378 .

[0065] The memory cell array 310 may include a plurality of memory cells MC coupled to word lines WL and bit lines. The memory cell array 310 may include a plurality of memory banks. The number of memory banks or the number of memory cells MC may be determined according to the capacity of the memory device 300.

[0066] The command input circuit 372 can receive a command CMD, and the address input circuit 374 can receive an address ADD from an external device, such as a memory controller. The address input circuit 374 can receive the address ADD and output an internal input address IADD. Each of the command CMD and the address ADD can include a multi-bit signal. The command decoder 376 can decode the command CMD input through the command input circuit 372 and generate an active command ACT, a precharge command PCG, and a normal refresh command REF. The command decoder 376 can generate a read command, a write command, and other commands by decoding the received command CMD.

[0067] The target command generation circuit 378 may generate the target refresh command TREF based on the normal refresh command REF. For example, the target command generation circuit 378 may generate the target refresh command TREF whenever the normal refresh command REF is input a preset number of times.

[0068] The refresh control circuit 330 can latch the internal input address IADD as the active address ACT_ADD according to the active command ACT. The refresh control circuit 330 can store a plurality of sampled addresses by randomly sampling the active address ACT_ADD. The refresh control circuit 330 can sequentially output the sampled addresses as the target address TADD according to the target refresh command TREF.

[0069] In detail, the refresh control circuit 330 may include an activation latch 332 , a sampling control circuit 334 , and a sampling circuit 336 .

[0070] The active latch 332 may latch the internal input address IADD as the active address ACT_ADD according to the active command ACT.

[0071] The sampling control circuit 334 can generate a sampling enable signal SAM_EN that is randomly enabled during a target refresh segment. The sampling control circuit 334 can include at least two pattern generation circuits with different periods, and generate a first pattern signal SOUT1 and a second pattern signal SOUT2 that randomly pulse at different periods for the target refresh segment. The sampling control circuit 334 can generate the sampling enable signal SAM_EN based on the first pattern signal SOUT1 and the second pattern signal SOUT2. For reference, the target refresh segment can be determined by a target refresh command TREF, and the target refresh segment can be demarcated by two adjacent target refresh commands TREF. Figure 8 The sampling control circuit 334 may have Figures 1 to 7 The sampling control circuit 100 depicted in FIG. 1 has substantially the same configuration and operation.

[0072] The sampling circuit 336 can store multiple sampled addresses by sampling the active address ACT_ADD according to the active command ACT and the sampling enable signal SAM_EN. When both the active command ACT and the sampling enable signal SAM_EN are enabled, the sampling circuit 336 can store the active address ACT_ADD as one of the sampled addresses. The sampling circuit 336 can sequentially output the stored sampled addresses as the target address TADD according to the target refresh command TREF. According to one embodiment, the sampling circuit 336 can use the stored sampled addresses to calculate one or more adjacent addresses and output the adjacent addresses as the target address TADD.

[0073] Reference Figure 9 , the sampling circuit 336 may include a latch control circuit 410 and a sampling latch circuit 430 .

[0074] The latch control circuit 410 can generate a latch enable signal LAT_EN based on an active command ACT and a sampling enable signal SAM_EN. The latch control circuit 410 can be enabled when both the active command ACT and the sampling enable signal SAM_EN are enabled. The sampling latch circuit 430 can include a plurality of latches L1 to Lk. The sampling latch circuit 430 can store an active address ACT_ADD in the plurality of latches L1 to Lk based on the latch enable signal LAT_EN. Whenever the latch enable signal LAT_EN is enabled, the sampling latch circuit 430 can store the active address ACT_ADD in the latches L1 to Lk as sampling addresses S_ADD1 to S_ADDk, respectively. Whenever a target refresh command TREF is input, the sampling latch circuit 430 can sequentially output any one of the sampling addresses S_ADD1 to S_ADDk stored in the latches L1 to Lk as the target address TADD.

[0075] The row control circuit 320 can activate the word line corresponding to the internal input address IADD in response to the activation of the activation command ACT, and can precharge the activated word line in response to the precharge command PCG. In order to select the word line to be refreshed during the normal refresh operation, a refresh counter (not shown) can be provided to generate a count address that increases sequentially according to the normal refresh command REF. The row control circuit 320 can perform a normal refresh operation of sequentially refreshing multiple word lines WL corresponding to the count address according to the normal refresh command REF. The row control circuit 320 can perform a target refresh operation of refreshing one or more adjacent word lines of the word line WL corresponding to the target address TADD according to the target refresh command TREF.

[0076] Reference Figures 1 to 9 , the operation of the storage device 300 will be described.

[0077] When the normal refresh command REF is input, the refresh counter may generate sequentially increasing count addresses, and the row control circuit 320 may perform a normal refresh operation of sequentially refreshing word lines WL corresponding to the count addresses.

[0078] Whenever the normal refresh command REF is inputted a predetermined number of times, the target command generation circuit 378 may generate a target refresh command TREF. The target refresh command TREF may define a target refresh section.

[0079] The sampling control circuit 334 may generate a sampling enable signal SAM_EN that is randomly enabled during a target refresh section.

[0080] Specifically, the first pattern generation circuit 120 may divide the target refresh section into a plurality of coarse sections tCOARSE and generate a first pattern signal SOUT1 that randomly pulses for each coarse section, wherein each coarse section tCOARSE has a random period or length. The second pattern generation circuit 130 may divide the target refresh section into a plurality of fine sections tFINE and generate a second pattern signal SOUT2 that randomly pulses for each fine section tFINE, wherein each fine section tFINE has a random period or length shorter than the random period or length of each coarse section tCOARSE. Thus, the second pattern generation circuit 130 may generate the second pattern signal SOUT2 that randomly pulses with a period shorter than that of the first pattern signal SOUT1.

[0081] The first sector extraction circuit 140 can randomly select one of the coarse sectors tCOARSE based on the first pattern signal SOUT1 and extract the second pattern signal SOUT2 for the selected coarse sector tCOARSE to generate a first sector extraction signal SOUT2_M1. The second sector extraction circuit 150 can select one of the fine sectors tFINE based on the first sector extraction signal SOUT2_M1 and extract the second pattern signal SOUT2 for the selected fine sector tFINE to generate a second sector extraction signal SOUT2_M2. The output control circuit 160 can generate a final sector signal FINAL_S that is set according to the target refresh command TREF and reset according to the second sector extraction signal SOUT2_M2, and output a sampling enable signal SAM_EN by filtering the first sector extraction signal SOUT2_M1 according to the final sector signal FINAL_S.

[0082] The sampling circuit 336 may store a plurality of sampling addresses S_ADD1 to S_ADDk by sampling the active address ACT_ADD according to the active command ACT and the sampling enable signal SAM_EN, and sequentially output the stored sampling addresses as the target address TADD according to the target refresh command TREF.

[0083] The row control circuit 320 may perform a target refresh operation of refreshing one or more adjacent word lines corresponding to the target address TADD according to the target refresh command TREF.

[0084] As described above, according to one embodiment, a sampling circuit using a dual pattern generation circuit operating at different cycles can be applied to the memory device 300 to sample addresses based on probability and perform a target refresh operation using the sampled addresses. Therefore, the accuracy of address sampling can be maximized, and the efficiency of the target refresh operation can be improved.

[0085] Figure 10A and Figure 10B FIG. 1 is a timing diagram for describing the tendency of a sampling circuit according to the prior art and one embodiment of the present invention.

[0086] Figure 10A This is a timing diagram for depicting the tendency of a sampling circuit using one pattern generation circuit. Figure 10B This is a timing diagram for describing the tendency of a sampling circuit using two pattern generation circuits operating at different cycles. Figure 10A and Figure 10B In FIG. 1 , a sampling circuit will be described by taking an example in which a PRBS-based random pattern generation circuit is configured.

[0087] Reference Figure 10AWhen a pattern generation circuit PRBS1 is used to perform a sampling operation, there is a risk of randomization because the sampling granularity on the time axis during each target refresh segment tREF is not high and thus has a certain tendency.

[0088] In addition, refer to Figure 10B When the sampling operation is performed using two pattern generation circuits PRBS1 and PRBS2 with different resolutions, ie, cycles or periods, the sampling granularity on the time axis during each target refresh segment tREF increases, thereby maximizing randomness.

[0089] Various embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are only used to illustrate the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and many variations are possible within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may be made based on the technical scope of the present disclosure. Multiple embodiments may be combined to form additional embodiments.

[0090] It should be noted that although the technical spirit of the present disclosure has been described in conjunction with the embodiments of the present disclosure, this is for illustrative purposes only and should not be interpreted as limiting. It should be understood by those skilled in the art that various changes may be made thereto without departing from the technical spirit of the present disclosure and the appended claims.

[0091] For example, for the logic gates and transistors provided as examples in the above embodiments, different positions and types may be implemented according to the polarity of the input signal.

Claims

1. An integrated circuit comprising: a first pattern generating circuit adapted to generate a first pattern signal having pulses randomly generated for a sampling section; a second pattern generating circuit adapted to generate a second pattern signal having pulses randomly generated for the sampling section; a first segment control section adapted to generate a coarse segment signal enabled for a first segment of the sampling segment according to the first pattern signal; a first filtering section adapted to generate a first segment extraction signal by filtering the second pattern signal according to the coarse segment signal; a second segment control unit adapted to generate a fine segment signal enabling a second segment of the sampling segment according to the first segment extraction signal; a second filtering section adapted to generate a second segment extraction signal by filtering the second pattern signal according to the fine segment signal; an output control circuit adapted to generate a sampling enable signal according to the first section extraction signal and the second section extraction signal; as well as The sampling circuit is adapted to sample the input signal according to the sampling enable signal.

2. The integrated circuit according to claim 1, wherein: The second pattern signal randomly generates pulses at a cycle shorter than that of the first pattern signal.

3. The integrated circuit according to claim 1, wherein: Each of the first pattern generating circuit and the second pattern generating circuit includes one selected from a random pattern generator based on a linear feedback shift register (LFSR) and a random pattern generator based on a pseudo-random binary sequence (PRBS).

4. The integrated circuit according to claim 1, wherein: Each of the first pattern generating circuit and the second pattern generating circuit includes a uniform random number sequence generator configured to generate a pattern signal in which pulses are randomly generated the same number of times within a specific period.

5. The integrated circuit according to claim 1, wherein: The first section control unit includes: a first random counter, adapted to generate a first sampling count signal by counting the number of times the first pattern signal is triggered; a first reference counter adapted to generate a first reference count signal by counting the number of times a sampling section signal for defining the sampling section is input; and A first comparator is adapted to output the coarse segment signal by comparing the first sample count signal with the first reference count signal.

6. The integrated circuit according to claim 1, wherein: The first filtering section includes a logic circuit adapted to perform a logical AND operation on the second pattern signal and the coarse segment signal.

7. The integrated circuit according to claim 1, wherein: The second section control unit includes: a second random counter, adapted to generate a second sampling count signal by counting the number of times the first section extraction signal is triggered; a second reference counter adapted to generate a second reference count signal by counting the number of times a sampling section signal for defining the sampling section is input; and A second comparator is adapted to output the fine segment signal by comparing the second sampling count signal with the second reference count signal.

8. The integrated circuit according to claim 1, wherein: The second filtering section includes a logic circuit adapted to perform a logical AND operation on the second pattern signal and the fine segment signal.

9. The integrated circuit according to claim 1, wherein: The output control circuit includes: a set-reset SR latch adapted to generate a final segment signal that is set according to a sampling segment signal for defining the sampling segment and is reset according to the second segment extraction signal; and The third filtering section is adapted to output the sampling enable signal by filtering the first section extraction signal according to the final section signal.

10. A method for operating an integrated circuit, comprising: Divide the sampling area into multiple coarse areas; generating a first pattern signal of randomly occurring pulses for each of the coarse segments; Dividing the sampling segment into a plurality of fine segments; generating a second pattern signal having randomly occurring pulses for each of the fine segments; randomly selecting one of the coarse segments; randomly selecting one of the fine segments for the selected coarse segment; generating a sampling enable signal according to the second pattern signal pulsed for the selected fine segment; as well as The input signal is sampled according to the sampling enable signal.

11. The operating method according to claim 10, in, Each of the coarse segment and the fine segment has a random period, and The random period of each of the fine segments is shorter than the random period of each of the coarse segments.

12. The operating method according to claim 10, wherein: Each of the first pattern signal and the second pattern signal randomly generates pulses the same number of times within a specific period.

13. The operating method according to claim 10, wherein: The randomly selecting one of the coarse segments comprises: generating a first sampling count signal by counting the number of times the first pattern signal is triggered; generating a first reference count signal by counting the number of times a sampling section signal for defining the sampling section is input; comparing the first sample count signal with the first reference count signal; and One of the coarse segments is selected according to a result of the comparison.

14. The operating method according to claim 10, wherein: The randomly selecting one of the fine segments for the selected coarse segment comprises: generating a first segment extraction signal by filtering the second pattern signal with respect to the selected coarse segment; generating a second sampling count signal by counting the number of times the first section extraction signal is triggered; generating a second reference count signal by counting the number of times a sampling section signal for defining the sampling section is input; comparing the second sampled count signal with the second reference count signal; and One of the fine segments is selected according to a result of the comparison.

15. The operating method according to claim 14, wherein: Generating a sampling enable signal according to the second pattern signal includes: generating a second segment extraction signal by filtering the second pattern signal with respect to the selected fine segment; generating a final segment signal, the final segment signal being set according to the sampled segment signal and being reset according to the second segment extraction signal; and The sampling enable signal is output by filtering the first section extraction signal according to the final section signal.

16. A storage device comprising: a first pattern generating circuit adapted to divide a target refresh section into a plurality of coarse sections and to generate a first pattern signal of randomly occurring pulses for each of the coarse sections; a second pattern generating circuit adapted to divide the target refresh section into a plurality of fine sections and to generate a second pattern signal of randomly occurring pulses for each of the fine sections; a first section extraction circuit adapted to generate a first section extraction signal by extracting the second pattern signal for a coarse section randomly selected from the coarse sections according to the first pattern signal; a second section extraction circuit adapted to generate a second section extraction signal by extracting the second pattern signal for a fine section randomly selected from the fine sections according to the first section extraction signal; an output control circuit adapted to generate a sampling enable signal according to the first section extraction signal and the second section extraction signal; as well as A sampling circuit is adapted to output a target address by sampling an active address according to the sampling enable signal.

17. The storage device according to claim 16, wherein: The second pattern signal randomly generates pulses at a cycle shorter than that of the first pattern signal.

18. The storage device according to claim 16, wherein: Each of the first pattern generating circuit and the second pattern generating circuit includes a uniform random number sequence generator configured to generate a pattern signal in which pulses are randomly generated the same number of times within a specific period. 19 . The memory device of claim 16 , further comprising a row control circuit adapted to refresh one or more adjacent word lines of a word line corresponding to the target address according to a target refresh command defining the target refresh section.

20. The storage device according to claim 16, wherein The sampling circuit comprises: a latch control circuit adapted to generate a latch enable signal according to an activation command and the sampling enable signal; and The sampling latch circuit is adapted to store the active address as a plurality of sampling addresses according to the latch enable signal, and output the sampling address as the target address according to a target refresh command for defining the target refresh section.

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