Etching method for gallium nitride device contact hole
By combining inductively coupled plasma and high-density plasma etching, the etching problem of ohmic contact holes in AlGaN/GaN high electron mobility transistor devices was solved, forming ohmic contact holes with high selectivity and low damage, thus improving ohmic contact performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2023-03-07
- Publication Date
- 2026-08-04
AI Technical Summary
Existing technologies make it difficult to form ohmic contact holes with high etch selectivity, low damage, uniform surface, and good stability in AlGaN/GaN high electron mobility transistor devices.
A combination of inductively coupled plasma etching and high-density plasma etching is used to first form grooves and etch the interlayer dielectric layer, and then fill them with conductive material to form ohmic contact holes.
This achieves high selectivity, low damage, and low cost for ohmic contact holes, thus improving ohmic contact performance.
Smart Images
Figure CN116230516B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to an etching method for contact holes in gallium nitride devices. Background Technology
[0002] Ohmic contacts, a type of metal-semiconductor contact, primarily form the source and drain electrodes in semiconductor devices. The performance of ohmic contacts directly affects the output current and knee voltage of the device; therefore, ohmic contact fabrication technology has always been a key research focus in semiconductor processing. In AlGaN / GaN high electron mobility transistor (HEP) devices, improving the ohmic contact is a core process in device fabrication, significantly impacting device performance, in order to limit scattering. Therefore, it is necessary to improve the ohmic contact fabrication process for AlGaN / GaN HEP transistors, especially the etching process for ohmic contact holes, to create ohmic contact holes with high etch selectivity, low damage, surface uniformity, and good stability.
[0003] To address the aforementioned issues, a novel etching method for gallium nitride device contact holes needs to be proposed. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an etching method for gallium nitride device contact holes, which solves the problem that it is difficult to form ohmic contact holes with high etching selectivity, low damage, uniform surface and good stability in the existing ohmic contact fabrication process of high electron mobility transistor devices.
[0005] To achieve the above and other related objectives, the present invention provides a method for etching contact holes in gallium nitride devices, comprising:
[0006] Step 1: Provide a substrate on which a GaN epitaxial layer and a barrier layer are formed;
[0007] Step 2: Form an interlayer dielectric layer covering the barrier layer on the substrate, form a photoresist layer on the interlayer dielectric layer, and use photolithography to open the photoresist layer, so that the interlayer dielectric layer in a certain area is exposed to define the formation area of the contact hole.
[0008] Step 3: Use inductively coupled plasma etching to etch the exposed interlayer dielectric layer to form a groove, so that the thickness of the interlayer dielectric layer at the bottom of the groove is a preset value;
[0009] Step 4: Use high-density plasma etching to etch the interlayer dielectric layer at the bottom of the groove, so that the barrier layer is exposed;
[0010] Step 5: Fill the groove with a conductive material.
[0011] Preferably, the substrate in step one is a silicon substrate.
[0012] Preferably, a buffer layer is formed between the GaN epitaxial layer and the substrate in step one.
[0013] Preferably, the material of the buffer layer in step one is AlxGaN.
[0014] Preferably, the material of the barrier layer in step one is AlGaN.
[0015] Preferably, the material of the interlayer dielectric layer in step two is one of silicon dioxide, silicon nitride, and aluminum oxide.
[0016] Preferably, the inductively coupled plasma etching process conditions in step three include: an RF source, an etching gas, and a carrier gas. Plasma is generated by the RF source and the carrier gas and etching gas flowing into the etching cavity, with an ionization rate of 0.01% and a plasma energy greater than 102 eV.
[0017] Preferably, the preset value in step three is 30 to 50 nanometers.
[0018] Preferably, the high-density plasma etching process conditions in step four include: a microwave source, an etching gas, and a carrier gas. Plasma is generated by the microwave source and the carrier gas and etching gas flowing into the etching cavity, with an ionization rate of 1% and a plasma energy of 1 to 15 eV.
[0019] Preferably, the conductive material in step five is tungsten.
[0020] As described above, the etching method for gallium nitride device contact holes of the present invention has the following beneficial effects:
[0021] The method of the present invention can obtain ohmic contact holes with good morphology and has the characteristics of high selectivity, low damage and low cost, which is beneficial to the filling of ohmic metal and the improvement of ohmic contact performance. Attached Figure Description
[0022] Figure 1 The diagram shown is a schematic representation of the process flow of the present invention.
[0023] Figure 2 The diagram shows the substrate of the present invention and the GaN epitaxial layer and barrier layer thereon.
[0024] Figure 3 The diagram shown is a schematic diagram of the first etching of the interlayer dielectric layer in this invention.
[0025] Figure 4This is a schematic diagram of the interlayer dielectric layer etched in the second etching step of the present invention.
[0026] Figure 5 The diagram shown is a schematic of the present invention, illustrating the filling of contact holes with conductive material. Detailed Implementation
[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0028] Please see Figure 1 This invention provides a method for etching contact holes in gallium nitride devices, comprising:
[0029] Step 1, please refer to Figure 2 A substrate 101 is provided, on which a GaN epitaxial layer 103 and a barrier layer 104 are formed; this is typically used in high electron mobility transistors (HEMTs). This is a heterojunction field-effect transistor, also known as a modulation-doped field-effect transistor (MODFET), a two-dimensional electron gas field-effect transistor (2-DEGFET), a selectively doped heterojunction transistor (SDHT), etc.
[0030] In one alternative embodiment, the substrate 101 in step one is a silicon substrate.
[0031] In an optional embodiment, a buffer layer 102 is further formed between the GaN epitaxial layer 103 and the substrate 101 in step one, and the material of the buffer layer 102 may be AlxGaN.
[0032] In one alternative implementation, the barrier layer 104 in step one is made of AlGaN.
[0033] Step 2: Form an interlayer dielectric layer 105 covering the barrier layer 104 on the substrate 101, and form a photoresist layer (not shown in the figure) on the interlayer dielectric layer 105. Use photolithography (exposure, development, vertical film, baking, etc.) to open the photoresist layer, so that the interlayer dielectric layer 105 in some areas is exposed to define the formation area of the contact hole.
[0034] In one optional embodiment, the material of the interlayer dielectric layer 105 in step two is one of silicon dioxide, silicon nitride, and aluminum oxide, or other materials known to those skilled in the art whose dielectric constant meets the actual process requirements, without being specifically limited here.
[0035] Step 3, please refer to Figure 3 The exposed interlayer dielectric layer 105 is etched using inductively coupled plasma etching to form a groove, so that the thickness of the interlayer dielectric layer 105 at the bottom of the groove is a preset value.
[0036] In one optional implementation, the inductively coupled plasma etching process conditions in step three include: an RF source, an etching gas, and a carrier gas. Plasma is generated by the RF source and the carrier gas and etching gas flowing into the etching cavity, with an ionization rate of 0.01% and a plasma energy greater than 102 eV.
[0037] Commonly used carrier gases include hydrogen, helium, nitrogen, argon, and carbon dioxide. The etching gas must be selected based on the material of the interlayer dielectric layer 105. For example, for quartz, there are many gas options, such as CF4, CF4+H2, and CHF3. Using CHF3 as the etching gas for quartz, the reaction process can be represented as: CHF3 + e → CHF+2 + F (free radical) + 2e, SiO2 + 4FSiF4 (gas) + O2 (gas). The oxygen ions released from the decomposition of SiO2 react with the CHF+2 groups under high pressure to generate various volatile gases such as CO↑, CO2↑, H2O↑, and OF↑. In etching gas operation, the interlayer dielectric layer 105 and the barrier layer should have a high selectivity. High selectivity means that only the layer of material to be etched is removed. A high-selectivity etching process does not etch the underlying material (it stops when the etching reaches an appropriate depth) and the protective photoresist is also not etched. In one alternative implementation, the preset value in step three is 30 to 50 nanometers, for example, 30 nanometers, 35 nanometers, 40 nanometers, 45 nanometers, or 50 nanometers.
[0038] Step 4, please refer to Figure 4 The interlayer dielectric layer 105 at the bottom of the groove is etched using a high-density plasma etching method, exposing the barrier layer 104, after which the remaining photoresist layer can be removed.
[0039] In one optional embodiment, the high-density plasma etching process conditions in step four include: a microwave source, an etching gas, and a carrier gas. Plasma is generated by the microwave source and the carrier gas and etching gas flowing into the etching cavity, with an ionization rate of 1% and a plasma energy of 1 to 15 eV.
[0040] Commonly used carrier gases include hydrogen, helium, nitrogen, argon, and carbon dioxide. The etching gas must be selected based on the material of the interlayer dielectric layer 105. For example, for quartz, there are many gas options, such as CF4, CF4+H2, and CHF3. Using CHF3 as the etching gas for quartz, the reaction process can be represented as: CHF3 + e → CHF+2 + F (free radical) + 2e, SiO2 + 4FSiF4 (gas) + O2 (gas). The oxygen ions released from the decomposition of SiO2 react with the CHF+2 groups under high pressure to generate various volatile gases such as CO↑, CO2↑, H2O↑, and OF↑. In etching gas operation, the interlayer dielectric layer 105 and the barrier layer should have a high selectivity. High selectivity means that only the layer of material to be etched is removed. A high-selectivity etching process does not etch the underlying material (it stops when the etching reaches an appropriate depth) and the protective photoresist is also not etched.
[0041] Step 5, please refer to Figure 5 The groove is filled with conductive material 106 to form a conductive structure that is electrically connected to the source and drain terminals.
[0042] In one optional embodiment, the conductive material 106 in step five is tungsten. It should be noted that the conductive material 106 can also be any material well-known to those skilled in the art, and no specific limitation is made here.
[0043] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0044] In summary, the method of this invention can obtain ohmic contact holes with good morphology and features high selectivity, low damage, and low cost, which is beneficial for the filling of ohmic metals and the improvement of ohmic contact performance. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0045] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for etching contact holes in a gallium nitride device, characterized in that, At least including: Step 1: Provide a substrate on which a GaN epitaxial layer and a barrier layer are formed; Step 2: Form an interlayer dielectric layer covering the barrier layer on the substrate, form a photoresist layer on the interlayer dielectric layer, and use photolithography to open the photoresist layer, so that the interlayer dielectric layer in a certain area is exposed to define the formation area of the contact hole. Step 3: Use inductively coupled plasma etching to etch the exposed interlayer dielectric layer to form a groove, so that the thickness of the interlayer dielectric layer at the bottom of the groove is a preset value; the inductively coupled plasma etching process conditions include: RF source, etching gas and carrier gas, plasma is generated by the RF source and the carrier gas and etching gas flowing into the etching chamber, the ionization rate is 0.01% and the plasma energy is greater than 102 eV; Step 4: Use high-density plasma etching to etch the interlayer dielectric layer at the bottom of the groove, so that the barrier layer is exposed; the high-density plasma etching process conditions include: microwave source, etching gas and carrier gas, plasma is generated by the microwave source and the carrier gas and etching gas flowing into the etching cavity, the ionization rate is 1% and the plasma energy is 1 to 15 eV. Step 5: Fill the groove with a conductive material.
2. The etching method for gallium nitride device contact holes according to claim 1, characterized in that: The substrate mentioned in step one is a silicon substrate.
3. The etching method for gallium nitride device contact holes according to claim 1, characterized in that: A buffer layer is also formed between the GaN epitaxial layer and the substrate in step one.
4. The etching method for gallium nitride device contact holes according to claim 3, characterized in that: The material of the buffer layer in step one is AlxGaN.
5. The etching method for gallium nitride device contact holes according to claim 1, characterized in that: The material of the barrier layer in step one is AlGaN.
6. The etching method for contact holes of gallium nitride devices according to claim 1, characterized in that: The material of the interlayer dielectric layer in step two is one of silicon dioxide, silicon nitride, and aluminum oxide.
7. The etching method for gallium nitride device contact holes according to claim 1, characterized in that: The preset value in step three is 30 to 50 nanometers.
8. The etching method for gallium nitride device contact holes according to claim 1, characterized in that: The conductive material in step five is tungsten.