Array substrate and display panel

Abstract

This invention discloses an array substrate and a display panel. The array substrate includes: a first signal line and a second signal line on the same layer; along a direction perpendicular to the plane of the substrate, the active layer of at least one first sub-pixel does not overlap with the second signal line, and the active layer of at least one second sub-pixel does not overlap with the second signal line; within a preset voltage range, the data writing voltage of at least one first sub-pixel is equal to the data writing voltage of at least one second sub-pixel, avoiding charging differences between the first and second sub-pixels, which would cause differences in display brightness between the first and second sub-pixels, thus improving the problem of poor dark lines and enhancing the display effect.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to an array substrate and a display panel. Background Technology

[0002] With the development of display technology, display devices with display panels have become an indispensable tool for people's lives and work. As the application of display panels becomes more and more widespread, cost reduction also needs to be considered when manufacturing display panels.

[0003] In existing technologies, cost reduction by decreasing the manufacturing process of array substrates has been gradually promoted in the market. However, there are problems with reducing the manufacturing process of zig-zag array substrates. When the manufacturing process of zig-zag array substrates is reduced, the common signal lines and data lines are located on the same layer. The common signal lines will overlap with the active layer of some sub-pixels to form capacitance, which will affect the data writing of these sub-pixels, resulting in a deterioration of the display effect of these sub-pixels and causing uneven display of the display panel.

[0004] Therefore, there is an urgent need for an array substrate design that can avoid affecting the writing of sub-pixel data. Summary of the Invention

[0005] In view of this, the present invention provides an array substrate and a display panel.

[0006] On one hand, the present invention provides an array substrate, comprising:

[0007] Substrate;

[0008] The sub-pixels are arranged in an array on one side of the substrate. The sub-pixels are arranged along a first direction to form sub-pixel rows and along a second direction to form sub-pixel columns. The second direction intersects the first direction. The sub-pixel rows include alternating first and second sub-pixel rows arranged along the second direction. The sub-pixel columns include adjacent first and second sub-pixel columns. The sub-pixels include first and second sub-pixels. The first sub-pixel is located in the first sub-pixel row and in the second sub-pixel column. The second sub-pixel is located in the second sub-pixel row and in the first sub-pixel column.

[0009] A first signal line is located on one side of the substrate and between the first sub-pixel column and the second sub-pixel column. The active layer of the first sub-pixel and the active layer of the second sub-pixel are connected to the first signal line.

[0010] The second signal line is on the same layer as the first signal line. The second signal line is at least partially located between the first sub-pixel column and the second sub-pixel column. Along a direction perpendicular to the plane where the substrate is located, the active layer of at least one first sub-pixel does not overlap with the second signal line, and the active layer of at least one second sub-pixel does not overlap with the second signal line.

[0011] Within a preset voltage range, the data write voltage of at least one first sub-pixel is equal to the data write voltage of at least one second sub-pixel.

[0012] On the other hand, the present invention provides an array substrate, comprising:

[0013] Substrate;

[0014] The sub-pixels are arranged in an array on one side of the substrate. The sub-pixels are arranged along a first direction to form sub-pixel rows and along a second direction to form sub-pixel columns. The second direction intersects the first direction. The sub-pixel rows include alternating first and second sub-pixel rows arranged along the second direction. The sub-pixel columns include adjacent first and second sub-pixel columns. The sub-pixels include first and second sub-pixels. The first sub-pixel is located in the first sub-pixel row and in the second sub-pixel column. The second sub-pixel is located in the second sub-pixel row and in the first sub-pixel column.

[0015] A first signal line is located on one side of the substrate and between the first sub-pixel column and the second sub-pixel column. The active layer of the first sub-pixel and the active layer of the second sub-pixel are connected to the first signal line.

[0016] The second signal line is on the same layer as the first signal line. The second signal line is at least partially located between the first sub-pixel column and the second sub-pixel column. Along a direction perpendicular to the plane where the substrate is located, the active layer of at least one first sub-pixel partially overlaps with the second signal line, and the active layer of at least one second sub-pixel partially overlaps with the second signal line.

[0017] Within a preset voltage range, the data write voltage of at least one first sub-pixel is equal to the data write voltage of at least one second sub-pixel.

[0018] In another aspect, the present invention provides a display panel comprising any of the array substrates described above.

[0019] Compared with the prior art, the array substrate provided by the present invention achieves at least the following beneficial effects:

[0020] The array substrate provided by the present invention includes: a substrate; sub-pixels arranged in an array, located on one side of the substrate, the sub-pixels being arranged along a first direction to form sub-pixel rows and along a second direction to form sub-pixel columns, the second direction intersecting the first direction, the sub-pixel rows including alternating first sub-pixel rows and second sub-pixel rows along the second direction, the sub-pixel columns including adjacent first sub-pixel columns and second sub-pixel columns; sub-pixels including first sub-pixels and second sub-pixels, the first sub-pixels being located in the first sub-pixel rows and in the second sub-pixel columns, the second sub-pixels being located in the second sub-pixel rows and in the first sub-pixel columns; a first signal line located on one side of the substrate and between the first sub-pixel columns and the second sub-pixel columns, the active layers of the first sub-pixels and the second sub-pixels being connected to the first signal line; and a second signal line on the same layer as the first signal line, the second signal line being at least partially located between the first sub-pixel columns and the second sub-pixel columns. Between pixel columns, having the second signal line and the first signal line on the same layer reduces manufacturing processes and lowers costs. Along a direction perpendicular to the plane of the substrate, the active layer of at least one first sub-pixel does not overlap with the second signal line, and the active layer of at least one second sub-pixel does not overlap with the second signal line. This means that the active layer of at least one first sub-pixel will not form a capacitor with the second signal line, and vice versa. This prevents the data writing voltage of at least one first sub-pixel and at least one second sub-pixel from being interfered with by capacitance. Within a preset voltage range, the data writing voltage of at least one first sub-pixel is equal to that of at least one second sub-pixel, avoiding charging differences between the first and second sub-pixels that could lead to differences in display brightness. This improves the problem of poor dark lines and enhances the display effect.

[0021] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0022] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0024] Figure 1 This is a schematic diagram of the structure of an array substrate in the prior art;

[0025] Figure 2 This is a schematic diagram of a structure of an array substrate provided by the present invention;

[0026] Figure 3 This is a schematic diagram of another structure of the array substrate provided by the present invention;

[0027] Figure 4 This is another structural schematic diagram of the array substrate provided by the present invention;

[0028] Figure 5 yes Figure 3 Cross-sectional view along line A-A';

[0029] Figure 6 This is another structural schematic diagram of the array substrate provided by the present invention;

[0030] Figure 7 yes Figure 6 Cross-sectional view along line B-B';

[0031] Figure 8 This is another structural schematic diagram of the array substrate provided by the present invention;

[0032] Figure 9 This is another structural schematic diagram of the array substrate provided by the present invention;

[0033] Figure 10 This is another structural schematic diagram of the array substrate provided by the present invention;

[0034] Figure 11 This is another structural schematic diagram of the array substrate provided by the present invention;

[0035] Figure 12 yes Figure 10 Cross-sectional view along the C-C' direction;

[0036] Figure 13 This is a schematic diagram of a display panel provided by the present invention. Detailed Implementation

[0037] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0038] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0039] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0040] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0041] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0042] To address the issue of capacitance generated by the overlap between the common signal lines and the active layers of some sub-pixels after reducing the fabrication process of the array substrate, which affects the charging of these sub-pixels, the inventors conducted the following research on the array substrate in related technologies:

[0043] Figure 1 This is a schematic diagram of the structure of an array substrate in the prior art. The array substrate 000 in the prior art includes:

[0044] Substrate 1';

[0045] The sub-pixels 2' are arranged in an array and located on one side of the substrate 1'. The sub-pixels 2' are arranged along the first direction X to form a sub-pixel row 3' and along the second direction Y to form a sub-pixel column 4'. The second direction Y intersects the first direction X. The sub-pixel row 3' includes a first sub-pixel row 5' and a second sub-pixel row 6' arranged alternately along the second direction Y. The sub-pixel column 4' includes an adjacent first sub-pixel column 7' and a second sub-pixel column 8'.

[0046] The first signal line 9' is located on one side of the substrate 1' along the first direction X. A sub-pixel column 4' is included between two adjacent first signal lines 9'. The active layer 13' of the sub-pixel 2' located in the first sub-pixel row 5' is electrically connected to the first signal line 9' adjacent to its left. The active layer 13' of the sub-pixel 2' located in the second sub-pixel row 6' is electrically connected to the first signal line 9' adjacent to its right.

[0047] The second signal line 10' is on the same layer as the first signal line 9' and is located between the first sub-pixel column 7' and the second sub-pixel column 8'.

[0048] It is understandable that sub-pixel 2' includes first sub-pixel 11' and second sub-pixel 12'. First sub-pixel 11' is located in first sub-pixel row 5' and second sub-pixel column 8', and second sub-pixel 12' is located in second sub-pixel row 6' and first sub-pixel column 7'. Figure 1The diagram only shows the second signal line 10' located between the first sub-pixel column 7' and the first signal line 9'. Of course, it is not limited to this. The second signal line 10' may also be located between the first signal line 9' and the second sub-pixel column 8'. Taking the second signal line 10' located between the first sub-pixel column 7' and the first signal line 9' as an example, the active layer 13' of the second signal line 10' and the second sub-pixel 12' overlaps to form a capacitor. The capacitor affects the data writing stage of the second sub-pixel 12', causing the data writing voltage of the second sub-pixel 12' to decrease. However, the active layer 13' of the second signal line 10' and the first sub-pixel 11' will not overlap to form a capacitor, so the data writing voltage of the first sub-pixel 11' does not change. This results in unequal data writing voltages between the first sub-pixel 11' and the second sub-pixel 12', causing a difference in the light emission brightness between the first sub-pixel 11' and the second sub-pixel 12', resulting in poor display effect.

[0049] In view of this, the present invention provides an array substrate and a display panel. Specific embodiments of the array substrate and display panel provided by the present invention will be described in detail below.

[0050] Reference Figure 2 , Figure 2 This is a schematic diagram of an array substrate provided by the present invention, illustrating a specific embodiment of the array substrate 100 provided by the present invention, including:

[0051] Substrate 1;

[0052] The sub-pixels 2 are arranged in an array and located on one side of the substrate 1. The sub-pixels 2 are arranged along the first direction X to form sub-pixel rows 3 and along the second direction Y to form sub-pixel columns 4. The second direction Y intersects the first direction X. The sub-pixel rows 3 include first sub-pixel rows 5 and second sub-pixel rows 6 arranged alternately along the second direction Y. The sub-pixel columns 4 include adjacent first sub-pixel columns 7 and second sub-pixel columns 8. The sub-pixels 2 include first sub-pixels 11 and second sub-pixels 12. The first sub-pixels 11 are located in the first sub-pixel row 5 and in the second sub-pixel column 8. The second sub-pixels 12 are located in the second sub-pixel row 6 and in the first sub-pixel column 7.

[0053] The first signal line 9 is located on one side of the substrate 1 and between the first sub-pixel column 7 and the second sub-pixel column 8. The active layer 13 of the first sub-pixel 11 and the active layer 13 of the second sub-pixel 12 are connected to the first signal line 9.

[0054] The second signal line 10 is on the same layer as the first signal line 9. The second signal line 10 is at least partially located between the first sub-pixel column 7 and the second sub-pixel column 8. Along the direction perpendicular to the plane of the substrate 1, the active layer 13 of at least one first sub-pixel 11 does not overlap with the second signal line 10, and the active layer 13 of at least one second sub-pixel 12 does not overlap with the second signal line 10.

[0055] Within a preset voltage range, the data write voltage of at least one first sub-pixel 11 is equal to the data write voltage of at least one second sub-pixel 12.

[0056] It should be noted that, in Figure 2 The diagram only illustrates sub-pixel 2 located in the first sub-pixel row 5. The active layer 13 of sub-pixel 2 is electrically connected to the first signal line 9 adjacent to its left. Sub-pixel 2 located in the second sub-pixel row 6 has its active layer 13 electrically connected to the first signal line 9 adjacent to its right, forming a ziazag structure. However, this is not limited to this; it could also be sub-pixel 2 located in the first sub-pixel row 5 with its active layer 13 electrically connected to the first signal line 9 adjacent to its right, and sub-pixel 2 located in the second sub-pixel row 6 with its active layer 13 electrically connected to the first signal line 9 adjacent to its left. The first signal line 9 is electrically connected. Of course, the number and arrangement of sub-pixels 2 can also be adjusted according to actual needs. This embodiment does not make specific limitations on this. Sub-pixels 2 include thin film transistors. Thin film transistors include active layer 13 and gate (not shown in the figure). The gate is electrically connected to gate line 133. Active layer 13 includes channel 132, source (not shown in the figure), and drain 131. One end of channel 132 is electrically connected to the source and the other end is electrically connected to the drain 131. The source is electrically connected to the first signal line 9 and the drain 131 is electrically connected to the pixel electrode.

[0057] Understandably, the preset voltage range can be set to ±5% of the standard voltage value; however, it is not limited to this and can be adjusted according to actual needs. Figure 2 The diagram only shows the array substrate 100, which includes a first region 14 and a second region 15. In the first region 14, the second signal line 10 is located between the first sub-pixel column 7 and the first signal line 9. The second signal line 10 overlaps with the active layer 13 of the second sub-pixel 12, generating capacitance and affecting the data writing voltage of the second sub-pixel 12. In the second region 15, the second signal line 10 is partially located between the first sub-pixel column 7 and the first signal line 9. To avoid the second signal line 10 overlapping with the second sub-pixel 12 and generating capacitance, the second signal line 10 is wound. This ensures that the data writing voltage of the second sub-pixel 12 is equal or approximately equal to that of the first sub-pixel 11, avoiding charging differences between the first sub-pixel 11 and the second sub-pixel 12. This ensures that the luminous brightness of the sub-pixel 2 in the second region 15 is equal or approximately equal, avoiding dark lines and improving the display effect.

[0058] Specifically, one end of the first signal line 9 is electrically connected to the driver chip 31. The first region 14 is located on the side of the second region 15 closer to the driver chip 31. Due to the voltage drop during the transmission of the data writing voltage along the first signal line 9, and because the second region 15 is located on the side of the first region 14 further away from the driver chip 31, the voltage drop in the second region 15 is greater. This may cause the second signal line 10 and the active layer 13 of the second sub-pixel 12 to overlap and generate capacitance within the first region 14, but this has a smaller impact on the data writing voltage of the second sub-pixel 12, resulting in a smaller difference in luminance between the second sub-pixel 12 and the first sub-pixel 11. However, within the second region 15, the active layer 13 of the second signal line 10 overlaps with the active layer 13 of the second sub-pixel 12, generating capacitance. There is a large voltage drop when the data writing voltage is transmitted along the first signal line 9. The capacitance generated by the overlap of the second signal line 10 and the second sub-pixel 12 further affects the data writing voltage of the second sub-pixel 12. Therefore, the brightness of the second sub-pixel 12 is greatly reduced, affecting the display effect. The second signal line 10 can be set to only wrap within the second region 15 to improve the brightness of the second sub-pixel 12 within the second region 15, so as to improve the overall effect. Of course, it is not limited to this. The array substrate 100 may also include multiple regions. The winding position and shape of the second signal line 10 can be adjusted according to actual needs. This embodiment does not impose specific limitations on this.

[0059] Compared with the prior art, the array substrate 100 provided in this embodiment has at least the following advantages:

[0060] The array substrate 100 provided by the present invention includes: a substrate 1; sub-pixels 2 arranged in an array, located on one side of the substrate 1, the sub-pixels 2 arranged along a first direction X to form sub-pixel rows 3, and arranged along a second direction Y to form sub-pixel columns 4, the second direction Y intersecting the first direction X, the sub-pixel rows 3 including first sub-pixel rows 5 and second sub-pixel rows 6 arranged alternately along the second direction Y, the sub-pixel columns 4 including adjacent first sub-pixel columns 7 and second sub-pixel columns 8; the sub-pixels 2 include first sub-pixels 11 and second sub-pixels 12, the first sub-pixels 11 being located in the first sub-pixel row 5 and in the second sub-pixel column 8, the second sub-pixels 12 being located in the second sub-pixel row 6 and in the first sub-pixel column 7; a first signal line 9, located on one side of the substrate 1 and between the first sub-pixel column 7 and the second sub-pixel column 8, the active layer 13 of the first sub-pixels 11 and the active layer 13 of the second sub-pixels 12 being connected to the first signal line 9; and a second signal line 10, on the same layer as the first signal line 9, the second signal line 10 being at least partially located in the first sub-pixel column 7. Between the second sub-pixel column 8 and the first signal line 9, the second signal line 10 is on the same layer, which can reduce the manufacturing process and lower costs. Along the direction perpendicular to the plane of the substrate 1, the active layer 13 of at least one first sub-pixel 11 does not overlap with the second signal line 10, and the active layer 13 of at least one second sub-pixel 12 does not overlap with the second signal line 10. That is, the active layer 13 of at least one first sub-pixel 11 will not form a capacitor with the second signal line 10, and the active layer 13 of at least one second sub-pixel 12 will not form a capacitor with the second signal line 10. This ensures that the data writing voltage of at least one first sub-pixel 11 and at least one second sub-pixel 12 will not be interfered with by the capacitor. Within a preset voltage range, the data writing voltage of at least one first sub-pixel 11 is equal to the data writing voltage of at least one second sub-pixel 12. This avoids charging differences between the first sub-pixel 11 and the second sub-pixel 12, which would cause differences in display brightness between the first sub-pixel 11 and the second sub-pixel 12. This improves the problem of poor dark lines and enhances the display effect.

[0061] In some alternative embodiments, refer to Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of another structure of the array substrate provided by the present invention. Figure 4 This is another structural schematic diagram of the array substrate provided by the present invention. The second signal line 10 includes a first part 16 and a second part 17 connected to each other. The second part 17 includes a first sub-part 18, a second sub-part 19 and a third sub-part 20 connected to each other.

[0062] When the first part 16 is located between the first sub-pixel column 7 and the first signal line 9, the second sub-part 19 is located on the side of the drain 131 of the second sub-pixel 12 away from the first signal line 9. One end of the first sub-part 18 is connected to the second sub-part 19 and the other end is connected to the first part 16. One end of the third sub-part 20 is connected to the end of the second sub-part 19 away from the first sub-part 18.

[0063] When the first part 16 is located between the first signal line 9 and the second sub-pixel column 8, the second sub-part 19 is located on the side of the drain 131 of the first sub-pixel 11 away from the first signal line 9. One end of the first sub-part 18 is connected to the second sub-part 19 and the other end is connected to the first part 16. One end of the third sub-part 20 is connected to the end of the second sub-part 19 away from the first sub-part 18.

[0064] It is understandable that the first part, 16, extends along the second direction, Y. Figure 3 The diagram only shows the first part 16 located between the first sub-pixel column 7 and the first signal line 9. Figure 4 The diagram only shows the first part 16 located between the first signal line 9 and the second sub-pixel column 8. The first part 16 extends along the second direction Y. The first part 16 does not overlap with the active layer 13 of the sub-pixel 2. The second part 17 is a winding portion. The length and winding direction of the second part 17 can be adjusted according to actual needs, and this embodiment does not impose specific limitations on this. When the first part 16 is located between the first sub-pixel column 7 and the first signal line 9, if the second part 17 is on the same straight line as the first part 16, the second part 17 will overlap with the active layer 13 of the second sub-pixel 12 to form a capacitor, affecting the data writing voltage of the second sub-pixel 12. Therefore, the second sub-part 19 is set to be located on the side of the drain 131 of the second sub-pixel 12 away from the first signal line 9. One end of the first sub-part 18 is connected to the second sub-part 19, and the other end is connected to the first part 16. One end of the third sub-part 20 is connected to the end of the second sub-part 19 away from the first sub-part 18, that is, the second part 19 is connected to the second sub-part 19 away from the first sub-part 18. 7 is located in the area where sub-pixel 2 is located, and at least partially in the area where second sub-pixel 12 is located. This allows the second part 17 to bypass the active layer 13 of the second sub-pixel 12, so as to avoid the second part 17 and the active layer 13 of the second sub-pixel 12 generating capacitance, which would affect the display brightness of the second sub-pixel 12. It can also prevent the second signal line 10 from contacting the first signal line 9 during the winding process, causing a short circuit. Furthermore, the first part 16 and the second part 17 are alternately connected, so that the second part 17 and the active layer 13 of the second sub-pixel 12 do not overlap in the direction perpendicular to the plane of the substrate 1.

[0065] Similarly, when the first part 16 is located between the first signal line 9 and the second sub-pixel column 8, if the second part 17 and the first part 16 are on the same straight line, the second part 17 will overlap with the active layer 13 of the first sub-pixel 11 to form a capacitor, affecting the data writing voltage of the first sub-pixel 11. Therefore, the second sub-part 19 is set to be located on the side of the drain 131 of the first sub-pixel 11 away from the first signal line 9. One end of the first sub-part 18 is connected to the second sub-part 19, and the other end is connected to the first part 16. One end of the third sub-part 20 is connected to the side of the second sub-part 19 away from the first sub-part 18. The second part 17 is located in the area where sub-pixel 2 is located, and at least partially in the area where first sub-pixel 11 is located. This allows the second part 17 to bypass the active layer 13 of the first sub-pixel 11. The second part 17 winds around the area of ​​sub-pixel 2, which can avoid the second signal line 10 from contacting the first signal line 9 and causing a short circuit. It can also avoid the second part 17 from generating capacitance with the active layer 13 of the first sub-pixel 11, which would affect the display brightness of the first sub-pixel 11. This makes the brightness of the first sub-pixel 11 and the second sub-pixel 12 equal or approximately equal, thus improving the display quality.

[0066] In some alternative embodiments, refer to Figure 3 and Figure 5 , Figure 5 yes Figure 3 A cross-sectional view along line A-A'. The array substrate 100 provided in this embodiment also includes:

[0067] The first metal layer 21 is located on one side of the substrate 1, and the first sub-part 18 is located on the first metal layer 21;

[0068] The second metal layer 22 is located on the side of the first metal layer 21 away from the substrate 1, and the first part 16, the second sub-part 19, the third sub-part 20 and the first signal line 9 are located in the second metal layer 22.

[0069] Understandably, in Figure 5 The diagram only illustrates that the array substrate 100 includes a substrate 1, a polysilicon layer 23, a first metal layer 21, a second metal layer 22, a common electrode layer 24, and a pixel electrode layer 25 stacked sequentially. Of course, the array substrate 100 may also include other film layers, such as an insulating layer between adjacent film layers, and is not limited thereto. For ease of illustration, only these are shown. Figure 3 The common electrode layer 24 and insulating layer are not shown in the diagram. The channel 132 of the active layer 13 of sub-pixel 2 is located in the polysilicon layer 23, and the source and drain electrodes 131 are located in the second metal layer 22, as shown in the reference diagram. Figure 3 Taking the second part 17 bypassing the active layer 13 of the second sub-pixel 12 as an example, the first sub-part 18 is located in the first metal layer 21. The orthographic projection of the first sub-part 18 on the substrate 1 can abut or partially overlap with the orthographic projection of the drain 131 of the second sub-pixel 12 on the substrate 1, which is beneficial to increase the opening area of ​​the second sub-pixel 12 and improve the display effect.

[0070] In some alternative embodiments, refer to Figure 6 , Figure 6 This is another structural schematic diagram of the array substrate provided by the present invention. The second signal line 10 includes a first part 16 and a second part 17 connected to each other. The second part 17 includes a first sub-part 18, a second sub-part 19 and a third sub-part 20 connected to each other.

[0071] When the first part 16 is located between the first sub-pixel column 7 and the first signal line 9, the second sub-part 19 is located on the side of the first signal line 9 away from the second sub-pixel 12. One end of the first sub-part 18 is connected to the second sub-part 19, and the other end is connected to the first part 16. One end of the third sub-part 20 is connected to the end of the second sub-part 19 away from the first sub-part 18.

[0072] When the first part 16 is located between the first signal line 9 and the second sub-pixel column 8, the second sub-part 19 is located on the side of the first signal line 9 away from the first sub-pixel 11. One end of the first sub-part 18 is connected to the second sub-part 19, and the other end is connected to the first part 16. One end of the third sub-part 20 is connected to the end of the second sub-part 19 away from the first sub-part 18.

[0073] Understandably, in Figure 6 The diagram only shows the second signal line 10 located between the first sub-pixel column 7 and the second sub-pixel column 8. The first part 16 extends along the second direction Y and is located between the first sub-pixel column 7 and the first signal line 9. If the second part 17 extends along the second direction Y and is on the same straight line as the first part 16, the second part 17 will overlap with the active layer 13 of the second sub-pixel 12 to form a capacitor, affecting the data write voltage of the second sub-pixel 12. Therefore, the second part 17 is positioned away from the first sub-pixel column 7 and away from the first signal line 9. Specifically, the second sub-part 19 is located on the side of the first signal line 9 away from the second sub-pixel 12. One end of the first sub-part 18 is connected to the second sub-part 19, and the other end is connected to the first part 16. One end of the third sub-part 20 is connected to the end of the second sub-part 19 away from the first sub-part 18. This avoids the second part 17 overlapping with the active layer 13 of the second sub-pixel 12 to prevent the generation of capacitance, thereby preventing the data write voltage of the second sub-pixel 12 from becoming low and not affecting the light emission brightness of the second sub-pixel 12, thus achieving the uniformity of the display panel 200.

[0074] Similarly, the first part 16 is located between the first signal line 9 and the second sub-pixel column 8. The first part 16 extends along the second direction Y. If the second part 17 extends along the second direction Y and the second part 17 and the first part 16 are on the same straight line, the second part 17 will overlap with the active layer 13 of the first sub-pixel 11 to form a capacitor, affecting the data writing voltage of the first sub-pixel 11. Therefore, the second part 17 is set to be wound around the first signal line 9 away from the second sub-pixel column 8. Specifically, the second sub-part 19 is located on the side of the first signal line 9 away from the first sub-pixel 11. One end of the first sub-part 18 is connected to the second sub-part 19 and the other end is connected to the first part 16. One end of the third sub-part 20 is connected to the end of the second sub-part 19 away from the first sub-part 18. This avoids the second part 17 overlapping with the active layer 13 of the first sub-pixel 11 to form a capacitor, so that the charging process of the first sub-pixel 11 is not affected by the capacitor, and avoids the difference in light emission brightness between the first sub-pixel 11 and the second sub-pixel 12.

[0075] In some alternative embodiments, refer to Figure 6 and Figure 7 , Figure 7 yes Figure 6 A cross-sectional view along the B-B' direction. The array substrate 100 provided in this embodiment also includes:

[0076] The first metal layer 21 is located on one side of the substrate 1, and the first sub-part 18 and the third sub-part 20 are located on the first metal layer 21;

[0077] The second metal layer 22 is located on the side of the first metal layer 21 away from the substrate 1, and the first part 16, the second sub-part 19 and the first signal line 9 are located in the second metal layer 22.

[0078] Understandably, in Figure 6 The diagram only shows the alternating connection of the first part 16 and the second part 17. The first part 16 is located between the first sub-pixel column 7 and the first signal line 9. The second part 17 is wound around a wire. The second sub-part 19 is located on the side of the first signal line 9 away from the active layer 13 of the second sub-pixel 12. One end of the first sub-part 18 is connected to the first part 16, and the other end is connected to the second sub-part 19. One end of the third sub-part 20 is connected to the end of the second sub-part 19 away from the first sub-part 18, and the other end is connected to the end of the first sub-part 18. Figure 7The diagram only shows that the array substrate 100 includes a stacked substrate 1, a first metal layer 21, a second metal layer 22, and a common electrode layer 24. Of course, it is not limited to this and also includes an insulating layer, etc. Along the direction perpendicular to the plane where the substrate 1 is located, the first sub-part 18 partially overlaps with the first signal line 9, and the third sub-part 20 partially overlaps with the first signal line 9. Therefore, the first sub-part 18 and the third sub-part 20 are disposed on the first metal layer 21, and the first part 16, the second sub-part 19, and the first signal line 9 are located on the second metal layer 22, thereby avoiding the problem of short circuit caused by the first sub-part 18 and the third sub-part 20 contacting the first signal line 9.

[0079] In some alternative embodiments, refer to Figure 8 and Figure 9 , Figure 8 This is another structural schematic diagram of the array substrate provided by the present invention. Figure 9 This is another structural schematic diagram of the array substrate provided by the present invention, illustrating another specific embodiment of the array substrate 100 provided in this embodiment, including:

[0080] Substrate 1;

[0081] The sub-pixels 2 are arranged in an array and located on one side of the substrate 1. The sub-pixels 2 are arranged along the first direction X to form sub-pixel rows 3 and along the second direction Y to form sub-pixel columns 4. The second direction Y intersects the first direction X. The sub-pixel rows 3 include first sub-pixel rows 5 and second sub-pixel rows 6 arranged alternately along the second direction Y. The sub-pixel columns 4 include adjacent first sub-pixel columns 7 and second sub-pixel columns 8. The sub-pixels 2 include first sub-pixels 11 and second sub-pixels 12. The first sub-pixels 11 are located in the first sub-pixel row 5 and in the second sub-pixel column 8. The second sub-pixels 12 are located in the second sub-pixel row 6 and in the first sub-pixel column 7.

[0082] The first signal line 9 is located on one side of the substrate 1 and between the first sub-pixel column 7 and the second sub-pixel column 8. The active layer 13 of the first sub-pixel 11 and the active layer 13 of the second sub-pixel 12 are connected to the first signal line 9.

[0083] The second signal line 10 is on the same layer as the first signal line 9. The second signal line 10 is at least partially located between the first sub-pixel column 7 and the second sub-pixel column 8. Along the direction perpendicular to the plane of the substrate 1, the active layer 13 of at least one first sub-pixel 11 partially overlaps with the second signal line 10, and the active layer 13 of at least one second sub-pixel 12 partially overlaps with the second signal line 10.

[0084] Within a preset voltage range, the data write voltage of at least one first sub-pixel 11 is equal to the data write voltage of at least one second sub-pixel 12.

[0085] Understandably, in Figure 8 and Figure 9 The diagram only shows sub-pixel 2 located in the first sub-pixel row 5. The active layer 13 of sub-pixel 2 is electrically connected to the first signal line 9 adjacent to its left. Sub-pixel 2 located in the second sub-pixel row 6 has its active layer 13 electrically connected to the first signal line 9 adjacent to its right, forming a ziazag structure. This reduces the fabrication process of the array substrate 100 and forces the second signal line 10 to be at least partially on the same layer as the first signal line 9. (Refer to...) Figure 8 When the second signal line 10 is located between the first sub-pixel column 7 and the first signal line 9, along the direction perpendicular to the plane of the substrate 1, the second signal line 10 overlaps with the active layer 13 of the second sub-pixel 12 to form a capacitor, resulting in a decrease in the data write voltage of the second sub-pixel 12 and a decrease in the luminous brightness of the second sub-pixel 12. In order to balance the luminous brightness of the first sub-pixel 11 and the second sub-pixel 12, the second signal line 10 is provided with an extension portion, which overlaps with the active layer 13 of the first sub-pixel 11, reducing the data write voltage of the first sub-pixel 11. This makes the data write voltages of the first sub-pixel 11 and the second sub-pixel 12 equal or approximately equal, thereby achieving equal or approximately equal luminous brightness of the first sub-pixel 11 and the second sub-pixel 12 and improving the display effect. Similarly, referring to... Figure 9 When the second signal line 10 is located between the first signal line 9 and the second sub-pixel column 8, along the direction perpendicular to the plane of the substrate 1, the second signal line 10 overlaps with the active layer 13 of the first sub-pixel 11 to form a capacitor, which causes the data writing voltage of the first sub-pixel 11 to decrease and the light emission brightness of the first sub-pixel 11 to decrease. In order to balance the light emission brightness of the first sub-pixel 11 and the second sub-pixel 12, the second signal line 10 is provided with an extension portion, which overlaps with the active layer 13 of the second sub-pixel 12 to reduce the data writing voltage of the second sub-pixel 12, so that the data writing voltages of the first sub-pixel 11 and the second sub-pixel 12 are equal or approximately equal, thereby achieving equal or approximately equal light emission brightness of the first sub-pixel 11 and the second sub-pixel 12 and improving the display effect.

[0086] In some alternative embodiments, reference continues to be made to... Figure 8 and Figure 9 The second signal line 10 includes a third part 26 and a fourth part 27 connected to each other, and the third part 26 extends along the second direction Y;

[0087] When the third part 26 is located between the first sub-pixel column 7 and the first signal line 9, the fourth part 27 overlaps with the active layer 13 of the first sub-pixel 11 in a direction perpendicular to the plane of the substrate 1.

[0088] When the third part 26 is located between the first signal line 9 and the second sub-pixel column 8, the fourth part 27 overlaps with the active layer 13 of the second sub-pixel 12 in a direction perpendicular to the plane of the substrate 1.

[0089] Understandable Figure 8 The diagram illustrates that when the third part 26 is located between the first sub-pixel column 7 and the first signal line 9, and extends along the second direction Y, the third part 26 overlaps with the active layer 13 of the second sub-pixel 12 to form a capacitor, affecting the charging of the second sub-pixel 12. The fourth part 27 is an extension that extends along a direction perpendicular to the plane of the substrate 1, causing the fourth part 27 to partially overlap with the active layer 13 of the first sub-pixel 11, affecting the charging of the first sub-pixel 11. This results in the data writing voltages of the first sub-pixel 11 and the second sub-pixel 12 being equal or approximately equal, avoiding a large difference in brightness between the first sub-pixel 11 and the second sub-pixel 12, and achieving uniform display.

[0090] Similarly, Figure 9 The diagram illustrates that when the third part 26 is located between the first signal line 9 and the second sub-pixel column 8 and extends along the second direction Y, the third part 26 overlaps with the active layer 13 of the first sub-pixel 11 to form a capacitor, affecting the data writing voltage of the first sub-pixel 11. The fourth part 27 is an extension that extends along a direction perpendicular to the plane of the substrate 1, causing the fourth part 27 to partially overlap with the active layer 13 of the second sub-pixel 12, affecting the charging of the second sub-pixel 12. This balances the data writing voltages of the first sub-pixel 11 and the second sub-pixel 12, making the data writing voltages of the first sub-pixel 11 and the second sub-pixel 12 equal or approximately equal. Consequently, the luminous brightness of the first sub-pixel 11 and the second sub-pixel 12 is the same or approximately the same, improving display uniformity.

[0091] In some alternative embodiments, reference continues to be made to... Figure 8 and Figure 9 The fourth part 27 includes the fourth sub-part 28 and the fifth sub-part 29 that are connected to each other;

[0092] When the third part 26 is located between the first sub-pixel column 7 and the first signal line 9, the fifth sub-part 29 is located on the side of the first signal line 9 away from the third part 26. Along the direction perpendicular to the plane where the substrate 1 is located, the fifth sub-part 29 overlaps with the active layer 13 of the first sub-pixel 11. One end of the fourth sub-part 28 is connected to the third part 26, and the other end is connected to the fifth sub-part 29.

[0093] When the third part 26 is located between the first signal line 9 and the second sub-pixel column 8, the fifth sub-part 29 is located on the side of the first signal line 9 away from the third part 26. Along the direction perpendicular to the plane where the substrate 1 is located, the fifth sub-part 29 overlaps with the active layer 13 of the second sub-pixel 12. One end of the fourth sub-part 28 is connected to the third part 26, and the other end is connected to the fifth sub-part 29.

[0094] Understandable Figure 8The diagram only shows the third part 26 located between the first sub-pixel column 7 and the first signal line 9. For the second signal line 10 to overlap with the active layer 13 of the first sub-pixel 11, the second signal line 10 must at least partially lie between the first signal line 9 and the second sub-pixel column 8. Therefore, the fifth sub-part 29 partially overlaps with the active layer 13 of the first sub-pixel 11. The fourth sub-part 28 connects the fifth sub-part 29 with the third part 26. Similarly... Figure 9 The diagram only shows the third sub-part 26 located between the first signal line 9 and the second sub-pixel column 8. For the second signal line 10 to overlap with the active layer 13 of the second sub-pixel 12, the second signal line 10 must be at least partially located between the first sub-pixel column 7 and the first signal line 9. Therefore, the fifth sub-part 29 partially overlaps with the active layer 13 of the second sub-pixel 12. The fourth sub-part 28 connects the fifth sub-part 29 to the third sub-part 26, ensuring that the data write voltages of both the first sub-pixel 11 and the second sub-pixel 12 are affected by the capacitor, guaranteeing that the light emission brightness of the first sub-pixel 11 and the second sub-pixel 12 is equal or approximately equal, thus avoiding dark lines. Furthermore, along the direction perpendicular to the plane of the substrate 1, the fourth sub-part 28 overlaps with the first signal line 9. A jumper can be provided for the fourth sub-part 28 to prevent it from being on the same layer as the first signal line 9, thus avoiding short circuits caused by contact between the fourth sub-part 28 and the first signal line 9.

[0095] In some alternative embodiments, refer to Figure 10 and Figure 11 , Figure 10 This is another structural schematic diagram of the array substrate provided by the present invention. Figure 11 This is another structural schematic diagram of the array substrate provided by the present invention. The fourth part 27 includes a fourth sub-part 28, a fifth sub-part 29 and a sixth sub-part 30 connected to each other.

[0096] When the third part 26 is located between the first sub-pixel column 7 and the first signal line 9, the fifth sub-part 29 is located on the side of the first signal line 9 away from the third part 26. Along the direction perpendicular to the plane where the substrate 1 is located, the fifth sub-part 29 overlaps with the active layer 13 of the first sub-pixel 11. One end of the fourth sub-part 28 is connected to the third part 26, and the other end is connected to one end of the fifth sub-part 29. One end of the sixth sub-part 30 is connected to the third part 26, and the other end is connected to the end of the fifth sub-part 29 away from the fourth sub-part 28.

[0097] When the third part 26 is located between the first signal line 9 and the second sub-pixel column 8, the fifth sub-part 29 is located on the side of the first signal line 9 away from the third part 26. Along the direction perpendicular to the plane where the substrate 1 is located, the fifth sub-part 29 overlaps with the active layer 13 of the second sub-pixel 12. One end of the fourth sub-part 28 is connected to the third part 26, and the other end is connected to one end of the fifth sub-part 29. One end of the sixth sub-part 30 is connected to the third part 26, and the other end is connected to the end of the fifth sub-part 29 away from the fourth sub-part 28.

[0098] Understandable Figure 10 The diagram only shows the third part 26 located between the first sub-pixel column 7 and the first signal line 9. For the second signal line 10 to overlap with the active layer 13 of the first sub-pixel 11, the second signal line 10 must at least partially lie between the first signal line 9 and the second sub-pixel column 8. Therefore, the fifth sub-part 29 partially overlaps with the active layer 13 of the first sub-pixel 11. The fourth sub-part 28 and the sixth sub-part 30 connect the fifth sub-part 29 with the third part 26. Similarly, Figure 11 The diagram only illustrates that when the third part 26 is located between the first signal line 9 and the second sub-pixel column 8, if the second signal line 10 and the active layer 13 of the second sub-pixel 12 are to overlap, the second signal line 10 must be at least partially located between the first sub-pixel column 7 and the first signal line 9. Therefore, the fifth sub-part 29 and the active layer 13 of the first sub-pixel 11 partially overlap. One end of the fifth sub-part 29 is connected to one end of the fourth sub-part 28, and the other end is connected to one end of the sixth sub-part 30. The end of the fourth sub-part 28 away from the fifth sub-part 29 is connected to the third part 26, and the end of the sixth sub-part 30 away from the fifth sub-part 29 is also connected to the third part 26. That is, the fourth sub-part 28 and the sixth sub-part 30 are connected in parallel. Since the presence of the fourth part 27 will increase the resistance of the second signal line 10, the resistance will affect the data transmission on the second signal line 10. Therefore, setting the fourth sub-part 28 and the sixth sub-part 30 in parallel can reduce the impedance of the second signal line 10 and improve the influence of the fourth part 27 on the second signal line 10.

[0099] Furthermore, the second signal line 10 configured in this embodiment enables the data write voltage of the first sub-pixel 11 and the second sub-pixel 12 to be reduced simultaneously, thereby ensuring that the data write voltages of the first sub-pixel 11 and the second sub-pixel 12 are equal or approximately equal, and that the luminous brightness of the first sub-pixel 11 and the second sub-pixel 12 is equal or approximately equal. However, the data write voltage of other sub-pixels 2 that are not adjacent to the second signal line 10 will not change, resulting in the luminous brightness of the first sub-pixel 11 and the second sub-pixel 12 being lower than that of other sub-pixels 2. The data write voltage of other sub-pixels 2 can be reduced by extending the length of the active layer 13 of other sub-pixels 2, thereby achieving a balance in the data write voltage of all sub-pixels 2 and improving the overall display effect. Of course, this is not the only possible approach.

[0100] In some alternative embodiments, refer to Figure 10 and Figure 12 , Figure 12 yes Figure 10 A cross-sectional view along the C-C' direction is provided in this embodiment. The array substrate 100 also includes:

[0101] The first metal layer 21 is located on one side of the substrate 1, and the fourth sub-part 28 and the sixth sub-part 30 are located on the first metal layer 21.

[0102] The second metal layer 22 is located on the side of the first metal layer 21 away from the substrate 1, and the third part 26, the fifth sub-part 29 and the first signal line 9 are located in the second metal layer 22.

[0103] Understandably, in Figure 12 The diagram only illustrates that the array substrate 100 provided in this embodiment includes a stacked substrate 1, a silicon layer 23, a first metal layer 21, and a second metal layer 22. Of course, it may also include other film layers, which will not be described in detail here. The active layer 13 of the sub-pixel 2 includes a source (not shown in the figure), a drain 131, and a channel 132. The source and drain 131 are located in the second metal layer 22, and the channel 132 is located in the silicon layer 23. The first signal line 9 is located in the second metal layer 22. When the second signal line 10 is located in the second metal layer 22, since the fourth sub-part 28 and the sixth sub-part 30 will overlap with the first signal line 9, it is necessary to set the fourth sub-part 28 and the second sub-part 19 in the first metal layer 21, and the third sub-part 26 and the fifth sub-part 29 in the second metal layer 22 to avoid short circuits.

[0104] Based on the same inventive concept, referring to Figure 13 , Figure 13 This is a schematic diagram of a display panel provided by the present invention. The present invention also provides a display panel 200, including the array substrate 100 provided in any of the above embodiments. The display panel 200 can be a liquid crystal display panel 200, but is not limited thereto. The display panel 200 provided in the embodiments of the present invention has the beneficial effects of the array substrate 100 provided in the embodiments of the present invention. For details, please refer to the specific description of the array substrate 100 in the above embodiments. This embodiment will not be repeated here.

[0105] As can be seen from the above embodiments, the array substrate provided by the present invention achieves at least the following beneficial effects:

[0106] The array substrate provided by the present invention includes: a substrate; sub-pixels arranged in an array, located on one side of the substrate, the sub-pixels being arranged along a first direction to form sub-pixel rows and along a second direction to form sub-pixel columns, the second direction intersecting the first direction, the sub-pixel rows including alternating first sub-pixel rows and second sub-pixel rows along the second direction, the sub-pixel columns including adjacent first sub-pixel columns and second sub-pixel columns; sub-pixels including first sub-pixels and second sub-pixels, the first sub-pixels being located in the first sub-pixel rows and in the second sub-pixel columns, the second sub-pixels being located in the second sub-pixel rows and in the first sub-pixel columns; a first signal line located on one side of the substrate and between the first sub-pixel columns and the second sub-pixel columns, the active layers of the first sub-pixels and the second sub-pixels being connected to the first signal line; and a second signal line on the same layer as the first signal line, the second signal line being at least partially located between the first sub-pixel columns and the second sub-pixel columns. Between pixel columns, having the second signal line and the first signal line on the same layer reduces manufacturing processes and lowers costs. Along a direction perpendicular to the plane of the substrate, the active layer of at least one first sub-pixel does not overlap with the second signal line, and the active layer of at least one second sub-pixel does not overlap with the second signal line. This means that the active layer of at least one first sub-pixel will not form a capacitor with the second signal line, and vice versa. This prevents the data writing voltage of at least one first sub-pixel and at least one second sub-pixel from being interfered with by capacitance. Within a preset voltage range, the data writing voltage of at least one first sub-pixel is equal to that of at least one second sub-pixel, avoiding charging differences between the first and second sub-pixels that could lead to differences in display brightness. This improves the problem of poor dark lines and enhances the display effect.

[0107] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. An array substrate, characterized by, The application relates to a display panel, comprising: a substrate; a plurality of sub-pixels arranged in an array on one side of the substrate, the sub-pixels being arranged in a first direction to form a plurality of sub-pixel rows and arranged in a second direction to form a plurality of sub-pixel columns, the second direction intersecting the first direction, the sub-pixel rows comprising first sub-pixel rows and second sub-pixel rows arranged alternately in the second direction, the sub-pixel columns comprising first sub-pixel columns and second sub-pixel columns arranged alternately, the sub-pixels comprising first sub-pixels and second sub-pixels, the first sub-pixels being located in the first sub-pixel rows and in the second sub-pixel columns, the second sub-pixels being located in the second sub-pixel rows and in the first sub-pixel columns; a first signal line located on one side of the substrate and between the first sub-pixel columns and the second sub-pixel columns, the active layers of the first sub-pixels and the active layers of the second sub-pixels being connected to the first signal line; a second signal line in the same layer as the first signal line, the second signal line being at least partially located between the first sub-pixel columns and the second sub-pixel columns, the active layers of at least one of the first sub-pixels and the active layers of at least one of the second sub-pixels partially overlapping the second signal line in a direction perpendicular to the plane in which the substrate lies; in a preset voltage range, the data write-in voltage of at least one of the first sub-pixels is equal to the data write-in voltage of at least one of the second sub-pixels; the second signal line comprises a third portion and a fourth portion connected to each other, the third portion extending in the second direction; when the third portion is located between the first sub-pixel columns and the first signal line, the fourth portion partially overlaps the active layers of the first sub-pixels in the direction perpendicular to the plane in which the substrate lies; when the third portion is located between the first signal line and the second sub-pixel columns, the fourth portion partially overlaps the active layers of the second sub-pixels in the direction perpendicular to the plane in which the substrate lies.

2. The array substrate of claim 1, wherein, the fourth portion comprises a fourth sub-portion and a fifth sub-portion connected to each other; when the third portion is located between the first sub-pixel columns and the first signal line, the fifth sub-portion is located on the side of the first signal line away from the third portion, the fifth sub-portion partially overlaps the active layers of the first sub-pixels in the direction perpendicular to the plane in which the substrate lies, one end of the fourth sub-portion is connected to the third portion and the other end is connected to the fifth sub-portion; when the third portion is located between the first signal line and the second sub-pixel columns, the fifth sub-portion is located on the side of the first signal line away from the third portion, the fifth sub-portion partially overlaps the active layers of the second sub-pixels in the direction perpendicular to the plane in which the substrate lies, one end of the fourth sub-portion is connected to the third portion and the other end is connected to the fifth sub-portion.

3. The array substrate of claim 1, wherein, the fourth portion comprises a fourth sub-portion, a fifth sub-portion and a sixth sub-portion connected to each other; When the third part is located between the first signal line and the first sub-pixel column, the fifth sub-part is located on a side of the first signal line away from the third part, the fifth sub-part overlaps with an active layer part of the first sub-pixel in a direction perpendicular to a plane where the substrate is located, one end of the fourth sub-part is connected to the third part, and the other end of the fourth sub-part is connected to one end of the fifth sub-part, one end of the sixth sub-part is connected to the third part, and the other end of the sixth sub-part is connected to an end of the fifth sub-part away from the fourth sub-part. When the third part is located between the first signal line and the first sub-pixel column, the fifth sub-part is located on a side of the first signal line away from the third part, the fifth sub-part overlaps with an active layer part of the first sub-pixel in a direction perpendicular to a plane where the substrate is located, one end of the fourth sub-part is connected to the third part, and the other end of the fourth sub-part is connected to one end of the fifth sub-part, one end of the sixth sub-part is connected to the third part, and the other end of the sixth sub-part is connected to an end of the fifth sub-part away from the fourth sub-part.

4. The array substrate of claim 3, wherein, Further comprising: a first metal layer located on a side of the substrate, the fourth sub-part and the sixth sub-part are located on the first metal layer; a second metal layer located on a side of the first metal layer away from the substrate, the third part, the fifth sub-part and the first signal line are located on the second metal layer.

5. A display panel, characterized by, An array substrate comprising any one of claims 1-4. An array substrate comprising any one of claims 1-4.

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