An ideal diode circuit

Abstract

An ideal diode circuit comprises a transistor, a low-voltage reference module, an ultra-low-voltage power supply module and a voltage drop detection circuit, the low-voltage reference module provides three different reference voltages and bias voltages, the ultra-low-voltage power supply module adopts N charge pumps in series to step up the voltage drop of the transistor, and outputs a control voltage Vcp to supply power for the internal circuit of the ideal diode, the voltage drop detection circuit compares the voltage drop of the transistor with the three reference voltages through comparators respectively, controls the opening or closing of the charge pump of the ultra-low-voltage power supply module, and realizes adaptive variable amplification multiple step-up of the voltage drop VIN-VOUT. The ideal diode control technology provided by the application utilizes variable charge pump amplification multiple, provides adaptive adjustment of the amplified voltage, and meets the continuous and stable operation of the circuit in the working voltage range of the ideal diode.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and relates to power management of integrated circuits, and is an ideal diode circuit. BACKGROUND

[0002] When a diode is in a forward conduction state, current flows from an anode terminal to a cathode terminal, the anode terminal inputs a voltage VIN, and the cathode terminal outputs a voltage VOUT, and the diode has a reverse blocking function and is commonly used for anti-reverse connection and anti-backflow protection in a circuit. The diode has an asymmetric conduction characteristic, and the resistance in the forward conduction state is much smaller than the resistance in the reverse conduction state. However, the diode still has a significant resistance in the forward conduction state, and there is a voltage drop loss, which reduces the conversion efficiency. At the same time, the diode generates a lot of heat when working, and needs to be cooled, which increases the application cost. In order to further reduce the loss of a rectifier device, the prior art proposes to use an ideal diode to replace a diode, and an ideal diode control circuit drives an NMOS tube to simulate an ideal diode with an ultra-low forward voltage drop and a negligible reverse current, and uses the low on-resistance of the NMOS tube to reduce the voltage drop (VIN-VOUT) under a large current, thereby reducing the power consumption P=V*I, where V is the voltage difference between the anode and the cathode of the diode, that is, VIN-VOUT, and I is the current flowing through.

[0003] Chinese application CN109450234A discloses a traditional intermittent ideal diode and a control circuit thereof, and proposes a scheme capable of maintaining the ideal diode in a continuous conduction state and stabilizing the voltage drop, in view of the problem of an external pump capacitor C1 existing in the ideal diode Q1. These schemes provide voltage for the internal control circuit of the ideal diode by using the voltage drop (VIN-VOUT) between the two ends of the ideal diode, that is, the voltage drop of the resistance current, and then boosting the voltage by using a charge pump. However, the ideal diode itself includes an NMOS tube Np and a parasitic diode D1, as shown in Figure 1As shown, the control circuit controls the opening or closing of the NMOS transistor by outputting a control voltage to the gate of the NMOS transistor. The on-voltage of the parasitic diode is about 0.6-0.65V, and the on-voltage Vds of the NMOS transistor is 0<Vds<0.6V. The Vds voltage increases with the increase of the output current when the resistance (W / L size) is fixed. When the Np is closed, the parasitic diode is turned on, and the voltage is about VIN-VOUT=Vbe=0.6V; when the Np is turned on, the on-resistance of the NMOS transistor is small due to its large size, and even as low as VIN-VOUT=0.1V. Therefore, the voltage difference between VIN and VOUT of the ideal diode generally varies between 0.1-0.6V. Therefore, if a fixed charge pump circuit is used, a fixed amplification factor will cause the ideal diode to not work effectively when the voltage difference VIN-VOUT in the working voltage range of 0.1-0.6V changes. For example, when VIN-VOUT=0.1V, if the charge pump has a fixed amplification factor of 5 times, the voltage is boosted to 0.5V, and the starting threshold of the NMOS transistor is about 1-1.5V. At this time, the supply voltage is too low to cause the control circuit to not work normally and not effectively open the NMOS transistor Np; if the charge pump has a fixed amplification factor of 20 times, VIN-VOUT=0.1V is boosted to 2V, which meets the power supply voltage requirement of the control circuit, but when VIN-VOUT=0.6V, the voltage is boosted to 12V, which is too high and exceeds the safe working range of the control circuit. The gate of the NMOS transistor is generally 5V low-voltage, and the high voltage will damage the gate of the NMOS transistor. Therefore, the fixed charge pump voltage supply cannot guarantee the continuous and stable safe working of the ideal diode in the working voltage range (VIN-VOUT)=0.1~0.6V. SUMMARY

[0004] The problem to be solved by the present application is that the existing ideal diode circuit uses a fixed charge pump to boost the voltage drop of the NMOS transistor to supply power to the control circuit of the ideal diode. When the voltage drop of the NMOS transistor changes in the working voltage range, the power supply of the control circuit cannot meet the voltage requirement.

[0005] The technical scheme of the present application is: an ideal diode circuit, comprising a transistor, a low-voltage reference module, an ultra-low voltage power supply module and a voltage drop detection circuit, the low-voltage reference module provides three different reference voltages and bias voltages, according to the voltage drop variation range of the transistor, the voltage drop is divided into three sections of low voltage, medium voltage and high voltage in proportion, and the starting voltage points of the three sections of voltage are taken as three reference voltages Vref1-Vref3, the ultra-low voltage power supply module adopts N series charge pumps to step up the voltage drop VIN-VOUT of the transistor, and outputs a control voltage Vcp to supply power for the internal circuit of the ideal diode, the voltage drop detection circuit comprises three comparators and two NAND gates, the three comparators compare the voltage drop VIN-VOUT of the transistor with the three reference voltages respectively, comparator comp1 compares VIN-VOUT with the low-voltage reference voltage Vref1, the output is connected to the transistor gate to control the conduction or closing of the transistor, comparators comp2 and comp3 compare VIN-VOUT with the medium-voltage reference voltage Vref2 and the high-voltage reference voltage Vref3 respectively, the outputs of comp2 and comp3 and the output of comp1 pass through a NAND gate respectively to generate an enable signal to control the opening or closing of the medium-voltage charge pump group and the high-voltage charge pump group in the ultra-low voltage power supply module, and realize self-adaptive variable amplification multiple step-up of the voltage drop VIN-VOUT; wherein, the number of the medium-voltage charge pump group is A, the number of the high-voltage charge pump group is B, N*Vref1 is greater than or equal to the threshold value of the transistor, (N-B)*Vref2 is greater than or equal to the threshold value of the transistor, (N-A-B)*Vref3 is greater than or equal to the threshold value of the transistor, and N*Vref1, (N-B)*Vref2 and (N-A-B)*Vref3 are all less than the voltage resistance value of the transistor.

[0006] Further, the three reference voltages are Vref1=0.1V, Vref2=0.25V and Vref3=0.4V, N=20, A=5 and B=5.

[0007] Further, the ultra-low voltage power supply module comprises an oscillator module, charge pumps CP1-CP20 and an enabling circuit, the oscillator module provides an oscillator signal for the charge pumps, the charge pumps CP1-CP20 are connected in series, the enabling circuit comprises a medium voltage enabling circuit and a high voltage enabling circuit, the medium voltage enabling circuit receives an enabling signal EN1 of the comparator comp3, EN1 is input to the gate of an nmos tube Nu1 after passing through an inverter, EN1 is also input to the gate of a pmos tube Pu1, the drains and sources of Pu1 and Nu1 are connected across CP11-CP15, Pu1 and Nu1 constitute a transmission gate, when EN1 is high, the transmission gate is closed, the charge pumps CP11-CP15 perform voltage boosting, otherwise, the transmission gate is opened, CP11-CP15 are short-circuited and do not perform voltage boosting; similarly, the high voltage enabling circuit receives an enabling signal EN2 of the comparator comp2, EN2 is input to the gate of an nmos tube Nu2 after passing through an inverter, EN2 is also input to the gate of a pmos tube Pu2, the drains and sources of Pu2 and Nu2 are connected across CP16-CP20, Pu2 and Nu2 constitute a transmission gate, which controls whether CP16-CP20 perform voltage boosting.

[0008] The application provides a novel ideal diode control technology, utilizes a variable charge pump amplification factor, and provides an adaptively adjusted amplification voltage to meet the condition that (VIN-VOUT)=0.1-0.6V in the working voltage range of the ideal diode, and the circuit can continuously and stably work.

[0009] Firstly, three comparators are adopted to compare the voltage drop of VIN-VOUT with reference voltages 0.1V, 0.25V and 0.4V respectively, to detect the current voltage drop, and the charge pump amplification factor in the ultra-low voltage power supply module is continuously changed with the change of the voltage drop, to provide a controllable power supply voltage, so that the circuit works in a safe voltage range.

[0010] Secondly, the application proposes an ultra-low voltage power supply technology, adopts low threshold devices with a threshold as low as 0.1V and low input charge pump technology, and can provide voltage boosting when VIN-VOUT=0.1V, to ensure the normal work of the circuit.

[0011] Finally, the low input voltage comparator and low voltage reference module designed by the application can realize the comparison of the low detection voltage and the reference signal meeting the working voltage range of the transistor.

[0012] Through the charge pump technology with a variable amplification factor, the application can provide a safe range power supply voltage for the ideal diode control circuit, so as to realize the reliable work of the ideal diode circuit. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 It is a structure principle schematic diagram of the N-type power tube of the ideal diode.

[0014] Figure 2 Circuit diagram of the ideal diode circuit of the present application.

[0015] Figure 3 Circuit diagram of the ultra-low voltage power supply module in the ideal diode circuit of the present application.

[0016] Figure 4 Circuit diagram of the oscillator OSC in the ultra-low voltage power supply module of the present application.

[0017] Figure 5 Circuit diagram of the comparator comp in the ideal diode circuit of the present application.

[0018] Figure 6 Circuit diagram of the low input voltage CP in the ideal diode circuit of the present application.

[0019] Figure 7 Circuit diagram of the low voltage reference module in the ideal diode circuit of the present application. DETAILED DESCRIPTION

[0020] The present application proposes an ideal diode and its control technology, which ensures the safety and reliability of the driving circuit in the switching process of the ideal diode. By comparing the transistor voltage drop VIN-VOUT with the set reference voltage, the boost multiple of the charge pump is adaptively adjusted.

[0021] The application comprises an NMOS transistor, a low-voltage reference module, an ultra-low-voltage power supply module and a voltage drop detection circuit. The low-voltage reference module provides three different reference voltages and bias voltages. According to the voltage drop range of the transistor, the voltage drop range is proportionally divided into three sections of low voltage, medium voltage and high voltage. The starting voltage points of the three sections of voltage are taken as three reference voltages Vref1-Vref3. The voltage of the body diode is 0.6-0.65V. The upper limit of the voltage range is about 0.6V. Therefore, the application preferably takes 0.1V, 0.25V and 0.4V as the optimal sampling voltage points, i.e. Vref1=0.1V, Vref2=0.25V and Vref3=0.4V. The ultra-low-voltage power supply module uses N series-connected charge pumps to step up the voltage drop VIN-VOUT of the transistor and outputs a control voltage Vcp to supply power to the internal circuit of the ideal diode. The voltage drop detection circuit comprises three comparators and two NAND gates. The three comparators compare the voltage drop VIN-VOUT of the transistor with the three reference voltages. The comparator comp1 compares VIN-VOUT with the low-voltage reference voltage Vref1. The output of the comparator comp1 is connected to the gate of the transistor to control the conduction or shutdown of the transistor. The comparators comp2 and comp3 compare VIN-VOUT with the medium-voltage reference voltage Vref2 and the high-voltage reference voltage Vref3, respectively. The outputs of comp2 and comp3 and the output of comp1 pass through a NAND gate, respectively, to generate an enable signal to control the start or shutdown of the medium-voltage charge pump group and the high-voltage charge pump group in the ultra-low-voltage power supply module, so as to realize adaptive variable amplification ratio step-up of the voltage drop VIN-VOUT. In the application, the number of the medium-voltage charge pump group is A and the number of the high-voltage charge pump group is B. N*Vref1 is greater than or equal to the threshold value of the transistor, (N-B)*Vref2 is greater than or equal to the threshold value of the transistor, (N-A-B)*Vref3 is greater than or equal to the threshold value of the transistor, and N*Vref1, (N-B)*Vref2 and (N-A-B)*Vref3 are all less than the voltage resistance value of the transistor. That is, by designing the reference voltage and the number of charge pumps, the variation range of the control voltage Vcp output by the ultra-low-voltage power supply module is set between the start threshold value and the voltage resistance value of the transistor. In actual application, the variation range of the control voltage Vcp is generally compressed inwardly within the range of the start threshold value and the voltage resistance value of the transistor. For example, when the start threshold value is 1V and the voltage resistance value is 10V, the control voltage Vcp is designed to be between 1.5V and 7V or between 2V and 6V. As an embodiment, when the voltage drop is 0-0.6V, the lowest sampling point is 0.1V. Therefore, 20 charge pumps are sufficient to meet the lower limit requirement. When the sampling point is reduced to 0.05, more charge pumps are needed. The application preferably takes N=20, A=5 and B=5.

[0022] The application will be described in detail below with reference to the embodiments.

[0023] AsFigure 2 Fig. 1 shows a specific embodiment of the ideal diode circuit of the present application. In the figure, VIN is the input terminal, and VOUT is the output terminal. Np is the Nmos transistor of the ideal diode, and D1 is the parasitic body diode. comp1, comp2, and comp3 are low input voltage comparators. Nand1B and Nand2B are NAND gates. The low voltage reference module provides three reference voltages, Vref1 = 0.1, Vref2 = 0.25, and Vref3 = 0.4, as well as the bias voltage B1 of the bias current source. The ultra-low voltage power supply module outputs the supply voltage Vcp. EN1 and EN2 are enable control signals that control the operation of the ultra-low voltage power supply module. When EN1 is high, CP11-CP15 in the ultra-low voltage power supply are turned off; when EN1 is low, CP11-CP15 in the ultra-low voltage power supply are turned on. When EN2 is high, CP16-CP20 in the ultra-low voltage power supply are turned off; when EN2 is low, CP16-CP20 in the ultra-low voltage power supply are turned on.

[0024] The source and body terminals of Np, the positive terminal of the parasitic diode D1, and the power terminal of the ultra-low voltage power supply are all connected to the VIN terminal. The drain terminal of Np, the negative terminal of the parasitic diode D1, the low power terminal of the ultra-low voltage power supply, the low power terminal of the low voltage reference module, the low power terminals of comp1, comp2, and comp3, and the low power terminals of nan1B and nand2B are all connected to the VOUT terminal.

[0025] The ultra-low voltage power supply outputs the control voltage Vcp, which is also connected to the high power terminals of the low voltage reference module, comp1, comp2, and comp3, and nan1B and nand2B, for power supply. The positive terminal of comp1, the negative terminal of comp2, and the negative terminal of comp3 are connected to the VIN terminal. The negative terminal of comp1 is connected to Vref1 = 0.1 V. The positive terminal of comp2 is connected to Vref2 = 0.25 V. The positive terminal of comp3 is connected to Vref3 = 0.4 V. The output terminal of comp1 is connected to the gate of Np, and the outputs of comp2 and comp3 are output as EN2 and EN1 after passing through NAND gates nand1B and nand2B, respectively, and the two enable signals are input to the control terminals of the ultra-low voltage power supply module.

[0026] The working principle of the ideal diode circuit of the application is as follows: the transmission tube Np is used as an ideal diode, which can significantly reduce the transmission voltage drop when a large current flows through VIN to VOUT. Since Np has a conduction resistance, the drain-source voltage drop Vds=VIN-VOUT increases with the increase of the current flowing through it. Np has a parasitic diode D1, which is only used to turn on when Np is turned off at a small current. The ultra-low voltage power supply module uses the voltage difference between the input VIN and VOUT to realize the step-up output voltage Vcp by using a series charge pump circuit to supply power to the control circuit low voltage reference, comp1, comp2, comp3, nand1B and nand2B. A total of 20 charge pumps CP are used in the ultra-low voltage power supply module, of which CP1-CP10 are always working, CP11-CP15 are controlled by the EN1 signal, and EN1=0 low level is turned on; EN1=1 high level is turned off. CP16-CP20 are controlled by the EN2 signal, and EN2=0 low level is turned on; EN2=1 high level is turned off. When CP1-CP10 are working, Vcp=(VIN-VOUT)*10 is realized; when CP1-CP15 are working, Vcp=(VIN-VOUT)*15 is realized; when CP1-CP20 are working, Vcp=(VIN-VOUT)*20 is realized.

[0027] The application designs three-gear voltage detection for the change range of VIN-VOUT, as follows.

[0028] When Np is turned off, the parasitic diode is turned on, and the voltage division is approximately equal to the voltage division of the diode VIN-VOUT=Vbe=0.6V. comp3 detects (VIN-VOUT)>Vref3=0.4V, outputs low potential, causes nand2B to output EN1=1 high level, and turns off the working of the charge pumps CP11-CP15 of the ultra-low voltage power supply module. comp2 detects (VIN-VOUT)>Vref2=0.25V, outputs low potential, causes nand1B to output EN1=1 high level, and turns off the working of the charge pumps CP16-CP20 of the ultra-low voltage power supply module. Only CP1-CP10 work in the ultra-low voltage power supply module to provide Vcp=(VIN-VOUT)*10 times step-up. At the same time, comp1 detects (VIN-VOUT)>Vref2=0.1V, outputs high potential, turns on Np, reduces the voltage difference VIN-VOUT, and realizes the power supply voltage range of 4<Vcp<6V when 0.4<(VIN-VOUT)<0.6.

[0029] When the voltage difference of VIN-VOUT reduces to 0.25-0.4V, (VIN-VOUT)<Vref3=0.4V, comp3 outputs high level; (VIN-VOUT)>Vref2=0.25V, comp2 outputs low level; (VIN-VOUT)>Vref1=0.1V, comp1 outputs high level. Therefore, nand1B outputs EN2 high level, and the working of the charge pump CP16-CP20 of the ultra-low voltage power supply module is closed. Nand2B outputs EN1 low level, and the working of the charge pump CP11-CP15 of the ultra-low voltage power supply module is opened. Therefore, CP1-CP15 in the ultra-low voltage power supply module works, and (VIN-VOUT)*15 times of voltage is provided, so that the power supply voltage range of 3.75Vcp<6V is realized.

[0030] When the voltage difference of VIN-VOUT reduces to 0.1-0.25V, (VIN-VOUT)<Vref3=0.4V, comp3 outputs high level; (VIN-VOUT)<Vref2=0.25V, comp2 outputs high level; (VIN-VOUT)>Vref1=0.1V, comp1 outputs high level. Therefore, nand1B outputs signal EN2 low level, and the working of the charge pump CP16-CP20 of the ultra-low voltage power supply module is opened. Nand2B outputs signal EN1 low level, and the working of the charge pump CP11-CP15 of the ultra-low voltage power supply module is opened. Therefore, CP1-CP20 in the ultra-low voltage power supply module works, and (VIN-VOUT)*20 times of voltage is provided, so that the power supply voltage range of 2Vcp<5V is realized.

[0031] When the voltage difference of VIN-VOUT reduces to less than 0.1V, comp1 outputs low level, and the gate of Np is closed. At the same time, nand1B and nand2B are directly closed, that is, nand1B and nand2B output high level, and the medium voltage charge pump group of 5 charge pumps and the high voltage charge pump group of 5 charge pumps of the ultra-low voltage power supply are all closed, only CP1-CP10 works, and (VIN-VOUT)*10 times of voltage is provided. At the same time, due to the closing of Np, the voltage difference of VIN-VOUT rises to the voltage drop voltage of the parasitic diode, Vbe=0.6V, and the charge pump circuit adopts 10 times of voltage to obtain Vcp=6V, which will not exceed the voltage withstand range of the low voltage device.

[0032] Figure 3 The circuit diagram of the ultra-low voltage power supply module of the application.

[0033] OSC is a low input voltage oscillator module, output oscillator signal. CP1-CP20 is a low input voltage charge pump, where N is its low voltage input, P is its high voltage output, Osc is its oscillator signal input. Invu1 and inVu2 are inverters. Pu1 and Pu2 are pmos tubes; Nu1 and Nu2 are nmos tubes. EN1 is a switch signal to control the function of CP11-CP15, EN2 is a switch signal to control the function of CP16-CP20.

[0034] OSC oscillator output control CP1 to CP20 Osc port. The N end of CP1 is connected to VIN, and the ground end of all CP1-CP20 is connected to VOUT. CP1~CP20 are connected in series, and the P end of CP20 outputs Vcp. The inverter, nmos tube Nu1 and Nu2 and pmos tube Pu1 and Pu2 constitute the enable circuit, including the middle voltage enable circuit and the high voltage enable circuit. The middle voltage enable circuit receives the enable signal EN1 of the comparator, EN1 is input to the gate of nmos tube Nu1 after passing through the inverter invu1, and EN1 is input to the gate of pmos tube Pu1 at the same time. The drain and source of Pu1 and Nu1 are connected across CP11~CP15. Pu1 and Nu1 constitute a transmission gate. When EN1 is high, the transmission gate is closed, the charge pump CP11 to CP15 is boosted, and vice versa. The transmission gate is opened, CP11 to CP15 is short-circuited, and the boosting is not performed. Similarly, the high voltage enable circuit receives the enable signal EN2 of the comparator, EN2 is input to the gate of nmos tube Nu2 after passing through the inverter invu2, and EN2 is input to the gate of pmos tube Pu2 at the same time. The drain and source of Pu2 and Nu2 are connected across CP16~CP20. Pu2 and Nu2 constitute a transmission gate. When EN2 is high, the transmission gate is closed, CP16 to CP20 is normally boosted, and vice versa. The transmission gate is opened, CP16 to CP120 is short-circuited, and the boosting is not performed.

[0035] When working normally, the OSC is turned on to provide oscillator signals to CP1-CP20 simultaneously. CP1-CP10 are always turned on, i.e. the input voltage difference between VIN and VOUT is provided to output VIN*10 with 10 times voltage boost. When EN1 and EN2 are both high, Pu1 and Nu1, Pu2 and Nu2 are both turned off, so CP11-CP15 and CP16-CP20 are both turned on, and CP1-CP20 finally realize 20 times voltage boost, i.e. Vcp=(VIN-VOUT)*20. When EN1 is high and EN2 is low, Pu1 and Nu1 are turned off, and Pu2 and Nu2 are turned on, so CP11-CP15 are turned on and CP16-CP20 are turned off, and CP1-CP15 realize 15 times voltage boost, i.e. Vcp=(VIN-VOUT)*15. When EN1 and EN2 are both low, Pu1 and Nu1, Pu2 and Nu2 are both turned on, so CP11-CP15 and CP16-CP20 are both turned off, and CP1-CP10 finally realize 10 times voltage boost, i.e. Vcp=(VIN-VOUT)*10.

[0036] Therefore, by controlling the two signals EN1 and EN2, the number of working charge pumps can be controlled, and different voltage boost levels of 10 times, 15 times and 20 times can be realized.

[0037] The OSC oscillator is a ring oscillator as shown in Figure 4 The invosc1, invosc2, invosc3, invosc4 and invosc5 are inverters with low threshold values, and the threshold values of the nmos and pmos in the inverters are about 0.1V. The cosc is a capacitor. The osc is an output oscillator signal. These devices form a ring oscillator with low input voltage.

[0038] The present application realizes voltage drop detection by using three comparators. As an embodiment, the circuit of the comparator comp is shown in Figure 5 The B+ is a bias current source control signal, the comp_out is an output signal, the VIN is a power supply, and the GND is a ground. The PC1, PC2, PC3 and PC4 are pmos, and the NC1, NC2 and NC3 are nmos. The source and body of PC1 and PC2 are connected to the VIN. The drain of PC1 is connected to the source and body of PC3 and PC4. The gate of PC1 and PC2 is connected to the B+ signal. The gate of PC3 is the input negative terminal of the comparator, and the gate of PC4 is the input positive terminal of the comparator. The drain of PC3 is connected to the drain and gate of NC1, and the gate of NC2. The source and body of NC1, NC2 and NC3 are connected to the ground. The drain of PC4 is connected to the drain of NC2 and the gate of NC3. The drain of NC3 is connected to the drain of NC2, and the output signal COMP_out is output.

[0039] Figure 6 The circuit diagram of the charge pump in the ultra-low voltage power supply module of the application is shown, Invcp1, invocp2, invocp3, invcp4, invcp5, invocp6, invcp7, invcp8 are all low threshold inverters, Pcp1, Pcp2 are low threshold pmos, Ncp1 and Ncp2 are low threshold nmos. The threshold of nmos and pmos is about 0.1V. The high power supply is VIN, and the low power supply is VOUT. C1 and C2 are capacitors. Osc is the input oscillator signal. N is the low voltage signal input end of the charge pump; P is the high voltage signal output end of the charge pump.

[0040] The input signal of invcp1 is osc, and the output of invcp1 is connected to the input of invcp2 and invcp5. The output of invcp2 is connected to the input of invcp3, the output of invcp3 is connected to the input of invcp4, and the output of invcp4 is connected to the lower plate of C2. The upper plate of C2 is connected to the drain of Pcp2 and Ncp2, and the gate of Pcp1 and Ncp1. The source and body of Pcp1 and Pcp2 are connected to P together. The source and body of Ncp1 and Ncp2 are connected to N together. The drain of Pcp1 and Ncp1 is connected, and the upper plate of C1 is connected. The lower plate of C1 is connected to the output of invcp8. The input of invcp8 is connected to the output of invcp7. The input of invcp7 is connected to the output of invcp6. The input of invcp6 is connected to the output of invcp5.

[0041] When the OSC signal is high, the invcp4 outputs high potential, connects the lower plate of C2, and raises the potential of C2 by a VIN potential difference. Since Ncp1 is a low threshold, Ncp1 is turned on, the upper plate of C1 is charged to N potential, and since the invcp8 outputs low potential, the potential difference of C1 is N potential. When the OSC signal is low, the invcp8 outputs high potential, connects the lower plate of C1, and raises the potential of C1 by a VIN potential difference. At the same time, the potential of the upper plate of C1 becomes (N+VIN), and Ncp2 is turned on. The invcp4 is low potential, and the potential of the capacitor C2 is charged to N potential by Ncp2. Since the gate and drain of Rcp1 have a difference of VIN, Rcp1 is turned on, C1 is charged to P potential, and the approximate potential P=(N+VIN). In the next OSC cycle, the OSC is high again, the potential of C2 is raised to (N+VIN), the potential of C1 remains N, and Rcp2 is turned on to transfer the potential of C2 to P=(N+VIN). At the same time, Ncp1 is turned on, and the potential of C1 remains N. Therefore, by using the OSC switch, C1 and C2 can be alternately charged and discharged between N and (N+VIN) voltages, so that the N voltage is boosted to P=N+VIN, that is, a single charge pump realizes the boost of VIN by a voltage difference of 20 times.

[0042] The oscillator module, the charge pump, and the enable circuit in the ultra-low voltage power supply module all use 0.1V low threshold devices, which can accurately detect the voltage and realize 20 times boost when the minimum VIN-VOUT=0.1V.

[0043] As an embodiment, Figure 7 The circuit diagram of the low voltage reference module provided by the application is shown. ND1 and ND2 are nmos depletion devices; N1 is a low threshold nmos tube, the threshold is 0.1V, and P1 is a pmos normal threshold tube. R1, R2, and R3 are resistors. B1 is an output current source bias voltage signal; Vref1, Vref2, and Vref3 are reference output voltages.

[0044] The drain of ND1 is connected to the source and body of P1, and to the high side of the power supply. The source and body of ND1 are connected together, connected to the drain of N1, and the gate of ND2. The source and body of N1 are connected together and grounded. The gate of P1 is connected to the drain, and the drain of ND2. The source and body of ND2 are connected to one end of R1, and output Vref3=0.4V; the other end of R1 is connected to one end of R2, and outputs Vref3=0.25V; the other end of R2 is connected to one end of R3, and the gate of N1, and outputs Vref1=0.1V; the other end of R3 is connected to ground.

[0045] Although ND1 provides bias, and low threshold enhancement tube N1 constitutes the reference operational amplifier two-in-one circuit, ND2 serves as the second stage, forming a follower, while R1, R2, R3 divide the voltage to be 0.4V, 0.25V and 0.1V respectively. The bias current of the channel is Vref1 / R3, and through P1 in the form of a diode, a bias voltage B1 is provided for the mirror current.

[0046] Finally, it should be noted that the above-described embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the same. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some or all of the technical features, and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An ideal diode circuit, characterized by: The system includes transistors, a low-voltage reference module, an ultra-low-voltage power supply module, and a voltage drop detection circuit. The low-voltage reference module provides three different reference voltages and bias voltages, proportionally divided into low-voltage, medium-voltage, and high-voltage segments based on the transistor's voltage drop range. The starting voltage points of these three segments are sampled as the three reference voltages Vref1 to Vref3. The ultra-low-voltage power supply module uses N charge pumps connected in series to boost the transistor's voltage drop VIN-VOUT, outputting a control voltage Vcp to power the internal circuitry of the ideal diode. The voltage drop detection circuit includes three comparators and two NAND gates. The three comparators compare the transistor's voltage drop VIN-VOUT with the three reference voltages. Comparator comp1 compares VIN-VOUT with the low-voltage reference voltage Vref1, and its output is connected to the transistor's gate to control the transistor's on / off state, mimicking the transistor's behavior. The diode is a true analog diode. Comparators comp2 and comp3 compare VIN-VOUT with the medium-voltage reference voltage Vref2 and the high-voltage reference voltage Vref3, respectively. The outputs of comp2 and comp3 and the output of comp1 are respectively passed through a NAND gate to generate an enable signal, which controls the opening or closing of the medium-voltage charge pump group and the high-voltage charge pump group in the ultra-low voltage power supply module, realizing the adaptive variable amplification factor boost of the voltage drop VIN-VOUT. Among them, let the number of medium-voltage charge pump groups be A and the number of high-voltage charge pump groups be B. We have: N*Vref1 is greater than or equal to the threshold of the transistor, (NB)*Vref2 is greater than or equal to the threshold of the transistor, (NAB)*Vref3 is greater than or equal to the threshold of the transistor, and N*Vref1, (NB)*Vref2, and (NAB)*Vref3 are all less than the withstand voltage of the transistor.

2. The ideal diode circuit according to claim 1, characterized in that: The three reference voltages are Vref1=0.1V, Vref2=0.25V, Vref3=0.4V, N=20, A=5, and B=5.

3. The ideal diode circuit according to claim 2, characterized in that: The ultra-low voltage power supply module includes an oscillator module, charge pumps CP1~CP20, and an enable circuit. The oscillator module provides the oscillator signal to the charge pumps. The charge pumps CP1~CP20 are connected in series. The enable circuit includes a medium-voltage enable circuit and a high-voltage enable circuit. The medium-voltage enable circuit receives the enable signal EN1 from comparator comp3. EN1 is input to the gate of NMOS transistor Nu1 after passing through an inverter. EN1 is also input to the gate of PMOS transistor Pu1. The drain and source of Pu1 and Nu1 are connected across CP11~CP15. Pu1 and Nu1 form the transmission... When EN1 is at a high potential, the transmission gate is closed, and the charge pumps CP11 to CP15 boost the voltage. Conversely, when EN1 is high, the transmission gate is open, and CP11 to CP15 are short-circuited, preventing voltage boosting. Similarly, the high-voltage enable circuit receives the enable signal EN2 from comparator comp2. EN2 is input to the gate of NMOS transistor Nu2 after passing through an inverter. EN2 is also input to the gate of PMOS transistor Pu2. The drain and source of Pu2 and Nu2 are connected across CP16 to CP20. Pu2 and Nu2 form the transmission gate, controlling whether CP16 to CP20 boost the voltage.

4. The ideal diode circuit according to claim 3, characterized in that: The oscillator module is a ring oscillator.

5. The ideal diode circuit according to claim 3, characterized in that: The oscillator module, charge pump, and enable circuit in the ultra-low voltage power supply module all use low threshold devices with a threshold of 0.1V.

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