A super junction MOSFET power device
By introducing specific doped regions and contact methods into the cell structure of superjunction MOSFETs, the problems of RLC oscillation and reverse recovery charge during the switching process of superjunction MOSFETs are solved, and the switching loss and leakage current can be reduced without affecting the normal operating frequency when increasing the output capacitance during high-frequency oscillation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHINA RESOURCES MICROELECTRONICS (CHONGQING) CO LTD
- Filing Date
- 2021-12-03
- Publication Date
- 2026-05-15
AI Technical Summary
Existing superjunction MOSFETs are prone to causing strong RLC oscillations in application circuits during switching, increasing switching losses and EMI noise, and injecting a large number of non-equilibrium carriers during reverse conduction, resulting in reverse recovery charge.
A superjunction MOSFET power device is designed by introducing N-type doped regions and second P-type doped regions into the cell structure, controlling their doping concentration and distribution to increase the output capacitance in the high-frequency oscillation range while keeping it unchanged in the normal operating frequency range, thus avoiding increased device switching losses, and reducing the injection of non-equilibrium carriers through Schottky contacts.
Without increasing device switching losses, the RLC oscillation during switching is reduced, and the reverse recovery charge is decreased without increasing leakage current.
Smart Images
Figure CN116230736B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor device technology and relates to a superjunction MOSFET power device. Background Technology
[0002] Superjunction MOSFETs are widely used due to their low on-resistance, ease of driving, and fast switching speed. The alternating arrangement of N-type and P-type pillars within the superjunction body, which compensates for each other at high voltage, is a key characteristic of superjunction MOSFETs. Compared to ordinary power MOSFETs, superjunction MOSFETs have lower on-resistance and parasitic capacitance, making them more advantageous in higher power and higher frequency applications. However, during switching, the rapid depletion of the N-pillars in the superjunction causes a sudden change in output capacitance, resulting in excessively large dV / dt and dI / dt at the drain and source of the superjunction MOSFET. This leads to strong RLC oscillations (R for resistance, L for inductance, and C for capacitance) in the application circuit, increasing switching losses and EMI noise. To reduce dV / dt and dI / dt during switching, a larger gate drive resistor or an increased output capacitance is required. On the other hand, in a superjunction MOSFET, the P-type pillars are directly connected to the source electrode and are staggered within the body region. When the superjunction MOSFET is reverse-biased, a large number of non-equilibrium carriers will be injected into the P-type pillars, resulting in a large reverse recovery charge. To reduce the number of non-equilibrium carriers in the superjunction, carrier lifetime control technology is widely used.
[0003] During the switching process of a superjunction MOSFET, using a large drive resistor or increasing the output capacitance significantly increases the device's switching power consumption and drive losses, limiting the application frequency and efficiency of the superjunction MOSFET. Another approach is to improve its output capacitance characteristics by adjusting the doping concentration of the superjunction pillars or the spacing between the N-pillars and P-pillars. However, while these techniques improve the superjunction output capacitance, they also affect other electrical characteristics of the device, such as specific breakdown voltage, on-resistance, and avalanche withstand capability. Furthermore, these techniques also increase the output capacitance to some extent, thus increasing switching losses. On the other hand, reducing carrier lifetime through carrier lifetime control techniques increases the leakage current and on-resistance of the superjunction MOSFET.
[0004] In view of this, how to provide a novel superjunction MOSFET device manufacturing technology to reduce RLC oscillation and reverse recovery charge of the device without increasing the device output capacitance has become an important technical problem that needs to be solved by those skilled in the art. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a superjunction MOSFET power device to solve the problem that in the prior art, superjunction MOSFETs are prone to causing strong RLC oscillations in the application circuit during switching, thereby increasing the switching losses and EMI noise of the superjunction MOSFET. Furthermore, when the superjunction MOSFET is reverse-conducting, a large number of non-equilibrium carriers will be injected into the P-type pillar region, resulting in a large amount of reverse recovery charge.
[0006] To achieve the above and other related objectives, the present invention provides a superjunction MOSFET power device comprising multiple cell structures, wherein the cell structures include:
[0007] Drain electrode;
[0008] An N-type drain layer is located on the drain electrode;
[0009] An N-type buffer layer is located on the N-type drain layer;
[0010] The first P-pillar and the second P-pillar are located on the N-type buffer layer and are spaced apart in the horizontal direction;
[0011] The P-type body region and the first P-type doped region are located on the first P-pillar and the second P-pillar, respectively, and are spaced apart in the horizontal direction.
[0012] N-pillars are located on the N-type buffer layer and sandwiched between the first P-pillars and the second P-pillars, and between the P-type body region and the first P-type doped region;
[0013] The N-type source region and the P-type body contact region are located on the upper surface of the P-type body region, and the P-type body contact region is located on the side of the N-type source region away from the first P-type doped region.
[0014] An N-type doped region and a second P-type doped region are located within the first P-type doped region, and the second P-type doped region is located on the side of the N-type doped region away from the P-type body region. The doping concentration of the N-type doped region is less than the doping concentration of the N-type source region, and the doping concentration of the second P-type doped region is less than the doping concentration of the P-type body contact region.
[0015] A gate structure is located on the P-type body region, the N-pillar, and the first P-type doped region, and is in contact with the N-type source region and the N-type doped region;
[0016] The source electrode covers the gate structure and contacts the N-type source region and the P-type body contact region, and the source electrode extends above the N-type doped region and the second P-type doped region.
[0017] Optionally, the bottom surface of the source electrode is in contact with the top surface of the N-type doped region and the top surface of the second P-type doped region, and the contact between the source electrode and the N-type doped region is a Schottky contact, and the contact between the source electrode and the second P-type doped region is a Schottky contact.
[0018] Optionally, the cell structure further includes a P-type contact region located vertically between the second P-type doped region and the source electrode. The top surface of the P-type contact region contacts the bottom surface of the source electrode, and the bottom surface of the P-type contact region contacts the top surface of the second P-type doped region. The doping concentration of the P-type contact region is higher than that of the second P-type doped region so that the contact between the P-type contact region and the source electrode is an ohmic contact.
[0019] Optionally, the upper surface of the region of the N-type doped region not shielded by the gate structure is in contact with the lower surface of the source electrode.
[0020] Optionally, the P-type contact region extends horizontally to the upper surface of the N-type doped region and is spaced at a predetermined distance from the gate structure. The upper surface of the area of the N-type doped region that is not blocked by the gate structure and the P-type contact region is in contact with the lower surface of the source electrode.
[0021] Optionally, the P-type contact region extends horizontally to the upper surface of the N-type doped region and extends below the gate structure.
[0022] Optionally, the doping concentration of the P-type contact region is at least 10 times that of the doping concentration of the second P-type doped region.
[0023] Optionally, the doping concentration of the P-type body contact region is at least 10 times that of the doping concentration of the second P-type doped region.
[0024] Optionally, the impedance of the second P-type doped region is less than the impedance of the Miller capacitor at the normal operating frequency and greater than the impedance of the Miller capacitor at the RLC oscillation frequency, wherein the normal operating frequency is less than 1 MHz and the RLC oscillation frequency is greater than 100 MHz.
[0025] Optionally, the bottom surface of the second P-type doped region is lower than the bottom surface of the P-type body contact region, and the bottom surface of the N-type doped region is lower than the bottom surface of the N-type source region.
[0026] Optionally, in the direction from the P-type body region to the first P-type doped region, the width of the second P-type doped region is smaller than the width of the N-type doped region.
[0027] Optionally, the gate structure includes a gate dielectric layer, a gate conductive layer, and an insulating protective layer, wherein the gate conductive layer is located on the gate dielectric layer, and the insulating protective layer covers the top and side surfaces of the gate conductive layer.
[0028] As described above, the superjunction MOSFET power device of the present invention has the following advantages: Compared with directly increasing the output capacitance of the device, the superjunction MOSFET power device of the present invention only increases the output capacitance of the device within the high-frequency oscillation range, while the output capacitance remains unchanged within the normal operating frequency range. Therefore, RLC oscillation during the switching process can be reduced without increasing the switching losses of the device. Furthermore, since the present invention does not reduce the lifetime of non-equilibrium carriers, it reduces reverse recovery charge without increasing the leakage current of the device. Attached Figure Description
[0029] Figure 1 The diagram shown is a cross-sectional view of the cell structure of the superjunction MOSFET power device of the present invention in Embodiment 1.
[0030] Figure 2 The diagram shown is a cross-sectional view of the cell structure of the superjunction MOSFET power device of the present invention in Embodiment 2.
[0031] Figure 3 The diagram shown is a cross-sectional view of the cell structure of the superjunction MOSFET power device of the present invention in Embodiment 3.
[0032] Figure 4 The diagram shown is a cross-sectional view of the cell structure of the superjunction MOSFET power device of the present invention in Embodiment 4.
[0033] Component designation explanation
[0034] 1 Drain electrode
[0035] 2 N-type drain layer
[0036] 3 N-type buffer layer
[0037] 4a First P column
[0038] 4b Second P column
[0039] 5 N column
[0040] 6 P-type body region
[0041] 7 P-type body contact area
[0042] 8 N-type source region
[0043] 9 Source electrode
[0044] 10 Gate dielectric layer
[0045] 11 Gate conductive layer
[0046] 12 N-type doped regions
[0047] 13a First P-type doped region
[0048] 13b Second P-type doped region
[0049] 14 Insulation protective layer
[0050] 15 P-type contact area Detailed Implementation
[0051] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0052] Please see Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0053] Example 1
[0054] This embodiment provides a superjunction MOSFET power device, including a multi-cell structure. Please refer to [link / reference]. Figure 1 The diagram shows a cross-sectional view of the cell structure, including a drain electrode 1, an N-type drain layer 2, an N-type buffer layer 3, a first P-pillar 4a, a second P-pillar 4b, a P-type body region 6, a first P-type doped region 13a, an N-pillar 5, an N-type source region 8, a P-type body contact region 7, an N-type doped region 12, a second P-type doped region 13b, a gate structure, and a source electrode 9.
[0055] Specifically, the N-type drain layer 2 is located on the drain electrode 1; the N-type buffer layer 3 is located on the N-type drain layer 2; the first P-pillar 4a and the second P-pillar 4b are located on the N-type buffer layer 3 and are spaced apart in the horizontal direction; the P-type body region 6 and the first P-type doped region 13a are located on the first P-pillar 4a and the second P-pillar 4b respectively and are spaced apart in the horizontal direction; the N-pillar 5 is located on the N-type buffer layer 3 and is sandwiched between the first P-pillar 4a and the second P-pillar 4b and between the P-type body region 6 and the first P-type doped region 13a.
[0056] It should be noted that a P-pillar is shared by two adjacent cell structures, that is, in the horizontal direction, P-pillars and N-pillars are alternately arranged.
[0057] Specifically, the N-type source region 8 and the P-type body contact region 7 are located on the upper surface of the P-type body region 6, and the P-type body contact region 7 is located on the side of the N-type source region 8 away from the first P-type doped region 13a.
[0058] Specifically, the N-type doped region 12 and the second P-type doped region 13b are located within the first P-type doped region 13a, and the second P-type doped region 13b is located on the side of the N-type doped region 12 away from the P-type body region 6. The doping concentration of the N-type doped region 12 is less than the doping concentration of the N-type source region 8, and the doping concentration of the second P-type doped region 13b is less than the doping concentration of the P-type body contact region 7. In this embodiment, the doping concentration of the P-type body contact region 7 is at least 10 times the doping concentration of the second P-type doped region 13b.
[0059] Specifically, the gate structure is located on the P-type body region 6, the N-type pillar 5, and the first P-type doped region 13a, and is in contact with the N-type source region 8 and the N-type doped region 12. In this embodiment, the gate structure includes a gate dielectric layer 10, a gate conductive layer 11, and an insulating protective layer 14. The gate conductive layer 11 is located on the gate dielectric layer 10, and the insulating protective layer 14 covers the top and side surfaces of the gate conductive layer 11. The gate dielectric layer 10 includes, but is not limited to, a silicon dioxide layer; the gate conductive layer 11 includes, but is not limited to, a polysilicon layer; and the insulating protective layer 14 includes, but is not limited to, a silicon dioxide layer.
[0060] Specifically, the source electrode 9 covers the gate structure and contacts the N-type source region 8 and the P-type body contact region 7, and the source electrode 9 extends above the N-type doped region 12 and the second P-type doped region 13b. The source electrode 9 may be made of a conductive metal material.
[0061] In this embodiment, the N-type doped region 12 and the second P-type doped region 13b are located on the upper surface of the first P-type doped region 13a, and the bottom surface of the source electrode 9 is in contact with the top surface of the N-type doped region 12 and the top surface of the second P-type doped region 13b.
[0062] As an example, the second P-type doped region 13b can be a part of the first P-type doped region 13a, meaning the second P-type doped region 13b and the first P-type doped region 13a can be formed simultaneously in a single ion implantation. By adjusting the ion implantation energy, junction temperature, and junction time, the doping concentration of the second P-type doped region 13b can be greater than or less than the doping concentration of the first P-type doped region 13a. Of course, the second P-type doped region 13b and the first P-type doped region 13a can also be formed separately in two ion implantations.
[0063] In the cell structure of the superjunction MOSFET power device of this embodiment, the first P-type doped region 13a and the source electrode 9 are connected through the second P-type doped region 13b, and the connection resistance is determined by the second P-type doped region 13b. By reasonably setting the impedance of the connection resistance, the coupling capacitance between the first P-type doped region 13a and the gate conductive layer 11 is exhibited as an input capacitance within the normal operating frequency range, and as an output capacitance within the RLC oscillation frequency range.
[0064] Specifically, since the doping concentration of the N-type doped region 12 is relatively low (less than the doping concentration of the N-type source region 8), the holes in the first P-type doped region 13a cannot flow into the source electrode 9 through the N-type doped region 12, but can only flow into the source electrode 9 through the second P-type doped region 13b. Therefore, the connection resistance between the first P-type doped region 13a and the source electrode 9 is determined by the doping concentration, width, and thickness of the second P-type doped region 13b.
[0065] As an example, the bottom surface of the second P-type doped region 13b is lower than the bottom surface of the P-type body contact region 7. In the direction from the P-type body region to the first P-type doped region, the width of the second P-type doped region 13b is smaller than the width of the N-type doped region 12, so that the second P-type doped region 13b is elongated in the vertical direction, which is beneficial to increasing the connection resistance between the first P-type doped region 13a and the source electrode 9.
[0066] It should be noted that, in order to ensure that the second P-type doped region 13b and the N-type doped region 12 mutually deplete each other, the thickness of the N-type doped region 12 is equal to or similar to that of the second P-type doped region 13b. In this embodiment, the bottom surface of the N-type doped region 12 is lower than the bottom surface of the N-type source region 8.
[0067] Specifically, the impedance of the second P-type doped region 13b is much smaller than that of the Miller capacitor at the normal operating frequency (less than 1 MHz) and much larger than that of the Miller capacitor at the RLC oscillation frequency (greater than 100 MHz). Therefore, the coupling capacitance between the first P-type doped region 13a and the gate conductive layer 11 is an input capacitor in the normal operating frequency range and an output capacitor in the RLC oscillation frequency range.
[0068] Specifically, by controlling the doping concentration of the N-type doped region 12 and the doping concentration of the second P-type doped region 13b, the contact between the source electrode 9 and the N-type doped region 12 is a Schottky contact, and the contact between the source electrode 9 and the second P-type doped region 13b is also a Schottky contact. When the superjunction MOSFET is operating in reverse conduction, the Schottky contact formed between the second P-type doped region 13b and the source electrode 9 is reverse biased. The Schottky contact formed between the N-type doped region 12 and the source electrode 9 is forward biased, but the PN junction formed between the N-type doped region 12 and the first P-type doped region 13a is reverse biased. Therefore, non-equilibrium carriers will not be injected into the second P-type doped region 13b, the first P-type doped region 13a below the N-type doped region 12, or the second P-pillar 4b. When the superjunction MOSFET is forward-biased, the Schottky contact formed by the N-type doped region 12 and the source electrode 9 is reverse-biased, and the Schottky contact formed by the second P-type doped region 13b and the source electrode 9 is forward-biased, thereby preventing the NPN transistor composed of the N-type doped region 12, the first P-type doped region 13a, and the N-pillar 5 from turning on.
[0069] Therefore, compared to directly increasing the output capacitance of the device, the superjunction MOSFET power device in this embodiment only increases the output capacitance within the high-frequency oscillation range, while keeping the output capacitance unchanged within the normal operating frequency range. This reduces RLC oscillations during switching without increasing device switching losses. Furthermore, since this invention does not reduce the lifetime of non-equilibrium carriers, it reduces reverse recovery charge without increasing the device's leakage current.
[0070] Example 2
[0071] This embodiment uses the same technical solution as Embodiment 1. The difference is that in Embodiment 1, the second P-type doped region 13b is in direct contact with the source electrode 9, while in this embodiment, the second P-type doped region 13b is in contact with the source electrode 9 through the P-type contact region 15.
[0072] Please see Figure 2The diagram shows a cross-sectional view of the cell structure of the superjunction MOSFET power device in this embodiment. The cell structure further includes a P-type contact region 15, which is located vertically between the second P-type doped region 13b and the source electrode 9. The top surface of the P-type contact region 15 contacts the bottom surface of the source electrode 9, and the bottom surface of the P-type contact region 15 contacts the top surface of the second P-type doped region 13b. The doping concentration of the P-type contact region 15 is higher than that of the second P-type doped region 13b, so that the contact between the P-type contact region 15 and the source electrode 9 is an ohmic contact.
[0073] As an example, the P-type contact area 15 and the P-type body contact area 7 can be formed simultaneously.
[0074] As an example, the doping concentration of the P-type contact region 15 is at least 10 times that of the doping concentration of the second P-type doped region 13b.
[0075] Specifically, the upper surface of the region of the N-type doped region 12 that is not shielded by the gate structure is in contact with the lower surface of the source electrode 9.
[0076] In the cell structure of the superjunction MOSFET power device in this embodiment, the holes in the first P-type doped region 13a cannot flow into the source electrode 9 through the N-type doped region 12, but can only flow into the source electrode 9 through the second P-type doped region 13b and the P-type contact region 15 in sequence. Therefore, the connection resistance between the first P-type doped region 13a and the source electrode 9 is mainly determined by the doping concentration, width and thickness of the second P-type doped region 13b.
[0077] Example 3
[0078] This embodiment uses the same technical solution as Embodiment 2. The difference is that in Embodiment 2, the P-type contact region 15 is only located above the second P-type doped region 13b, while in this embodiment, the P-type contact region 15 extends horizontally to the upper surface of the N-type doped region 12 and is spaced at a preset distance from the gate structure.
[0079] Please see Figure 3 The diagram shows a cross-sectional view of the cell structure of the superjunction MOSFET power device in this embodiment. The upper surface of the region of the N-type doped region 12 that is not shielded by the gate structure and the P-type contact region 15 is in contact with the lower surface of the source electrode 9. That is, a part of the N-type doped region 12 is in direct contact with the lower surface of the source electrode 9, and a part of the region is in contact with the source electrode 9 through the P-type contact region 15.
[0080] Example 4
[0081] This embodiment uses the same technical solution as Embodiment 3. The difference is that in Embodiment 3, the P-type contact region 15 is spaced apart from the gate structure by a preset distance, while in this embodiment, the P-type contact region 15 extends horizontally to the upper surface of the N-type doped region 12 and further extends below the gate structure.
[0082] Please see Figure 4 The diagram shows a cross-sectional view of the cell structure of the superjunction MOSFET power device in this embodiment, wherein the N-type doped region 12 and the second P-type doped region 13b are both in contact with the source electrode 9 through the P-type contact region 15.
[0083] In summary, compared to directly increasing the output capacitance of the device, the superjunction MOSFET power device of this invention only increases the output capacitance within the high-frequency oscillation range, while maintaining the same output capacitance within the normal operating frequency range. Therefore, RLC oscillation during switching can be reduced without increasing device switching losses. Furthermore, since this invention does not reduce the lifetime of non-equilibrium carriers, it reduces reverse recovery charge without increasing leakage current. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.
[0084] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A superjunction MOSFET power device, comprising a plurality of cell structures, characterized in that, The cellular structure includes: Drain electrode; An N-type drain layer is located on the drain electrode; An N-type buffer layer is located on the N-type drain layer; The first P-pillar and the second P-pillar are located on the N-type buffer layer and are spaced apart in the horizontal direction; The P-type body region and the first P-type doped region are located on the first P-pillar and the second P-pillar, respectively, and are spaced apart in the horizontal direction. N-pillars are located on the N-type buffer layer and sandwiched between the first P-pillars and the second P-pillars, and between the P-type body region and the first P-type doped region; The N-type source region and the P-type body contact region are located on the upper surface of the P-type body region, and the P-type body contact region is located on the side of the N-type source region away from the first P-type doped region. An N-type doped region and a second P-type doped region are located within the first P-type doped region, and the second P-type doped region is located on the side of the N-type doped region away from the P-type body region. The doping concentration of the N-type doped region is less than the doping concentration of the N-type source region, and the doping concentration of the second P-type doped region is less than the doping concentration of the P-type body contact region. A gate structure is located on the P-type body region, the N-pillar, and the first P-type doped region, and is in contact with the N-type source region and the N-type doped region; The source electrode covers the gate structure and contacts the N-type source region and the P-type body contact region, and the source electrode extends above the N-type doped region and the second P-type doped region.
2. The superjunction MOSFET power device according to claim 1, characterized in that: The bottom surface of the source electrode is in contact with the top surface of the N-type doped region and the top surface of the second P-type doped region, and the contact between the source electrode and the N-type doped region is a Schottky contact, and the contact between the source electrode and the second P-type doped region is a Schottky contact.
3. The superjunction MOSFET power device according to claim 1, characterized in that: The cell structure further includes a P-type contact region, which is located vertically between the second P-type doped region and the source electrode. The top surface of the P-type contact region contacts the bottom surface of the source electrode, and the bottom surface of the P-type contact region contacts the top surface of the second P-type doped region. The doping concentration of the P-type contact region is higher than that of the second P-type doped region so that the contact between the P-type contact region and the source electrode is an ohmic contact.
4. The superjunction MOSFET power device according to claim 3, characterized in that: The upper surface of the region of the N-type doped region that is not shielded by the gate structure is in contact with the lower surface of the source electrode.
5. The superjunction MOSFET power device according to claim 3, characterized in that: The P-type contact region extends horizontally to the upper surface of the N-type doped region and is spaced at a predetermined distance from the gate structure. The upper surface of the area of the N-type doped region that is not blocked by the gate structure and the P-type contact region is in contact with the lower surface of the source electrode.
6. The superjunction MOSFET power device according to claim 3, characterized in that: The P-type contact region extends horizontally to the upper surface of the N-type doped region and extends below the gate structure.
7. The superjunction MOSFET power device according to claim 3, characterized in that: The doping concentration of the P-type contact region is at least 10 times that of the second P-type doped region.
8. The superjunction MOSFET power device according to claim 1 or 3, characterized in that: The doping concentration of the P-type body contact region is at least 10 times that of the doping concentration of the second P-type doped region.
9. The superjunction MOSFET power device according to claim 1, characterized in that: The impedance of the second P-type doped region is less than the impedance of the Miller capacitor at the normal operating frequency and greater than the impedance of the Miller capacitor at the RLC oscillation frequency, wherein the normal operating frequency is less than 1 MHz and the RLC oscillation frequency is greater than 100 MHz.
10. The superjunction MOSFET power device according to claim 1, characterized in that: The bottom surface of the second P-type doped region is lower than the bottom surface of the P-type body contact region, and the bottom surface of the N-type doped region is lower than the bottom surface of the N-type source region.
11. The superjunction MOSFET power device according to claim 1, characterized in that: In the direction from the P-type body region to the first P-type doped region, the width of the second P-type doped region is smaller than the width of the N-type doped region.
12. The superjunction MOSFET power device according to claim 1, characterized in that: The gate structure includes a gate dielectric layer, a gate conductive layer, and an insulating protective layer. The gate conductive layer is located on the gate dielectric layer, and the insulating protective layer covers the top and side surfaces of the gate conductive layer.