Reverse conducting insulated gate bipolar transistor and preparation method thereof

Abstract

The present application relates to a reverse-conducting insulated gate bipolar transistor (IGBT) and a method for fabricating the same. The reverse-conducting insulated gate bipolar transistor comprises: a drift region doped with a first conductivity type, a base region doped with a second conductivity type, and a plurality of parallel trenches extending from the surface of the drift region into the drift region, the trenches penetrating the base region and contacting the drift region at their bottoms. The trenches are provided with an insulating dielectric layer and a conductive material surrounded by the insulating dielectric layer. The base region comprises an active region and a dummy cell region, which are alternately distributed. An IGBT unit is formed by an emitter region corresponding to the active region, a contact region, and the adjacent base region, drift region, and collector region. The base region corresponding to the dummy cell region and the adjacent contact region, drift region, and cathode region form a reverse recovery transistor unit. The insulating dielectric layer of the trenches within the dummy cell region is provided with grooves. The present application optimizes the reverse recovery performance of an RC IGBT and reduces the turn-off loss of a diode without significantly increasing the process and cost.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a reverse-conducting insulated gate bipolar transistor and a method for preparing the same. Background Art

[0002] Insulated gate bipolar transistors (IGBTs) are key semiconductor components in electronic systems and are widely used in various medium- and high-voltage power control systems, such as motor drives and power conversion. IGBT devices contain three electrodes: a collector, an emitter, and a gate for controlling the switching of the device. When the gate is turned off, the IGBT of the related art is equivalent to a PNP-type transistor with an open base region, and therefore does not have reverse freewheeling capability. As a result, the IGBT of the related art can only be used as a unidirectional conducting device, that is, current can only flow from the collector to the emitter. However, most power circuit systems have the requirement for bidirectional current conduction. Therefore, in recent years, a new type of reverse conducting insulated gate bipolar transistor (RC IGBT) structure has been proposed.

[0003] Compared to related IGBTs, the RC-IGBT integrates an anti-parallel diode with the related IGBT on the same chip. This allows the RC IGBT's current to flow both from collector to emitter and vice versa, replacing the anti-parallel, separate freewheeling diode found in related IGBTs. This saves approximately one-third of the total chip area and significantly reduces chip manufacturing, packaging, and testing costs. This integrated diode structure also reduces the diode's thermal resistance and significantly improves its surge current capability. It also significantly mitigates the chip's significant junction temperature fluctuations and improves the device's power cycling capability.

[0004] However, because the diode and IGBT are integrated into the same chip, RC IGBTs suffer from poor reverse recovery performance. Using carrier lifetime control technology to increase the diode's reverse recovery speed and reduce reverse recovery losses would adversely affect the performance and reliability of the IGBT in operating mode. Summary of the Invention

[0005] The purpose of this application is to provide a reverse-conducting insulated gate bipolar transistor and a preparation method thereof, which can optimize the reverse recovery performance of the RC IGBT and reduce the turn-off loss of the diode without significantly increasing the process and cost.

[0006] In the first aspect, an embodiment of the present application provides a reverse-conducting insulated gate bipolar transistor, comprising: a drift region doped with a first conductive type; a base region doped with a second conductive type formed on the surface of the drift region, the base region comprising an active region and a virtual cell region that are staggered; a plurality of trenches extending from the surface of the drift region into the drift region and arranged in parallel, the trenches passing through the base region and contacting the drift region at the bottom, an insulating dielectric layer and a conductive material surrounded by the insulating dielectric layer provided in the trenches, the conductive material being led out from the first metal layer at the top to form a gate electrode; an emitter region heavily doped with the first conductive type and a contact region heavily doped with the second conductive type are formed on the surface of the active region of the base region, the first side surface of the emitter region is adjacent to the side surface of the corresponding trench, and the second side surface of the emitter region is adjacent to the side surface of the corresponding trench. The side surface is adjacent to the contact area, and the emitter area and the contact area are jointly led out from the first metal layer to form an emitter; a buffer layer doped with the first conductive type is formed on the back side of the drift area; a collector area heavily doped with the second conductive type and a cathode area heavily doped with the first conductive type are formed on the surface of the buffer layer, and the collector area and the cathode area are jointly led out from the second metal layer to form a collector; the emitter area corresponding to the active area, the contact area and the adjacent base area, the drift area and the collector area constitute an IGBT unit; the virtual cell area serves as the transistor anode area, and the base area corresponding to the transistor anode area and the adjacent contact area, the drift area and the cathode area constitute a reverse recovery transistor unit; wherein, the insulating dielectric layer of the trench located in the virtual cell area is provided with a groove.

[0007] In a possible implementation, the depth of the groove is 0.8 μm±0.1 μm.

[0008] In a possible implementation, an oxide layer is formed between the first metal layer and the tops of the plurality of trenches.

[0009] In a possible implementation, the reverse conducting insulated gate bipolar transistor further includes a carrier storage layer located between the drift region and the base region, and the carrier storage layer is adjacent to side surfaces of adjacent trenches.

[0010] In a possible implementation, the insulating dielectric layer is made of silicon dioxide, and the conductive material is made of polysilicon.

[0011] In a possible implementation, either one of the first conductivity type and the second conductivity type is an n-type, and the other one of the first conductivity type and the second conductivity type is a p-type.

[0012] In the second aspect, an embodiment of the present application provides a method for preparing a reverse conducting insulated gate bipolar transistor as described above, comprising: forming a drift region doped with a first conductive type; forming a base region doped with a second conductive type on the upper surface of the drift region by ion implantation and / or diffusion, the base region comprising an active region and a virtual cell region that are staggered; etching a plurality of parallel grooves on the upper surface of the drift region, the grooves passing through the base region and the bottom of which is in contact with the drift region; forming an insulating dielectric layer on the inner wall of the groove, and filling the groove with a conductive material; forming a groove by dry etching the insulating dielectric layer of the groove located in the virtual cell region; forming an emitter region heavily doped with the first conductive type and a second conductive type on the upper surface of the active region of the base region by ion implantation and / or diffusion. type heavily doped contact region; a first metal layer is deposited on the surface of the emitter region and the contact region, a conductive material is led out from the top first metal layer to form a gate electrode, and the emitter region and the contact region are jointly led out from the first metal layer to form an emitter; thinning is performed on the back side of the drift region, and a buffer layer doped with the first conductive type is formed by deep ion injection and / or diffusion; first conductive type ions are shallowly injected on the surface of the buffer layer to form a cathode region heavily doped with the first conductive type; second conductive type ions are shallowly injected on the surface of the buffer layer to form a collector region heavily doped with the second conductive type, and the collector region and the cathode region are staggered; a second metal layer is deposited on the surface of the collector region and the cathode region, and the collector region and the cathode region are jointly led out from the second metal layer to form a collector.

[0013] In a possible implementation, before depositing the first metal layer, the preparation method further includes forming an oxide layer on top of the plurality of trenches.

[0014] In one possible implementation, before forming the base region, the preparation method further includes forming a carrier storage layer doped with the first conductive type on the surface of the drift region by deep ion injection and / or diffusion, and the groove runs through the carrier storage layer.

[0015] In a possible implementation, the dry etching gas is any one of octafluorocyclopentene, carbon tetrafluoride, and trifluoromethane.

[0016] According to the reverse conducting insulated gate bipolar transistor and the preparation method thereof provided by the embodiment of the present application, a base region doped with a second conductive type is formed on the surface of a drift region doped with a first conductive type, and the base region includes an active region and a virtual cell region that are staggered; a plurality of trenches are extended from the surface of the drift region into the drift region and are arranged in parallel, the trenches pass through the base region and the bottoms are in contact with the drift region, an insulating dielectric layer and a conductive material surrounded by the insulating dielectric layer are provided in the trenches, and the conductive material is led out from the first metal layer at the top to form a gate electrode; an emitter region heavily doped with the first conductive type and a contact region heavily doped with the second conductive type are formed on the surface of the active region of the base region, a first side surface of the emitter region is adjacent to a side surface of the corresponding trench, and a second side surface of the emitter region is adjacent to a side surface of the corresponding trench. Adjacent to the contact region, the emitter region and the contact region are jointly drawn out from the first metal layer to form an emitter; a buffer layer doped with the first conductivity type is formed on the back side of the drift region; a collector region heavily doped with the second conductivity type and a cathode region heavily doped with the first conductivity type are formed on the surface of the buffer layer, and the collector region and the cathode region are jointly drawn out from the second metal layer to form a collector; an IGBT unit is composed of the contact region corresponding to the active region, the emitter region, and its adjacent trench, base region, drift region, and collector region; a dummy cell region serves as the transistor anode region, and a reverse recovery transistor unit is composed of the trench corresponding to the transistor anode region, the base region, the drift region, and the cathode region; wherein the insulating dielectric layer of the trench located in the dummy cell region is provided with a groove. Thus, by etching the groove in the insulating dielectric layer of the trench in the dummy cell region without significantly increasing the process and cost, the concentration of electron holes nearby can be reduced, thereby reducing the carrier injection efficiency, optimizing the reverse recovery performance of the RCIGBT, and reducing the turn-off loss of the diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive work. In addition, in the drawings, the same reference numerals are used for the same components, and the drawings are not drawn according to the actual scale.

[0018] Figure 1 A schematic structural diagram of a reverse-conducting insulated gate bipolar transistor provided in an embodiment of the present application is shown;

[0019] Figure 2 Show Figure 1 A schematic diagram of a partially enlarged structure of a virtual cell region of a reverse-conducting insulated gate bipolar transistor is shown;

[0020] Figure 3 Show Figure 1Schematic diagram of reverse recovery waveform simulation of reverse conducting insulated gate bipolar transistor shown;

[0021] Figure 4 Show Figure 1 The scatter plot shows the trade-off between reverse breakdown voltage and reverse recovery loss of a reverse conducting insulated gate bipolar transistor.

[0022] Description of reference numerals:

[0023] 1. Drift region; 2. Base region; 21. Active region; 22. Virtual cell region; 3. Trench; 30. Carrier storage layer; 31. Insulating dielectric layer; 32. Conductive material; 33. Recess; 41. Emitter region; 42. Contact region; 5. First metal layer; 50. Oxide layer; 6. Buffer layer; 71. Collector region; 72. Cathode region; 8. Second metal layer; G, Gate electrode; E, Emitter; C, Collector. DETAILED DESCRIPTION

[0024] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0025] Figure 1 FIG. 1 shows a schematic structural diagram of a reverse-conducting insulated gate bipolar transistor provided in an embodiment of the present application. Figure 2 Show Figure 1 The diagram shows a partially enlarged structural diagram of a virtual cell region of a reverse conducting insulated gate bipolar transistor.

[0026] like Figure 1 and Figure 2 As shown, the reverse conducting insulated gate bipolar transistor (hereinafter referred to as RC-IGBT) provided in the embodiment of the present application includes:

[0027] A drift region 1 doped with a first conductivity type;

[0028] A base region 2 doped with a second conductive type is formed on the surface of the drift region 1. The base region 2 includes an active region 21 and a dummy cell region (Dummy) 22 that are staggered.

[0029] A plurality of trenches 3 extending from the surface of the drift region 1 into the drift region 1 and arranged in parallel, the trenches 3 penetrating the base region 2 and contacting the drift region 1 at their bottoms, an insulating dielectric layer 31 and a conductive material 32 surrounded by the insulating dielectric layer 31 being disposed in the trenches 3, and the conductive material 32 being led out from the top first metal layer 5 to form a gate electrode G;

[0030] An emitter region 41 heavily doped with a first conductivity type and a contact region 42 heavily doped with a second conductivity type are formed on the surface of the active region 21 of the base region 2. A first side surface of the emitter region 41 is adjacent to a side surface of the corresponding trench 3, and a second side surface of the emitter region 41 is adjacent to the contact region 42. The emitter region 41 and the contact region 42 are jointly led out from the first metal layer 5 to form an emitter E.

[0031] A buffer layer 6 doped with a first conductivity type is formed on the back side of the drift region 1;

[0032] On the surface of the buffer layer 6, a collector region 71 heavily doped with the second conductivity type and a cathode region 72 heavily doped with the first conductivity type are formed in an alternating manner. The collector region 71 and the cathode region 72 are jointly led out from the second metal layer 8 to form a collector electrode C.

[0033] The IGBT unit is composed of the emitter region 41 corresponding to the active region 21, the contact region 42 and the adjacent base region 2, the drift region 1 and the collector region 71;

[0034] The dummy cell region 22 serves as the anode region of the transistor, and is composed of the base region 2 corresponding to the anode region of the transistor and its adjacent contact region 42 , the drift region 1 and the cathode region 72 to form a reverse recovery transistor unit;

[0035] The insulating dielectric layer 31 of the trench 3 located in the dummy cell region 22 is provided with a groove 33 .

[0036] It should be noted that in the embodiment of the present application, any one of the first conductivity type and the second conductivity type is n-type, and the other of the first conductivity type and the second conductivity type is p-type. The semiconductor substrate of the device is considered to be composed of silicon (Si) material. However, the substrate can also be composed of any other material suitable for manufacturing RC IGBT, such as germanium (Ge), silicon carbide (SiC), etc. In the following description, the material of the insulating dielectric layer of the device can be composed of silicon oxide (SiOx), but other dielectric materials can also be used, such as silicon nitride (SixNy), aluminum oxide (AlxOy) and silicon oxynitride (SixNyOz). In the following description, a p-type conductive semiconductor region can be formed by doping one or more impurities into the original semiconductor region. These impurities can be, but are not limited to, boron (B), aluminum (Al), gallium (Ga), etc. An n-type conductive semiconductor region can also be formed by doping the original semiconductor region with one or more impurities. These impurities can be, but are not limited to, phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (H+), etc. In the following description, heavily doped p-type conductive semiconductor regions are marked as p+ regions, and heavily doped n-type conductive semiconductor regions are marked as n+ regions. For example, in a silicon substrate, unless otherwise specified, the impurity concentration of a heavily doped region is generally 1×1019cm3 to 1×1021cm 3 In the following description, a lightly doped p-type conductive semiconductor region is labeled as a p-region, and a lightly doped n-type conductive semiconductor region is labeled as an n-region. For example, in a silicon substrate, unless otherwise specified, the impurity concentration of a lightly doped region is generally 1×1012cm 3 to 1×1015cm 3 between.

[0037] In addition, the following embodiments will be described using an n-type MOS channel RC IGBT device, wherein the first conductivity type is n-type and the second conductivity type is p-type. However, it should be noted that the present application is also applicable to a p-type MOS channel RC IGBT device.

[0038] like Figure 1 As shown, the drift region 1 is lightly doped with n-, and the base region 2 is p-type doped on the basis of the drift region 1. The emitter region 41 is heavily doped with n+, and the contact region 42 is heavily doped with p+. The buffer layer 6 is lightly doped with n-. The collector region 71 is heavily doped with p+, and the cathode region 72 is heavily doped with n+. Optionally, the insulating dielectric layer 31 is made of silicon dioxide SiO2, and the conductive material 32 is made of polycrystalline silicon Si.

[0039] A plurality of trenches 3 extending from the surface of the drift region 1 into the drift region 1 and arranged in parallel, for example Figure 1 The four trenches 3 shown in FIG. 3 penetrate the base region 2 and contact the drift region 1 at the bottom. An insulating dielectric layer 31 and a conductive material 32 surrounded by the insulating dielectric layer 31 are provided in the trench 3. The conductive material 32 is drawn out from the first metal layer 5 at the top to form a gate electrode G. In addition, the active region 21 and the dummy cell region 22 are alternately distributed along the lateral direction of the device. Some trenches 3 are located in the active region 21, for example. Figure 1 The two trenches 3 shown are located in the active area 21; part of the trenches 3 is located in the dummy cell area 22, for example Figure 1 The two trenches 3 shown are located in the dummy cell region 22 .

[0040] like Figure 2 As shown, the process parameters of the dummy cell region 22 are consistent with those of the active region 21, except that it does not contain a heavily n+ doped region and has no emitter region lead-out. It can serve as the anode of the reverse diode path. The main function of the dummy cell region 22 is to reduce the current gain of the trench gate IGBT, lower the amplitude of the IGBT short-circuit current, shield the peak electric field of the diode, and improve short-circuit reliability. Furthermore, a groove 33 is etched in the insulating dielectric layer 31 of the trench 3 within the dummy cell region 22, while the groove 33 is not etched in the insulating dielectric layer 31 of the trench 3 within the active region 21.

[0041] The operating principle of the RC-IGBT device in the embodiment of the present application is as follows: The RC-IGBT device has three electrodes: an emitter E at the top, a collector C at the bottom, and a gate electrode G. Among them, the gate electrode G, the insulating dielectric layer 31, the p-base region 2, the n+ type emitter region 41, the p+ contact region 42, and the n-drift region 1 together constitute a metal oxide semiconductor (hereinafter referred to as "MOS") structure. In addition, the p-base region 2, the n-drift region 1, and the p+ collector region 71 on the back together constitute a PNP bipolar transistor. The MOS structure and the PNP transistor together constitute an IGBT structure, so that the MOS structure can be used to control the current of the PNP transistor from the collector C to the emitter E, which is called the forward conduction of the RC IGBT current. On the other hand, the p+ contact region 42, the p-base region 2, the n-drift region 1, and the n+ cathode region 72 on the back together constitute a PIN diode (i.e., a reverse recovery transistor unit), wherein the p+ contact region 42 and the p-base region 2 serve as the anode of the PIN diode, and the n+ cathode region 72 serves as the cathode of the PIN diode. When the voltage of the emitter E of the RC-IGBT device is higher than the preset voltage value of the collector C, the PIN diode can be turned on, and then the current flows from the emitter E to the collector C, which is called reverse conduction of the RC IGBT current.

[0042] When the RC IGBT device is in the reverse conduction state, there are two conductive paths: the first conductive path is from the front p-base region 2 to the n-drift region 1, then through the n-buffer layer 6, and finally out of the back n+ cathode region 72. The device is equivalent to a PIN diode structure. The holes injected from the front and the electrons injected from the back in the n-drift region 1 are used to modulate the conductivity. At this time, the reverse conduction voltage drop (VF) is low. The second conductive path is through the front MOS source region, n-type channel region, n-drift region 1 and n-buffer layer 6, and finally out of the back n+ cathode region 72. The device is equivalent to an n-channel MOSFET structure. At this time, the device is in both PIN and MOSFET operating modes. Because the injection of front n-channel electron carriers suppresses the injection of holes from the front diode p-base region, the conductivity modulation of the n-drift region is weakened, and the reverse conduction voltage drop (VF) of the device will increase.

[0043] Therefore, after the insulating dielectric layer 31 of the trench 3 in the virtual cell region 22 is etched to form a groove 33, when the diode undergoes reverse recovery, the groove 33 can be used to reduce the electron-hole concentration in the vicinity thereof, thereby reducing the carrier injection efficiency, optimizing the reverse recovery performance of the RC IGBT, and reducing the turn-off loss of the diode.

[0044] According to the reverse conducting insulated gate bipolar transistor provided by the embodiment of the present application, a base region 2 doped with a second conductive type is formed on the surface of a drift region 1 doped with a first conductive type, and the base region 2 includes an active region 21 and a dummy cell region 22 that are staggered; a plurality of trenches 3 extend from the surface of the drift region 1 into the drift region 1 and are arranged in parallel, the trenches 3 pass through the base region 2 and are in contact with the drift region 1 at the bottom, an insulating dielectric layer 31 and a conductive material 32 surrounded by the insulating dielectric layer 31 are provided in the trenches 3, and the conductive material 32 is led out from the first metal layer 5 at the top to form a gate electrode G; an emitter region 41 heavily doped with a first conductive type and a contact region 42 heavily doped with a second conductive type are formed on the surface of the active region 21 of the base region 2, a first side surface of the emitter region 41 is adjacent to a side surface of the corresponding trench 3, and a second side surface of the emitter region 41 is adjacent to the contact region 42 The emitter region 41 and the contact region 42 are jointly drawn out from the first metal layer 5 to form an emitter E; a buffer layer 6 doped with a first conductive type is formed on the back of the drift region 1; a collector region 71 heavily doped with a second conductive type and a cathode region 72 heavily doped with a first conductive type are formed on the surface of the buffer layer 6, and the collector region 71 and the cathode region 72 are jointly drawn out from the second metal layer 8 to form a collector C; the IGBT unit is composed of the contact region 42 corresponding to the active region 21, the emitter region 41 and its adjacent trench 3, the base region 2, the drift region 1 and the collector region 71; the virtual cell region 22 serves as the transistor anode region, and the reverse recovery transistor unit is composed of the trench 3, the base region 2, the drift region 1 and the cathode region 72 corresponding to the transistor anode region; wherein, the insulating dielectric layer 31 of the trench 3 located in the virtual cell region 22 is provided with a groove 33. Therefore, without significantly increasing the process and cost, by etching the groove 33 in the insulating dielectric layer 31 of the groove 3 in the virtual cell area 22, the electron hole concentration in the vicinity can be reduced, thereby reducing the carrier injection efficiency, optimizing the reverse recovery performance of the RCIGBT, and reducing the turn-off loss of the diode.

[0045] In some embodiments, the depth of the groove 33 is 0.8 μm±0.1 μm.

[0046] like Figure 2 As shown, a groove 33 is etched in the insulating dielectric layer 31 of the trench 3 in the virtual cell area 22. The depth d of the groove 33 needs to be optimized and tested. If the depth d is too large, it is easy to cause the stability and reliability of the device to decrease. If the depth d is too small, the carrier regulation effect is not obvious.

[0047] This application simulates and designs the RC-IGBT under the conditions of a reverse breakdown voltage of 600 V and a current of 5 A. It is found that when the depth of the groove 33 is 0.8 μm ± 0.1 μm, the carrier injection efficiency meets the design requirements, which can optimize the reverse recovery performance of the RC IGBT and reduce the turn-off loss of the diode.

[0048] Figure 3 Show Figure 1 Schematic diagram of reverse recovery waveform simulation of reverse conducting insulated gate bipolar transistor shown; Figure 4 Show Figure 1 The scatter plot shows the trade-off between reverse breakdown voltage and reverse recovery loss of a reverse conducting insulated gate bipolar transistor.

[0049] like Figure 3 As shown, the solid line curve represents the RC-IGBT structure provided by the embodiment of the present application, and the dotted line curve represents the RC-IGBT structure of the related art. It can be seen that under the same conditions, the turn-off charge of the RC-IGBT structure of the embodiment of the present application is lower than that of the RC-IGBT structure of the related art. Figure 4 As shown, the circular points represent the RC-IGBT structure of the embodiment of the present application, and the square points represent the RC-IGBT structure of the related art. It can be seen that although the reverse breakdown voltage VF of the RC-IGBT structure of the embodiment of the present application is slightly increased by 0.2V compared with the RC-IGBT structure of the related art, the reverse recovery loss Err of the RC-IGBT structure of the embodiment of the present application is reduced by 32% compared with the RC-IGBT structure of the related art.

[0050] Furthermore, recess 33 is formed by dry etching, using an etching gas selected from octafluorocyclopentene (C5F8), carbon tetrafluoride (CF4), and trifluoromethane (CHF3). The high selectivity of the etching gas for SiO2 / Si facilitates the formation of recess 33. To optimize etching performance, such as etch rate, SiO2 / Si selectivity, and etch profile control, it is important to ensure that the highly selective gas does not affect the IGBT region. During reverse recovery, recess 33 improves the overall diode reverse recovery performance and reduces reverse recovery losses.

[0051] In some embodiments, an oxide layer 50 is further formed between the first metal layer 5 and the tops of the plurality of trenches 3. The oxide layer 50 may be provided with contact vias, so that the conductive material 32 of the trenches 3 is connected to the first metal layer 5 through the contact vias to form a gate electrode G. In addition, the oxide layer 50 also covers the emitter region 41 and the contact region 42, which are connected to the first metal layer 5 through the contact vias to form an emitter E.

[0052] In some embodiments, the RC-IGBT further includes a carrier storage layer (CS) 30 located between the drift region 1 and the base region 2. The carrier storage layer 30 is adjacent to the side surfaces of the adjacent trenches 3. The function of the carrier storage layer 30 is to reduce the hole injection efficiency in the diode operating state and to increase the emitter carrier concentration in the IGBT operating state, thereby reducing the on-state voltage drop.

[0053] In addition, the embodiment of the present application further provides a method for manufacturing the reverse conducting insulated gate bipolar transistor as described above, comprising the following steps S1 to S11:

[0054] Step S1: forming a drift region 1 doped with a first conductivity type;

[0055] Step S2: forming a base region 2 doped with a second conductivity type on the upper surface of the drift region 1 by ion implantation and / or diffusion, wherein the base region 2 includes an active region 21 and a dummy cell region 22 that are alternately distributed;

[0056] Step S3: etching a plurality of trenches 3 arranged in parallel on the upper surface of the drift region 1, wherein the trenches 3 penetrate the base region 2 and the bottoms of the trenches 3 are in contact with the drift region 1;

[0057] Step S4: forming an insulating dielectric layer 31 on the inner wall of the trench 3 and filling the trench 3 with a conductive material 32;

[0058] Step S5: forming a groove 33 in the insulating dielectric layer 31 of the trench 3 located in the dummy cell area 22 by dry etching;

[0059] Step S6: forming an emitter region 41 heavily doped with the first conductivity type and a contact region 42 heavily doped with the second conductivity type on the upper surface of the active region 21 of the base region 2 by ion implantation and / or diffusion;

[0060] Step S7: depositing a first metal layer 5 on the surface of the emitter region 41 and the contact region 42, and drawing a conductive material 32 from the top of the first metal layer 5 to form a gate electrode G. The emitter region 41 and the contact region 42 are drawn from the first metal layer 5 together to form an emitter E.

[0061] Step S8: thinning the back side of the drift region 1 and forming a first conductive type doped buffer layer 6 by deep ion implantation and / or diffusion;

[0062] Step S9: shallowly implanting first conductive type ions into the surface of the buffer layer 6 to form a cathode region 72 heavily doped with the first conductive type;

[0063] Step S10: shallowly implanting ions of the second conductive type into the surface of the buffer layer 6 to form a collector region 71 heavily doped with the second conductive type, wherein the collector region 71 and the cathode region 72 are alternately distributed;

[0064] Step S11 : depositing a second metal layer 8 on the surfaces of the collector region 71 and the cathode region 72 . The collector region 71 and the cathode region 72 are drawn out from the second metal layer 8 to form a collector electrode C.

[0065] In some embodiments, before depositing the first metal layer 5, an oxide layer 50 is further formed on top of the plurality of trenches 3. The oxide layer 50 may be provided with contact vias, so that the conductive material 32 of the trench 3 is connected to the first metal layer 5 through the contact vias to form a gate electrode G. In addition, the oxide layer 50 also covers the emitter region 41 and the contact region 42, which are connected to the first metal layer 5 through the contact vias to form an emitter E.

[0066] In some embodiments, before forming the base region 2, a carrier storage layer 30 doped with the first conductivity type is formed on the surface of the drift region 1 by deep ion implantation and / or diffusion, and the trench 3 penetrates the carrier storage layer 30. The function of the carrier storage layer 30 is to reduce the hole injection efficiency when the diode is operating, and to increase the emitter carrier concentration when the IGBT is operating, thereby reducing the on-state voltage drop.

[0067] In some embodiments, the dry etching gas is any one of octafluorocyclopentene, carbon tetrafluoride, and trifluoromethane. The high selectivity of the etching gas for SiO2 / Si facilitates the formation of recess 33. To optimize etching performance, such as etching rate, SiO2 / Si selectivity, and etching profile control, it is important to ensure that the highly selective SiO2 / Si gas does not affect the IGBT region. During reverse recovery of the diode, recess 33 is utilized to improve the overall reverse recovery performance of the device and reduce reverse recovery losses.

[0068] It should be noted that, according to the above preparation method, the RC IGBT device of the embodiment of the present application does not require an additional photoresist plate compared to the RC-IGBT device of the related art, that is, the manufacturing cost is not increased.

[0069] According to the method for preparing a reverse-conducting insulated gate bipolar transistor provided in an embodiment of the present application, by providing a groove 33 in the insulating dielectric layer 31 of the groove 3 located in the virtual cell area 22, the groove 33 can be etched in the insulating dielectric layer 31 of the groove 3 in the virtual cell area 22 without significantly increasing the process and cost, thereby reducing the electron hole concentration in the vicinity, thereby reducing the carrier injection efficiency, optimizing the reverse recovery performance of the RC IGBT, and reducing the turn-off loss of the diode.

[0070] It should be noted that references in this specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," and the like indicate that the described embodiment may include a particular feature, structure, or characteristic, but not necessarily every embodiment includes that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not.

[0071] It should be readily understood that “on,” “above,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers therebetween, and “above” or “over” includes not only the meaning of “above” or “over,” but also includes “above” or “over” with no intervening features or layers therebetween (i.e., directly on something).

[0072] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A reverse conducting insulated gate bipolar transistor, characterized in that: include: a drift region doped with a first conductivity type; A base region doped with a second conductive type is formed on the surface of the drift region, wherein the base region includes an active region and a dummy cell region that are staggered; a plurality of trenches extending from the surface of the drift region into the drift region and arranged in parallel, the trenches penetrating the base region and having bottoms in contact with the drift region, an insulating dielectric layer and a conductive material surrounded by the insulating dielectric layer being disposed in the trenches, the conductive material being led out from the top first metal layer to form a gate electrode; An emitter region heavily doped with a first conductivity type and a contact region heavily doped with a second conductivity type are formed on the surface of the active region of the base region, a first side surface of the emitter region is adjacent to a side surface of the corresponding trench, a second side surface of the emitter region is adjacent to the contact region, and the emitter region and the contact region jointly lead out an emitter from the first metal layer; A buffer layer doped with a first conductive type is formed on the back side of the drift region; A collector region heavily doped with the second conductive type and a cathode region heavily doped with the first conductive type are formed on the surface of the buffer layer, and the collector region and the cathode region are jointly led out from the second metal layer to form a collector electrode; An IGBT unit is formed by the emitter region corresponding to the active region, the contact region and the adjacent base region, the drift region and the collector region; The virtual cell region serves as an anode region of the transistor, and the base region corresponding to the anode region of the transistor and the adjacent contact region, the drift region and the cathode region form a reverse recovery transistor unit; Wherein, the insulating dielectric layer of the trench located in the virtual cell area is provided with a groove.

2. The reverse conducting insulated gate bipolar transistor according to claim 1, wherein: The depth of the groove is 0.8 μm±0.1 μm.

3. The reverse conducting insulated gate bipolar transistor according to claim 1, wherein: An oxide layer is formed between the first metal layer and the tops of the plurality of trenches.

4. The reverse conducting insulated gate bipolar transistor according to claim 1, wherein: The invention further includes a carrier storage layer located between the drift region and the base region, wherein the carrier storage layer is adjacent to side surfaces of the adjacent trenches.

5. The reverse conducting insulated gate bipolar transistor according to claim 1, wherein The insulating dielectric layer is made of silicon dioxide, and the conductive material is made of polysilicon.

6. The reverse conducting insulated gate bipolar transistor according to claim 1, wherein: Either one of the first conductivity type and the second conductivity type is an n-type, and the other one of the first conductivity type and the second conductivity type is a p-type.

7. A method for preparing a reverse conducting insulated gate bipolar transistor according to any one of claims 1 to 6, characterized in that: include: forming a drift region doped with a first conductivity type; forming a base region doped with a second conductive type on the upper surface of the drift region by ion implantation and / or diffusion, wherein the base region includes an active region and a dummy cell region that are alternately distributed; Etching a plurality of trenches arranged in parallel on the upper surface of the drift region, wherein the trenches penetrate the base region and the bottoms of the trenches are in contact with the drift region; forming an insulating dielectric layer on an inner wall of the trench and filling the trench with a conductive material; forming a groove in the insulating dielectric layer of the trench located in the dummy cell region by dry etching; forming an emitter region heavily doped with a first conductivity type and a contact region heavily doped with a second conductivity type on an upper surface of the active region of the base region by ion implantation and / or diffusion; Depositing a first metal layer on the surface of the emitter region and the contact region, the top of the conductive material is led out from the first metal layer to form a gate electrode, and the emitter region and the contact region are jointly led out from the first metal layer to form an emitter; Thinning the back side of the drift region and forming a first conductive type doped buffer layer by deep ion implantation and / or diffusion; Performing shallow implantation of first conductive type ions on the surface of the buffer layer to form a cathode region heavily doped with the first conductive type; Performing shallow implantation of second conductive type ions on the surface of the buffer layer to form a collector region heavily doped with the second conductive type, wherein the collector region and the cathode region are staggered; A second metal layer is deposited on the surfaces of the collector region and the cathode region, and the collector region and the cathode region are jointly led out from the second metal layer to form a collector electrode.

8. The preparation method according to claim 7, characterized in that Before depositing the first metal layer, the method further includes forming an oxide layer on top of the plurality of trenches.

9. The preparation method according to claim 7, characterized in that Before forming the base region, the method further includes forming a carrier storage layer doped with a first conductive type on the surface of the drift region by deep ion implantation and / or diffusion, and the trench penetrates the carrier storage layer.

10. The preparation method according to claim 7, characterized in that The dry etching gas is any one of octafluorocyclopentene, carbon tetrafluoride and trifluoromethane.

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