Light-emitting diode epitaxial wafer and preparation method thereof

Abstract

The present invention relates to the technical field of light-emitting diodes, and in particular to a light-emitting diode epitaxial wafer and a preparation method thereof. The epitaxial wafer comprises: a substrate, a low-temperature GaN buffer layer, an undoped high-temperature GaN buffer layer, an n-type GaN layer, a light-emitting layer, an electron blocking layer, a p-type GaN layer, and a p-type contact layer stacked in sequence; the light-emitting layer is composed of a first multi-quantum well barrier layer, an n-type isolation layer, a stress compensation layer, a second multi-quantum well barrier layer, a p-type isolation layer, and a third multi-quantum well barrier layer stacked in sequence; the content of an In component in each barrier layer of the first multi-quantum well barrier layer linearly changes from large to small, and the content of an Al component linearly changes from small to large along the epitaxial growth direction; the content of an In component in each barrier layer of the second multi-quantum well barrier layer linearly changes from small to large, and the content of an Al component linearly changes from large to small along the epitaxial growth direction.

Description

Technical Field

[0001] The present invention relates to the technical field of light-emitting diodes, and in particular to a light-emitting diode epitaxial wafer and a preparation method thereof. Background Art

[0002] As a representative of third-generation semiconductors, gallium nitride (GaN) has become the most promising material for future semiconductors due to its wide bandgap and high electron mobility. GaN-based devices, in particular, are widely used in electronic systems such as wireless communications and radar in the microwave and millimeter wave bands, and hold great promise for development in optoelectronics and microelectronics.

[0003] Currently, epitaxial structures are commonly used, consisting of a substrate, a buffer layer, an n-type layer, a multi-quantum well, an electron blocking layer, a p-type GaN layer, and a p-type contact layer. The primary source of light emission is the multi-quantum well layer. For GaN epitaxial layers, polarization effects are a significant factor influencing device performance. As the In content increases, the lattice mismatch between the InGaN well layer and the GaN barrier layer increases rapidly, and the compressive strain in the InGaN well layer increases rapidly, leading to a strong piezoelectric polarization effect in the well layer and the generation of a large number of misfit dislocations. The resulting spontaneous polarization and piezoelectric polarization cause the wave functions of electrons and holes in the quantum well to separate spatially, thereby reducing the recombination probability of electrons and holes. This also leads to severe band bending, which reduces the quantum well's ability to confine carriers, resulting in a large leakage current.

[0004] In order to improve the photoelectric conversion efficiency of GaN-based light-emitting devices, one method is to reduce the piezoelectric polarization effect, and another method is to reduce the spontaneous polarization effect. However, many structures are not effective in reducing polarization. For example, InGaN, AlInN or AlxGa1-xN are used as quantum barriers, and the thickness of the wells and barriers in the quantum wells, the number of quantum wells, and the doping of the quantum well barriers are adjusted to limit the overflow of carriers and improve the ability of holes to be evenly distributed, that is, to increase the recombination probability of the wave function, but the effect is limited. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention provides a light emitting diode epitaxial wafer and a preparation method thereof.

[0006] The present invention adopts the following technical solution: a light emitting diode epitaxial wafer, comprising:

[0007] A substrate, a low-temperature GaN buffer layer, an undoped high-temperature GaN buffer layer, an n-type GaN layer, a light-emitting layer, an electron blocking layer, a p-type GaN layer, and a p-type contact layer are stacked in sequence;

[0008] The light-emitting layer is composed of a first multi-quantum well barrier layer, an n-type isolation layer, a stress compensation layer, a second multi-quantum well barrier layer, a p-type isolation layer, and a third multi-quantum well barrier layer stacked in sequence;

[0009] The content of the In component in each barrier layer of the first multi-quantum well barrier layer changes linearly from large to small along the epitaxial growth direction, and the content of the In component in each barrier layer of the second multi-quantum well barrier layer changes linearly from small to large along the epitaxial growth direction;

[0010] The Al content in each barrier layer of the first multi-quantum well barrier layer changes linearly from small to large along the epitaxial growth direction, and the Al content in each barrier layer of the second multi-quantum well barrier layer changes linearly from large to small along the epitaxial growth direction.

[0011] In the present invention, the Al composition and In composition in each barrier layer of the first multi-quantum well barrier layer and each barrier layer of the second multi-quantum well barrier layer change linearly, so that the original sudden potential energy gradient at the boundary between the adjacent barrier layer and the well layer in the light-emitting layer is modulated into a potential energy gradient with a linear buffer change, thereby effectively reducing the influence of the excessive sudden change of the potential energy gradient at the well-barrier boundary, which hinders the transport of holes to the deep quantum well, and at the same time weakening the piezoelectric polarization effect caused by the lattice mismatch between the well layer and the barrier layer, thereby improving the wave function overlap efficiency; through the design of linear component change, polarization-induced holes are generated in the well layer or barrier layer, and the hole concentration is made equivalent to the background electron concentration of the well layer or barrier layer material, thereby generating a compensation effect, and finally forming a high-resistance layer of the well layer or barrier layer, thereby effectively improving the luminescence efficiency of the epitaxial wafer.

[0012] Furthermore, a thickness ratio of a single layer of the first multi-quantum well barrier layer to a single layer of the second multi-quantum well barrier layer is 1:1.

[0013] Furthermore, each barrier layer of the first multi-quantum well layer is doped with Si element, and the doping concentration is 5×10 17 cm -3 ~1×10 19 cm -3 The n-type isolation layer is doped with Si element, and the doping concentration is 5×10 17 cm -3 ~1×10 19 cm -3 .

[0014] Furthermore, each barrier layer of the third multi-quantum well barrier layer is doped with Mg element, and the doping concentration is 5×10 17 cm -3 ~1×10 19 cm -3 The p-type isolation layer is doped with Mg element, and the doping concentration is 5×10 17 cm -3~1×10 19 cm -3 .

[0015] Furthermore, each well layer of the first multi-quantum well barrier layer, the second multi-quantum well barrier layer and the third multi-quantum well barrier layer is grown under an N2 atmosphere, and each barrier layer of the first multi-quantum well barrier layer, the second multi-quantum well barrier layer and the third multi-quantum well barrier layer is grown under an H2 atmosphere.

[0016] Furthermore, the first multi-quantum well barrier layer is composed of 5 to 8 first quantum well barrier layers stacked on each other, and the first quantum well barrier layer includes first In y1 Ga 1-y1 N-well layer and the first AlIn y2 GaN barrier layer, the thickness of the first quantum well barrier layer is between 3nm and 5nm; the second multi-quantum well barrier layer is composed of 3 to 10 second quantum well barrier layers stacked on each other, and the second quantum well barrier layer includes a second In y1 Ga 1-y1 N-well layer and second AlIn y2 GaN barrier layer, the thickness of the second quantum well barrier layer is between 2nm and 6nm, the third multi-quantum well barrier layer is composed of 2 to 3 third quantum well barrier layers stacked on each other, and the third quantum well barrier layer includes a third In y1 Ga 1-y1 N well layer and the third AlIn y2 GaN barrier layer, the thickness of the third quantum well barrier layer is between 2nm and 5nm, wherein 0.1<y1<0.5, 0<y2<0.15.

[0017] Furthermore, the stress compensation layer is composed of 5 to 8 Si3N4 layers and A y3 Ga 1-y3 N layer is a periodic stacking group stacked on each other, or composed of 5 to 8 AlN layers stacked in sequence with A y3 Ga 1-y3 N layers are stacked in a periodic manner, wherein the A y3 Ga 1-y3 The element A in the N layer is at least one of In, Al, B, and Zn, and 0.01≤y3≤0.1.

[0018] Furthermore, the thickness of the Si3N4 layer or the AlN layer is 1nm to 3nm, and the A y3 Ga 1-y3 The thickness of the N layer is 1nm to 3nm, and the Si3N4 layer or the AlN layer is y3 Ga 1-y3 The ratio of the thickness of the N layer is 1:1.

[0019] Furthermore, the thickness of the n-type isolation layer is 10 nm to 17 nm, the thickness of the p-type isolation layer is 10 nm to 17 nm, and both the n-type isolation layer and the p-type isolation layer are GaN layers.

[0020] The present invention also provides a method for preparing a light-emitting diode epitaxial wafer, which is used to prepare the light-emitting diode epitaxial wafer in the above-mentioned solution, and the preparation method comprises:

[0021] providing a substrate;

[0022] growing a low-temperature GaN buffer layer on the substrate;

[0023] growing an undoped high-temperature GaN buffer layer on the low-temperature GaN buffer layer;

[0024] growing an n-type GaN layer on the undoped high-temperature GaN buffer layer;

[0025] Growing a light-emitting layer on the n-type GaN layer, the light-emitting layer being composed of a first multi-quantum well barrier layer, an n-type isolation layer, a stress compensation layer, a second multi-quantum well barrier layer, a p-type isolation layer, and a third multi-quantum well barrier layer stacked in sequence;

[0026] depositing an electron blocking layer on the third multi-quantum well barrier layer;

[0027] depositing a p-type GaN layer on the electron blocking layer;

[0028] A p-type contact layer is deposited on the p-type GaN layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 Schematic diagram of the structure of a light emitting diode epitaxial wafer according to a first embodiment of the present invention;

[0031] Figure 2 for Figure 1 A magnified schematic diagram of part A in the middle;

[0032] Figure 3 Flowchart of a method for preparing a light emitting diode epitaxial wafer according to a first embodiment of the present invention.

[0033] Description of reference numerals:

[0034] 11 substrate, 12 low-temperature GaN buffer layer, 13 undoped high-temperature GaN buffer layer, 14n-type GaN layer, 15 light-emitting layer, 151 first multi-quantum well barrier layer, 1511 first quantum well barrier layer, 152 n-type isolation layer, 153 stress compensation layer, 154 second multi-quantum well barrier layer, 1541 second quantum well barrier layer, 155 p-type isolation layer, 156 third multi-quantum well barrier layer, 1561 third quantum well barrier layer, 16 electron blocking layer, 17 p-type GaN layer, 18 p-type contact layer. DETAILED DESCRIPTION

[0035] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the embodiments of the present invention, and should not be construed as limiting the present invention.

[0036] In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0038] In the embodiments of the present invention, unless otherwise expressly specified or limited, the terms "installed," "connected," "connected," "fixed," etc. should be understood in a broad sense. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the embodiments of the present invention based on specific circumstances.

[0039] Example 1

[0040] Reference Figures 1 to 3A light-emitting diode epitaxial wafer includes: a substrate 11, a low-temperature GaN buffer layer 12, an undoped high-temperature GaN buffer layer 13, an n-type GaN layer 14, a light-emitting layer 15, an electron blocking layer 16, a p-type GaN layer 17, and a p-type contact layer 18 stacked in sequence; the substrate 11 can be one of a Si substrate, a sapphire substrate, a SiC substrate, and a SiO2 substrate. In this embodiment, the substrate 11 is a sapphire substrate.

[0041] The light-emitting layer 15 is composed of a first multi-quantum well barrier layer 151, an n-type isolation layer 152, a stress compensation layer 153, a second multi-quantum well barrier layer 154, a p-type isolation layer 155, and a third multi-quantum well barrier layer 156 stacked in sequence; wherein the content of the In component in each barrier layer of the first multi-quantum well barrier layer 151 linearly changes from large to small along the epitaxial growth direction, and the content of the In component in each barrier layer of the second multi-quantum well barrier layer 154 linearly changes from small to large along the epitaxial growth direction; the content of the Al component in each barrier layer of the first multi-quantum well barrier layer 151 linearly changes from small to large along the epitaxial growth direction, and the content of the Al component in each barrier layer of the second multi-quantum well barrier layer 154 linearly changes from large to small along the epitaxial growth direction.

[0042] In the present invention, the Al composition and In composition in each barrier layer of the first multi-quantum well barrier layer 151 and each barrier layer of the second multi-quantum well barrier layer 154 change linearly, so that the original sudden potential energy gradient at the boundary between the adjacent barrier layer and the well layer in the light-emitting layer 15 is modulated into a potential energy gradient with a linear buffer change, thereby effectively reducing the influence of the excessive sudden potential energy gradient at the well-barrier boundary on the transport of holes to the deep quantum well, and at the same time weakening the piezoelectric polarization effect caused by the lattice mismatch between the well layer and the barrier layer, thereby improving the wave function overlap efficiency; through the design of linear composition change, polarization-induced holes are generated in the well layer or barrier layer, and the hole concentration is made equivalent to the background electron concentration of the well layer or barrier layer material, thereby producing a compensation effect, and finally forming a high-resistance layer of the well layer or barrier layer, effectively improving the luminescence efficiency of the epitaxial wafer.

[0043] In this embodiment, the first multi-quantum well barrier layer 151 is composed of six first quantum well barrier layers 1511 stacked one on top of the other. The first quantum well barrier layer 1511 includes first In y1 Ga 1-y1 N-well layer and the first AlIn y2 GaN barrier layer, the thickness of the first quantum well barrier layer 1511 is between 3nm and 5nm; the second multi-quantum well barrier layer 154 is composed of 6 second quantum well barrier layers 1541 stacked on each other, and the second quantum well barrier layer 1541 includes a second In y1 Ga 1-y1 N-well layer and second AlIn y2GaN barrier layer, the thickness of the second quantum well barrier layer 1541 is between 2nm and 6nm, the third multi-quantum well barrier layer 156 is composed of two third quantum well barrier layers 1561 stacked on each other, and the third quantum well barrier layer 1561 includes a third In y1 Ga 1-y1 N well layer and the third AlIn y2 The thickness of the GaN barrier layer and the third quantum well barrier layer 1561 is between 2 nm and 5 nm, wherein 0.1<y1<0.5, 0<y2<0.15; specifically, the thickness of the first quantum well barrier layer 1511 is 4 nm, the thickness of the second quantum well barrier layer 1541 is 4 nm, and the thickness of the third quantum well barrier layer 1561 is 3.5 nm; y1=0.3, y2=0.1.

[0044] In this embodiment, the thickness ratio of the single layer barrier layer of the first multi-quantum well barrier layer 151 to the single layer barrier layer of the second multi-quantum well barrier layer 154 is 1:1; y2 The content of In component in GaN barrier layer changes linearly from 15% to 0 along the epitaxial growth direction. y2 The content of In component in GaN barrier layer changes linearly from 0 to 15% along the epitaxial growth direction. y2 The content of Al component in GaN barrier layer changes linearly from 10% to 40% along the epitaxial growth direction. y2 The content of Al component in GaN barrier layer changes linearly from 40% to 10% along the epitaxial growth direction; the first AlIn y2 GaN barrier layer and the second AlIn y2 The thickness ratio of the GaN barrier layer is 1:1.

[0045] In this embodiment, the growth pattern of each well layer of the first multi-quantum well barrier layer 151, each well layer of the second multi-quantum well barrier layer 154, and each well layer of the third multi-quantum well barrier layer 156 is a trapezoidal form, and the In composition therein remains unchanged, between 10% and 50%; in this embodiment, each first In y1 Ga 1-y1 N well layer, each second In y1 Ga 1-y1 N well layer and each third In y1 Ga 1- y1 The content of In component in the N-well layer is 30%.

[0046] Each barrier layer of the first multi-quantum well layer 151 is doped with Si element, with a doping concentration of 5×10 17 cm -3 ~1×10 19 cm -3, Si element is doped in the n-type isolation layer 152, and the doping concentration is 5×10 17 cm -3 ~1×10 19 cm -3 ; The electron potential barrier is reduced, the mobility of electrons is enhanced, the electron concentration of the first multi-quantum well barrier layer 151 is balanced, and excessive electron overshoot is prevented, thereby weakening the droop effect; In this embodiment, each barrier layer of the first multi-quantum well barrier layer 151 is doped with 5×10 18 cm -3 Si element, the n-type isolation layer 152 is doped with 5×10 18 cm -3 of Si element.

[0047] Each barrier layer of the third multi-quantum well layer 156 is doped with Mg element, with a doping concentration of 5×10 17 cm -3 ~1×10 19 cm -3 Mg is doped in the p-type isolation layer 155 at a concentration of 5×10 17 cm -3 ~1×10 19 cm -3 ; The hole barrier height is reduced, the hole mobility is increased, the hole injection efficiency is improved, the electron-hole recombination efficiency is improved, and the electron barrier height is increased, which weakens the droop effect caused by electron overshoot; In this embodiment, each barrier layer of the third multi-quantum well barrier layer 156 is doped with 5.5×10 18 cm -3 Mg element, the p-type isolation layer 155 is doped with 5.5×10 18 cm -3 of Mg element.

[0048] The well layers of the first multi-quantum well barrier layer 151, the second multi-quantum well barrier layer 154 and the third multi-quantum well barrier layer 156 are all grown under an N2 atmosphere, and the barrier layers of the first multi-quantum well barrier layer 151, the second multi-quantum well barrier layer 154 and the third multi-quantum well barrier layer 156 are all grown under an H2 atmosphere; the well layers in the light-emitting layer 15 are all nitrogen polar and the barrier layers are all gallium polar. Since the polarity directions of the nitrogen polar surface and the gallium polar surface are opposite, the spontaneous polarity effect is reduced and the wave function overlap efficiency is increased.

[0049] The stress compensation layer 153 is composed of 5 to 8 Si3N4 layers and A y3 Ga 1-y3 N layer is a periodic stacking group stacked on each other, or composed of 5 to 8 AlN layers stacked in sequence with A y3 Ga1-y3 N layers form a periodic stack of layers stacked on top of each other, where A y3 Ga 1-y3 The element A in the N layer is at least one of In, Al, B, and Zn, 0.01≤y3≤0.1; the thickness of the Si3N4 layer or the AlN layer is 1nm to 3nm, A y3 Ga 1-y3 The thickness of the N layer is 1nm to 3nm, and the Si3N4 layer or AlN layer is y3 Ga 1-y3 The thickness ratio of the N layer is 1:1; the role of the stress compensation layer 153 is to continuously block and change the extension of the dislocation line from the bottom layer through the Si3N4 layer, so that multiple dislocation lines cross and achieve the effect of annihilation. At the same time, due to the relatively small atomic volume of A, it can be inserted or filled in the blank position caused by the dislocation, indirectly weakening the piezoelectric polarization effect. At the same time, the Si3N4 layer and A y3 Ga 1-y3 The thickness of the N layer is thin, and as it changes periodically, the compressive stress is weakened and brought into the second multi-quantum well barrier layer 154 to cause a piezoelectric polarization effect, that is, a strained superlattice structure is formed. In this embodiment, the stress compensation layer 153 is composed of 6 Si3N4 layers and A layers stacked in sequence. y3 Ga 1- y3 The N layer is a periodic stack of layers stacked on top of each other. The thickness of the Si3N4 layer is 2nm. y3 Ga 1-y3 The thickness of the N layer is 2nm, and the y3 Ga 1-y3 The element A in the N layer is Al, and y3=0.05.

[0050] The thickness of the n-type isolation layer 152 is 10nm-17nm, and the thickness of the p-type isolation layer 155 is 10nm-17nm; both the n-type isolation layer and the p-type isolation layer are GaN layers; in this embodiment, the thickness of the n-type isolation layer 152 is 13nm, and the thickness of the p-type isolation layer 155 is 13nm.

[0051] The present invention also provides a method for preparing a light-emitting diode epitaxial wafer, which is used to prepare the light-emitting diode epitaxial wafer in the above-mentioned solution, and the preparation method comprises:

[0052] S1: providing a substrate 11;

[0053] In this embodiment, a sapphire substrate was selected and placed in a metal-organic chemical vapor deposition (MOCVD) reaction chamber. The metal-organic sources included trimethylgallium (TMGa), triethylgallium (TEGa), trimethylaluminum (TMAl), boron trichloride (BCl3), and trimethylindium (TMIn). The nitrogen source was ammonia (NH3), and the carrier gases were N2 and H2. The p-type dopant and n-type dopant were Cp2Mg and SiH4, respectively. The sapphire substrate was treated with H2 and NH3 at a temperature of 1000-1150°C for 4-15 minutes to prevent surface oxidation and contamination. Specifically, the sapphire substrate was treated with H2 and NH3 at a temperature of 1100°C for 9 minutes.

[0054] S2: growing a low-temperature GaN buffer layer 12 on the substrate 11;

[0055] In this embodiment, in this embodiment, TMGa and NH3 are introduced into an H2 (hydrogen) atmosphere, the temperature is lowered to between 450°C and 650°C, the pressure is controlled between 400 and 760 Torr, the V / III molar ratio is between 500 and 3200, and a low-temperature GaN buffer layer 12 with a thickness of 15 to 35 nm is grown; wherein V / III is the ratio of the N source to the Ga source.

[0056] Specifically, the temperature is lowered to 500° C., the pressure is controlled at 580 Torr, the V / III molar ratio is 1000, and a 20 nm thick low-temperature GaN buffer layer 12 is grown.

[0057] S3: growing an undoped high-temperature GaN buffer layer 13 on the low-temperature GaN buffer layer 12;

[0058] In this embodiment, after the growth of the low-temperature GaN buffer layer 12 is completed, the substrate temperature is subjected to in-situ thermal annealing treatment, and the substrate temperature is raised to between 950 and 1200°C. The annealing time is between 5 and 10 minutes. After annealing, TMGa and NH3 are introduced, and the temperature is adjusted to between 1000 and 1200°C to grow an undoped high-temperature GaN buffer layer 13 with a thickness of between 0.8um and 4um. During this growth process, the pressure is between 100Torr and 600Torr, and the V / III molar ratio is between 300 and 3300.

[0059] Specifically, the temperature is raised to 1000° C., and the annealing time is 7 minutes. After annealing, the temperature is adjusted to 1100° C. to grow an undoped high-temperature GaN buffer layer 13 with a thickness of 1 μm. During this growth process, the pressure is 350 Torr and the V / III molar ratio is 1500.

[0060] S4: growing an n-type GaN layer 14 on the undoped high-temperature GaN buffer layer 13;

[0061] In this embodiment, the substrate 11 is heated at a temperature of 1000-1100° C., the reaction chamber pressure is 100-200 torr, and the atmosphere is H 2 . The V / III molar ratio is 1000-1300, the Si doping concentration is 1×10 18 cm -3 ~1×10 19 cm -3 , grow an n-type GaN layer 14 with a thickness of 2 to 4 μm.

[0062] Specifically, at 1050°C, a reaction chamber pressure of 150 torr, and an H2 atmosphere, with a V / III molar ratio of 1150 and a Si doping concentration of 5×10 18 cm -3 , grow a 3 μm thick n-type GaN layer 14.

[0063] S5: growing a light-emitting layer 15 on the n-type GaN layer 14, wherein the light-emitting layer 15 is composed of a first multi-quantum well barrier layer 151, an n-type isolation layer 152, a stress compensation layer 153, a second multi-quantum well barrier layer 154, a p-type isolation layer 155, and a third multi-quantum well barrier layer 156 stacked in sequence;

[0064] In this embodiment, the light-emitting layer 15 is grown in a manner that includes inserting an n-type isolation layer 152 and a stress compensation layer 153 between the first multi-quantum well barrier layer 151 and the second multi-quantum well barrier layer 154 from bottom to top; inserting a p-type isolation layer 155 between the second multi-quantum well barrier layer 154 and the third multi-quantum well barrier layer 156; the growth atmosphere of each well layer of the first multi-quantum well barrier layer 151, each well layer of the second multi-quantum well barrier layer 154, and each well layer of the third multi-quantum well barrier layer 156 is all N2. The growth temperature is between 750°C and 950°C, and each well layer is transformed into a nitrogen-polarity quantum well. The growth atmosphere of each barrier layer of the first multi-quantum well barrier layer 151, each barrier layer of the second multi-quantum well barrier layer 154, and each barrier layer of the third multi-quantum well barrier layer 156 is all H2, and the growth temperature is between 950°C and 1080°C, and each barrier layer is transformed into a gallium-polarity quantum barrier. The growth pressure of the well barrier is between 200Torr and 500Torr, and the V / III molar ratio of the well barrier is between 400 and 5300.

[0065] The In composition in each barrier layer of the first multi-quantum well barrier layer 151 gradually changes from 0.15 to 0, and the In composition in each barrier layer of the second multi-quantum well barrier layer 154 gradually changes from 0 to 0.15; the Al composition in each barrier layer of the first multi-quantum well barrier layer 151 gradually changes from 0.1 to 0.4, and the Al composition in each barrier layer of the second multi-quantum well barrier layer 154 gradually changes from 0.4 to 0.1. The thickness of a single barrier layer in the first multi-quantum well barrier layer 151 and the thickness of a single barrier layer in the second multi-quantum well barrier layer 154 are 1:1; the growth pattern of each well layer in the light-emitting layer 15 is a trapezoidal form, and the In composition therein remains unchanged, between 0.15 and 0.5.

[0066] The growth method of the first multi-quantum well barrier layer 151 structure is as follows: introducing TMGa, NH3, TMln, SiH4, and TMAl to grow the first multi-quantum well barrier layer 1511, which is composed of 5 to 8 stacked first quantum well barrier layers 1511. The first quantum well barrier layer 1511 includes the first In layer stacked in sequence. y1 Ga 1-y1 N-well layer and the first AlIn y2 The thickness of the GaN barrier layer and the first quantum well barrier layer 1511 is between 3nm and 5nm. The barrier layers in the first multi-quantum well barrier layer 151 are all doped with Si elements with a doping concentration of 5×10 17 cm -3 ~1×10 19 cm -3 The second multi-quantum well barrier layer 154 is grown by stacking 3 to 10 second quantum well barrier layers 1541 on top of each other, and the second quantum well barrier layer 1541 includes a second In layer stacked sequentially. y1 Ga 1-y1 N-well layer and second AlIn y2 GaN barrier layer, the thickness of the second quantum well barrier layer 1541 is between 2nm and 6nm; the growth method of the structure of the third multi-quantum well barrier layer 156 is: it is composed of 2 to 3 third quantum well barrier layers 1561 stacked on each other, and the third quantum well barrier layer 1561 includes a third In layer stacked in sequence. y1 Ga 1-y1 N well layer and the third AlIn y2 The thickness of the GaN barrier layer and the third quantum well barrier layer 1561 is between 2 nm and 5 nm. The barrier layers in the third multi-quantum well barrier layer 156 are all doped with Mg elements with a doping concentration of 5×10 17 cm -3 ~1×10 19 cm -3 , where 0.1<y1<0.5, 0<y2<0.15.

[0067] The thickness of the n-type isolation layer 152 is 10-17 nm, the growth atmosphere is H2 and N2, the growth temperature is 750-1000°C, the growth pressure is between 200 Torr and 500 Torr, and the V / III molar ratio of the well barrier is between 400-4000. The thickness of the p-type isolation layer 155 is 10-17 nm, the growth atmosphere is H2 and N2, the growth temperature is 750-1000°C, the growth pressure is between 200 Torr and 500 Torr, and the V / III molar ratio of the well barrier is between 400-4000. The Si element doping concentration of the n-type isolation layer 152 is 5×10 17 cm -3 ~1×10 19 cm -3 The Mg doping concentration of the p-type isolation layer 155 is 5×10 17 cm -3 ~1×10 19 cm -3 .

[0068] The thickness of Si3N4 or AlN in the stress compensation layer 153 is 1-3 nm. y3 Ga 1-y3 The thickness of N is 1 to 3 nm, the thickness ratio is 1:1, the growth cycle is 5 to 10, the growth temperature is 700 to 1000°C, the reaction chamber pressure is 100 to 200 torr, and under H2 atmosphere, the V / III molar ratio is 1000 to 1300, TMln, TMGa, NH3, TMAl, BCl3, DMZn are introduced, 0.01≤y3≤0.1, and element A can be one or more of In, Al, B or Zn.

[0069] Specifically, the well layer growth atmosphere of all the multi-quantum well barrier layers in the light-emitting layer 15 is N2, the growth temperature is 810°C, and each well layer is converted into a nitrogen-polarity quantum well. The barrier layer growth atmosphere of all the multi-quantum well barrier layers in the light-emitting layer 15 is H2, the growth temperature is 1050°C, and each barrier layer is converted into a gallium-polarity quantum barrier. The growth pressure of the well barrier is 200 Torr, and the V / III molar ratio of the well barrier is 2000. The growth mode of the well layer in all the multi-quantum well barrier layers in the light-emitting layer 15 is a trapezoidal form, and the In composition therein remains unchanged at 0.3.

[0070] Specifically, the first multi-quantum well barrier layer 151 is composed of six first quantum well barrier layers 1511 stacked on top of each other. The thickness of the first quantum well barrier layer 1511 is 4 nm. All the barrier layers in the first multi-quantum well barrier layer 151 are doped with Si at a doping concentration of 5×10 18 cm -3The second multi-quantum well barrier layer 154 is composed of six second quantum well barrier layers 1541 stacked on top of each other, and the thickness of the second quantum well barrier layer 1541 is 4 nm. The third multi-quantum well barrier layer 156 is composed of two third quantum well barrier layers 1561 stacked on top of each other, and the thickness of the third quantum well barrier layer 1561 is 3.5 nm. The barrier layers in the third multi-quantum well barrier layer 156 are all doped with Mg, and the doping concentration is 5.5×10 18 cm -3 .

[0071] Specifically, the thickness of the n-type isolation layer 152 is 12 nm, the growth atmosphere is H2 and N2, the growth temperature is 800°C, the growth pressure is 250 Torr, and the V / III molar ratio of the well barrier is 1000; the thickness of the p-type isolation layer 155 is 12 nm, the growth atmosphere is H2 and N2, the growth temperature is 860°C, the growth pressure is 250 Torr, the V / III molar ratio of the well barrier is 2600, and the Si doping concentration of the n-type isolation layer 152 is 3×10 18 cm -3 The Mg doping concentration of the p-type isolation layer 155 is 3.5×10 18 cm -3 .

[0072] Specifically, the stress compensation layer 153 is composed of six Si3N4 layers and A y3 Ga 1-y3 The N layer is a periodic stack of layers stacked on top of each other, the thickness of Si3N4 is 2nm, A y3 Ga 1-y3 The thickness of the N layer is 2 nm, the thickness ratio is 1:1, the growth temperature is 800°C, the reaction chamber pressure is 150 torr, under H2 atmosphere, the V / III molar ratio is 1100, TMln, TMGa, NH3, TMAl are introduced during growth, and element A is Al.

[0073] S6: depositing an electron blocking layer 16 on the third multi-quantum well barrier layer 156;

[0074] In this embodiment, the electron blocking layer 16 is AlGaN with a thickness of 30-50 nm, a growth temperature of 900-1000° C., and a reaction chamber pressure of 100-200 torr; specifically, the AlGaN thickness is 40 nm, the growth temperature is 950° C., and the reaction chamber pressure is 150 torr.

[0075] S7: depositing a p-type GaN layer 17 on the electron blocking layer 16;

[0076] In this embodiment, the p-type GaN layer 17 has a thickness of 15-30 nm, a growth temperature of 900-1000° C., and a reaction chamber pressure of 200-300 Torr. Specifically, the p-type GaN layer 17 has a thickness of 20 nm, a growth temperature of 950° C., and a reaction chamber pressure of 250 Torr.

[0077] S8 : depositing a p-type contact layer 18 on the p-type GaN layer 17 .

[0078] In this embodiment, the p-type contact layer 18 is a GaN layer heavily doped with Mg, with a thickness of 1-6 nm and a growth temperature of 800-950° C.; specifically, the thickness is 3 nm and the growth temperature is 900° C.

[0079] The light emitting diode epitaxial wafer prepared by the preparation method of this embodiment has the same size and specification as the light emitting diode epitaxial wafer prepared by the control example. The light efficiency is improved by 0.48% compared with the control example through testing by the testing instrument. The specific results are shown in Table 1.

[0080] Example 2

[0081] The difference between this embodiment and the first embodiment is that the total number of stacked groups of the stress compensation layer 153 in this embodiment is 5, the number of first quantum well barrier layers 1511 in the first multi-quantum well barrier layer 151 is 5, and the thickness of each first quantum well barrier layer 1511 is 3 nm, the number of second quantum well barrier layers 1541 in the second multi-quantum well barrier layer 154 is 3, and the thickness of the second quantum well barrier layer 1541 is 2 nm, and the thickness of the third quantum well barrier layer 1561 is 2 nm, and the Si element doping concentration in each barrier layer of the first multi-quantum well barrier layer 151 and the n-type isolation layer 152 is 5×10 17 cm -3 The Mg doping concentration in each barrier layer of the third multi-quantum well barrier layer 156 and the p-type isolation layer 155 is 5×10 17 cm -3 .

[0082] The light emitting diode epitaxial wafer prepared by the preparation method of this embodiment has the same size and specification as the light emitting diode epitaxial wafer prepared by the control example. The light efficiency is improved by 0.15% compared with the control example through testing by the testing instrument. The specific results are shown in Table 1.

[0083] Example 3

[0084] The difference between this embodiment and the first embodiment is that the total number of stacked groups of the stress compensation layer 153 in this embodiment is 7 groups. y3 Ga 1-y3The A element in the N layer is In. The number of first quantum well barrier layers 1511 in the first multi-quantum well barrier layer 151 is 7, and the thickness of each first quantum well barrier layer 1511 is 4.5 nm. The number of second quantum well barrier layers 1541 in the second multi-quantum well barrier layer 154 is 4, and the thickness of the second quantum well barrier layer 1541 is 3.5 nm. The number of third quantum well barrier layers 1561 in the third multi-quantum well barrier layer 156 is 3, and the thickness of the third quantum well barrier layer 1561 is 3 nm. The Si element doping concentration in each barrier layer of the first multi-quantum well barrier layer 151 and the n-type isolation layer 152 is 1×10 18 cm -3 The Mg doping concentration in each barrier layer of the third multi-quantum well barrier layer 156 and the p-type isolation layer 155 is 1×10 18 cm -3 .

[0085] The light emitting diode epitaxial wafer prepared by the preparation method of this embodiment has the same size and specification as the light emitting diode epitaxial wafer prepared by the control example. The light efficiency is improved by 0.41% compared with the control example through testing by the testing instrument. The specific results are shown in Table 1.

[0086] Example 4

[0087] The difference between this embodiment and the first embodiment is that: y3 Ga 1-y3 The A element in the N layer is In, the thickness of each first quantum well barrier layer 1511 is 5 nm, the number of second quantum well barrier layers 1541 in the second multi-quantum well barrier layer 154 is 5, the thickness of the second quantum well barrier layer 1541 is 4.5 nm, the thickness of the third quantum well barrier layer 1561 is 4.5 nm, and the Si element doping concentration in each barrier layer of the first multi-quantum well barrier layer 151 and the n-type isolation layer 152 is 3×10 18 cm -3 The Mg doping concentration in each barrier layer of the third multi-quantum well barrier layer 156 and the p-type isolation layer 155 is 3.5×10 18 cm -3 .

[0088] The light emitting diode epitaxial wafer prepared by the preparation method of this embodiment has the same size and specification as the light emitting diode epitaxial wafer prepared by the control example. The light efficiency is improved by 0.26% compared with the control example through testing by the testing instrument. The specific results are shown in Table 1.

[0089] Example 5

[0090] The difference between this embodiment and the first embodiment is that the total number of stacked groups of the stress compensation layer 153 in this embodiment is 5 groups. y3 Ga 1-y3The A element in the N layer is In. The number of first quantum well barrier layers 1511 in the first multi-quantum well barrier layer 151 is 5. The number of second quantum well barrier layers 1541 in the second multi-quantum well barrier layer 154 is 7, and the thickness of the second quantum well barrier layer 1541 is 5 nm. The number of third quantum well barrier layers 1561 in the third multi-quantum well barrier layer 156 is 3, and the thickness of the third quantum well barrier layer 1561 is 5 nm. The Si element doping concentration in each barrier layer of the first multi-quantum well barrier layer 151 and the n-type isolation layer 152 is 2.5×10 18 cm -3 The Mg doping concentration in each barrier layer of the third multi-quantum well barrier layer 156 and the p-type isolation layer 155 is 4.5×10 18 cm -3 .

[0091] The light emitting diode epitaxial wafer prepared by the preparation method of this embodiment has the same size and specification as the light emitting diode epitaxial wafer prepared by the control example. The light efficiency is improved by 0.36% compared with the control example through testing by the testing instrument. The specific results are shown in Table 1.

[0092] Example 6

[0093] The difference between this embodiment and the first embodiment is that: y3 Ga 1-y3 The A element in the N layer is B. The number of first quantum well barrier layers 1511 in the first multi-quantum well barrier layer 151 is 7, and the thickness of each first quantum well barrier layer 1511 is 5 nm. The number of second quantum well barrier layers 1541 in the second multi-quantum well barrier layer 154 is 8, and the thickness of the second quantum well barrier layer 1541 is 3 nm. The thickness of the third quantum well barrier layer 1561 is 2.5 nm. The Si element doping concentration in each barrier layer of the first multi-quantum well barrier layer 151 and the n-type isolation layer 152 is 7.5×10 18 cm -3 The Mg doping concentration in each barrier layer of the third multi-quantum well barrier layer 156 and the p-type isolation layer 155 is 6.5×10 18 cm -3 .

[0094] The light emitting diode epitaxial wafer prepared by the preparation method of this embodiment has the same size and specification as the light emitting diode epitaxial wafer prepared by the control example. The light efficiency is improved by 0.32% compared with the control example through testing by the testing instrument. The specific results are shown in Table 1.

[0095] Example 7

[0096] The difference between this embodiment and the first embodiment is that the total number of stacked groups of the stress compensation layer 153 in this embodiment is 7 groups. y3 Ga 1-y3The A element in the N layer is B. The number of first quantum well barrier layers 1511 in the first multi-quantum well barrier layer 151 is 5, and the thickness of each first quantum well barrier layer 1511 is 3.5 nm. The number of second quantum well barrier layers 1541 in the second multi-quantum well barrier layer 154 is 9, and the thickness of the second quantum well barrier layer 1541 is 2.5 nm. The number of third quantum well barrier layers 1561 in the third multi-quantum well barrier layer 156 is 3. The Si element doping concentration in each barrier layer of the first multi-quantum well barrier layer 151 and the n-type isolation layer 152 is 8×10 18 cm -3 The Mg doping concentration in each barrier layer of the third multi-quantum well barrier layer 156 and the p-type isolation layer 155 is 8.5×10 18 cm -3 .

[0097] The light emitting diode epitaxial wafer prepared by the preparation method of this embodiment has the same size and specification as the light emitting diode epitaxial wafer prepared by the control example. The light efficiency is improved by 0.37% compared with the control example through testing by the testing instrument. The specific results are shown in Table 1.

[0098] Example 8

[0099] The difference between this embodiment and the first embodiment is that the total number of stacked groups of the stress compensation layer 153 in this embodiment is 7 groups. y3 Ga 1-y3 The A element in the N layer is Zn. The thickness of each first quantum well barrier layer 1511 is 3 nm, the thickness of the second quantum well barrier layer 1541 is 5.5 nm, and the thickness of the third quantum well barrier layer 1561 is 4 nm. The Si element doping concentration in each barrier layer of the first multi-quantum well barrier layer 151 and the n-type isolation layer 152 is 9×10 18 cm -3 The Mg doping concentration in each barrier layer of the third multi-quantum well barrier layer 156 and the p-type isolation layer 155 is 9×10 18 cm -3 .

[0100] The light emitting diode epitaxial wafer prepared by the preparation method of this embodiment has the same size and specification as the light emitting diode epitaxial wafer prepared by the control example. The light efficiency is improved by 0.38% compared with the control example through testing by the testing instrument. The specific results are shown in Table 1.

[0101] Embodiment 9

[0102] The difference between this embodiment and the first embodiment is that the total number of stacked groups of the stress compensation layer 153 in this embodiment is 8 groups. y3 Ga 1-y3The A element in the N layer is Zn. The number of first quantum well barrier layers 1511 in the first multi-quantum well barrier layer 151 is 8, and the thickness of each first quantum well barrier layer 1511 is 5 nm. The number of second quantum well barrier layers 1541 in the second multi-quantum well barrier layer 154 is 10, and the thickness of the second quantum well barrier layer 1541 is 6 nm. The number of third quantum well barrier layers 1561 in the third multi-quantum well barrier layer 156 is 3, and the thickness of the third quantum well barrier layer 1561 is 5 nm. The Si element doping concentration in each barrier layer of the first multi-quantum well barrier layer 151 and the n-type isolation layer 152 is 1×10 19 cm -3 The Mg doping concentration in each barrier layer of the third multi-quantum well barrier layer 156 and the p-type isolation layer 155 is 1×10 19 cm -3 .

[0103] The light emitting diode epitaxial wafer prepared by the preparation method of this embodiment has the same size and specification as the light emitting diode epitaxial wafer prepared by the control example. The light efficiency is improved by 0.25% compared with the control example through testing by the testing instrument. The specific results are shown in Table 1.

[0104] Control Example

[0105] In this comparative example, the light emitting diode epitaxial wafer prepared by the existing preparation technology has a quantum well barrier layer thickness of 130 nm. The light efficiency of the light emitting diode using the epitaxial wafer is 226 lm / W when tested by a test instrument.

[0106] Table 1: Comparison of some parameters of various embodiments and comparative examples and the corresponding improvement in light efficiency

[0107]

[0108]

[0109] As can be seen from Table 1, the present invention effectively improves the light efficiency compared to the control example by providing a stress compensation layer 153 and each multi-quantum well barrier layer on the light-emitting layer 15, and changing the Si element doping concentration in each barrier layer of the first multi-quantum well barrier layer 151 and the n-type isolation layer 152, and the Mg element doping concentration in each barrier layer of the third multi-quantum well barrier layer 156 and the p-type isolation layer 155.

[0110] In summary, the Al composition and In composition in each barrier layer of the first multi-quantum well barrier layer 151 and each barrier layer of the second multi-quantum well barrier layer 154 change linearly, so that the original sudden potential energy gradient at the boundary between the adjacent barrier layer and the well layer in the light-emitting layer 15 is modulated into a potential energy gradient with a linear buffer change, thereby effectively reducing the influence of the excessive sudden change of the potential energy gradient at the well-barrier boundary on the transport of holes to the deep quantum well, and at the same time weakening the piezoelectric polarization effect caused by the lattice mismatch between the well layer and the barrier layer, thereby improving the wave function overlap efficiency; through the design of linear component change, polarization-induced holes are generated in the well layer or barrier layer, and the hole concentration is made equivalent to the background electron concentration of the well layer or barrier layer material, thereby generating a compensation effect, and finally forming a well layer or barrier layer high resistance layer; each barrier layer of the first multi-quantum well barrier layer 151 and the n-type isolation layer 152 are doped with Si elements, which reduces the electron potential The barrier layer 154 is provided with a p-type isolation layer 155, which increases the mobility of the electrons and makes the electron concentration of the first multi-quantum well barrier layer 151 reach a balance, thereby preventing excessive electron overshoot and thus weakening the droop effect. The barrier layers of the third multi-quantum well barrier layer 156 and the p-type isolation layer 155 are doped with Mg elements, which reduces the hole barrier height, increases the mobility of the holes, improves the hole injection efficiency, and improves the recombination efficiency of electrons and holes. At the same time, it also increases the height of the electron barrier and weakens the droop effect caused by electron overshoot. The role of the stress compensation layer 153 is to continuously block and change the extension of the dislocation line from the bottom layer through the Si3N4 layer, so that multiple dislocation lines cross and achieve the effect of annihilation. At the same time, due to the small relative atomic volume of A, the vacant position caused by the dislocation can be inserted or filled, which indirectly weakens the piezoelectric polarization effect. At the same time, the Si3N4 layer and A y3 Ga 1-y3 The N layer is thin and changes periodically, thereby weakening the compressive stress and bringing it into the second multi-quantum well barrier layer 154 to cause a piezoelectric polarization effect, that is, forming a strained superlattice structure, thereby effectively improving the luminous efficiency of the epitaxial wafer.

[0111] Under the premise that no conflict occurs, those skilled in the art may freely combine and superimpose the above-mentioned additional technical features.

[0112] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A light-emitting diode epitaxial wafer, characterized in that: include: A substrate, a low-temperature GaN buffer layer, an undoped high-temperature GaN buffer layer, an n-type GaN layer, a light-emitting layer, an electron blocking layer, a p-type GaN layer, and a p-type contact layer are stacked in sequence; The light-emitting layer is composed of a first multi-quantum well barrier layer, an n-type isolation layer, a stress compensation layer, a second multi-quantum well barrier layer, a p-type isolation layer, and a third multi-quantum well barrier layer stacked in sequence; The content of the In component in each barrier layer of the first multi-quantum well barrier layer changes linearly from large to small along the epitaxial growth direction, and the content of the In component in each barrier layer of the second multi-quantum well barrier layer changes linearly from small to large along the epitaxial growth direction; The content of the Al component in each barrier layer of the first multi-quantum well barrier layer changes linearly from small to large along the epitaxial growth direction, and the content of the Al component in each barrier layer of the second multi-quantum well barrier layer changes linearly from large to small along the epitaxial growth direction; The well layers of the first multi-quantum well barrier layer, the second multi-quantum well barrier layer and the third multi-quantum well barrier layer are all grown under an N2 atmosphere, and the barrier layers of the first multi-quantum well barrier layer, the second multi-quantum well barrier layer and the third multi-quantum well barrier layer are all grown under an H2 atmosphere. The well layers in the light-emitting layer are all nitrogen polarity, and the barrier layers are all gallium polarity.

2. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The thickness ratio of a single layer of the first multi-quantum well barrier layer to a single layer of the second multi-quantum well barrier layer is 1:

1.

3. The light emitting diode epitaxial wafer according to claim 1, characterized in that: Each barrier layer of the first multi-quantum well layer is doped with Si element, with a doping concentration of 5×10 17 cm -3 ~1×10 19 cm -3 The n-type isolation layer is doped with Si element, and the doping concentration is 5×10 17 cm -3 ~1×10 19 cm -3 .

4. The light emitting diode epitaxial wafer according to claim 1, characterized in that: Each barrier layer of the third multi-quantum well layer is doped with Mg element, with a doping concentration of 5×10 17 cm -3 ~1×10 19 cm -3 The p-type isolation layer is doped with Mg element, and the doping concentration is 5×10 17 cm -3 ~1×10 19 cm -3 .

5. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The first multi-quantum well barrier layer is composed of 5 to 8 first quantum well barrier layers stacked on each other. The first quantum well barrier layer includes first In y1 Ga 1-y1 N-well layer and the first AlIn y2 GaN barrier layer, the thickness of the first quantum well barrier layer is between 3nm and 5nm; the second multi-quantum well barrier layer is composed of 3 to 10 second quantum well barrier layers stacked on each other, and the second quantum well barrier layer includes a second In y1 Ga 1-y1 N-well layer and the second AlIn y2 GaN barrier layer, the thickness of the second quantum well barrier layer is between 2nm and 6nm, the third multi-quantum well barrier layer is composed of 2 to 3 third quantum well barrier layers stacked on each other, and the third quantum well barrier layer includes a third In y1 Ga 1-y1 N well layer and the third AlIn y2 GaN barrier layer, the thickness of the third quantum well barrier layer is between 2nm and 5nm, wherein 0.1<y1<0.5, 0<y2<0.

15.

6. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The stress compensation layer is composed of 5 to 8 Si3N4 layers and A y3 Ga 1-y3 N layer is a periodic stacking group stacked on each other, or composed of 5 to 8 AlN layers stacked in sequence with A y3 Ga 1-y3 N layers are stacked in a periodic manner, wherein the A y3 Ga 1-y3 The element A in the N layer is at least one of In, Al, B, and Zn, and 0.01≤y3≤0.

1.

7. The light emitting diode epitaxial wafer according to claim 6, characterized in that: The thickness of the Si3N4 layer or the AlN layer is 1nm to 3nm. y3 Ga 1-y3 The thickness of the N layer is 1nm to 3nm, and the Si3N4 layer or the AlN layer is y3 Ga 1-y3 The ratio of the thickness of the N layer is 1:

1.

8. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The thickness of the n-type isolation layer is between 10 nm and 17 nm, the thickness of the p-type isolation layer is between 10 nm and 17 nm, and both the n-type isolation layer and the p-type isolation layer are GaN layers.

9. A method for preparing a light-emitting diode epitaxial wafer, characterized in that: The method is used to prepare the light-emitting diode epitaxial wafer according to any one of claims 1 to 8, and the preparation method comprises: providing a substrate; growing a low-temperature GaN buffer layer on the substrate; growing an undoped high-temperature GaN buffer layer on the low-temperature GaN buffer layer; growing an n-type GaN layer on the undoped high-temperature GaN buffer layer; Growing a light-emitting layer on the n-type GaN layer, the light-emitting layer being composed of a first multi-quantum well barrier layer, an n-type isolation layer, a stress compensation layer, a second multi-quantum well barrier layer, a p-type isolation layer, and a third multi-quantum well barrier layer stacked in sequence; depositing an electron blocking layer on the third multi-quantum well barrier layer; depositing a p-type GaN layer on the electron blocking layer; A p-type contact layer is deposited on the p-type GaN layer.

Images