An adaptive timing circuit within a chip

Abstract

The application discloses an adaptive timing circuit in a chip and relates to the field of integrated circuit design.The adaptive timing circuit in the chip comprises a first charging module, a second charging module and a charging switch module.The first charging module is used for charging an off-chip capacitor; the second charging module is used for charging an on-chip capacitor; and the charging switch module is used for charging the off-chip capacitor and the on-chip capacitor when the switch is opened.The adaptive timing circuit further comprises a comparison and judgment module which is used for comparing the voltage of the off-chip capacitor with the voltage of the on-chip capacitor and outputting the smaller voltage to a shaping and timing module.Compared with the prior art, the adaptive timing circuit has the beneficial effects that: the adaptive timing circuit adopts an internal integrated fixed timer, automatically detects whether there is an external capacitor, and adopts the timing time of the external capacitor matched with the internal constant current source as the standard if there is the external capacitor; if there is no external capacitor, the adaptive timing circuit defaults to adopt the internal integrated fixed timer; the internal and external timers can be automatically switched smoothly, the cost is low, and the timing effect is good.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, and particularly relates to an adaptive timing circuit in a chip. BACKGROUND

[0002] A conventional chip-level timing circuit usually generates a more accurate clock by using an external crystal oscillator or an internal RC oscillator, and generates different reference frequencies by using a programmable frequency divider.

[0003] However, for many analog chips, the method of generating a programmable clock (timer) is costly and needs to be improved. SUMMARY

[0004] The present application aims to provide an adaptive timing circuit in a chip to solve the problems in the background art.

[0005] To achieve the above object, the present application provides the following technical scheme.

[0006] An adaptive timing circuit in a chip comprises:

[0007] A first charging module for charging an off-chip capacitor;

[0008] A second charging module for charging an on-chip capacitor;

[0009] A charging switch module for switching the first charging module and the second charging module to charge the off-chip capacitor and the on-chip capacitor when the switch is open;

[0010] A comparison and judgment module for comparing the voltages of the off-chip capacitor and the on-chip capacitor and outputting the smaller voltage to a shaping and timing module;

[0011] The shaping and timing module for ending the timing when the input voltage reaches a threshold voltage and providing a control signal to a reset module;

[0012] The reset module for controlling the charging switch module to open when starting and controlling the charging switch module to close after receiving the control signal;

[0013] The reset module is connected to the charging switch module, the charging switch module is connected to the first charging module and the second charging module, the first charging module is connected to the comparison and judgment module, the second charging module is connected to the comparison and judgment module, the comparison and judgment module is connected to the shaping and timing module, and the shaping and timing module is connected to the reset module.

[0014] As a further scheme of the present application, the first charging module comprises a current source I1 and an off-chip capacitor C1, the current source I1 is connected to the charging switch module, the comparison and judgment module, and the off-chip capacitor C1, and the other end of the off-chip capacitor C1 is grounded.

[0015] As a further embodiment of the present invention: the second charging module includes a current source I0 and an on-chip capacitor C0. The current source I0 is connected to the charging switch module, the comparison and judgment module, and the on-chip capacitor C0. The other end of the on-chip capacitor C0 is grounded.

[0016] As a further embodiment of the present invention: the charging switch module includes a switch S1 and a switch S0. One end of the switch S1 is connected to the first charging module and the other end of the switch S1 is grounded. One end of the switch S0 is connected to the second charging module and the other end of the switch S0 is grounded.

[0017] As a further embodiment of the present invention: the comparison and judgment module includes a comparator COMP1 and a selection output unit MUX. The non-inverting terminal of the comparator COMP1 is connected to the second charging module and the first input terminal of the selection output unit MUX. The inverting terminal of the comparator COMP1 is connected to the first charging module and the second input terminal of the selection output unit MUX. The output terminal of the comparator COMP1 is connected to the third input terminal of the selection output unit MUX. The output terminal of the selection output unit MUX is connected to the shaping and timing module.

[0018] As a further embodiment of the present invention: the shaping and timing module includes a comparator COMP2 and a NOR gate U1. The non-inverting input of the comparator COMP2 is connected to the comparison and judgment module, the inverting input of the comparator COMP2 is connected to a 1.2V voltage, the output of the comparator COMP2 is connected to the first input of the NOR gate U1, the second input of the NOR gate U1 is connected to the reset module, and the output of the NOR gate U1 is connected to the reset module.

[0019] As a further embodiment of the present invention: the reset module includes a signal ONE-SHOT, a NOR gate U2, and an inverter U3. The signal ONE-SHOT is connected to the first input terminal of the NOR gate U2, the second input terminal of the NOR gate U2 is connected to the output terminal of the NOR gate U1, the output terminal of the NOR gate U2 is connected to the second input terminal of the NOR gate U1 and the input terminal of the inverter U3, and the inverter U3 outputs a control signal.

[0020] Compared with the prior art, the beneficial effects of the present invention are: the present invention adopts an internally integrated fixed timer and automatically detects whether the timer has an external capacitor. If there is an external capacitor, the timing time is based on the external capacitor and the built-in constant current source. If there is no external capacitor, the internally integrated fixed timer is used by default. The internal and external timers can be automatically and smoothly switched, which is low in cost and has good timing effect. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of an adaptive timing circuit within a chip.

[0022] Figure 2 A diagram illustrating the selection of charging paths for different routes.

[0023] Figure 3 This is a specific example diagram of an adaptive timing circuit within a chip.

[0024] Figure 4 The waveform diagrams for each node are shown below.

[0025] Figure 5 This is a typical circuit diagram for a One-shot module.

[0026] Figure 6 The circuit waveforms are shown for each point. Detailed Implementation

[0027] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0028] Please see Figure 1 An adaptive timing circuit within a chip, comprising:

[0029] The first charging module is used to charge the off-chip capacitors;

[0030] The second charging module is used to charge the on-chip capacitors;

[0031] The charging switch module is used to charge the external and internal capacitors of the first and second charging modules when the switch is opened.

[0032] The comparison and judgment module is used to compare the voltage of the external capacitor and the internal capacitor, and output the smaller voltage to the shaping and timing module.

[0033] The shaping and timing module is used to end the timing when the input voltage reaches the threshold voltage, providing a control signal to the reset module.

[0034] The reset module is used to control the charging switch module to open during startup; and to control the charging switch module to close after receiving a control signal.

[0035] The reset module is connected to the charging switch module, the charging switch module is connected to the first charging module and the second charging module, the first charging module is connected to the comparison and judgment module, the second charging module is connected to the comparison and judgment module, the comparison and judgment module is connected to the shaping and timing module, and the shaping and timing module is connected to the reset module.

[0036] In a specific embodiment: Please refer to Figure 1 and Figure 2The chip internally generates current sources I0 and I1, which act as current mirrors to each other, and I1 = K * I0. Since pF-level capacitors are easy to manufacture inside the IC, the on-chip capacitor C0 uses pF level capacitors, while the off-chip capacitor C1 is typically nF level. I1 is set to > I0, and (I1 / C1) is guaranteed to < (I0 / C0). For example... Figure 2 As shown, before startup, both switches S1 and S2 are closed, and Vc0 and Vc1 are both at 0 potential. At time T1, startup begins, and S1 and S2 open simultaneously, starting the timing. I0 charges the internal C0 while I1 charges the external C1. If the external C1 is not connected, Vc1 increases rapidly. During the timing period, Vc0 is always less than Vc1. Module M0 selects the voltage Vc0 with the slower (smaller) rise rate between Vc0 and Vc1 and outputs it. Module M1 shapes the output Vc0 of M0 and times it until Vc0 reaches the reference voltage Vbg set in the chip, at which point the timing ends. By resetting module M2, S0 and S1 are closed again, and Vc0 and Vc1 are simultaneously cleared to zero, ending the timing period.

[0037] In this embodiment: Please refer to Figure 3 The first charging module includes a current source I1 and an external capacitor C1. The current source I1 is connected to the charging switch module, the comparison and judgment module, and the external capacitor C1. The other end of the external capacitor C1 is grounded.

[0038] After the external capacitor C1 is charged, the voltage Vc1 on capacitor C1 continues to increase until it reaches the upper limit of the capacitance of capacitor C1 (this situation will not occur during actual use).

[0039] In this embodiment: Please refer to Figure 3 The second charging module includes a current source I0 and an on-chip capacitor C0. The current source I0 is connected to the charging switch module, the comparison and judgment module, and the on-chip capacitor C0. The other end of the on-chip capacitor C0 is grounded.

[0040] Similarly, when capacitor C0 is charged, its voltage Vc0 increases.

[0041] In this embodiment: Please refer to Figure 3 The charging switch module includes switch S1 and switch S0. One end of switch S1 is connected to the first charging module and the other end of switch S1 is grounded. One end of switch S0 is connected to the second charging module and the other end of switch S0 is grounded.

[0042] When switches S1 and S0 are closed, current sources I1 and I0 are grounded through switches S1 and S0 respectively, and do not charge capacitors C1 and C0.

[0043] In this embodiment: Please refer to Figure 3 and Figure 4The comparison and judgment module includes a comparator COMP1 and a selector output MUX. The non-inverting input of the comparator COMP1 is connected to the first input of the second charging module and the selector output MUX. The inverting input of the comparator COMP1 is connected to the second input of the first charging module and the selector output MUX. The output of the comparator COMP1 is connected to the third input of the selector output MUX. The output of the selector output MUX is connected to the shaping and timing module.

[0044] For a specific example, the chip internally generates current sources I0 and I1, which act as current mirrors to each other. I0 = 1uA, I1 = 100uA, C0 = 10pF, and C1 = 10nF. Therefore, (I1 / C1) << (I0 / C0). With switches S0 and S1 closed, the charge on capacitors C0 and C1 is cleared. The timing circuit uses a high-level pulse from the Set signal of the One-shot transducer as the start signal. At time T1, the circuit begins to start, with Tp flipping from low to high. Simultaneously, switches S0 and S1 open, and Vc0 and Vc1 rise from 0 potential. Comp1 compares the voltages of Vc0 and Vc1, and through the combination of comparator Comp1 and the output selector MUX, automatically selects the lower voltage Vt from Vc0 and Vc1 and sends it to the positive terminal of comparator Comp2.

[0045] In this embodiment: Please refer to Figure 3 and Figure 4 The shaping and timing module includes comparator COMP2 and NOR gate U1. The non-inverting input of comparator COMP2 is connected to the comparison and judgment module, the inverting input of comparator COMP2 is connected to a 1.2V voltage, the output of comparator COMP2 is connected to the first input of NOR gate U1, the second input of NOR gate U1 is connected to the reset module, and the output of NOR gate U1 is connected to the reset module.

[0046] In this example, Vc0 is set to a small value, and the negative terminal of comparator Comp2 is a fixed reference voltage of 1.2V. When Vc0 reaches 1.2V, the output of comparator COMP2 changes from low level to high level, causing the output state of the reset module to change.

[0047] In this embodiment: Please refer to Figure 3 and Figure 4 The reset module includes a signal ONE-SHOT, a NOR gate U2, and an inverter U3. The signal ONE-SHOT is connected to the first input terminal of the NOR gate U2, the second input terminal of the NOR gate U2 is connected to the output terminal of the NOR gate U1, the output terminal of the NOR gate U2 is connected to the second input terminal of the NOR gate U1 and the input terminal of the inverter U3, and the inverter U3 outputs a control signal.

[0048] The change in the output of comparator COMP2 causes the final output Tp to change from high to low, closing switches S1 and S0. This rapidly discharges the voltage across capacitors C0 and C1, ending the timing cycle T0 and resetting the system. The system then waits for the next high-level pulse from the Set signal to trigger, after which the T0 cycle repeats.

[0049] Please see Figure 5 and Figure 6 The One-shot module is a typical monostable multivibrator circuit, and a typical circuit diagram is shown below. Figure 5 As shown; the output waveforms at each point are as follows Figure 6 As shown; Figure 4 The required pulse signal, the high-level pulse width of the set signal, can be controlled by a monostable multivibrator circuit (One-shot module).

[0050] The working principle of this invention is as follows: the first charging module charges the external capacitor; the second charging module charges the internal capacitor; when the charging switch module is open, the first and second charging modules charge the external and internal capacitors respectively; the comparison and judgment module compares the voltage of the external and internal capacitors and outputs the smaller voltage to the shaping and timing module; when the input voltage of the shaping and timing module reaches the threshold voltage, the timing ends and a control signal is provided to the reset module; when the reset module starts, it controls the charging switch module to open; after receiving the control signal, it controls the charging switch module to close.

[0051] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0052] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An adaptive timing circuit in a chip, characterized in that: the adaptive timing circuit in the chip comprises: a first charging module for charging an off-chip capacitor; a second charging module for charging an on-chip capacitor; a charging switch module for switching open when the first charging module and the second charging module charge the off-chip capacitor and the on-chip capacitor; a comparison and judgment module for comparing the voltage of the off-chip capacitor and the on-chip capacitor, and outputting the smaller voltage to a shaping and timing module; the shaping and timing module for ending timing when the input voltage reaches a threshold voltage, and providing a control signal for a reset module; the reset module for controlling the charging switch module to switch open when starting, and controlling the charging switch module to switch close after receiving the control signal; the reset module is connected to the charging switch module, the charging switch module is connected to the first charging module and the second charging module, the first charging module is connected to the comparison and judgment module, the second charging module is connected to the comparison and judgment module, the comparison and judgment module is connected to the shaping and timing module, and the shaping and timing module is connected to the reset module; the charging switch module comprises a switch S1 and a switch S0, one end of the switch S1 is connected to the first charging module, the other end of the switch S1 is grounded, one end of the switch S0 is connected to the second charging module, and the other end of the switch S0 is grounded.

2. The adaptive timing circuit within a chip of claim 1, wherein, The first charging module comprises a current source I1 and an off-chip capacitor C1, the current source I1 is connected to the charging switch module, the comparison and judgment module, and the off-chip capacitor C1, and the other end of the off-chip capacitor C1 is grounded.

3. The adaptive timing circuit within a chip of claim 1, wherein, The second charging module comprises a current source I0 and an on-chip capacitor C0, the current source I0 is connected to the charging switch module, the comparison and judgment module, and the on-chip capacitor C0, and the other end of the on-chip capacitor C0 is grounded.

4. The adaptive timing circuit within a chip of claim 1, wherein, The comparison and judgment module comprises a comparator COMP1 and a selection output device MUX, the non-inverting terminal of the comparator COMP1 is connected to the second charging module and the first input terminal of the selection output device MUX, the inverting terminal of the comparator COMP1 is connected to the first charging module and the second input terminal of the selection output device MUX, the output terminal of the comparator COMP1 is connected to the third input terminal of the selection output device MUX, and the output terminal of the selection output device MUX is connected to the shaping and timing module.

5. The adaptive timing circuit within a chip of claim 1, wherein, The shaping and timing module comprises a comparator COMP2 and an or gate U1, the non-inverting terminal of the comparator COMP2 is connected to the comparison and judgment module, the inverting terminal of the comparator COMP2 is connected to a 1.2V voltage, the output terminal of the comparator COMP2 is connected to the first input terminal of the or gate U1, the second input terminal of the or gate U1 is connected to the reset module, and the output terminal of the or gate U1 is connected to the reset module.

6. The adaptive timing circuit within a chip of claim 5, wherein, The reset module comprises a signal device ONE-SHOT, an or gate U2, and an inverter U3, the first input terminal of the or gate U2 is connected to the signal device ONE-SHOT, the second input terminal of the or gate U2 is connected to the output terminal of the or gate U1, the output terminal of the or gate U2 is connected to the second input terminal of the or gate U1 and the input terminal of the inverter U3, and the inverter U3 outputs the control signal.

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