Method for manufacturing a device having a cavity

Abstract

A method for manufacturing a device having a cavity includes obtaining a device wafer including a first substrate and a device structure formed on the first substrate; depositing a first dielectric layer on the device wafer; etching the first dielectric layer to expose at least a portion of the device structure and a portion of the first substrate; after the etching, depositing a second dielectric layer on the device wafer and the first dielectric layer; performing a surface treatment on a surface of the second dielectric layer; obtaining a second substrate; and bonding the second substrate to the second dielectric layer of the device wafer, thereby forming a cavity between the second substrate and the device wafer.

Description

Technical Field

[0001] This disclosure relates to the field of electronic devices, and more specifically, to a method for manufacturing a device having a cavity. Background Technology

[0002] Devices such as film bulk acoustic resonators (FBAR) or filters, microelectromechanical system (MEMS) microphones, pressure sensors, accelerometers, and piezoelectric micromachined ultrasonic transducers (PMUTs) may include cavity structures for proper operation. In related technologies, the ability to fabricate such devices with improved reliability is highly anticipated. Summary of the Invention

[0003] According to one aspect of this disclosure, a method for manufacturing a device having a cavity is provided. The method includes: obtaining a device wafer including a first substrate and a device structure formed on the first substrate; depositing a first dielectric layer on the device wafer; etching the first dielectric layer to expose at least a portion of the device structure and a portion of the first substrate; after etching, depositing a second dielectric layer on the device wafer and the first dielectric layer; performing a surface treatment on a surface of the second dielectric layer; obtaining a second substrate; and bonding the second substrate to the second dielectric layer located on the device wafer, thereby forming a cavity between the second substrate and the device wafer. Attached Figure Description

[0004] The disclosed embodiments are illustrated in conjunction with the accompanying drawings, which are incorporated in and form part of this application, and the drawings, together with the following description, serve to explain the disclosed embodiments.

[0005] Figure 1 This is a cross-sectional view of a device with a cavity provided in an embodiment of this disclosure;

[0006] Figure 2A-2I This is a cross-sectional view of a structure formed in the process of manufacturing an apparatus having a cavity, as a comparative example of an embodiment of this disclosure;

[0007] Figure 3 This is a manufacturing method provided by the embodiments of this disclosure. Figure 1 Flowchart of the process of the intermediate unit;

[0008] Figure 4A-4J The embodiments provided in this disclosure are in Figure 3 A cross-sectional view of the structure formed during the process;

[0009] Figure 5 This is a cross-sectional view of a device having a cavity according to another embodiment of this disclosure;

[0010] Figure 6 This is a manufacturing method provided by the embodiments of this disclosure. Figure 5 A flowchart of the process of the device;

[0011] Figures 7A-7D The embodiments provided in this disclosure are in Figure 6 A cross-sectional view of the structure formed during the process. Detailed Implementation

[0012] The following text, in conjunction with the specific embodiments illustrated in the accompanying drawings, provides a detailed description of this disclosure. However, these embodiments do not limit this disclosure. The scope of protection of this disclosure covers changes to the structure, method, or function made by those skilled in the art based on these embodiments.

[0013] To facilitate the illustration of the accompanying drawings, the dimensions of certain structures or parts may be enlarged relative to other structures or parts. Therefore, the drawings in this disclosure are only for illustrating the basic structure of the subject matter. Unless otherwise indicated, the same numerals in different drawings represent the same or similar elements.

[0014] Furthermore, terms indicating relative spatial positions in the text, such as “top,” “bottom,” “above,” “below,” “over,” “under,” etc., are used for explanatory purposes to describe the relationship between an element or feature depicted in the drawings and another element or feature therein. Terms indicating relative spatial positions can refer to a position different from that depicted in the drawings when the device is used or operated. For example, if the device shown in the figure is flipped, a unit described as being “below” or “under” another element or feature will be “above” that element or feature. Therefore, the descriptive term “below” can include both above and below positions. The device may be oriented in other ways (e.g., rotated 90 degrees or facing another direction), and descriptive terms appearing in the text and relating to space should be interpreted accordingly. When a component or layer is referred to as being “above” or “connected to” another part or layer, it may be directly above or directly connected to the other part or layer, or there may be intermediate elements or layers present.

[0015] Conventional methods for fabricating devices with cavities may include: depositing a dielectric layer on a first substrate (device wafer); planarizing the dielectric layer by chemical mechanical polishing (CMP); removing a portion of the dielectric layer to form the cavity by etching spaces; and bonding the first substrate to a second substrate (cap wafer) via the dielectric layer to form the cavity. The CMP process on the dielectric layer prepares the surface of the dielectric layer to be suitable for bonding to the second substrate. However, the CMP process may cause a portion of the dielectric layer surface near the cavity space to tilt, and the tilted surface may not bond to the second substrate. Therefore, the effective bonding area will be reduced, and the bonding strength may be significantly affected, negatively impacting the reliability of the device.

[0016] This disclosure provides an improved method for manufacturing a device with a cavity, which avoids the formation of tilted surfaces through a CMP process, thereby effectively improving the bonding strength between a first substrate and a second substrate. According to one embodiment of this disclosure, the manufacturing method includes: depositing a first dielectric layer on a first substrate on which a device structure is formed; planarizing the first dielectric layer by CMP; removing a portion of the first dielectric layer by etching to form a cavity space; depositing a thin second dielectric layer to cover the surface of the first dielectric layer and the surface of the device structure; using a microphysical etching process to remove a portion of the second dielectric layer, thereby activating the surface of the second dielectric layer; and then bonding the second substrate to the second dielectric layer. The manufacturing method according to this disclosure avoids the problem of "tilted surfaces," ensuring the adhesion and bonding of the second dielectric layer without reducing the bonding area and bonding strength of the second substrate.

[0017] Some devices may require larger cavities or trap-rich layers to help improve device performance. Therefore, in some embodiments of this disclosure, trap-rich layers are added, or grooves are formed in a second substrate to increase the volume of the cavity.

[0018] Figure 1 This is a cross-sectional view of a device 1000 having a cavity 500 according to an embodiment of the present disclosure.

[0019] like Figure 1 As shown, the device 1000 includes: a device wafer 100, a first dielectric layer 110, a second dielectric layer 120, a second substrate 200 (also called a "cap wafer"), a trap-rich layer 210, and a buffer layer 220. The device wafer 100 includes: a first substrate 101 and a device structure 300 disposed on the first substrate 101.

[0020] Device structure 300 may include at least a portion of a semiconductor device or a microelectromechanical system (MEMS) device. For example, device structure 300 may include at least a portion of at least one of a filmbulk acoustic resonator (FBAR) resonator or filter, a MEMS microphone, a pressure sensor, an accelerometer, and a piezoelectric micromachined ultrasonic transducer (PMUT), or other devices having a cavity structure.

[0021] A first dielectric layer 110 is disposed on a first substrate 101 located at both ends of the device structure 300. The first dielectric layer 110 is separated from both ends of the device structure 300 by a predetermined distance. The first dielectric layer 110 forms the sidewall of the cavity 500.

[0022] The second dielectric layer 120 covers the top and side surfaces of the first dielectric layer 110, the top and side surfaces of the device structure 300, and a portion of the top surface of the first substrate 101 between the device structure 300 and the first dielectric layer 110.

[0023] A trap-rich layer 210 is disposed below the second substrate 200. A buffer layer 220 is disposed below the trap-rich layer 210. The second substrate 200 is bonded to a second dielectric layer 120 disposed on the device wafer 100 through the buffer layer 220 to form a cavity 500.

[0024] Figure 2A-2I This is a comparative example of a structure formed in the process of manufacturing an apparatus having a cavity, according to an embodiment of the present disclosure.

[0025] like Figure 2A As shown, in step S0, a device wafer 100 is obtained. The device wafer 100 includes a first substrate 101 and a device structure 300 formed on the first substrate 101. The device structure 300 may include at least a portion of a device prepared to fabricate a cavity. For example, the device may be a semiconductor device or a microelectromechanical system (MEMS) device, which may include at least one of a thin-film bulk acoustic resonator or filter, a MEMS microphone, a pressure sensor, an accelerometer, and a piezoelectric micromachined ultrasonic transducer or other device having a cavity structure.

[0026] like Figure 2B As shown, in step S1, a first dielectric layer 110 is deposited on the device wafer 100. The first dielectric layer 110 may be formed by silicon, silicon oxide, silicon nitride, aluminum nitride, silicon oxynitride or other materials, or a combination of two or more of the above materials.

[0027] like Figure 2C As shown, in step S2, the top surface of the first dielectric layer 110 is planarized using, for example, a chemical mechanical polishing (CMP) process. Therefore, the top surface of the first dielectric layer 110 is parallel to the top surface of the first substrate 101. Figure 2D As shown, in step S3, a photolithography process is performed.

[0028] Specifically, firstly, in Figure 2C A photoresist layer 400 is coated on the structure. The photoresist layer 400 is exposed to light using a mask (not shown) with a specific pattern, and the exposed photoresist layer is developed using a solvent, thereby transferring the mask pattern to the photoresist layer 400. The photoresist layer 400 exposes a portion of the first dielectric layer 110 that needs to be removed. Figure 2E As shown, in step S4, the first dielectric layer 110 is etched by using the photoresist layer 400 as an etching mask to expose at least a portion of the device structure 300 and a portion of the first substrate 101, thereby forming a space for forming the cavity 500 (hereinafter referred to as "cavity space 500").

[0029] like Figure 2F As shown, in step S5, the photoresist layer 400 is removed, and the remaining structure is cleared. At this point, the surface of the first dielectric layer 110 has undergone a series of processes such as photolithography, etching, and removal, thus changing the surface properties of the first dielectric layer 110. For example, the surface of the first dielectric layer 110 may no longer have abundant unsaturated bonds, or the surface of the first dielectric layer 110 may have been "contaminated" by organic molecules during the series of processes. Therefore, the surface of the first dielectric layer 110 no longer has the same bonding activity as when it was just completed with CMP. If the first dielectric layer 110 with such a surface is directly bonded to the second substrate 200, the first dielectric layer 110 may not bond effectively to the second substrate 200, or at least the bond strength may be weak.

[0030] To solve the above problems, such as Figure 2G As shown, in step S6, a slight CMP process is performed on the surface of the first dielectric layer 110 to remove unsuitable bonding portions from the surface layer of the first dielectric layer 110, thereby restoring the bonding activity of the surface of the first dielectric layer 110. At this time, due to the presence of the cavity space 500, the CMP process may cause a portion of the surface of the first dielectric layer 110 near the cavity 500 to tilt, forming a tilted surface 110a. Figure 2H and Figure 2I As shown, in step S7, the second substrate 200 is bonded to the device wafer 100 via the first dielectric layer 110.

[0031] At this point, the tilted surface 110a may not be bonded to the second substrate 200, thereby reducing the effective bonding area, weakening the bonding strength, and causing device reliability issues. Figure 3 Manufacturing according to embodiments of this disclosure Figure 1 The flowchart of process 1100 of device 1000.

[0032] Figure 4A-4J This is a cross-sectional view of the structure formed in process 1100 according to an embodiment of this disclosure.

[0033] like Figure 4A As shown, in step S100, a device wafer 100 is obtained. The device wafer 100 includes a first substrate 101 and a device structure 300 formed on the first substrate 101. The device structure 300 may include at least a portion of a device prepared to fabricate a cavity. For example, the device may be a semiconductor device or a microelectromechanical system (MEMS) device, which may include at least one of a film bulk acoustic resonator (FBAR) resonator or filter, a MEMS microphone, a pressure sensor, an accelerometer, and a piezoelectric micromachined ultrasonic transducer (PMUT) or other device having a cavity structure.

[0034] like Figure 4B As shown, in step S101, a first dielectric layer 110 is deposited on the device wafer 100. The first dielectric layer 110 may be formed by silicon, silicon oxide, silicon nitride, aluminum nitride, silicon oxynitride or other materials, or a combination of two or more of the above materials.

[0035] like Figure 4C As shown, in step S2, the top surface of the first dielectric layer 110 is planarized using, for example, a chemical mechanical polishing (CMP) process. Therefore, the top surface of the first dielectric layer 110 is parallel to the top surface of the first substrate 101. Figure 4D As shown, in step S103, a photolithography process is performed, and the first dielectric layer 110 is etched to expose at least a portion of the device structure 300 and a portion of the first substrate 101, thereby forming a space for forming the cavity 500 (hereinafter referred to as "cavity space 500").

[0036] Step S103 is similar to steps S3, S4, and S5 described above, therefore a detailed explanation of step S103 will not be repeated. Figure 4E As shown, in step S104, in Figure 4D A second dielectric layer 120 is deposited on the structure.

[0037] The second dielectric layer 120 covers the top and side surfaces of the first dielectric layer 110, as well as the top and side surfaces of the device structure 300. The second dielectric layer 120 is a thin layer with a thickness between about 10 nm and about 100 nm. The second dielectric layer 120 may be formed from silicon, silicon oxide, silicon nitride, aluminum nitride, silicon oxynitride, or other materials, or a combination of two or more of the above materials. The second dielectric layer 120 serves as a protective layer on the surface of the device structure 300 to prevent damage to the surface of the device structure 300 in subsequent processes. The material of the second dielectric layer 120 may be the same as the material of the surface layer of the first dielectric layer 110. In embodiments of this disclosure, the surface of the first dielectric layer 110 is not subjected to CMP processing. Therefore, the surface of the first dielectric layer 110 will not be damaged by CMP processes to form a tilted surface, for example... Figure 2G The inclined surface 110a is shown. Therefore, the entire top surface of the first dielectric layer 110 is parallel to the surface of the first substrate 101, and the entire surface of the second dielectric layer 120 covering the surface of the first dielectric layer 110 is also parallel to the surface of the first substrate 101. Figure 4F As shown, in step S105, a surface treatment process is performed on the surface of the second dielectric layer 120 to activate the surface of the second dielectric layer 120 for bonding.

[0038] The surface treatment process can be a microphysical etching process, which may include at least one of air plasma etching, ion beam etching (IBE), fast atom beam (FAB) etching, or any other physical impact process. The surface treatment process removes a portion of the surface of the second dielectric layer 120, such that at least a portion of the molecular bonds of the material on the surface of the second dielectric layer 120 are broken to facilitate subsequent bonding processes. At this time, the surface of the second dielectric layer 120 has not been treated by a CMP process, therefore the portion of the surface of the second dielectric layer 120 near the boundary of the cavity space 500 will not be tilted. Therefore, the entire top surface of the second dielectric layer 120 is parallel to the surface of the first substrate 101. Therefore, during subsequent bonding processes to bond the second substrate 200, the entire top surface of the second dielectric layer 120 can be effectively bonded to the second substrate 200. Figures 2A to 2I Compared to the process described above, this increases the bonding surface area and bonding strength.

[0039] like Figure 4GAs shown, in step S106, a second substrate (cap wafer) 200 is obtained, and a trap-rich layer 210 is formed on the second substrate 200. The second substrate 200 may be formed of monocrystalline silicon. The trap-rich layer 210 may be formed of polycrystalline silicon, amorphous silicon, silicon nitride, aluminum nitride, or gallium nitride, or a combination of two or more of the above materials.

[0040] like Figure 4H As shown, in step S107, a buffer layer 220 is formed on the trap-rich layer 210, and the surface of the buffer layer 220 is polished using, for example, a CMP surface polishing process to form a material surface suitable for bonding. The buffer layer 220 can be formed of silicon oxide or silicon nitride. Figure 4I and Figure 4J As shown, in step S108, the buffer layer 220 on the second substrate 200 and the second dielectric layer 120 on the device wafer 100 are attached and bonded to form a cavity 500.

[0041] Figure 5 This is a cross-sectional view of a device 2000 having a cavity 600 according to an embodiment of the present disclosure. Figure 5 The device 2000 is similar to Figure 1 The device 2000 differs from the device 1000 in that portions of the second substrate 200, the trap-rich layer 210, and the buffer layer 220, which are perpendicularly aligned with the cavity space 500 formed on the device wafer 100, are removed to form a recess 200a. The recess 200a and the cavity space 500 together form a cavity 600. Therefore, the volume of the cavity 600 in the device 2000 is larger than the volume of the cavity 500 in the device 1000. Apart from the cavity 600, the other components of the device 2000 are the same as those of the device 1000, and therefore a detailed description of these components will not be repeated. Figure 6 Manufacturing of embodiments of this disclosure Figure 5 The flowchart of process 2100 of device 2000.

[0042] Except for the additional steps S150 and S151 performed after step S107 and before step S108, process 2100 is similar to Figure 3 Process 1100. Therefore, a detailed description of steps S150 and S151 is provided below, and the detailed descriptions of other steps will not be repeated. Figures 7A-7D This is a cross-sectional view of the structure formed in steps S150, S151 and S108 of process 2100 according to an embodiment of the present disclosure.

[0043] like Figure 7AAs shown, in step S150, after forming a trap-rich layer 210 and a buffer layer 220 on the second substrate 200, a groove 200a is formed on the second substrate 200 by etching the buffer layer 220, the trap-rich layer 210, and the second substrate 200. The position of the groove 200a corresponds vertically to the cavity space 500 formed on the device wafer 100.

[0044] After etching and other processes, the surface of the buffer layer 220 may not be suitable for bonding. Therefore, as Figure 7B As shown, in step S151, a surface treatment process is performed on the surface of the buffer layer 220 to remove a portion of the buffer layer 220, thereby breaking at least a portion of the molecular bonds of the material on the surface of the buffer layer 220 to facilitate subsequent bonding processes. The surface treatment process can be a microphysical etching process, which may include at least one of air plasma etching, ion beam etching (IBE), or fast atom beam (FAB) etching, and any other physical impact process. Figure 7C and Figure 7D As shown, in step S108, the buffer layer 220 located on the second substrate 200 and the second dielectric layer 120 located on the device wafer 100 are bonded together.

[0045] Therefore, the groove 200a formed on the second substrate 200 and the cavity space 500 formed on the device wafer 100 together form the cavity 600.

[0046] Other embodiments of this disclosure will be apparent to those skilled in the art upon consideration of the specification and practice of this invention. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are determined by the appended claims.

Claims

1. A method for manufacturing a device having a cavity, characterized in that, include: An apparatus wafer is obtained, wherein the apparatus wafer includes a first substrate and an apparatus structure formed on the first substrate; A first dielectric layer is deposited on the wafer of the device; The first dielectric layer is etched to expose a portion of the device structure and the first substrate; After etching, a second dielectric layer is deposited on the device wafer and the first dielectric layer; The surface of the second dielectric layer is surface treated; Obtaining a second substrate; and The second substrate is bonded to the second dielectric layer located on the device wafer, thereby forming the cavity between the second substrate and the device wafer.

2. The method according to claim 1, characterized in that, The device having a cavity includes: a semiconductor device or a microelectromechanical system (MEMS) device, and The device structure formed on the first substrate includes at least a portion of the device having a cavity.

3. The method according to claim 2, characterized in that, The semiconductor device or the microelectromechanical system (MEMS) device includes at least one of: a thin-film bulk acoustic resonator or filter, a MEMS microphone, a pressure sensor, an accelerometer, and a piezoelectric micromachining ultrasonic transducer.

4. The method according to claim 1, characterized in that, The first dielectric layer is formed of silicon, silicon oxide, silicon nitride, aluminum nitride, or silicon oxynitride; or, The first dielectric layer is formed by a combination of two or more materials selected from silicon, silicon oxide, silicon nitride, aluminum nitride, and silicon oxynitride.

5. The method according to claim 1, characterized in that, Before etching the first dielectric layer, the process also includes: The top surface of the first dielectric layer is planarized using a chemical mechanical polishing process.

6. The method according to claim 1, characterized in that, The thickness of the second dielectric layer is in the range of 10 nm to 100 nm.

7. The method according to claim 1, characterized in that, The second dielectric layer is formed of silicon, silicon oxide, silicon nitride, aluminum nitride, or silicon oxynitride; or, The second dielectric layer is formed by a combination of two or more materials selected from silicon, silicon oxide, silicon nitride, aluminum nitride, and silicon oxynitride.

8. The method according to claim 1, characterized in that, The surface treatment of the second dielectric layer includes: Microphysical etching is performed on the surface of the second dielectric layer to remove the surface layer of the second dielectric layer.

9. The method according to claim 8, characterized in that, The microphysical etching includes at least one of air plasma etching, ion beam etching, and fast atomic beam etching.

10. The method according to claim 1, characterized in that, The second substrate is formed of single-crystal silicon.

11. The method according to claim 1, characterized in that, Before bonding the second substrate to the second dielectric layer located on the device wafer, the method further includes: A trap-rich layer is formed on the second substrate; and A buffer layer is deposited in the trap-rich layer.

12. The method according to claim 11, characterized in that, The trap-rich layer is formed of silicon, silicon oxide, silicon nitride, aluminum nitride, or silicon oxynitride; or, The trap-rich layer is formed by a combination of two or more materials selected from silicon, silicon oxide, silicon nitride, aluminum nitride, and silicon oxynitride.

13. The method according to claim 11, characterized in that, After depositing the buffer layer and before bonding the second substrate to the second dielectric layer, the method further includes: The buffer layer is surface polished using a chemical mechanical polishing process.

14. The method according to claim 11, characterized in that, The buffer layer is formed of silicon oxide or silicon nitride.

15. The method according to claim 11, characterized in that, After depositing the buffer layer and before bonding the second substrate to the second dielectric layer, the method further includes: A groove is formed on the second substrate by etching the buffer layer, the trap-rich layer, and the second substrate; The surface of the buffer layer is surface treated; wherein, after the second substrate is bonded to the second dielectric layer, the groove is part of the cavity.

16. The method according to claim 15, characterized in that, The surface treatment performed on the buffer layer includes: Microphysical etching is performed on the surface of the buffer layer to remove the surface layer of the buffer layer.

17. The method according to claim 16, characterized in that, The microphysical etching includes at least one of air plasma etching, ion beam etching, and fast atomic beam etching.

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