Digital low-dropout regulator and control method thereof

Abstract

A digital low-dropout regulator and a control method thereof are provided. The digital low-dropout regulator can include a power switch circuit, an error detector, and a control circuit coupled to the power switch circuit and the error detector. The power switch circuit can be configured to receive an input voltage to generate an output voltage, wherein a voltage difference between the input voltage and the output voltage is controlled by a switch control code. The error detector can be configured to generate an error code based on an error between the output voltage and a target voltage. The control circuit can be configured to determine a compensation based on the switch control code and the error code, and update the switch control code based on the compensation to cause the output voltage to approach the target voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to voltage control, and in particular, to a digital low-dropout regulator (DLDO) and a control method thereof. BACKGROUND

[0002] When a central processing unit (CPU) operates in a busy state, a larger amount of current is drawn from a power supply; in contrast, when the CPU operates in an idle state, the amount of current supplied by the power supply is reduced. In order to allow the overall system to operate stably, a loop system is typically provided inside the CPU to dynamically adjust certain circuit configurations in response to the amount of current supplied. In the related art, the amount of adjustment of the circuit configurations is performed based on a fixed compensation gain. However, the setting of the compensation gain needs to be traded off between the stability and the speed of the system. For example, a larger compensation gain is more likely to cause oscillation of the system, and a smaller compensation gain will make the circuit configurations track the change of the current load more slowly.

[0003] Therefore, there is a need for a novel architecture and a related control method to balance the stability and the tracking speed of the system without or with less side effects, and to improve the overall performance. SUMMARY

[0004] One object of the present application is to provide a digital low-dropout regulator (DLDO) and a control method thereof to provide a corresponding compensation gain in response to the operating conditions of various loads, thereby balancing the stability and the tracking speed of the system.

[0005] At least one embodiment of the present application provides a digital low-dropout regulator. The digital low-dropout regulator can include a power switch circuit, an error detector, and a control circuit, wherein the control circuit is coupled to the power switch circuit and the error detector. The power switch circuit can be used to receive an input voltage to generate an output voltage, wherein the voltage difference between the input voltage and the output voltage is controlled by a switch control code. The error detector can be used to generate an error code according to the error between the output voltage and a target voltage. The control circuit can be used to determine a compensation amount according to the switch control code and the error code, and to update the switch control code according to the compensation amount, so that the output voltage approximates the target voltage.

[0006] The control method can include receiving, by a power switch circuit of the digital low-dropout regulator, an input voltage to generate an output voltage, wherein a voltage difference between the input voltage and the output voltage is controlled by a switch control code; generating, by an error detector of the digital low-dropout regulator, an error code according to an error between the output voltage and a target voltage; and determining, by a control circuit of the digital low-dropout regulator, a compensation amount according to the switch control code and the error code, and updating the switch control code according to the compensation amount, so as to make the output voltage approach the target voltage.

[0007] The digital low-dropout regulator and the control method thereof can determine the compensation amount according to the switch control code and the error code. Since the switch control code can be changed with the change of the supply current, the equivalent compensation gain of the present application can be changed according to different supply currents, so as to balance the system stability and the tracking speed. In addition, the embodiments of the present application do not greatly increase the additional cost. Therefore, the present application can balance the system stability and the tracking speed without side effects or with less side effects, so as to improve the overall performance. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A schematic diagram of a digital low-dropout regulator according to an embodiment of the present application.

[0009] Figure 2 Some details of a proportional-integral-derivative controller according to an embodiment of the present application.

[0010] Figure 3 Changes of the output voltage when the load current changes according to an embodiment of the present application.

[0011] Figure 4 Some details of a compensation estimation circuit 200 according to an embodiment of the present application.

[0012] Figure 5 A working flow of a control method of a digital low-dropout regulator according to an embodiment of the present application. DETAILED DESCRIPTION

[0013] Figure 1 A schematic diagram of a digital low-dropout regulator (DLDO) 10 according to an embodiment of the present application, wherein the digital low-dropout regulator 10 can receive an input voltage V IN from the outside and provide an output voltage V OUTA supply voltage is used for one or more sub-circuits in an electronic device, such as a central processing unit. In the present embodiment, the digital low-dropout regulator 10 can include a power switch circuit 110, an error detector 120, and a control circuit such as a proportional-integral-derivative (PID) controller 130 coupled to the power switch circuit 110 and the error detector 120. In the present embodiment, the equivalent circuit of the output load of the digital low-dropout regulator 10 can include inductance L LOAD , capacitance C LOAD , and the like, but the present application is not limited thereto. The power switch circuit 110 can be used to receive an input voltage V IN to generate an output voltage V OUT , where the voltage difference AV between the input voltage V IN and the output voltage V OUT is controlled by a switch control code D CODE (e.g., a 12-bit switch control code D CODE <11:0>). In particular, the power switch circuit 110 can include a plurality of current supply paths in parallel, and the switch control code D CODE is used to control the number of enabled current supply paths among the plurality of current supply paths (e.g., the number of enabled current supply paths among 4096 current supply paths is controlled by a 12-bit switch control code D CODE <11:0>). For ease of understanding, it is assumed that the decimal value of the switch control code D LOAD represents the number of enabled current supply paths among the plurality of current supply paths. In addition, each of the plurality of current supply paths can be considered to be composed of a resistance (e.g., an inherent resistance on the signal path) and a switch. Assuming that the resistance value of each resistance is R and the load current flowing through the power switch circuit 110 is I IN , the equivalent resistance value R OUT coupled between the input voltage V EFF and the output voltage V IN and the voltage difference AV between the input voltage V OUT and the output voltage V OUT may be represented as follows, respectively:

[0014] and

[0015]

[0016] but the present application is not limited thereto.

[0017] The error detector 120 can be used to generate an error code D ERRIn this embodiment, the error detector 120 can include an analog-to-digital converter 121 and an error processing circuit 122. The analog-to-digital converter 121 can be used to convert the output voltage V OUT to an output voltage code D OUT (e.g., the analog output voltage V OUT is converted to the digital output voltage code D OUT ), and the error processing circuit 122 can be used to calculate the difference between the output voltage code D OUT and a target voltage code corresponding to the target voltage (e.g., the target voltage can be converted to a digital value of the target voltage as the target voltage code) as an error code D ERR . In this embodiment, the analog-to-digital converter 121 can be considered as a fast speed sensor (FSS) analog-to-digital converter. For example, when the analog-to-digital converter 121 detects that the output voltage V OUT is dropping (which causes some sub-circuits to operate slower), it can be known that the electronic device (e.g., the central processing unit) is operating in a busy state, and thus the number of enabled current supply paths can need to be increased to supply sufficient current; on the other hand, when the analog-to-digital converter 121 detects that the output voltage V OUT is rising (which causes some sub-circuits to operate faster), it can be known that the electronic device (e.g., the central processing unit) is operating in an idle state, and thus the number of enabled current supply paths can be reduced.

[0018] The PID controller 130 can be used to generate a switch control code D COD based on at least the error code D ERR . In particular, a compensation amount is determined based on the switch control code D CODE and the error code D ERR , and the switch control code is updated based on the compensation amount so that the output voltage V OUT approaches the target voltage. Figure 2 For some details of the PID controller 130 according to an embodiment of the present application, the PID controller 130 can include a proportional part operation unit 131, an integral part operation unit 132, a differential part operation unit 133, adders 134 and 135, inverters 136 and 137, and a compensation estimation circuit 200. In this embodiment, the proportional part operation unit 131, the integral part operation unit 132, and the differential part operation unit 133 can apply a proportional gain K p , an integral gain K i , and a differential gain K d to the error code D ERRfor subsequent processing. In detail, the integral part operation unit 132, the adder 134, and the flip-flop 136 can constitute an integrator with an integral gain K i to perform an integral operation on the error code D ERR . For example, the adder 134 can multiply the error code D ERR by the integral gain K i , add the multiplication result to the output (e.g., a previous accumulated result generated at a previous cycle of an operation clock) of the flip-flop 136 to generate a current accumulated result, and output the current accumulated result at a next cycle of the operation clock. In addition, the adder 135 can add the output of the proportional part operation unit 131, the output of the flip-flop 136, and the output of the differential part operation unit 133 to generate the switch control code D CODE , and output the switch control code D CODE to the power switch circuit 110 through the flip-flop 137. Note that the integral operation functions to eliminate a steady state error, and the integral gain K i is a key to the stability of the overall system. In the case where the integral gain K i is fixed and the compensation estimation circuit 200 is disabled, the design of the integral gain K i needs to trade off between the stability of the system and the tracking speed for the target voltage. In order to take into account both the stability of the system and the tracking speed, the present application can achieve an effect similar to dynamically adjusting the integral gain K LOAD in accordance with the magnitude of the load current I i .

[0019] For the sake of understanding, please refer to Figure 3 . Figure 3 Fig. 2 is a graph showing the change in the output voltage V LOAD in accordance with the change in the load current I OUT according to an embodiment of the present application. Assume that initially the load current I LOAD is I LOAD,0 and the voltage level of the output voltage V OUT is V OUT,0 , at which time D ERR = 0 (indicating that the voltage difference between the output voltage V OUT and the target voltage is smaller than the resolution m of the error detector 120), and the value of the switch control code D CODE is D CODE,0 . When the load current I LOAD suddenly increases by ΔI (I LOAD = I LOAD,0 + ΔI), the switch control code D CODEThe value has not yet been updated (maintained at D). CODE,0 Therefore, the output voltage V OUT The voltage level is determined by V OUT,0 Change to V OUT,0 'as follows:

[0020]

[0021] If the output voltage V OUT Because the load current I LOAD The voltage drop caused by the change is denoted by E, and the load current is I. LOAD The relationship between the change in pressure ΔI and the pressure drop E can be expressed as follows:

[0022]

[0023] Assuming that the switch control code D is used... CODE The value is adjusted to D CODE,1 This can make the output voltage V OUT The voltage level is compensated to V OUT,1 (Make error code D) ERR Returning to 0), output voltage V OUT voltage level V OUT,1 In switch control code D CODE The value is D CODE,1 In this case, it can be represented as follows:

[0024] Assuming input voltage V IN The voltage difference ΔV between the voltage and the target voltage is V. DIFF Then the switch control code D CODE The value D before compensation CODE,0 With the compensated value D CODE,1 The relationship between them can be represented as follows:

[0025]

[0026] As can be seen from the above derivation, the present invention can improve the switching control code D by compensating for the integral operation. CODE Converging to the target value D CODE,1 The speed, where the resolution of the error detector 120 is m, therefore the voltage drop E = m × D ERR Therefore, the switch control code D CODE The compensation amount can be expressed as follows:

[0027] As can be seen from the above, the switch control code D CODE The compensation amount can be based on the switch control code D. CODED CODE,0 , the error code D ERR , and a predetermined coefficient K. Thus, as shown in Fig. 1, the PID controller 130 can transmit the product of the output of the adder 135 (i.e., the switch control code D CODE ), the error code D ERR , and the predetermined coefficient K to the adder 134 for compensation for the integral operation. Figure 2

[0028] Since the compensation amount of the switch control code D CODE is proportional to the current value of the switch control code D CODE (e.g., D CODE,0 ), when the electronic device is operated in a heavy load state, D CODE,0 is large. In this case, if the voltage level of the output voltage V LOAD deviates from the voltage level of the target voltage due to a change in the load current I OUT , the compensation estimation circuit 200 can use a large compensation amount to compensate for the switch control code D CODE to accelerate the convergence speed of the switch control code D CODE . Conversely, when the electronic device is operated in a light load state, D CODE,0 is small. In this case, if the voltage level of the output voltage V LOAD deviates from the voltage level of the target voltage due to a change in the load current I OUT , the compensation estimation circuit 200 can use a small compensation amount to compensate for the switch control code D CODE to avoid oscillation in the convergence process. Thus, the digital low-dropout regulator 10 of the present application can take into account both the system stability and the tracking speed of the switch control code D CODE , thereby improving the overall performance.

[0029] Figure 4 Fig. 2 shows some details of the compensation estimation circuit 200 according to an embodiment of the present application. As shown in Fig. 2, the compensation estimation circuit 200 can include an accumulator 210, wherein the accumulator 210 can control the number of times that the switch control code D ERR is accumulated to obtain D CODE ×D ERR in accordance with the error code D CODE . It should be noted that, in practice, the predetermined coefficient K does not necessarily equal m / V DIFF exactly, especially in order to simplify the hardware for calculating K×D ERR ×D CODE , K can be set to 2 N N, wherein N is a positive integer. For example, N can be selected to be a suitable positive integer such that 2 N N is as close as possible to m / V DIFF .​DIFF Where K is preferably slightly less than m / V DIFF And the switch control code D CODE The target value D can be gradually approached through multiple compensation operations. CODE,1 For example, suppose m is 20 millivolts (mV) and V DIFF If the voltage is 100mV, then K can be set to 1 / 8 (N=3). Since the predetermined coefficient K is 2... N Therefore, in the digital domain, multiplying a value by 2 can be accomplished by shifting each bit of the value to the right by N bits (or removing three consecutive bits starting from the least significant bit). N One-third of the operation. For example... Figure 4 As shown, the compensation estimation circuit 200 may further include a shifter 220 for converting the switch control code D... CODE With error code D ERR The product (i.e., the D output of the accumulator) ERR ×D CODE Shift by N bits to generate the switch control code D CODE The compensation amount K×ERR×D CODE In some embodiments, the shifter 220 may shift the switch control code D according to a predetermined coefficient K. CODE Shift by N bits to generate the switch control code D CODE The product of the predetermined coefficients K×D CODE Then the accumulator 210 can be based on the error code D ERR To control K×D CODE The number of times is accumulated to obtain the switch control code D. CODE The compensation amount K×ERR×D CODE As long as the compensation estimation circuit 200 can output the switch control code D CODE The compensation amount K×ERR×D CODE The operation of the accumulator 210 and shifter 220 can be varied.

[0030] Figure 5 A digital low-dropout regulator according to one embodiment of the present invention (e.g.) Figure 1 The control method and workflow of the digital low-differential voltage regulator 10 shown are illustrated. It should be noted that... Figure 5 The illustrated workflow is for illustrative purposes only and is not intended to limit the scope of the invention. In particular, one or more steps may be performed... Figure 5 The workflow shown may have been added, deleted, or modified. Furthermore, these steps do not necessarily need to be followed exactly as long as they do not affect the overall result. Figure 5 Execute in the order shown.

[0031] In step S510, the digital LDO can receive an input voltage using a power switch circuit to generate an output voltage, wherein a voltage difference between the input voltage and the output voltage is controlled by a switch control code.

[0032] In step S520, the digital LDO can generate an error code using an error detector according to an error between the output voltage and a target voltage.

[0033] In step S530, the digital LDO can determine a compensation amount according to the switch control code and the error code using a control circuit, and update the switch control code according to the compensation amount, so that the output voltage approaches the target voltage.

[0034] In summary, the digital LDO and the control method thereof can determine the compensation amount according to the switch control code and the error code. Since the switch control code can be changed with the change of the supply current, the equivalent compensation gain of the present application can be changed according to different supply currents, so as to balance the system stability and the tracking speed. In addition, the embodiments of the present application do not greatly increase the additional cost. Therefore, the present application can balance the system stability and the tracking speed without side effects or with less side effects, so as to improve the overall performance.

[0035] The above only describes the preferred embodiments of the present application, and any equivalent changes and modifications made within the scope of the patent application of the present application shall be included in the scope of the present application.

[0036]

Symbol Description

[0037] 10: Digital LDO

[0038] 110: Power switch circuit

[0039] 120: Error detector

[0040] 121: Analog-to-digital converter

[0041] 122: Error processing circuit

[0042] 130: PID controller

[0043] V IN : Input voltage

[0044] V OUT : Output voltage

[0045] D OUT : Output voltage code

[0046] D ERR : Error code

[0047] DCODE : switch control code

[0048] I LOAD : load current

[0049] L LOAD : inductance

[0050] C LOAD : capacitance

[0051] 131: proportional part operation unit

[0052] 132: integral part operation unit

[0053] 133: differential part operation unit

[0054] 134, 135: adder

[0055] 136, 137: inverter

[0056] 200: compensation estimation circuit

[0057] 210: accumulator

[0058] 220: shifter

[0059] I LOAD,0 : current value

[0060] ΔI: current change

[0061] V OUT,0 , V OUT,0 ', V OUT,1 : voltage level

[0062] S510-S530: steps

Claims

1. A digital low-dropout regulator, comprising: a power switch circuit configured to receive an input voltage to generate an output voltage, wherein a voltage difference between the input voltage and the output voltage is controlled by a switch control code; an error detector configured to generate an error code based on an error between the output voltage and a target voltage; and a control circuit coupled to the power switch circuit and the error detector, configured to determine a compensation based on the switch control code and the error code, and update the switch control code based on the compensation, such that the output voltage approaches the target voltage, wherein the control circuit comprises a compensation estimation circuit configured to calculate the compensation based on a product of the switch control code, the error code, and a predetermined coefficient.

3. The digital low-dropout regulator of claim 2, wherein the compensation estimation circuit comprises a shifter configured to shift the product of the switch control code and the error code by N bits to generate the compensation.

2. The digital low-dropout regulator of claim 1, wherein the predetermined factor is two N one, and N is a positive integer.

4. The digital low-dropout regulator of claim 1, wherein the power switch circuit comprises a plurality of current supply paths connected in parallel, and the switch control code is configured to control a number of the plurality of current supply paths that are enabled.

5. The digital low-dropout regulator of claim 1, wherein the error detector comprises: an analog-to-digital converter configured to convert the output voltage to an output voltage code; an error processing circuit configured to calculate a difference between the output voltage code and a target voltage code as the error code, wherein the target voltage code corresponds to the target voltage.

6. A control method for a digital low-dropout regulator, comprising: receiving, by a power switch circuit of the digital low-dropout regulator, an input voltage to generate an output voltage, wherein a voltage difference between the input voltage and the output voltage is controlled by a switch control code; generating, by an error detector of the digital low-dropout regulator, an error code based on an error between the output voltage and a target voltage; and determining, by a control circuit of the digital low-dropout regulator, a compensation based on the switch control code and the error code, and updating the switch control code based on the compensation, such that the output voltage approaches the target voltage, wherein determining, by the control circuit of the digital low-dropout regulator, the compensation based on the switch control code and the error code comprises: calculating the compensation based on a product of the switch control code, the error code, and a predetermined coefficient.

8. The control method of claim 7, wherein calculating the compensation based on a product of the switch control code, the error code, and a predetermined coefficient comprises:

7. The control method according to claim 6, wherein the predetermined coefficient is 2 N one, and N is a positive integer. shifting, by a shifter, the product of the switch control code and the error code by N bits to generate the compensation. ​

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