Storage system

Abstract

An embodiment of the present disclosure provides a storage system, including: a plurality of storage chips, each of the storage chips being configured to have parameters for characterizing the process corner of the storage chip therein; a controller configured to obtain the parameters of each of the storage chips and adjust the delay of a read command sent to the storage chip corresponding to the parameters based on the parameters. The embodiments of the present disclosure can improve the data transmission uniformity of the storage system.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a storage system. Background Art

[0002] Semiconductor storage can be classified into non-volatile storage and volatile storage. Dynamic Random Access Memory (DRAM), as volatile storage, has advantages such as high storage density and fast read and write speeds, and is widely used in various electronic systems.

[0003] A DRAM system usually consists of a controller and multiple memory chips. Due to differences in manufacturing processes and the like, the performance of different memory chips also has corresponding differences, which will affect the overall performance of the DRAM system. Summary of the Invention

[0004] The embodiments of the present disclosure provide a storage system, which can at least improve the problem of data signal transmission conflict in the storage system.

[0005] In some embodiments of the present disclosure, on the one hand, a storage system is provided, including: multiple memory chips, each of the memory chips being configured to have parameters for characterizing the process corner of the memory chip therein; a controller configured to obtain the parameters of each of the memory chips and adjust the delay of the read command sent to the memory chip corresponding to the parameters based on the parameters.

[0006] In some embodiments, the parameter is a characterization parameter stored in the memory chip.

[0007] In some embodiments, the memory chip includes: a non-volatile storage module; the memory chip is configured to obtain the characterization parameter and store the characterization parameter in the non-volatile storage module before being packaged with the controller.

[0008] In some embodiments, the non-volatile storage module includes one-time programmable storage units.

[0009] In some embodiments, the parameter is a count value for characterizing the process corner of the memory chip, and the memory chip is configured to perform counting and obtain the count value within a preset time after each power-on startup of the storage system.

[0010] In some embodiments, the storage chip includes: a ring oscillator; a counter connected to the ring oscillator for counting the oscillation period of the ring oscillator within a preset time to obtain a count value; and a controller connected to the ring oscillator and the counter for controlling the ring oscillator to start oscillating and obtaining the count value.

[0011] In some embodiments, the enable signal of the ring oscillator is provided by the controller.

[0012] In some embodiments, the controller includes: a command generation module for providing a reference read command; and a delay module for receiving the reference read command and outputting the read command with a delay compared to the reference read command based on the parameter.

[0013] In some embodiments, the delay module includes: a plurality of inverters connected in series, where the first inverter receives the reference read command and the last inverter outputs the read command; a plurality of switches, each switch being connected in parallel with at least one of the inverters; and the controller is configured to control the number of the switches that are turned on based on the parameter.

[0014] In some embodiments, the number of all the inverters is an even number.

[0015] In some embodiments, the number of the inverters connected in parallel with each switch is an even number.

[0016] In some embodiments, the controller is configured to, after each power-on startup of the storage system, obtain the parameter of each storage chip and adjust the delay of the read command sent to the storage chip corresponding to the parameter until polling to obtain the parameters of all the storage chips and adjusting the delays of the read commands sent to all the storage chips.

[0017] In some embodiments, the storage chip further includes: a scan chain interface configured to obtain the parameter based on a command signal sent by the controller and output the parameter to the controller; and the controller further includes: an acquisition module configured to send the command signal to the scan chain interface and receive the parameter output by the scan chain interface.

[0018] In some embodiments, a plurality of the storage chips are stacked on the surface of the controller in sequence.

[0019] In some embodiments, the storage system further includes: a carrier substrate, where the controller is located on the surface of the carrier substrate, and a plurality of the storage chips are stacked on the surface of the carrier substrate in sequence.

[0020] The technical solutions provided by the embodiments of the present disclosure have the following advantages:

[0021] In the technical solution of the storage system provided by the embodiments of the present disclosure, each storage chip is configured such that the storage chip has parameters for characterizing the process corner of the storage chip, and the controller is configured to obtain the parameters of each storage chip and adjust the delay of the read command sent to the storage chip corresponding to the parameters based on the parameters. In this way, the delay of the read command sent to each storage chip can be compensated differently based on the process corner to make up for the problem of slow data transmission of the storage chip itself caused by the slow process corner and compensate for the problem of fast data transmission of the storage chip itself caused by the fast process corner, so that the data of the storage chips with different process corners are output from the data port at the expected time, improving the neatness of the data, avoiding data transmission conflicts between different storage chips, and improving the storage performance of the storage system. Description of the Drawings

[0022] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the drawings in the figures do not constitute a scale limitation.

[0023] Figure 1 It is a schematic structural diagram of a storage system;

[0024] Figure 2 is Figure 1 a schematic diagram of data transmission in the storage system provided;

[0025] Figure 3 It is a schematic diagram of a functional module of the storage system provided by the embodiments of the present disclosure;

[0026] Figure 4 It is another schematic diagram of a functional module of the storage system provided by the embodiments of the present disclosure;

[0027] Figure 5 It is a schematic diagram of a circuit structure of a delay module in the storage system provided by the embodiments of the present disclosure;

[0028] Figure 6 It shows a timing diagram of read commands and data corresponding to different storage chips in the storage system;

[0029] Figure 7 It is a schematic diagram of a structure of the storage system provided by the embodiments of the present disclosure;

[0030] Figure 8 It is another schematic diagram of a structure of the storage system provided by the embodiments of the present disclosure. Detailed Embodiments

[0031] Figure 1 It is a schematic structural diagram of a storage system, Figure 2 For Figure 1 The provided schematic diagram of data transmission in the storage system. Refer to Figure 1 , the storage system may include: a controller 13; a plurality of storage chips 12 located on the surface of the controller 13 and stacked, and the storage chips 12 may be DRAM chips.

[0032] Due to the process differences among different storage chips 12, the electrical properties exhibited by different storage chips 12 also vary. For example, the threshold voltage or conduction current of transistors in different storage chips 12 is different, resulting in different data transmission delays inside different storage chips 12. This will cause the data signals received by the controller 13 from different storage chips 12 to be uneven (skew), the levels of different data signals to be inconsistent, and data conflicts to exist in the data signals of different storage chips 12, affecting the overall performance of the storage system. Specifically, refer to Figure 2 , Figure 2 Example 1 in Figure 2 is an ideal transmission schematic diagram of data signals corresponding to two storage chips 12, where DQ1 and DQ2 are data signals respectively transmitted from different storage chips 12 to the controller 13.

[0033] Based on this, the embodiments of the present disclosure provide a storage system. After the storage system is powered on and started, the controller obtains the parameters used to characterize the process corner of the storage chip, and adjusts the delay of the read command based on the parameters to improve the data conflict problem of the storage system, improve the alignment neatness of the data signals, and further improve the read and write performance of the storage system.

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will elaborate on each embodiment of the present disclosure in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are proposed to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the present disclosure can still be implemented.

[0035] Figure 3 It is a schematic diagram of a functional module of the storage system provided by the embodiments of the present disclosure. Figure 4Another schematic diagram of the functional modules of the storage system provided by the embodiments of the present disclosure.

[0036] Referring to Figure 3 and Figure 4 The storage system provided by the embodiments of the present disclosure includes: a plurality of storage chips 100, each storage chip 100 is configured to have parameters for characterizing the process corner of the storage chip 100 therein; a controller 200, the controller 200 is configured to obtain the parameters of each storage chip 100 and adjust the delay of the read command sent to the storage chip 100 corresponding to the parameters based on the parameters.

[0037] There is a problem that different storage chips 100 have different chip - inherent delays due to different process corners. The storage chip 100 with a slow process corner has a larger inherent delay, and the storage chip 100 with a fast process corner has a smaller inherent delay. Among them, after the storage chip 100 receives the read command RD, in response to the read command RD, data starts to be read out from the storage unit and output to the data port DQ. Therefore, the delay of the read command RD is related to the moment when the data is read out from the storage unit. By adjusting the different delays of the read command RD, the moment when the data is read out from the storage unit is different, which in turn affects the moment when the data of different storage chips 100 is output from the data port DQ. Specifically, for the same storage chip 100 or multiple storage chips with the same process corner, the longer the delay of the read command RD, the later the data is read out from the storage unit 10. In the embodiments of the present disclosure, different parameters correspond to different process corners. Since the delay of the read command RD is adjustable based on the parameters, the delay of the read command RD can be compensated based on the process corner of the storage chip 100, so as to improve the consistency of the moment when the data of each storage chip 100 is read out from the storage unit and output from the data port DQ.

[0038] Specifically, by adjusting the delay of the read command RD, the corresponding memory chip 100 receives the read command RD at different times, and thus the data starts to be read from the memory cell at different times. If the parameter indicates that the process corner of the memory chip 100 is a slow process corner, the controller 200 controls the delay of the read command RD to be shortened, so that the memory chip 100 receives the read command RD earlier, so that the data of the memory chip 100 with a slow process corner can be output from the data port DQ relatively earlier; if the parameter indicates that the process corner of the memory chip 100 is a fast process corner, the controller 200 controls the delay of the read command RD to be lengthened, so that the memory chip 100 receives the read command RD later, so that the data of the memory chip 100 with a fast process corner can be output from the data port DQ relatively later. In this way, the controller 200 compensates the delay of the read command RD for different memory chips 100 based on the process corner, so that the actual time when the data of each memory chip 100 is transmitted to the data port DQ will meet the expectation, improving the neatness of the data signal, preventing the problem of data transmission conflict of different memory chips 100, and improving the read and write performance of the memory system.

[0039] The memory chip 100 provided by the embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0040] In some embodiments, the memory chip 100 may be a DRAM memory chip, such as a DDR (double data rate) 4 DRAM memory chip or a DDR5 DRAM memory chip. In other embodiments, the memory chip 100 may also be an SRAM (Static Random-Access Memory) memory chip, a NAND memory chip, a NOR memory chip, a FeRAM memory chip or a PcRAM memory chip.

[0041] The design of the memory chip 100 needs to meet conditions such as process corner, voltage and temperature. The combination formed by the process corner, voltage and temperature is called PVT (process, voltage, temperature) condition.

[0042] In some embodiments, if a 5 - corner model is adopted, the process corners of different memory chips 100 can be divided into TT (typical nmos and typical pmos) process corner, FF (fast nmos and fast pmos) process corner, SS (slow nmos and slow pmos) process corner, FS (fast nmos and slow pmos) process corner, and SF (slow nmos and fast pmos) process corner. Among them, Typical means that the drive current is an average value, Fast means that the drive current is its maximum value, and Slow means that the drive current is its minimum value (this drive current is the Ids current). This is an explanation from the measurement perspective. Typical, Fast, and Slow can also be understood as the speed of carrier mobility. Carrier mobility refers to the average drift velocity of carriers under the action of a unit electric field.

[0043] In some embodiments, the parameter can be a characterization parameter stored in the memory chip 100. Since the characterization parameter is pre - stored in the memory chip 100, when the controller 200 needs to adjust the read command of the memory system, it can directly obtain the parameter from the memory chip 100, saving the time required for the memory chip 100 to operate to obtain the parameter.

[0044] Process corner Characterization parameter SS 01 TT 00 FF 10

[0045] Table 1

[0046] The characterization parameter can be a binary value. In some embodiments, if there are three types of process corners, the correspondence between the characterization parameter and the process corner can be as shown in Table 1.

[0047] Process corner Characterization parameter SS 000 TT 001 SF 010 FS 011 FF 100

[0048] Table 2

[0049] In some other embodiments, if there are five types of process corners, the correspondence between the characterization parameter and the process corner can be as shown in Table 2.

[0050] Reference Figure 3 , the memory chip 100 can include a non - volatile memory module 110, which is used to store the characterization parameter. Using the non - volatile memory module 110 to store the characterization parameter, in this way, even if the memory chip 100 is powered on or off, the ability of the memory chip 100 to store the characterization parameter remains unchanged.

[0051] In some embodiments, the non-volatile storage module 110 may include one-time programmable (OTP) storage cells. In other embodiments, the non-volatile storage module 110 may also be a programmable read-only memory (PROM) cell or an electrically erasable programmable read-only memory (EEPROM).

[0052] It can be understood that after the storage chip 100 is designed and fabricated, the process corners of the storage chip 100 can be detected, and the characterization parameters of the detected process corners can be stored in the non-volatile storage module 110 of the storage chip 100. Specifically, before the storage wafer is diced to obtain discrete storage chips 100, the process corners can be detected and the characterization parameters can be stored in the non-volatile storage module 110 of each storage chip 100; alternatively, after the storage wafer is diced to obtain discrete storage chips 100, the process corners can be detected and the characterization parameters can be stored in the non-volatile storage module 110 of each storage chip 100.

[0053] In some embodiments, referring to Figure 3 , the storage chip 100 may further include a scan chain interface 103, which is configured to obtain parameters based on a command signal issued by the controller and output the parameters to the controller. The controller 200 may further include a parameter acquisition module 21, which is configured to issue a command signal to the scan chain interface 103 and receive the parameters output by the scan chain interface 103.

[0054] Specifically, the scan chain interface 103 can serve as a medium for transmitting signals between the controller 200 and the non-volatile storage module 110, and the characterization parameters are transmitted to the inside of the controller 200 via the scan chain interface 103. Among them, the parameter acquisition module 21 issues a command signal to the scan chain interface 103. After receiving the command signal, the scan chain interface 103 obtains the characterization parameters stored in the non-volatile storage module 110, and then the characterization parameters are transmitted to the parameter acquisition module 21 via the scan chain interface 103.

[0055] In some embodiments, the parameter can also be a count value used to characterize the process corner of the memory chip 100, and the memory chip 100 is configured to perform counting and obtain the count value within a preset time after each power-on startup of the memory system. In this way, there is no need to set a non-volatile memory module for storing parameters in the memory chip 100, which is beneficial to saving the area of the memory chip 100; in addition, after the memory system is powered on and starts up, counting is performed and the count value is obtained, and this count value can more accurately reflect the process corner of the memory chip 100 at the current time, which is beneficial to improving the accuracy of the parameter in characterizing the process corner.

[0056] Reference Figure 4 , in some embodiments, the memory chip 100 may include: a ring oscillator 110; a counter 210, the counter 210 is connected to the ring oscillator 110 and is used to count the oscillation period of the ring oscillator 110 within a preset time to obtain a count value.

[0057] Specifically, the enable signal TM of the ring oscillator 110 can be provided by the controller 200. The speed of oscillation of the ring oscillator 110 is related to the process corner of the memory chip 100. If the process corner is a fast process corner, the ring oscillator 110 oscillates faster; if the process corner is a slow process corner, the ring oscillator 110 oscillates slower. The counter 210 counts the oscillation period of the ring oscillator 110 within a preset time, and can thus reflect the speed of oscillation of the ring oscillator 110 through the count value. It can be understood that the preset time can be a range value, but for different memory chips 100 of the same memory system, the preset time should be the same fixed value to ensure that the count value is obtained within a time period of the same duration.

[0058] In some other embodiments, the enable signal TM of the ring oscillator 110 can also be provided internally by the memory chip 100. For example, the power-on startup of the memory chip 100 can be used as the excitation condition for providing the enable signal TM to the ring oscillator 110.

[0059] In some embodiments, the ring oscillator 110 may include: an AND gate 230, one input terminal of the AND gate 230 receives the enable signal TM; a plurality of cascaded inverters 240 connected in series, the input terminal of the first cascaded inverter 240 is connected to the output terminal of the AND gate 230, the output terminal of the last cascaded inverter 240 is connected to the other input terminal of the AND gate 230, and the output terminal of the last cascaded inverter 240 is also connected to the counter 210. Specifically, if the ring oscillator 110 oscillates once, the counter 210 counts once.

[0060] Among them, the number of cascaded inverters 240 can be an odd number.

[0061] In some embodiments, the counter 210 may be an up-counter. It should be noted that the counter 210 may also have a reset terminal for receiving a reset signal, which may be issued by the controller 200, so that the counter 210 is reset before counting, ensuring that the initial values of the counters 210 of different memory chips 100 are the same before counting, and also ensuring that the initial values of the counter 210 of the same memory chip 100 are the same before counting in different test phases.

[0062] In some embodiments, the counter 210 may further include a latch module for latching the count value. In this way, after the memory system is powered on and started, the memory chip 100 can first obtain the count value and save it. After a certain period of time, the controller then calls the count value to obtain the process corner of the memory chip 100, so as to adjust the reference voltage of the memory chip 100. Thus, it is beneficial to improve the test flexibility of the memory system, and all the memory chips 100 can obtain the corresponding count values simultaneously.

[0063] Correspondingly, referring to Figure 4 , the memory chip 100 may further include: a scan chain interface 103, which is configured to obtain a count value based on a command signal issued by the controller 200 and output the count value to the controller 200; the controller 200 further includes: a parameter acquisition module 21, which is configured to issue a command signal to the scan chain interface 103 and receive the count value output by the scan chain interface 103. Specifically, the parameter acquisition module 21 issues a command signal to the scan chain interface 103. After receiving the command signal, the scan chain interface 103 obtains the count value of the counter 210, and then the count value is transmitted to the parameter acquisition module 21 via the scan chain interface 103.

[0064] In some embodiments, the controller 200 may include: a command generation module 201 for providing a reference read command RD0; a delay module 202 for receiving the reference read command RD0 and outputting a read command RD with a delay compared to the reference read command RD0 based on a parameter.

[0065] Specifically, after obtaining the parameters for characterizing the process corner, the controller 200 outputs a read command RD corresponding to the parameters based on the parameters. Among them, if the parameters characterize the process corner as a fast process corner, a read command RD with a longer delay compared to the reference read command RD0 is output to compensate for the delay of the read command RD of the memory chip 100, making up for the problem that the data delay of the memory chip 100 itself is shorter caused by the fast process corner, so that the memory chip 100 with the fast process corner can receive the read command RD later, so that the time when the data of the memory chip 100 is transmitted to the data port DQ meets the expectation; if the parameters characterize the process corner as a slow process corner, a read command RD with a shorter delay compared to the reference read command RD0 is output to compensate for the delay of the read command of the memory chip 100, making up for the problem that the data delay of the memory chip 100 itself is longer caused by the slow process corner, so that the memory chip 100 with the slow process corner can receive the read command RD earlier, so that the time when the data of the memory chip 100 is transmitted to the data port DQ meets the expectation.

[0066] In some embodiments, Figure 5 is a schematic circuit diagram of the delay module 201. Refer to Figure 5 , the delay module 201 may include: a plurality of serially connected inverters 211, the inverter 211 at the first position receives the reference read command RD0, and the output of the inverter 211 at the last position is the read command RD; a plurality of switches K, each switch K is connected in parallel with at least one inverter 211; and the controller 200 is configured to adjust the number of the switches K that are turned on based on the parameters.

[0067] Among them, the more the number of the switches K that are turned on, the shorter the delay of the read command RD compared to the reference read command RD0; the fewer the number of the switches K that are turned on, the longer the delay of the read command RD compared to the reference read command RD0.

[0068] If the parameters characterize the process corner as a fast process corner, the fewer the number of the switches K that are turned on, the longer the delay of the read command RD is extended, so that the time when the data is read out from the memory cell is later. Correspondingly, the time when the data is read out from the memory cell and transmitted to the data port DQ is later; if the parameters characterize the process corner as a slow process corner, the more the number of the switches K that are turned on, the shorter the delay of the read command RD is shortened, so that the time when the data is read out from the memory cell is earlier. Correspondingly, the time when the data is read out from the memory cell and transmitted to the data port is earlier.

[0069] The storage system includes multiple storage chips 100. Even though the storage system has pre-designed the delay of data read from the storage unit to output from the data port DQ for different storage chips 100, due to the problem of different process corners in the storage chips 100, there is still a problem that the delay of data read deviates from the pre-design. In the embodiments of the present disclosure, the controller 200 further obtains the parameters that can characterize the process corner of each storage chip 100, and adjusts the delay of the read command RD for controlling the storage chip 100 to read data according to the parameters corresponding to the process corner, that is, compensates for the delay of the read command RD according to the process corner, so as to adjust the actual time when the data of the storage chip 100 is read from the storage unit to be transmitted to the data port DQ, so that the actual time when the data of each storage chip 100 arrives at the data port DQ conforms to the pre-design, avoiding the problem of data transmission conflict corresponding to different storage chips 100, and improving the storage performance of the storage system.

[0070] A delay module 201 is formed by multiple sequentially connected inverters 211, which can not only realize the function of obtaining different delays of the read command RD, but also has a simple circuit structure, occupies a small space of the chip area of the controller 200, and is beneficial to reducing the design difficulty of the controller 200 while saving the chip area.

[0071] It can be understood that in other embodiments, other suitable delay circuits can also be used as the delay module.

[0072] It should be noted that in some embodiments, the sizes of the inverters 211 can be the same, and the inverters 211 have the same delay characteristics; in other embodiments, the sizes of the inverters 211 can also be different, and the inverters 211 have different delay characteristics.

[0073] In some embodiments, the number of all the inverters 211 in the delay module 201 can be an even number, and the number of the inverters 211 connected in parallel with the switch K can also be an even number. In this way, the phase of the read command RD is the same as that of the reference read command RD0.

[0074] In some embodiments, the controller 200 is configured to, after each power-on startup of the storage system, obtain the parameters of each storage chip 100, and adjust the delay of the read command RD sent to the storage chip 100 corresponding to the parameters until polling to obtain the parameters of all storage chips 100 and adjusting the delay of the read command RD sent to all storage chips 100.

[0075] In some specific examples, the delay of the read command RD corresponding to each memory chip 100 can be latched and recorded. For example, information on the number of switches K that need to be controlled to conduct corresponding to each memory chip 100 is recorded. During the subsequent period when the read command RD is issued again, the previously recorded delay of the read command RD is sent to the corresponding memory chip 100. For example, for different memory chips 100, the number of the previously recorded conductive switches K is enabled.

[0076] In some other specific examples, the controller 200 may further include multiple delay modules. Each delay module can send read commands RD with different delays to the memory chip 100. Among them, after power-on startup, each delay module records the delay of the read command RD sent to the memory chip 100. And after adjusting the delays of the read commands RD sent to all memory chips 100, each delay of the corresponding read command RD is recorded by a corresponding delay module. After that, each time a different delay module is enabled to send a read command RD to the corresponding memory chip 100, so that the delay of the read command RD sent to this memory chip 100 meets the requirements. In this way, there is no need to adjust again before each issuance of the read command RD, which is beneficial to reducing the power consumption of the storage system and improving the storage speed of the storage system. Specifically, in some embodiments, referring to Figure 4 After the storage system is powered on and starts up, a enable signal TM is first sent from the controller 200 to the memory chip 100 to enable the ring oscillator 110 to start oscillating, and the counter 210 counts the oscillation periods within a preset time period to obtain a count value, and this count value is used as a parameter representing the process corner.

[0077] In some embodiments, referring to Figure 3 the controller 200 obtains a characterization parameter from the non-volatile storage module, and this characterization parameter is used as a parameter representing the process corner.

[0078] The working principle of the controller 200 will be described in more detail below.

[0079] In one example, the controller 200 can adjust the delay of the read command RD of the storage chip 100 in the following way: perform a read-write operation test, obtain the delay from issuing the reference read command to the data output from the data port, and obtain the storage chip 100 with a delay that does not meet the expectation; use the storage chip 100 with a delay that meets the expectation as a standard, or use the storage chip 100 with a standard process corner as a standard, obtain the parameter values of the storage chip 100 with a delay that does not meet the expectation, and adjust the number and / or position of the turned-on switch K. After the adjusted storage chip 100 performs the read-write operation test again, if the delay of the data still does not meet the requirements, continue to adjust the number and / or position of the turned-on switch K until the data of the adjusted storage chip 100 meets the requirements. It can be understood that the delay from issuing the reference read command to the data being read out from the data port includes the following two delays: the delay from issuing the reference read command to the storage unit starting to read out the data; the delay from the data being read out from the storage unit to being output from the data port DQ.

[0080] Among them, in a specific example, after the storage system is powered on and starts up, before performing the read-write operation test, the ring oscillators 110 and the counters 210 of all the storage chips 100 can start to work to obtain and save the corresponding count values; after the first read-write operation test, the controller 200 obtains the count values of the storage chips 100 with a delay that does not meet the expectation. In this way, it is beneficial to shorten the overall test time required for the storage system.

[0081] In another specific example, after the storage system is powered on and starts up and after the first read test, the ring oscillators 110 and the counters 210 of the storage chips 100 with a delay that does not meet the expectation start to work, obtain the corresponding count values and send the count values to the controller 200. In this way, only the storage chips 100 with a delay that does not meet the expectation are counted, which is beneficial to reducing the power consumption of the storage system.

[0082] As Figure 6 shown, Figure 6 the first row in shows the timing diagram of the read command RD and the data DQ1 of a storage chip 100, and the second and third rows both show the timing diagram of the read command RD and the data DQ2 of another storage chip 100. Among them, the second row is the timing diagram corresponding to not adjusting the delay of the read command RD of the storage chip 100, and the third row is the timing diagram corresponding to after adjusting the delay of the read command RD of the storage chip 100. It can be found from Figure 6 that for another storage chip 100, if the delay of the read command RD is not adjusted, there will be a problem of data transmission conflict between different storage chips 100. After adjusting the delay of the read command RD of the storage chip 100, the problem of data conflict between different storage chips 100 will be improved.

[0083] As Figure 7 shown, in some embodiments, a plurality of memory chips 100 are stacked in sequence on the surface of a controller 200, and the memory system is a 3D stacked structure. Figure 8 Another structural schematic diagram of the memory system provided by the embodiments of the present disclosure. In other embodiments, as Figure 8 shown, the memory system may further include: a carrier substrate 300, the controller 200 is located on the surface of the carrier substrate 300, and a plurality of memory chips 100 are stacked in sequence on the surface of the carrier substrate 300, and the memory system constitutes a 2.5D stacked structure.

[0084] The embodiments of the present disclosure provide a memory system with excellent structural performance, which can adjust the delay of a read command RD for controlling data transmission delay according to the process corner of the memory chip 100, so that the data of each memory chip 100 is output from the data port DQ at an expected moment, and the read and write performance of the memory system is improved.

[0085] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A storage system, characterized in that, Comprising: A plurality of memory chips, each of the memory chips being configured to have parameters for characterizing the process corner of the memory chip within the memory chip; A controller configured to obtain the parameters of each of the memory chips and, based on the parameters, adjust the delay of a read command sent to the memory chip corresponding to the parameters.

2. The storage system according to claim 1, wherein The parameters are characterization parameters stored within the memory chip.

3. The storage system according to claim 2, wherein The memory chip includes: a non-volatile memory module; the memory chip is configured to obtain the characterization parameters and store the characterization parameters in the non-volatile memory module before being packaged with the controller.

4. The storage system according to claim 3, wherein The non-volatile memory module includes one-time programmable memory cells.

5. The storage system according to claim 1, wherein The parameters are count values for characterizing the process corner of the memory chip, and the memory chip is configured to perform counting and obtain the count values within a preset time after each power-on startup of the memory system.

6. The storage system according to claim 5, wherein The memory chip includes: A ring oscillator; A counter connected to the ring oscillator for counting the oscillation period of the ring oscillator within a preset time to obtain the count value; The controller is connected to the ring oscillator and the counter for controlling the ring oscillator to start oscillating and obtain the count value.

7. The storage system according to claim 6, characterized in that, The enable signal of the ring oscillator is provided by the controller.

8. The storage system according to claim 1, wherein The controller includes: A command generation module for providing a reference read command; A delay module for receiving the reference read command and outputting the read command with a delay compared to the reference read command based on the parameters.

9. The storage system according to claim 8, wherein, The delay module includes: A plurality of serially connected inverters, the inverter at the first position receiving the reference read command, and the inverter at the last position outputting the read command; A plurality of switches, each switch being connected in parallel with at least one of the inverters; The controller is configured to control the number of conducting switches among the plurality of switches based on the parameters.

10. The storage system according to claim 9, characterized in that, The total number of all the inverters is an even number.

11. The storage system according to claim 9, wherein The number of inverters connected in parallel with each switch is an even number.

12. The storage system according to claim 1, wherein, The controller is configured to, after each power-on startup of the memory system, obtain the parameters of each of the memory chips and adjust the delay of the read command sent to the memory chip corresponding to the parameters until polling to obtain the parameters of all the memory chips and adjusting the delay of the read commands sent to all the memory chips.

13. The storage system according to claim 1, wherein The memory chip further includes: a scan chain interface configured to obtain the parameters based on a command signal issued by the controller and output the parameters to the controller; the controller further includes: An acquisition module configured to issue the command signal to the scan chain interface and receive the parameters output by the scan chain interface.

14. The storage system according to claim 1, wherein A plurality of the memory chips are stacked on the surface of the controller in sequence.

15. The storage system according to claim 1, wherein The memory system further includes: a carrier substrate, the controller is located on the surface of the carrier substrate, and a plurality of the memory chips are stacked on the surface of the carrier substrate in sequence.

Images