Memory chip and memory system

Abstract

An embodiment of the present disclosure provides a storage chip and a storage system. The storage chip is applied to the storage system and includes: the storage chip is configured to perform counting and obtain a count value after being powered on and started. The count value is used to characterize the process corner of the storage chip. The storage chip also has a reference voltage with an adjustable magnitude. The magnitude of the reference voltage is adjustable based on the count value, and the storage chip adjusts the delay of data read from the storage unit to output from the data port based on the reference voltage. The embodiments of the present disclosure are beneficial to improving the neatness of data signal transmission and preventing data conflicts.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a storage chip and a storage system. Background Art

[0002] Semiconductor storage can be divided into non-volatile storage and volatile storage. As volatile storage, Dynamic Random Access Memory (DRAM) has the advantages of high storage density, fast read and write speeds, etc., and is widely used in various electronic systems.

[0003] A DRAM system usually consists of a controller and multiple storage chips. Due to differences in manufacturing processes and the like, the performance of different storage chips also has corresponding differences, which will affect the overall performance of the DRAM system. Summary of the Invention

[0004] Embodiments of the present disclosure provide a storage chip and a storage system to improve the problem of data signal transmission conflicts in the storage system.

[0005] In some embodiments of the present disclosure, on the one hand, a storage chip is provided, which is applied to a storage system and includes: the storage chip is configured to count and obtain a count value after being powered on and started, the count value is used to characterize the process corner of the storage chip, the storage chip also has a reference voltage with an adjustable magnitude, the magnitude of the reference voltage is adjustable based on the count value, and the storage chip adjusts the delay of data read from the storage unit to output from the data port based on the reference voltage.

[0006] In some embodiments, the storage chip includes: a ring oscillator; a counter, the counter is connected to the ring oscillator and is used to count the oscillation period of the ring oscillator within a preset time to obtain the count value.

[0007] In some embodiments, the storage chip further includes: a scan chain interface, the scan chain interface is configured to obtain the count value based on a command signal issued by the controller and output the count value to the controller.

[0008] In some embodiments, the data has a readout path, which includes the process of the data being read out from the storage unit to being output from the data port. The data transmitted on the readout path is defined as intermediate data. The storage chip includes: a delay module, which is arranged on the readout path, receives the intermediate data at the input end, receives the reference voltage at the control end, and outputs the intermediate data at the output end based on the reference voltage. The length of the delay from receiving the intermediate data to outputting the intermediate data by the delay module corresponds to the magnitude of the reference voltage; an adjustment module, whose output end is connected to the control end of the delay module, receives a preset reference voltage at the input end, receives a control signal at the control end, and outputs an adjustable reference voltage at the output end based on the control signal and the preset reference voltage.

[0009] In some embodiments, the adjustment module includes: an operational amplifier, whose positive input end receives the preset reference voltage; an adjustment unit, which is connected to the negative input end and the output end of the operational amplifier. The output end of the adjustment unit outputs the reference voltage, and also adjusts the magnitude of the equivalent resistance between the output end of the adjustment unit and the output end of the operational amplifier, or adjusts the magnitude of the equivalent resistance between the output end of the adjustment unit and the ground end, based on the control signal.

[0010] In some embodiments, the adjustment unit includes: N first resistors connected in series between the negative input end and the output end of the operational amplifier, where N is an integer greater than 1, at least one second resistor, which is connected between the negative input end and the ground end; M first switches, which connect the output end of the adjustment unit and one end of the corresponding first resistor, and the first switches are selectively turned on based on the control signal to adjust the magnitude of the equivalent resistance between the output end of the adjustment unit and the output end of the operational amplifier, where M is a positive integer less than or equal to N.

[0011] In some embodiments, the adjustment unit includes: X second resistors connected in series between the negative input end and the ground end, where X is a positive integer greater than 1; Y second switches, which connect the output end of the adjustment unit and one end of the corresponding second resistor, and the second switches are selectively turned on based on the control signal to adjust the magnitude of the equivalent resistance between the output end of the adjustment unit and the ground end, where Y is a positive integer less than or equal to X.

[0012] In some embodiments, the delay module includes: an even number of inverters connected in sequence, the power supply end of the inverter is connected to the reference voltage, the input end of the first inverter receives the intermediate data, and the output end of the last inverter outputs the intermediate data.

[0013] In some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure provides a storage system, including: a plurality of storage chips provided in the foregoing embodiments; a controller configured to obtain the count value of the storage chips and adjust the magnitude of the reference voltage of the storage chips corresponding to the count value based on the count value.

[0014] In some embodiments, the storage chip includes: a ring oscillator; a counter connected to the ring oscillator for counting the oscillation period of the ring oscillator within a preset time to obtain the count value; the controller is connected to the ring oscillator and the counter for controlling the ring oscillator to start oscillating and obtaining the count value.

[0015] In some embodiments, the storage chip further includes: a scan chain interface configured to obtain the count value based on a command signal issued by the controller and output the count value to the controller; the controller further includes: an acquisition module configured to issue the command signal to the scan chain interface and receive the count value output by the scan chain interface.

[0016] In some embodiments, the controller is configured to, after each power-on startup of the storage system, obtain the count value of each storage chip and adjust the magnitude of the reference voltage of the storage chips corresponding to the count value until polling to obtain the count values of all the storage chips and adjusting the magnitudes of the reference voltages of all the storage chips.

[0017] In some embodiments, the data has a readout path, and the readout path includes the process of the data being read out from the storage unit to being output from the data port. The data transmitted on the readout path is defined as intermediate data; the storage chip includes: a delay module disposed on the readout path, with an input end receiving the intermediate data, a control end receiving the reference voltage, and an output end outputting the intermediate data based on the reference voltage. The length of the delay from the delay module receiving the intermediate data to outputting the intermediate data corresponds to the magnitude of the reference voltage; an adjustment module, with an output end connected to the control end of the delay module, an input end receiving a preset reference voltage, a control end receiving a control signal, and an output end outputting an adjustable reference voltage based on the control signal and the preset reference voltage; the controller is connected to the control end of the adjustment module, and the controller is used to obtain the count value and generate the control signal based on the count value.

[0018] In some embodiments, the adjustment module includes: an operational amplifier, the positive input terminal of which receives the preset reference voltage; an adjustment unit, which is connected to the negative input terminal and the output terminal of the operational amplifier, the output terminal of the adjustment unit outputs the reference voltage, and further adjusts the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the output terminal of the operational amplifier, or adjusts the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the ground terminal, based on the control signal; the controller is connected to the adjustment unit and provides the control signal to the adjustment unit.

[0019] In some embodiments, the adjustment unit includes: N first resistors connected in series between the negative input terminal and the output terminal of the operational amplifier, N being an integer greater than 1, at least one second resistor connected between the negative input terminal and the ground terminal; M first switches, the first switches are connected to the output terminal of the adjustment unit and one end of the corresponding first resistor, and the first switches are selectively turned on based on the control signal to adjust the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the output terminal of the operational amplifier, M being a positive integer less than or equal to N; the controller is connected to the M first switches.

[0020] In some embodiments, the adjustment unit includes: X second resistors connected in series between the negative input terminal and the ground terminal, X being a positive integer greater than 1; Y second switches, the second switches are connected to the output terminal of the adjustment unit and one end of the corresponding second resistor, and the second switches are selectively turned on based on the control signal to adjust the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the ground terminal, Y being a positive integer less than or equal to X; the controller is connected to the Y second switches.

[0021] In some embodiments, the controller is configured to generate the control signal for controlling the reference voltage to be less than the preset reference voltage if the count value represents a fast process corner, and generate the control signal for controlling the reference voltage to be greater than the preset reference voltage if the count value represents a slow process corner.

[0022] In some embodiments, multiple memory chips are stacked on the surface of the controller in sequence; or, the memory system further includes: a carrier substrate, the controller is located on the surface of the carrier substrate, and multiple memory chips are stacked on the surface of the carrier substrate in sequence.

[0023] The technical solution provided by the embodiments of the present disclosure has the following advantages:

[0024] In the technical solution provided by the embodiments of the present disclosure, after the storage chip is powered on and starts up, it can perform counting and obtain a count value. The count value is used to characterize the process corner of the storage chip, and the reference voltage in the storage chip is adjustable based on the count value. If the count value indicates that the process corner of the storage chip is a slow process corner, then the reference voltage of this storage chip is adjusted to be larger than that of the storage chip with a faster process corner, so as to shorten the delay of the data of the storage chip with the slow process corner. If the count value indicates that the process corner of the storage chip is a fast process corner, then the reference voltage of this storage chip is reduced, so that the delay of the data of the storage chip with the fast process corner becomes relatively longer. In this way, the reference voltages of different storage chips are compensated based on their different process corners, so that the data transmission delays of different storage chips will meet the expectations, improving the neatness of data signals, preventing data transmission conflict problems from occurring among different storage chips, and improving the read and write performance of the storage system. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the drawings do not constitute a proportional limitation.

[0026] Figure 1 It is a schematic structural diagram of a storage system;

[0027] Figure 2 is Figure 1 a schematic diagram of data transmission in the provided storage system;

[0028] Figure 3 It is a schematic structural diagram of a storage chip provided by the embodiments of the present disclosure;

[0029] Figure 4 It is a schematic structural diagram of an adjustment module in the storage chip provided by the embodiments of the present disclosure;

[0030] Figure 5 It is a schematic circuit diagram of an adjustment module in the storage chip provided by the embodiments of the present disclosure;

[0031] Figure 6 It is another schematic circuit diagram of an adjustment module in the storage chip provided by the embodiments of the present disclosure;

[0032] Figure 7 It is yet another schematic circuit diagram of an adjustment module in the storage chip provided by the embodiments of the present disclosure;

[0033] Figure 8 It is a schematic circuit diagram of a delay module in the storage chip provided by the embodiments of the present disclosure;

[0034] Figure 9A schematic structural diagram of a storage system provided by an embodiment of the present disclosure;

[0035] Figure 10 A schematic diagram of functional modules of a storage chip and a controller of a storage system provided by an embodiment of the present disclosure;

[0036] Figure 11 A schematic structural diagram of an adjustment module and a controller of a storage system provided by an embodiment of the present disclosure;

[0037] Figure 12 Another schematic structural diagram of a storage system provided by an embodiment of the present disclosure. Detailed implementation manners

[0038] Figure 1 A schematic structural diagram of a storage system, Figure 2 is Figure 1 a schematic diagram of data transmission in the provided storage system. Refer to Figure 1 , the storage system may include: a controller 13; a plurality of storage chips 12 stacked on the surface of the controller 13, and the storage chips 12 may be DRAM chips.

[0039] Due to the process differences among different storage chips 12, the electrical performances of different storage chips 12 are also different. For example, the threshold voltages or conduction currents of transistors in different storage chips 12 are different, resulting in different data transmission delays inside different storage chips 12. This will cause the data signals received by the controller 13 from different storage chips 12 to be non-uniform (skew), the levels of different data signals to be inconsistent, and data conflicts to exist in the data signals of different storage chips 12, affecting the overall performance of the storage system. Specifically, refer to Figure 2 , Figure 2 Example 1 in Figure 2 is an ideal transmission schematic diagram of data signals corresponding to two storage chips 12, where DQ1 and DQ2 are data signals respectively transmitted from different storage chips 12 to the controller 13.

[0040] Based on this, embodiments of the present disclosure provide a storage chip, which is applied to a storage system, and the reference voltage for controlling the data transmission delay in the storage chip is adjustable based on the count value representing the process corner, so as to improve the data conflict problem of the storage system, improve the neatness of data signal alignment, and further improve the read and write performance of the storage system.

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will elaborate on each embodiment of the present disclosure with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are presented for the readers to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0042] Figure 3 It is a schematic structural diagram of the storage chip provided by the embodiment of the present disclosure.

[0043] Reference Figure 3 , the storage chip 100 provided by the embodiment of the present disclosure is applied to a storage system and includes: The storage chip 100 is configured to perform counting and obtain a count value after power-on startup. The count value is used to represent the process corner of the storage chip 100. There is also an adjustable reference voltage V ref in the storage chip 100. ref The magnitude of the reference voltage V ref is adjustable based on the count value, and the storage chip 100 adjusts the delay of data read from the storage unit 10 to output from the data port DQ based on the reference voltage V

[0044] The reference voltage V ref is related to the delay of data read from the storage unit 10 to output from the data port DQ. Specifically, for the same storage chip 100 or the same storage chip 100 with the same process corner, the larger the reference voltage V ref , the smaller the delay of data read from the storage unit 10 to output from the data port DQ. That is to say, different storage chips 100 have the problem of different delays of the chips themselves due to different process corners. The storage chip 100 with a slow process corner has a larger delay itself, and the storage chip 100 with a fast process corner has a smaller delay itself. In the embodiments of the present disclosure, different count values correspond to different process corners. Since the reference voltage V ref is adjustable based on the count value, the delay can be compensated based on the process corner of the storage chip 100 to improve the delay consistency of each storage chip 100. Specifically, if the count value represents that the process corner of the storage chip 100 is a slow process corner, the reference voltage V ref, so as to shorten the latency of the data of the memory chip 100 at the slow process corner; if the count value indicates that the process corner of the memory chip 100 is a fast process corner, then the reference voltage V of the memory chip 100 is reduced ref , so as to extend the latency of the data of the memory chip 100 at the fast process corner. In this way, different memory chips 100 perform corresponding compensation on the reference voltage V ref . As a result, the actual latencies of the respective memory chips 100 tend to be the same or exactly the same. In this way, the data transmission latencies of different memory chips 100 will meet the expectations, improving the neatness of data signals, preventing data transmission conflict problems among different memory chips 100, and improving the read and write performance of the memory system.

[0045] The memory chip 100 provided by the embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0046] In some embodiments, the memory chip 100 may be a DRAM memory chip, such as a DDR (double data rate) 4 DRAM memory chip or a DDR5 DRAM memory chip. In other embodiments, the memory chip 100 may also be an SRAM (Static Random-Access Memory) memory chip, a NAND memory chip, a NOR memory chip, a FeRAM memory chip, or a PcRAM memory chip.

[0047] The design of the memory chip 100 needs to meet conditions such as process corner, voltage, and temperature. The combination formed by the process corner, voltage, and temperature is called PVT (process, voltage, temperature) condition.

[0048] In some embodiments, if a 5-process corner model is adopted, the process corners of different memory chips 100 can be divided into TT (typical nmos and typical pmos) process corners, FF (fast nmos and fast pmos) process corners, SS (slow nmos and slow pmos) process corners, FS (fast nmos and slow pmos) process corners, and SF (slow nmos and fast pmos) process corners. Among them, Typical means that the drive current is an average value, Fast means that the drive current is its maximum value, and Slow means that the drive current is its minimum value (this drive current is the Ids current). This is an explanation from the measurement perspective. Typical, Fast, and Slow can also be understood as the speed of carrier mobility. Carrier mobility refers to the average drift velocity of carriers under the action of a unit electric field.

[0049] Reference Figure 3 , the memory chip 100 may include: a ring oscillator 110; a counter 210, connected to the ring oscillator 110, for counting the oscillation period of the ring oscillator 110 within a preset time to obtain a count value.

[0050] Specifically, the enable signal TM of the ring oscillator 110 can be issued by a controller. The speed of oscillation of the ring oscillator 110 is related to the process corner of the memory chip 100. If the process corner is a fast process corner, the ring oscillator 110 oscillates faster; if the process corner is a slow process corner, the ring oscillator 110 oscillates slower. The counter 210 counts the oscillation period of the ring oscillator 110 within a preset time, and can thus reflect the speed of oscillation of the ring oscillator 110 through the count value. It can be understood that the preset time can be a range value, but for different memory chips 100 of the same memory system, the preset time should be the same fixed value to ensure that the count value is obtained within the same time period.

[0051] In some other embodiments, the enable signal TM of the ring oscillator 110 can also be provided internally by the memory chip 100. For example, the power-on startup of the memory chip 100 can be used as the excitation condition for providing the enable signal TM to the ring oscillator 110.

[0052] In some embodiments, the ring oscillator 110 may include: an AND gate 230, one input terminal of the AND gate 230 receives an enable signal TM; a plurality of cascaded inverters 240 connected in series, the input terminal of the first cascaded inverter 240 is connected to the output terminal of the AND gate 230, the output terminal of the last cascaded inverter 240 is connected to the other input terminal of the AND gate 230, and the output terminal of the last cascaded inverter 240 is further connected to the counter 210. Specifically, if the ring oscillator 110 oscillates once, the counter 210 counts once.

[0053] Wherein, the number of cascaded inverters 240 may be an odd number.

[0054] In some embodiments, the counter 210 may be an up counter. It should be noted that the counter 210 may further have a reset terminal for receiving a reset signal, and the reset signal may be issued by a controller to reset the counter 210 before counting, ensuring that the initial values of the counters 210 of different memory chips 100 are the same before counting, and also ensuring that the initial values of the counters 210 of the same memory chip 100 are the same before counting in different test phases.

[0055] In some embodiments, the counter 210 may further include a latch module for latching the count value. In this way, after the memory system is powered on and starts up, the memory chip 100 can first obtain the count value and save the count value. After a certain period of time, the controller then calls the count value to obtain the process corner of the memory chip 100, so as to adjust the reference voltage of the memory chip 100. In this way, it is beneficial to improve the test flexibility of the memory system, and all the memory chips 100 can obtain the corresponding count values simultaneously.

[0056] In some embodiments, the data has a read path, and the read path includes the process of data being read from the memory cell 10 to being output from the data port DQ. The data transmitted on the read path is defined as intermediate data; the memory chip 100 includes: a delay module 101, the delay module 101 is arranged on the read path, the input terminal receives the intermediate data, the control terminal receives the reference voltage V ref , and the output terminal outputs the intermediate data based on the reference voltage V ref . The length of the delay from when the delay module 101 receives the intermediate data to when it outputs the intermediate data corresponds to the magnitude of the reference voltage V ref ; an adjustment module 102, the output terminal of the adjustment module 102 is connected to the control terminal of the delay module 101, the input terminal receives a preset reference voltage V R , the control terminal receives a control signal Con, and the output terminal outputs an adjustable reference voltage V R based on the control signal Con and the preset reference voltage V ref .

[0057] Through the delay module 101, the delay of data can be controlled from any transmission path on the data readout path, making the design of the memory chip 100 more flexible; through the adjustment module 102, a reference voltage V with adjustable magnitude can be output based on the preset reference voltage V R and the control signal Con, and the preset reference voltage V ref can be the preset reference voltage specified in the user manual of the memory chip 100, that is, the preset reference voltage can be the voltage value designed for the memory chip 100 under ideal conditions. R Specifically, on the data readout path, there can be a driving module, a buffer module, a latch module, etc. The delay module 101 can be set at any position on the readout path. For example, it can be set at the previous stage or the next stage of the driving module, at the previous stage or the next stage of the buffer module, at the previous stage or the next stage of the latch module, or inside the driving module, the buffer module, or the latch module. The control signal Con can be given by the controller of the memory system, and the control signal Con is also related to the process corner of the memory chip 102.

[0058]

[0059] Figure 4 Figure 4 FIG. is a schematic structural diagram of an adjustment module in the memory chip provided by an embodiment of the present disclosure. Refer to Figure 4 In some embodiments, the adjustment module 102 may include: an operational amplifier 112, and the positive input terminal of the operational amplifier 112 receives the preset reference voltage V R ; an adjustment unit 122, the adjustment unit 122 is connected to the negative input terminal and the output terminal of the operational amplifier 112, and the output terminal OUT of the adjustment unit 122 outputs the reference voltage V ref , and based on the control signal, the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112 is adjusted, or the magnitude of the equivalent resistance between the output terminal of the adjustment unit 122 and the ground terminal is adjusted.

[0060] According to the principle of "virtual short" of the operational amplifier, the voltage at the negative input terminal of the operational amplifier 112 is the same as the voltage at the positive input terminal. By the structure of the operational amplifier 112 and the adjustment unit 122, a reference voltage V with adjustable magnitude is obtained ref , making the circuit structure of the adjustment module 102 simple, and the adjustment module 102 occupies a small area of the memory chip 100, which is beneficial to saving the chip area of the memory chip 100. Specifically, it is beneficial to saving the chip area of the memory chip 100. Specifically, define the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal as R1, and define the equivalent resistance between the negative input terminal of the operational amplifier 112 and the ground terminal as R2, then the reference voltage V refis related to a preset reference voltage V R satisfies the following relationship:

[0061] V ref =(V R / R2)*R1 (1)

[0062] Adjusting at least one of R1 or R2 can adjust the reference voltage V ref magnitude. Therefore, the magnitude of R1 can be selected for adjustment, the magnitude of R2 can be selected for adjustment, or the magnitudes of both R1 and R2 can be adjusted simultaneously to adjust the reference voltage V ref magnitude.

[0063] Reference Figure 5 , Figure 5 , Fig. is a schematic circuit diagram of a regulation module. The regulation unit 122 may include: N first resistors r1 connected in series between the negative input terminal and the output terminal of the operational amplifier 112, where N is an integer greater than 1, at least one second resistor r2, and the second resistor r2 is connected between the negative input terminal and the ground terminal; M first switches k1, the first switch k1 is connected to the output terminal OUT of the regulation unit 122 and one end of the corresponding first resistor r1, and the first switch k1 is selectively turned on based on the control signal Con to adjust the magnitude of the equivalent resistance between the output terminal of the regulation unit 122 and the output terminal of the operational amplifier 112, and M is a positive integer less than or equal to N. N can be any natural number greater than 1 such as 2, 3, or 4, and M can be any natural number such as 1, 2, or 3.

[0064] Among them, the first switch k1 can be a MOS transistor or a transmission gate. It should be noted that the resistance values of each first resistor r1 can be the same or different; the resistance values of each second resistor r2 can be the same or different. According to the different conduction situations of the first switch k1, the magnitude of the equivalent resistance between the output terminal OUT of the regulation unit 122 and the output terminal of the operational amplifier 112 is also different.

[0065] Reference Figure 5 , according to the principle of "virtual short" of the operational amplifier, the voltage at the negative input terminal of the operational amplifier 112 is the same as the voltage at the positive input terminal, that is, the voltage at the negative input terminal is V R . Based on the voltage at the negative input terminal and the resistance from the negative input terminal to the ground terminal, the current from the negative input terminal to the ground terminal can be obtained, and this current is also the current of the path from the output terminal of the operational amplifier 112 to the ground terminal; only one of the multiple first switches k1 is turned on. Based on the different conduction situations of the first switch k1, combined with the current and the equivalent resistance between the output terminal OUT of the regulation unit 122 and the ground terminal, the reference voltage V output by the output terminal OUT of the regulation unit 122 can be calculated. refFor example, if the first switch K1 connected to the node connecting the first resistor R1 and the second resistor R2 is turned on, the reference voltage V output from the output terminal OUT of the adjustment unit 122 ref与 preset reference voltage V R is the same.

[0066] In addition, the more the number of the first resistor R1 and the first switch K1, the more the number of levels of the magnitude of the reference voltage V output by the adjustment module 102 ref is, and the more the number of levels that the delay of data transmission can be adjusted accordingly, which is more conducive to adjusting to obtain the delay of data meeting the matching requirements. In the specific actual circuit, it is also necessary to consider the area of the storage chip 100 occupied by the adjustment module 102. If the number of the first resistor R1 and the first switch K1 is too large, the area of the storage chip 100 will increase accordingly. Therefore, based on the above two requirements, the number of the first resistor R1 and the first switch K1 can be reasonably selected.

[0067] Reference Figure 6 , Figure 6 is another schematic circuit diagram of the adjustment module. The adjustment unit 122 includes: X second resistors R2 connected in series between the negative input terminal and the ground terminal, where X is a positive integer greater than 1; Y second switches K2, the second switch K2 is connected to the output terminal OUT of the adjustment unit 122 and one end of the corresponding second resistor R2, and the second switch K2 is selectively turned on based on the control signal Con to adjust the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal, and Y is a positive integer less than or equal to X. X can be any natural number greater than 1 such as 2, 3, or 4, and Y can be any natural number such as 1, 2, or 3.

[0068] Among them, the second switch K2 can be a MOS transistor or a transmission gate. It should be noted that the resistance values of each second resistor R2 can be the same or different. According to the different conduction conditions of the second switch K2, the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal is also different.

[0069] In addition, the more the number of the second resistor R2 and the second switch K2, the more the number of levels of the magnitude of the reference voltage V output by the adjustment module 102 ref is, and the more the number of levels that the delay of data transmission can be adjusted accordingly, which is more conducive to adjusting to obtain the delay of data meeting the matching requirements. In the specific actual circuit, it is also necessary to consider the area of the storage chip 100 occupied by the adjustment module 102. If the number of the second resistor R2 and the second switch K2 is too large, the area of the storage chip 100 will increase accordingly. Therefore, based on the above two requirements, the number of the second resistor R2 and the second switch K2 can be reasonably selected.

[0070] Reference Figure 6, in some embodiments, the adjustment unit 122 may further include: at least one first resistor r1, the first resistor r1 is connected between the negative input terminal and the output terminal of the operational amplifier 112, and in the case where there are multiple first resistors r1, the multiple first resistors r1 are connected in series.

[0071] Reference Figure 6 , according to the principle of "virtual short" of the operational amplifier, the voltage at the negative input terminal of the operational amplifier 112 is the same as the voltage at the positive input terminal. For the calculation method of the output terminal OUT of the adjustment unit 122, reference can be made to the foregoing relevant description.

[0072] Reference Figure 7 , Figure 7 FIG. is another structural schematic diagram of the adjustment module. In some embodiments, the adjustment unit 122 may include: N first resistors r1 connected in series between the negative input terminal and the output terminal of the operational amplifier 112, where N is an integer greater than 1; M first switches k1, the first switch k1 is connected to the output terminal OUT of the adjustment unit 122 and one end of the corresponding first resistor r1, and the first switch k1 is selectively turned on based on the control signal Con to adjust the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112, where M is a positive integer less than or equal to N; X second resistors r2 connected in series between the negative input terminal and the ground terminal, where X is a positive integer greater than 1; Y second switches k2, the second switch k2 is connected to the output terminal OUT of the adjustment unit 122 and one end of the corresponding second resistor r2, and the second switch k2 is selectively turned on based on the control signal Con to adjust the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal, where Y is a positive integer less than or equal to X.

[0073] For the calculation method of the voltage at the output terminal OUT of the adjustment unit 122, reference can be made to the foregoing such as Figure 5 and Figure 6 related description.

[0074] Specifically, through the first switch k1 and the second switch k2, the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112 can be adjusted, and the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal can also be adjusted. In this way, it is beneficial to more flexibly adjust the reference voltage V ref magnitude, and the space for the gear position of the reference voltage V ref is larger.

[0075] Reference Figure 8 , Figure 8 FIG. is a circuit structural schematic diagram of the delay module. The delay module 101 may include: an even number of inverters 111 connected in sequence, and the power supply terminal of the inverter 111 is connected to the reference voltage V ref, the input terminal of the first inverter 111 receives intermediate data, and the output terminal of the last inverter 111 outputs the intermediate data.

[0076] Among them, the intermediate data output from the output terminal of the last (i.e., the last in position) inverter 111 has a delay compared to the intermediate data received by the first (i.e., the first in position) inverter 111, and the magnitude of this delay is related to the delay time of each inverter 111. By referring to the reference voltage V ref , the magnitude of the delay time of the inverter 111 can be adjusted, so as to finally adjust the magnitude of the delay of the intermediate data transmitted through the delay module 101, so as to achieve the purpose of changing the magnitude of the delay from when the data is read out from the storage unit to when it is output from the data port DQ. It should be noted that, in some embodiments, the sizes of the inverters 111 can be the same, and the inverters 111 have the same delay characteristics; in other embodiments, the sizes of the inverters 111 can also be different, and the inverters 111 have different delay characteristics.

[0077] Using an even number of sequentially connected inverters 111 to form the delay module 101 can not only realize the function of delaying the transmission of intermediate data, but also the circuit structure of the delay module 101 is simple, occupying a small space in the chip area of the memory chip 100, which is beneficial to reducing the design difficulty of the memory chip 100 while saving the chip area.

[0078] It can be understood that, in other embodiments, other suitable delay circuits can also be used as the delay module.

[0079] In some embodiments, referring to Figure 3 , the memory chip 100 may further include: a scan chain interface 103, and the scan chain interface 103 is configured to obtain a count value based on a command signal issued by the controller and output the count value to the controller.

[0080] Specifically, in some embodiments, the scan chain interface 103 can be used as a medium for transmitting signals between the controller and the counter 210, and the count value is transmitted to the controller through the scan chain interface 103.

[0081] In the technical solution of the memory chip 100 provided in the above embodiments, the delay of the data transmitted from the storage unit to the data port can be adjusted according to the magnitude of the reference voltage. Since the magnitude of the reference voltage can be adjusted based on the process corner, the influence of different process corners on the data transmission delay can be solved, ensuring that the data transmission delay meets the expectation to prevent the problem of data signal conflict.

[0082] For example, if the count value indicates that the process corner is a fast process corner, the reference voltage of the corresponding memory chip 100 is decreased, so that the speed of data read from the memory cell to output from the data port becomes relatively slower, and the delay of data read from the memory cell to output from the data port is increased; if the count value indicates that the process corner is a slow process corner, the reference voltage of the corresponding memory chip 100 is increased, so that the speed of data read from the memory cell to output from the data port becomes relatively faster, and the delay of data read from the memory cell to output from the data port is increased.

[0083] Correspondingly, an embodiment of the present disclosure further provides a memory system, which includes the memory chip provided in any of the above embodiments. The memory system provided in the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the foregoing embodiments, reference may be made to the detailed description of the foregoing embodiments, and details will not be repeated hereinafter.

[0084] Figure 9 FIG. is a schematic structural diagram of a memory system provided in an embodiment of the present disclosure.

[0085] With reference to Figure 3 and Figure 9 , the memory system includes: a plurality of memory chips 100 provided in any of the above embodiments. The memory chip 100 is configured to, after being powered on and started up, perform counting and obtain a count value, where the count value is used to represent the process corner of the memory chip 100. The memory chip 100 further has an adjustable reference voltage V ref , and the magnitude of the reference voltage V ref is adjustable based on the count value. Moreover, the memory chip 100 adjusts the delay of data read from the memory cell 10 to output from the data port DQ based on the reference voltage V ref . A controller 200 is configured to obtain the count value of the memory chip 100 and adjust the magnitude of the reference voltage V ref of the memory chip 100 corresponding to the count value based on the count value.

[0086] The memory system includes a plurality of memory chips 100. Even if the memory system pre-designs the delay of data read from the memory cell to output from the data port DQ of different memory chips 100, due to the problem of different process corners of the memory chips 100, there is still a problem that the delay of data read deviates from the pre-design. In the embodiments of the present disclosure, the controller 200 further obtains the count value that can represent the process corner of each memory chip 100, and adjusts the reference voltage V ref of the memory chip 100 according to the count value corresponding to the process corner, that is, adjusts the reference voltage V refCompensation is performed to adjust the delay of the data read from the storage cells of the storage chip 100 to the output from the data port DQ, so that the actually manifested data read delay conforms to the pre-design, avoiding the problem of data transmission conflicts corresponding to different storage chips 100, and improving the storage performance of the storage system.

[0087] In some embodiments, referring to Figure 9 , the storage chip 100 may include: a ring oscillator 110; a counter 210 connected to the ring oscillator 110 for counting the oscillation periods of the ring oscillator 110 within a preset time to obtain a count value; and a controller 200 connected to the ring oscillator 110 and the counter 210 for controlling the ring oscillator 110 to start oscillating and obtaining the count value.

[0088] Specifically, in some examples, the enable signal TM of the ring oscillator 110 may be issued via the controller 200.

[0089] In some embodiments, referring to Figure 9 , the storage chip 100 may further include: a scan chain interface 103 configured to obtain a count value based on a command signal issued by the controller 200 and output the count value to the controller 200; the controller 200 further includes: a parameter acquisition module 201 configured to issue a command signal to the scan chain interface 103 and receive the count value output by the scan chain interface 103.

[0090] Specifically, the parameter acquisition module 201 issues a command signal to the scan chain interface 103. After receiving the command signal, the scan chain interface 103 obtains the count value of the counter 210, and then the count value is transmitted to the parameter acquisition module 201 via the scan chain interface 103. After obtaining the count value, the controller 200 generates a corresponding control signal Con.

[0091] Figure 10 As a schematic diagram of a functional module of the storage chip and the controller, referring to Figure 10 , in some embodiments, the data has a read path, and the read path includes the process of the data being read from the storage unit 10 to the output from the data port DQ. The data transmitted on the read path is defined as intermediate data; the storage chip 100 includes: a delay module 101 disposed on the read path, with an input end receiving the intermediate data, a control end receiving the reference voltage V ref , and an output end outputting the intermediate data based on the reference voltage V ref , and the length of the delay of the delay module 101 from receiving the intermediate data to outputting the intermediate data is related to the reference voltage V refcorresponds to the size; an adjustment module 102, the output end of the adjustment module 102 is connected to the control end of the delay module 101, and the input end receives a preset reference voltage V R , the control end receives a control signal Con, and the output end outputs an adjustable reference voltage V R based on the control signal Con and the preset reference voltage V ref ; the controller 200 is connected to the control end of the adjustment module 102, and the controller 200 is used to obtain a count value and generate a control signal Con based on the count value.

[0092] For the delay module 101, reference can be made to the corresponding detailed description in the foregoing embodiments, and details are not described herein again.

[0093] Specifically, different control signals Con correspond to different count values, and different control signals correspond to different reference voltages V ref corresponding. The controller 200 generates a corresponding control signal Con based on the count value, so that the memory chip 100 obtains a reference voltage V corresponding to the count value ref .

[0094] As Figure 11 shown, Figure 11 is a schematic structural diagram of the adjustment module and the controller. In some embodiments, the adjustment module 102 may include: an operational amplifier 112, and the positive input end of the operational amplifier 112 receives a preset reference voltage V R ; an adjustment unit 122, the adjustment unit 122 is connected to the negative input end and the output end of the operational amplifier 112, and the output end OUT of the adjustment unit 122 outputs a reference voltage V ref , and also based on the control signal Con, adjusts the size of the equivalent resistance between the output end OUT of the adjustment unit 122 and the output end of the operational amplifier 112, or adjusts the size of the equivalent resistance between the output end OUT of the adjustment unit 122 and the ground end; the controller 200 is connected to the adjustment unit 122 and provides a control signal to the adjustment unit 122.

[0095] Specifically, the size of the equivalent resistance between the output end OUT of the adjustment unit 122 and the output end of the operational amplifier 112, and / or the size of the equivalent resistance between the output end OUT of the adjustment unit 122 and the ground end, is determined by the control signal Con issued by the controller 200.

[0096] As Figure 5As shown, in some embodiments, the adjustment unit 122 may include: N first resistors r1 connected in series between the negative input terminal and the output terminal of the operational amplifier 112, where N is an integer greater than 1, at least one second resistor r2, and the second resistor r2 is connected between the negative input terminal and the ground terminal; M first switches k1, the first switch k1 is connected to the output terminal OUT of the adjustment unit 122 and one end of the corresponding first resistor r1, and the first switch k1 is selectively turned on based on the control signal Con to adjust the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112, where M is a positive integer less than or equal to N; the controller 200 is connected to the M first switches k1.

[0097] In addition, the first switch k1 is also connected between the negative input terminal of the operational amplifier 112 and the output terminal OUT of the adjustment unit 122. The first switch k1 is selectively turned on according to the control signal Con, that is, the controller 200 sends a corresponding independent control signal Con to each first switch k1 to select which first switch k1 is turned on, so as to adjust the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112, and further adjust the reference voltage V ref magnitude.

[0098] Reference Figure 6 , in some embodiments, the adjustment unit 122 also includes: X second resistors r2 connected in series between the negative input terminal of the operational amplifier 112 and the ground terminal, where X is a positive integer greater than 1; Y second switches k2, the second switch k2 is connected to the output terminal OUT of the adjustment unit 122 and one end of the corresponding second resistor r2, and the second switch k2 is selectively turned on based on the control signal Con to adjust the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal, where Y is a positive integer less than or equal to X; the controller 200 is connected to the Y second switches k2.

[0099] The second switch k2 is selectively turned on according to the control signal Con, that is, the controller 200 sends a corresponding independent control signal Con to each second switch k2 to select which second switch k2 is turned on, so as to adjust the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal, and further adjust the reference voltage V ref magnitude.

[0100] It can be understood that, in some embodiments, as Figure 7 shown, the adjustment unit 122 may only include one of the first switch k1 or the second switch k2. In other embodiments, the adjustment unit 122 may also include both the first switch k1 and the second switch k2.

[0101] It should also be noted that, as shown in the foregoing embodiments, regarding the design of the adjustment unit 122, the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112 can be adjusted only, or the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal can be adjusted only, or both the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the output terminal of the operational amplifier 112 and the magnitude of the equivalent resistance between the output terminal OUT of the adjustment unit 122 and the ground terminal can be adjusted. For the specific circuit implementation, reference can be made to the description of the foregoing embodiments and will not be elaborated herein.

[0102] In some embodiments, the controller 200 is configured to generate a control signal Con for controlling the reference voltage V ref less than the standard reference voltage if the count value represents a fast process corner, and generate a control signal Con for controlling the reference voltage V ref greater than the standard reference voltage if the count value represents a slow process corner.

[0103] Among them, the standard reference voltage can be the ideal reference voltage of the pre-designed memory chip 100. In an ideal situation, the delay of data read from the memory cell to the data port of the memory chip 100 under this standard reference voltage meets the expectation. If the count value represents a fast process corner, the control signal generated by the controller 200 can make the value of the reference voltage V ref smaller than the standard reference voltage, that is, compensate the reference voltage V ref of the memory chip 100 with a fast process corner. In this way, the delay of data read from the memory cell to the data port is longer than that before compensation, which can compensate for the problem of fast transmission speed brought by the fast process corner, making the delay of data read from the memory cell to the data port more in line with the expectation, that is, the delay after compensation tends to be consistent with the delay in the ideal situation (i.e., pre-designed). If the count value represents a slow process corner, the control signal generated by the controller 200 can make the value of the reference voltage V ref greater than the standard reference voltage, that is, compensate the reference voltage V ref of the memory chip 100 with a slow process corner. In this way, the delay of data read from the memory cell to the data port is shorter than that before compensation, which can compensate for the problem of slow transmission speed brought by the slow process corner, making the delay of data read from the memory cell to the data port more in line with the expectation, that is, the delay after compensation tends to be consistent with the delay in the ideal situation. In this way, the timing of the data signals output from different memory chips 100 will not conflict, which is beneficial to improving the performance of the memory system.

[0104] In addition, in some embodiments, if the count value represents the standard process corner, the reference voltage V of the corresponding memory chip 100ref It may be the same as the standard reference voltage.

[0105] In some embodiments, the controller 200 is configured to, after each startup of the storage system, obtain the count value of each storage chip 100, and adjust the reference voltage V of the storage chip 100 corresponding to the count value ref until polling to obtain the count values of all storage chips 100 and adjusting the reference voltages V of all storage chips 100 ref in magnitude.

[0106] Specifically, after the storage system is powered on and started, the controller 200 first sends an enable signal TM to the storage chip 100 to enable the ring oscillator 110 to start oscillating, and the counter 210 counts the oscillation period within a preset time period.

[0107] The working principle of the controller 200 will be described in more detail below.

[0108] In one example, the controller 200 can adjust the reference voltage of the storage chip 100 in the following manner: perform a read / write operation test, obtain the delay from when the data of each storage chip 100 is read out from the storage unit to when it is transmitted to the data port, and obtain the storage chips 100 with delays not meeting the expectations; use the storage chips 100 with delays meeting the expectations as the standard, or use the storage chips 100 with standard process corners as the standard, obtain the count values of the storage chips 100 with delays not meeting the expectations, and adjust the reference voltages of these storage chips 100. After the adjusted storage chips 100 perform the read / write operation test again, if the delay of the data still does not meet the requirements, continue to adjust the reference voltages of the storage chips 100 until the data of the adjusted storage chips 100 meets the requirements.

[0109] Among them, in a specific example, after the storage system is powered on and started and before the read / write operation test, the ring oscillators 110 and counters 210 of all storage chips 100 can start working to obtain and save the corresponding count values; after the first read / write operation test, the controller 200 obtains the count values of the storage chips 100 with delays not meeting the expectations. In this way, it is beneficial to shorten the overall test time required for the storage system.

[0110] In another specific example, after the storage system is powered on and started and after the first read / write test, the ring oscillators 110 and counters 210 of the storage chips 100 with delays not meeting the expectations start working, obtain the corresponding count values and send the count values to the controller 200. In this way, only the storage chips 100 with delays not meeting the expectations are counted, which is beneficial to reducing the power consumption of the storage system.

[0111] Such asFigure 9 As shown, in some embodiments, multiple memory chips 100 are stacked on the surface of the controller 200 in sequence, and the memory system has a 3D stacked structure. Figure 12 Another structural schematic diagram of the memory system provided by the embodiments of the present disclosure. In some other embodiments, as Figure 12 shown, the memory system may further include: a carrier substrate 300, the controller 200 is located on the surface of the carrier substrate 300, and multiple memory chips 100 are stacked on the surface of the carrier substrate 300 in sequence, and the memory system forms a 2.5D stacked structure.

[0112] The embodiments of the present disclosure provide a memory system with excellent structural performance, which can adjust the reference voltage for controlling the data transmission speed according to the process corners of the memory chips 100, so that the delay of data transmission of each memory chip 100 meets the expectations and improves the read / write performance of the memory system.

[0113] Those of ordinary skill in the art can understand that the above-described embodiments are specific embodiments for implementing the present disclosure. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the scope defined by the claims.

Claims

1. A storage chip, applied to a storage system, characterized in that Including: The memory chip is configured to count and obtain a count value after power-on startup, where the count value is used to characterize the process corner of the memory chip. There is also an adjustable reference voltage in the memory chip, the magnitude of the reference voltage is adjustable based on the count value, and the memory chip adjusts the delay of data read from the memory cell to output from the data port based on the reference voltage.

2. The storage chip according to claim 1, wherein The memory chip includes: A ring oscillator; A counter, which is connected to the ring oscillator and is configured to count the oscillation period of the ring oscillator within a preset time to obtain the count value.

3. The storage chip according to claim 1 or 2, characterized in that, The memory chip further includes: a scan chain interface, which is configured to obtain the count value based on a command signal issued by a controller and output the count value to the controller.

4. The storage chip according to claim 1, wherein The data has a read path, which includes the process of data being read from the memory cell to output from the data port. The data transmitted on the read path is defined as intermediate data. The memory chip includes: A delay module, which is arranged on the read path, receives the intermediate data at the input end, receives the reference voltage at the control end, and outputs the intermediate data at the output end based on the reference voltage. The length of the delay from receiving the intermediate data to outputting the intermediate data by the delay module corresponds to the magnitude of the reference voltage. An adjustment module, the output end of the adjustment module is connected to the control end of the delay module, receives a preset reference voltage at the input end, receives a control signal at the control end, and outputs the adjustable reference voltage at the output end based on the control signal and the preset reference voltage.

5. The storage chip according to claim 4, characterized in that, The adjustment module includes: An operational amplifier, whose positive input terminal receives the preset reference voltage; An adjustment unit, which is connected to the negative input terminal and the output terminal of the operational amplifier. The output terminal of the adjustment unit outputs the reference voltage, and also adjusts the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the output terminal of the operational amplifier, or adjusts the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the ground terminal based on the control signal.

6. The storage chip according to claim 5, wherein, The adjustment unit includes: N first resistors connected in series between the negative input terminal and the output terminal of the operational amplifier, where N is an integer greater than 1, and at least one second resistor, which is connected between the negative input terminal and the ground terminal; M first switches, which connect the output terminal of the adjustment unit and one end of the corresponding first resistor. The first switches are selectively turned on based on the control signal to adjust the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the output terminal of the operational amplifier, where M is a positive integer less than or equal to N.

7. The storage chip according to claim 5 or 6, characterized in that, The adjustment unit includes: X second resistors connected in series between the negative input terminal and the ground terminal, where X is a positive integer greater than 1; Y second switches, where the second switches are connected to the output end of the adjustment unit and one end of the corresponding second resistor, and the second switches are selectively turned on based on the control signal to adjust the magnitude of the equivalent resistance between the output end of the adjustment unit and the ground end, where Y is a positive integer less than or equal to X.

8. The storage chip according to claim 4, characterized in that, The delay module includes: An even number of inverters connected in sequence, where the power supply terminals of the inverters are connected to the reference voltage, the input terminal of the first inverter receives the intermediate data, and the output terminal of the last inverter outputs the intermediate data.

9. A storage system, characterized in that, Comprising: A plurality of memory chips as described in any one of claims 1-8; A controller configured to obtain the count value of the memory chip and adjust the magnitude of the reference voltage of the memory chip corresponding to the count value based on the count value.

10. The storage system according to claim 9, wherein, The memory chip includes: A ring oscillator; A counter connected to the ring oscillator for counting the oscillation period of the ring oscillator within a preset time to obtain the count value; The controller is connected to the ring oscillator and the counter for controlling the ring oscillator to start oscillating and obtaining the count value.

11. The storage system according to claim 10, wherein The memory chip further includes: a scan chain interface configured to obtain the count value based on a command signal issued by the controller and output the count value to the controller; the controller further includes: An acquisition module configured to issue the command signal to the scan chain interface and receive the count value output by the scan chain interface.

12. The storage system according to claim 9, wherein The controller is configured to, after each power-on startup of the memory system, obtain the count value of each memory chip and adjust the magnitude of the reference voltage of the memory chip corresponding to the count value until the count values of all the memory chips are obtained by polling and the reference voltages of all the memory chips are adjusted.

13. The storage system according to claim 9, wherein The data has a readout path, and the readout path includes the process of the data being read out from the memory cell to being output from the data port. The data transmitted on the readout path is defined as intermediate data; the memory chip includes: A delay module provided on the readout path, having an input terminal receiving the intermediate data, a control terminal receiving the reference voltage, and an output terminal outputting the intermediate data based on the reference voltage. The length of the delay from when the delay module receives the intermediate data to when it outputs the intermediate data corresponds to the magnitude of the reference voltage; An adjustment module, where the output terminal of the adjustment module is connected to the control terminal of the delay module, the input terminal receives a preset reference voltage, the control terminal receives a control signal, and the output terminal outputs an adjustable reference voltage based on the control signal and the preset reference voltage; The controller is connected to the control terminal of the adjustment module, and the controller is used to obtain the count value and generate the control signal based on the count value.

14. The storage system according to claim 13, wherein The adjustment module includes: An operational amplifier, where the positive input terminal of the operational amplifier receives the preset reference voltage; An adjustment unit, the adjustment unit is connected to the negative input terminal and the output terminal of the operational amplifier, the output terminal of the adjustment unit outputs the reference voltage, and further based on the control signal, adjusts the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the output terminal of the operational amplifier, or adjusts the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the ground terminal; The controller is connected to the adjustment unit and provides the control signal to the adjustment unit.

15. The storage system according to claim 14, characterized in that, The adjustment unit includes: N first resistors connected in series between the negative input terminal and the output terminal of the operational amplifier, N is an integer greater than 1, at least one second resistor, the second resistor is connected between the negative input terminal and the ground terminal; M first switches, the first switches connect the output terminal of the adjustment unit and one end of the corresponding first resistor, the first switches are selectively turned on based on the control signal to adjust the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the output terminal of the operational amplifier, M is a positive integer less than or equal to N; The controller is connected to the M first switches.

16. The storage system according to claim 14 or 15, characterized in that, The adjustment unit includes: X second resistors connected in series between the negative input terminal and the ground terminal, X is a positive integer greater than 1; Y second switches, the second switches connect the output terminal of the adjustment unit and one end of the corresponding second resistor, the second switches are selectively turned on based on the control signal to adjust the magnitude of the equivalent resistance between the output terminal of the adjustment unit and the ground terminal, Y is a positive integer less than or equal to X; The controller is connected to the Y second switches.

17. The storage system according to claim 13, wherein The controller is configured to generate the control signal for controlling the reference voltage to be less than the preset reference voltage if the count value represents a fast process corner, and generate the control signal for controlling the reference voltage to be greater than the preset reference voltage if the count value represents a slow process corner.

18. The storage system according to claim 9, wherein A plurality of the memory chips are stacked on the surface of the controller in sequence; or, the memory system further includes: a carrier substrate, the controller is located on the surface of the carrier substrate, and a plurality of the memory chips are stacked on the surface of the carrier substrate in sequence.

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