Method of forming a semiconductor device

Abstract

The method includes forming an etch mask to cover the mandrel, the first spacer, and the second spacer, and the first spacer and the second spacer are in contact with opposite sidewalls of the mandrel. The etch mask is then patterned, and the etch mask includes a first portion covering the first spacer, a second portion covering the second spacer, and a bridge portion connecting the first portion to the second portion. The bridge portion has a first sidewall. A first etch process is performed on the mandrel using the etch mask to define a pattern, and after the first etch process, the mandrel includes a second bridge portion having a second sidewall that is vertically aligned with the corresponding first sidewall. After etching through the mandrel, a second etch process is performed to laterally recess the second bridge portion of the mandrel. Embodiments of the present application also relate to methods of forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of this application relate to methods for forming semiconductor devices. Background Technology

[0002] Integrated circuits include interconnect structures, which can include metal lines and vias to serve as three-dimensional wiring structures. The function of interconnect structures is to correctly connect densely packaged devices together.

[0003] Metal wires and vias are formed in interconnect structures. Metal wires and vias are typically formed using a damascene process. This process may include forming trenches and via openings in a dielectric layer, depositing a barrier layer, and subsequently filling the trenches and via openings with a conductive material. Following a chemical mechanical polishing (CMP) process, the top surfaces of the metal wires are flush with the ground, leaving the metal wires and vias in the trenches and via openings, respectively. Controllably reducing the size of metal wires and vias is a challenging task. Summary of the Invention

[0004] Some embodiments of this application provide a method of forming a semiconductor device, comprising: forming a first etch mask to cover a mandrel, a first spacer, and a second spacer, wherein the first spacer and the second spacer are in contact with opposite sidewalls of the mandrel; patterning the first etch mask, wherein, after patterning, the first etch mask includes: a first portion covering the first spacer; a second portion covering the second spacer; and a bridge portion connecting the first portion to the second portion, wherein the bridge portion includes a first sidewall; performing a first etch process on the mandrel using the first etch mask to define a pattern, wherein, after the first etch process, the mandrel includes a second bridge portion having a second sidewall perpendicularly aligned to the corresponding first sidewall; and performing a second etch process after etching through the mandrel to laterally recess the second bridge portion of the mandrel.

[0005] Other embodiments of this application provide a method of forming a semiconductor device, comprising: forming a mandrel between a first spacer and a second spacer; forming an etch mask including: a first portion overlapping the first spacer; a second portion overlapping the second spacer; and a bridge portion overlapping the mandrel, wherein the mandrel includes a portion located between the first spacer and the second spacer, the portion being exposed by the etch mask; and etching the mandrel using the etch mask to define a pattern for the mandrel, wherein, after etching the mandrel, a remaining portion of the mandrel directly overlapping the bridge portion includes a first sidewall laterally recessed from a second sidewall of the bridge portion, and wherein, when etching the mandrel, both the first sidewall and the second sidewall are exposed to an etching gas for the etching.

[0006] Further embodiments of this application provide a method for forming a semiconductor device, comprising: forming a first spacer and a second spacer parallel to each other, wherein the first spacer and the second spacer are spaced apart; forming a mandrel including a bridging portion located between the first spacer and the second spacer, wherein the bridging portion includes a first opposing sidewall physically contacting the first spacer and the second spacer, and wherein the bridging portion has a first width, the first width being measured in a direction perpendicular to the longitudinal direction of the first spacer; and using an etching gas to laterally recess the first opposing sidewall of the mandrel such that the mandrel has a second width less than the first width, wherein during the lateral recess, the sidewalls of the first spacer and the second spacer are exposed to the etching gas, and wherein after the lateral recess, the first spacer and the second spacer are spaced apart. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1 , Figure 2A , Figure 2B , Figure 3 , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 13C and Figure 14 Cross-sectional views, top views, and perspective views are shown according to some embodiments of an intermediate stage in forming an interconnect structure including metal wires and through-holes.

[0009] Figure 15 A process flow for forming metal wires and through holes according to some embodiments is shown. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0012] A method is provided for forming an interconnect structure comprising metal wires having small end spacing. According to some embodiments, a plurality of mandrels are formed of a first material. Spacers are formed on the sidewalls of the mandrels, the spacers being formed of a second material different from the first material. The mandrels between two spacers are patterned, leaving bridging portions that physically interconnect the two spacers. In patterning the mandrels, the etching gas is selected such that a first etch rate of the mandrels is significantly higher than a second etch rate of the spacers. After the mandrels are fully patterned, the bridging portions are laterally etched to reduce the width of the bridging portions, while the spacing between the two spacers is substantially not reduced. Through the lateral etching process, the end spacing can be reduced without increasing the linewidth of the resulting metal wires. While forming metal wires is used as an example, the embodiments can also be applied to forming other types of components, including but not limited to dielectric components, polysilicon, etc. The embodiments discussed herein are intended to provide examples enabling the making or use of the subject matter of the invention, and modifications that can be made while remaining within the scope of consideration of the different embodiments will be readily understood by those skilled in the art. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. While the method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0013] Figure 1 , Figure 2A , Figure 2B , Figure 3 , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 13C and Figure 14 Cross-sectional views, top views, and perspective views are shown according to some embodiments of an intermediate stage in forming an interconnect structure including metal wires. The corresponding processes are also schematically reflected in, for example... Figure 15 The process flow 200 shown is as follows.

[0014] Figure 1 A cross-sectional view of wafer 10 is shown, wherein the portion shown is a part of the device die within wafer 10. According to some embodiments, wafer 10 is a device wafer that includes active devices such as transistors and / or diodes, and possibly passive devices such as capacitors, inductors, resistors, etc. According to alternative embodiments, wafer 10 may be an interposer wafer without active devices, which may include or may not include passive devices. Wafer 10 may also be a reconstructed wafer including device dies, packages, etc., sealed in a sealant such as a molding compound.

[0015] According to some embodiments, wafer 10 includes a semiconductor substrate 12 and components formed on the top surface of the semiconductor substrate 12. The semiconductor substrate 12 may be formed of crystalline semiconductor materials such as silicon, germanium, or silicon-germanium and / or III-V compound semiconductors such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. The semiconductor substrate 12 may also be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Shallow trench isolation (STI) regions (not shown) may be formed in the semiconductor substrate 12 to isolate active regions in the semiconductor substrate 12. Although not shown, vias may be formed to extend into the semiconductor substrate 12, wherein the vias are used to electrically couple components on opposite sides of the semiconductor substrate 12 to each other. An active device 14, which may include a transistor, is formed on the top surface of the semiconductor substrate 12.

[0016] A dielectric layer 16 is formed over a substrate 12. According to some embodiments, the dielectric layer 16 is formed of or comprises a low-k dielectric material having a dielectric constant (k value) of less than about 3.5 or less than about 3.0. The dielectric layer 16 may be formed of a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to some embodiments, forming the dielectric layer 16 includes depositing a dielectric material containing a pore-forming agent, and then performing a curing process to remove the pore-forming agent, and thus the remaining dielectric layer 16 is porous.

[0017] Conductive components 18 are formed in the dielectric layer 16. According to some embodiments, each conductive component 18 includes a diffusion barrier layer and a copper-containing material located above the diffusion barrier layer. The diffusion barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc., and has the function of preventing copper in the copper-containing material from diffusing into the dielectric layer 16. Optionally, the conductive component 18 may be unbarriered and may be formed of cobalt, tungsten, etc. The conductive component 18 may have a single damascene structure or a double damascene structure.

[0018] According to some embodiments, dielectric layer 16 is an inter-metal dielectric (IMD) layer, and conductive component 18 is a metal line and / or via. According to alternative embodiments, dielectric layer 16 is an inter-layer dielectric (ILD) layer, and conductive component 18 is a contact plug. Additional components may or may not be present between dielectric layer 16 and device 14, and these additional components are indicated as structure 15, which may include dielectric layers such as contact etch stop layers, inter-layer dielectrics, etch stop layers, and IMDs. Structure 15 may also include contact plugs, vias, metal lines, etc.

[0019] A dielectric layer 24 is deposited over the dielectric layer 16 and the conductive component 18. Throughout the description, the dielectric layer 24 can be used as an etch stop layer (ESL) and is therefore referred to as etch stop layer 24 or ESL 24. The etch stop layer 24 may comprise nitrides, silicon-carbon based materials, carbon-doped oxides, or metal-containing dielectrics such as SiCN, SiOCN, SiOC, AlO x AlN, AlCN, or combinations thereof. The etch stop layer 24 can be a single layer formed of a homogeneous material or a composite layer comprising multiple dielectric layers. According to some embodiments, the etch stop layer 24 includes an aluminum nitride (AlN) layer, a SiOC layer above the AlN layer, and an aluminum oxide (AlO) layer above the SiOC layer. x )layer.

[0020] A dielectric layer 26 is deposited over ESL 24. According to some embodiments, dielectric layer 26 is formed of a silicon-containing dielectric material such as silicon oxide. Dielectric layer 26 may also be formed of a low-k dielectric material and is therefore referred to hereinafter as low-k dielectric layer 26. Low-k dielectric layer 26 may be formed using a material selected from the same (or different) group of candidate materials for forming dielectric layer 16. When selected from the same group of candidate materials, the materials of dielectric layers 16 and 26 may be the same as or different from each other.

[0021] According to some embodiments, mask layers 28A, 28B, and 28C are formed over dielectric layer 26. The corresponding processes are shown as follows: Figure 15 Process 202 in the process flow 200 shown. It should be understood that the mask layers 28A, 28B, and 28C shown are examples, and different layer schemes may be used. Mask layers 28A, 28B, and 28C are individually and collectively referred to below as mask layer 28. According to some embodiments, mask layers 28A and 28C are formed of or comprise a metal-free dielectric such as silicon oxide, which may be formed, for example, using tetraethyl orthosilicate (TEOS) as a precursor.

[0022] Mask layer 28B is deposited after mask layer 28A and before mask layer 28C. Mask layer 28B may include metal nitrides, such as titanium nitride, tantalum nitride, tungsten nitride, titanium carbide, tantalum carbide, tungsten carbide, etc. Mask layer 28 may be formed using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), subatmospheric pressure chemical vapor deposition (SACVD), etc. Mask layer 28 may have approximately Peace Treaty The thickness is within the range between these values.

[0023] Next, a core layer 30 is deposited. The corresponding process is shown as follows. Figure 15Process 204 in the process flow 200 shown. The mandrel layer 30 may be formed of or include amorphous silicon, amorphous carbon, tin oxide, silicon oxide, silicon nitride, silicon oxynitride, etc., and other materials may be used. The mandrel layer 30 may be deposited as a blanket layer, which may be a planar layer with a uniform thickness. According to some embodiments, the thickness T1 of the mandrel layer 30 may be in the range of about 10 nm to about 40 nm, and may be in the range of about 25 nm to about 40 nm.

[0024] The next step is to perform an etching process to pattern the blanket-like mandrel layer 30 and form the mandrel 30, such as... Figure 2A and Figure 2B As shown in the figure. The corresponding process is shown as follows. Figure 15 Process 206 in the process flow 200 shown. Figure 2B It shows Figure 2A A top view of the structure shown, and Figure 2A It shows Figure 2B The section 2A-2A is shown. Multiple mandrels 30 with different widths can exist. For example, the two middle mandrels 30 shown have a width W1, which can be equal to or greater than the minimum line width (critical dimension) achievable using forming technology. The leftmost and rightmost mandrels 30 shown can have widths W2 and W3 greater than the minimum line width.

[0025] refer to Figure 3 Deposited spacer layer 32. The corresponding process is shown as follows. Figure 15 Process 208 in the process flow 200 shown. Deposition processes include conformal deposition processes such as CVD, ALD, etc. The material of the spacer layer 32 is chosen to be different from that of the mandrel 30, so that in the subsequent wire-end push-out process ( Figure 8A , Figure 8B and Figure 8C ), mandrel 30 and spacer 32 ( Figures 4A to 4B The etching selectivity should be as high as possible, for example, greater than 5, greater than 10, or even greater. According to some embodiments, the spacer layer 32 is formed of or includes metal oxides or metal nitrides, such as titanium oxide, titanium nitride, etc.

[0026] Next, an anisotropic etching process is performed to etch the spacer layer 32. The corresponding process is shown as follows. Figure 15 Process 210 in the process flow 200 shown. The remaining portion of the spacer layer 32 forms the spacer 32, as shown. Figure 4A and Figure 4B As shown in the image. Figure 4B It shows Figure 4A A top view of the structure shown, and Figure 4AIt shows Figure 4B Section 4A-4A in the middle. Although Figure 4A A cross-sectional view of the spacer 32 with a sharp angle is shown, but the angle may be curved, as indicated by dashed lines. The top edge of the spacer 32 may also be flush with or below the top surface of the mandrel 30, as also indicated by dashed lines. According to some embodiments, the anisotropic etching process is carried out using an etching gas such as Cl2, HBr, CH4, or combinations thereof. A carrier gas such as N2, argon, etc., may also be added to the etching gas. A gap 34 is provided between the spacers 32 formed on adjacent mandrels 30, and the gap 34 may have a gap S1 in the range of about 0.5 W1 and about 1.5 W1.

[0027] Figure 5A and Figure 5B Cross-sectional and top views of the etched mask 38 are shown respectively. The corresponding process is illustrated as follows. Figure 15 Process 212 in the process flow 200 shown. According to some embodiments, the etching mask 38 is three-layered; however, other types, such as single-layer etching masks, double-layer etching masks, four-layer etching masks, etc., may also be used. The etching mask 38 may include a bottom layer (sometimes also called the lower layer) 38BL, an intermediate layer 38ML above the bottom layer 38BL, and a top layer 38TL (sometimes also called the upper layer) above the intermediate layer 38ML.

[0028] According to some embodiments, the bottom layer 38BL and the top layer 38TL are formed of photoresist, and the bottom layer 38BL is cross-linked. The intermediate layer 38ML can be formed of an inorganic material, which can be a nitride (such as silicon nitride), an oxide oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), etc. The intermediate layer 38ML has high etch selectivity relative to the top layer 38TL and the bottom layer 38BL, and therefore the top layer 38TL can be used as an etch mask for patterning the intermediate layer 38ML, and the intermediate layer 38ML can be used as an etch mask for patterning the bottom layer 38BL. The top layer 38TL is patterned to form an opening 39, which is used to define a trench in the low-k dielectric layer 26. The photolithography process in the patterning can be implemented using, for example, extreme ultraviolet (EUV) light with a wavelength of 193 nm.

[0029] like Figure 5A As shown, the middle layer 38ML and the bottom layer 38BL are unpatterned blanket layers. (Reference) Figure 5B The top layer 38TL may include block portions 38TL' and bridge portions 38TL' that interconnect the block portions 38TL'. The width W4 of the bridge portions 38TL' may be equal to or greater than the minimum width allowed by the forming technique. For example, when the exposure wavelength is 193nm, the width W4 may be approximately 23nm.

[0030] Next, the patterned top layer 38TL is used as an etching mask to etch the intermediate layer 38ML, causing the opening 39 to extend into the intermediate layer 38ML. After etching through the intermediate layer 38ML, the bottom layer 38BL is further patterned by etching, during which the intermediate layer 38ML serves as an etching mask. The top layer 38TL is consumed during the patterning of the bottom layer 38BL. The intermediate layer 38ML may be partially or completely consumed during the patterning of the bottom layer 38BL. In the patterned bottom layer 38BL, the opening 39 extends downwards, exposing a portion of the mandrel 30. The resulting structure is... Figure 6A and Figure 6B The text shows that, Figure 6B A top view is shown, and Figure 6A It shows Figure 6B Section 6A-6A in the middle. Figure 6B The structure shown is similar to Figure 5B The structures shown are essentially the same, except that the pattern of the top layer 38TL has been transferred to the bottom layer 38BL. Therefore, the bottom layer 38BL includes the (block-like) portion 38BL'. Figure 6B ) and the bridge portion 38BL' of the interconnecting block portion 38BL'.

[0031] According to some embodiments, such as Figure 6A As shown, the edges 38BL'E of some blocky bottom layer portions 38BL' can be perpendicularly aligned with the interface between the mandrel 30 and their adjacent spacers 32. It should be understood that due to process variations, the edges of the bottom layer 38BL may be slightly offset laterally, for example, slightly overlapping with the mandrel 30 or spacers 32.

[0032] Figure 7A , Figure 7B and Figure 7C The first etching process 40 is shown to etch the exposed portion of the mandrel 30. The corresponding process is shown as follows: Figure 15 Process 214 in the process flow 200 shown. Figure 7C A top view is shown, and Figure 7A and Figure 7B They are shown respectively Figure 7C Sections 7A-7A and 7B-7B are etched. The mandrel 30 ( Figure 6B The exposed portion of the mandrel 30. After etching process 40, the portion of the mandrel 30 protected by the block portion 38BL' and the bridge portion 38BL" is retained, and the remaining portions are respectively referred to as the (mandrel) block portion 30' and the (mandrel) bridge portion 30", such as Figure 7A , Figure 7B and Figure 7C As shown in the diagram, the width of the bridge section 38BL” can be equal to the width W4.

[0033] According to some embodiments, etching process 40 is an anisotropic etching process. According to some embodiments, the DC bias voltage is selected to be sufficiently high, for example, above about 100 volts, to achieve anisotropic etching. The etching gas is also selected to make the etching selectivity ER30 / ER32 (which is the ratio of the etching rate ER30 of the mandrel portion 30' / 30" to the etching rate ER32 of the spacer 32) high. ER30 / ER32 can be as high as possible to achieve precise process control. For example, ER30 / ER32 is above about 5, and can be above about 10, above about 20, above 50, or higher. According to some embodiments, for example, when the mandrel portion 30' / 30" comprises amorphous silicon and the spacer 32 comprises titanium nitride, the etching gas may include Cl2, HBr, N2, etc., and combinations thereof. It should be understood that the etching gas is related to the combination of materials of the mandrel portion 30' / 30" and the spacer 32, and different etching gases may be used when different combinations are used.

[0034] The first etching process 40 ends when the etching passes through the mandrel portion 30' / 30”, which can be determined by detecting the signal of the material of the mask layer 28C. After the first etching process 40, the edge 30'E of the mandrel block portion 30' is perpendicularly aligned with the edge 38BL'E of the block portion 38BL', and the edge 30”E of the mandrel bridge portion 30” is (… Figure 7C Align it perpendicularly with the edge 38BL”E of the bottom layer bridge portion 38BL”.

[0035] Figure 8A , Figure 8B , Figure 8C and Figure 8D The second etching process 42 is shown to make the mandrel portion 30” laterally recessed. The corresponding process is shown as follows. Figure 15 Process 216 in the process flow 200 shown. Figure 8D A 3D view of some layers is shown. Figure 8C A top view is shown, and Figure 8A and Figure 8B They are shown respectively Figure 8CThe cross sections 8A-8A and 8B-8B are shown. The second etching process 42 is performed using a process gas capable of etching the mandrel portion 30' / 30” without etching the spacer 32 and mask layer 28C. Therefore, etching process 42 stops on mask layer 28. For example, the etching gas is selected to make the etching selectivity ER30 / ER32 high. ER30 / ER32 can be as high as possible to achieve precise process control. For example, ER30 / ER32 is higher than about 5, and can be higher than about 10, higher than about 20, higher than about 50, or higher. According to some embodiments, for example, when the mandrel portion 30' / 30” comprises amorphous silicon and the spacer 32 comprises titanium nitride, the etching gas may include Cl2, CH4, NF3, etc., and combinations thereof.

[0036] According to some embodiments, the second etching process 42 is performed using the same process conditions (including the same etching gas and the same parameters, such as the same gas flow rate, the same bias power, the same partial pressure, etc.). Therefore, the etching is anisotropic. Because the etching stops on the mask layer 28C, although the etching is anisotropic, there may be a lateral (isotropic) etching effect. As described above, because the etching gas is selected to make the etching selectivity ER30 / ER32 high, the spacer 32 is not etched or is substantially not laterally etched in the second etching process 42. On the other hand, the mandrel portion 30' / 30 is laterally etched.

[0037] For example, Figure 8A The diagram illustrates a lateral recess of the mandrel portion 30' from its corresponding edge 38BL'E by a lateral recess distance R1. According to some embodiments, the duration of the second etching process 42 is selected such that the lateral recess distance R1 is greater than about 0.5 nm, and can be greater than about 1 nm, or greater than about 2 nm. The lateral recess distance R1 can be in the range of about 1 nm to about 5 nm. On the other hand, also due to high etching selectivity, the spacer 32 is substantially not laterally recessed. For example, the lateral recess distance of the spacer 32 from its corresponding edge 38BL'E can be less than about 1 / 5, less than about 1 / 10, 1 / 20, or 1 / 50 of the recess distance R1, or even smaller, and can be less than about 0.5 nm, less than about 0.2 nm, or less than about 0.1 nm. Therefore, the corresponding edge 32E can be perpendicularly aligned with the corresponding edge 38BL'E, or can extend slightly laterally beyond the corresponding edge 38BL'E.

[0038] According to some embodiments where the second etching process 42 employs the same process conditions as etching process 40, the duration T42 of the second etching process 42 may be equal to or greater than the duration T40 of etching process 40, such that the lateral recess distance R1 is sufficiently high. For example, the ratio T42 / T40 may be greater than 1 or greater than about 1.5, and may be in the range between about 1 and about 2.0.

[0039] Figure 8C The mandrel bridging portion 30” is shown to also have its edge 30”E laterally recessed from the corresponding edge 38BL”E of the bottom layer 38BL, for example, laterally recessed by a distance R1. Therefore, the width W5 of the mandrel portion 30” is reduced to a difference of less than or equal to 2R1 from the width W4’ of the bottom layer portion 38BL”. According to some embodiments, the width W4’ is a minimum width achievable by a corresponding forming technique and can be equal to or slightly less than the width W4’. Figure 7C For example, when an exposure wavelength of 193 nm is used, the width W4' can be in the range of approximately 22 nm to approximately 24 nm, and the width W5 can be reduced to the range of approximately 18 nm to approximately 20 nm. The ratio W5 / W4 can be in the range of approximately 60% to approximately 90%.

[0040] On the other hand, due to the high etching selectivity of ER30 / ER32, the lateral spacing S1 between adjacent spacers 32 (such as...) Figure 8C (marked) and Figure 6B The intervals S1 in the intervals are the same or substantially the same. For example, Figure 8C The interval S1 in the middle is relative to Figure 6B The increase in the spacing S1 (if any) is less than about 0.5 nm, less than about 0.2 nm, or less than about 0.1 nm.

[0041] According to an optional embodiment, the second etching process 42 is implemented using different process conditions than the first etching process 40. Different process conditions may include different etching gases and / or different etching parameters, such as different etching gas flow rates, different bias power, different gas partial pressures, etc. According to some embodiments, the second etching process 42 is implemented using a lower bias power than the first etching process 40. For example, the bias power of the second etching process 42 may be less than about 80% of the bias power used in the first etching process 40, and may be in the range of about 20% to about 80%. Reducing the bias power can reduce the anisotropic effect and increase the isotropic etching effect, resulting in an increased lateral recess of the mandrel portion 30". Other process conditions, such as chamber pressure, etching gas flow rate, etc., may also be adjusted to increase the isotropic effect used in the second etching process 42. For example, the flow rate and / or chamber pressure during the second etching process 42 may be increased to be higher than that of the first etching process 40.

[0042] According to some alternative embodiments, the second etching process 42 includes an anisotropic first portion and a second portion that is more isotropic than the first portion. The second portion may be partially or completely isotropic.

[0043] According to an optional embodiment, the first etching process 40 and the second etching process 42 may employ different process gases. For example, in the first etching process 40, due to anisotropic effects, the corresponding etching selectivity ER30 / ER32 may have a first value V1, which is not very high, for example, in the range of about 2 to about 5. Due to anisotropic etching behavior (such as high bias power) and due to the protection of the bottom layer 38BL on the spacer 32, the spacer 32 is not etched and there is no anisotropic etching of the spacer 32. In the second etching process 42, the process gas is changed such that the corresponding etching selectivity ER30' / ER32' increases to a second value V2, which is higher than the etching selectivity value V1. For example, the ratio V2 / V1 may be greater than about 1.2 and may be in the range of about 1.2 to about 5.

[0044] According to some alternative embodiments, different etching gases are used in etching processes 40 and 42 in combination with adjusted process parameters to achieve transverse etching of the mandrel portion 30' / 30" without transverse etching of the spacer 32.

[0045] According to some alternative embodiments, the second etching process 42 includes a first sub-process and a second sub-process following the first sub-process. The first sub-process may employ the same process conditions as the first etching process 40, and the second sub-process may employ different process conditions than the first etching process 40, wherein the different process conditions are as described above. According to some alternative embodiments, the process conditions may gradually transition from the process conditions of the first etching process 40 to the process conditions of the second etching process 42. For example, the bias power may be gradually reduced.

[0046] The following Figure 9A , Figure 9B and Figures 9C to 13A , Figure 13B and Figure 13C This illustration demonstrates the formation of a dual-dotted structure using a mask formed in a prior process. The illustrated process is a via-first process, wherein the via pattern is formed prior to trench formation. It should be understood that the illustrated process is one of exemplary available processes, and other processes are also within the scope of this application.

[0047] According to some embodiments, the bottom layer 38BL is removed, and the resulting structure is... Figure 9A , Figure 9B and Figure 9C The diagram shows that this structure is used to form, for example... Figure 10A , Figure 10B and Figure 10C The trench shown. According to an optional embodiment, it can be used directly. Figure 8A , Figure 8B and Figure 8C The structure shown is formed (without first removing the bottom layer 38BL) to form as... Figure 10A , Figure 10B and Figure 10C The trench shown in the figure is in which the bottom layer 38BL is consumed during the formation of the trench.

[0048] right Figure 8A , Figure 8B , Figure 8C and Figure 8D The structure shown (or Figure 9A , Figure 9B and Figure 9C The structure shown is subjected to an etching process to etch through mask layers 28C and 28B. Therefore, trenches 46 penetrating the metal hard mask layers 28C and 28B are formed in the hard mask 28, as... Figure 10A , Figure 10B and Figure 10C As shown in the figure. The corresponding process is shown as follows. Figure 15 Process 218 in the process flow 200 shown. Trench 46 defines the pattern of the subsequently formed metal lines. Mask layer 28A is thus exposed. Trench 46 can stop on mask layer 28A, and mask layer 28A serves as an etch stop layer. Mask layers 28C and 28B can be etched using different etch chemicals, and each can be etched using an anisotropic etching process (dry etching process) or an isotropic etching process. For example, when using dry etching, mask layer 28C can be etched using a mixture of NF3 and NH3 gases or a mixture of HF and NH3 gases, or when using wet etching, mask layer 28C can be etched using an HF solution. When using dry etching, mask layer 28B can be etched using gases including BCl3, Cl2, CF4, CHF3, NF3, O2, Ar, etc., or combinations thereof, or when using wet etching, mask layer 28B can be etched using a phosphoric acid solution.

[0049] According to some embodiments, when the etching mask layer 28B is completed, the spacer 32 and the mandrel portions 30' and 30" can be completely consumed. According to an alternative embodiment, after etching through the mask layers 28C and 28B, some mandrel portions 30' and 30" and spacer 32 remain, and these components can be removed, for example, in a separate process by a wet etching process.

[0050] Figure 11A and Figure 11BA cross-sectional view of the formation of the through-hole opening 50 is shown. The corresponding process is shown as follows. Figure 15 Process 220 in the process flow 200 shown. Figure 11A and Figure 11B The following are examples of the methods used to illustrate the relationship between the two methods. Figure 10C The cross-sectional views are obtained from the same cross-sections 10A-10A and 10B-10B. An etching mask 48 is formed and patterned, which can be a single-layer etching mask, a double-layer etching mask, or a triple-layer etching mask. The etching mask 48 is used to etch through the mask layer 28A to define the pattern. Next, the dielectric layer 26 is etched, such that via openings 50 are formed in the dielectric layer 26. According to some embodiments, the etching of the dielectric layer 26 is performed using an etching gas selected from C4F6, C4F8, C5F8, CF4, CHF3, CH2F2, NF3, N2, O2, Ar, He, and combinations thereof. The etching stops at an intermediate level between the top and bottom surfaces of the dielectric layer 26. The via openings 50 can be formed using a single patterning process or a double patterning process. The bottom of the via openings 50 is located at an intermediate level between the top and bottom surfaces of the dielectric layer 26. After the etching process, the etching mask 48 is removed.

[0051] In a subsequent process, dielectric layer 26 is etched to transfer the trench pattern into dielectric layer 26, wherein mask layer 28B is used as an etching mask. The corresponding process is shown as follows. Figure 15 Process 222 in the process flow 200 shown. In the etching process, etching is performed through mask layer 28A to expose the underlying dielectric layer 26. According to some embodiments, mask layer 28C is consumed during the etching of mask layer 28A. Next, the dielectric layer 26 is etched in an anisotropic etching process such that trench 46 extends into the dielectric layer 26. The resulting structure is... Figure 12A and Figure 12B As shown in the image. Simultaneously, the via 50 extends downwards to the bottom of the dielectric layer 26. According to some embodiments, the etching of the dielectric layer 26 is performed using an etching gas selected from C4F6, C4F8, C5F8, CF4, CHF3, CH2F2, NF3, N2, O2, Ar, He, and combinations thereof. According to some embodiments, the trench 46 extends to an intermediate level between the top and bottom surfaces of the dielectric layer 26, and this intermediate level may be located midway between the top and bottom surfaces of the dielectric layer 26. Next, an etching process is performed to etch through the etch stop layer 24 and expose the conductive component 18.

[0052] Figure 13A , Figure 13B and Figure 13C The formation of metal wires and vias is shown. The corresponding process is shown as follows. Figure 15 Process 224 in the process flow 200 shown. Figure 13C A top view is shown, and Figure 13A and Figure 13B They respectively show from Figure 13C The cross-sectional views are obtained from sections 13A-13A and 13B-13B. According to some embodiments, a metallic material such as cobalt, tungsten, or combinations thereof fills the via openings 50 and trenches 46. The metallic material can be deposited using a barrier-free process, wherein no barrier layer is formed, and the metallic material is in physical contact with the conductive component 18 and the dielectric layer 26. According to an alternative embodiment, the conductive material may include a diffusion barrier layer and metallic material situated on the diffusion barrier layer. The barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc. The metallic material may be formed of or include copper, tungsten, etc.

[0053] In subsequent processes, planarization processes such as chemical mechanical polishing (CMP) or mechanical polishing are performed to remove excess portions of the conductive material. According to some embodiments, dielectric layer 26 serves as a CMP stop layer. According to alternative embodiments, mask layers 28A or 28B serve as CMP stop layers, and after the planarization process, mask layers 28B and 28A are etched in subsequent processes. Vias 54 and metal lines 56 are formed, which together form a dual damascene process.

[0054] refer to Figure 13C Metal wires 56A and 56B have an end-to-end spacing (also called wire end spacing) W5. As per reference... Figure 8A , Figure 8B and Figure 8C The lateral recess of the mandrel portion 30” discussed has a very small line-end spacing W5. The line-end spacing W5 can be reduced to less than the minimum line-end spacing achievable through the corresponding photolithography process, and therefore the limit on the line-end spacing can be pushed even lower. On the other hand, the width W6 of the metal line 56 is not reduced because the spacer 32 is not laterally recessed. The sum of the widths W6 and W7 is also not reduced. Therefore, pushing the line-end spacing does not sacrifice the linewidth.

[0055] Figure 14 The diagram illustrates the formation of an upper component, comprising an etch stop layer 60, a dielectric layer 62, a via 64, and a metal line 66. Forming the via 64 and metal line 66 can be similar to forming the via 54 and metal line 56. However, it should be understood that the upper metal line and via can have a larger spacing and width than the via 54 and metal line 56. This relaxes the requirements for line end spacing. Therefore, in the process used to etch the corresponding mandrel bridging portion (for forming the metal line 66), this process corresponds to... Figure 6A , Figure 6B , Figure 7A , Figure 7B and Figure 7CThe process shown does not cause the corresponding mandrel bridging portion to be laterally recessed or substantially not laterally recessed. For example, the lateral recess distance of the mandrel bridging portion is less than about 0.2 nm or 0.1 nm.

[0056] Embodiments of the present invention have several advantageous features. By forming a mandrel and spacers with high etch selectivity, the mandrel bridge portion can be reduced during mandrel etching, thereby reducing the line-end spacing. No etch spacers are used. Therefore, the line-end spacing can be reduced without increasing the linewidth.

[0057] According to some embodiments, the method includes: forming a first etch mask to cover a mandrel, a first spacer, and a second spacer, wherein the first spacer and the second spacer are in contact with opposite sidewalls of the mandrel; patterning the first etch mask, wherein, after patterning, the first etch mask includes: a first portion covering the first spacer; a second portion covering the second spacer; and a bridge portion connecting the first portion to the second portion, wherein the bridge portion includes a first sidewall; performing a first etch process on the mandrel using the first etch mask to define a pattern, wherein, after the first etch process, the mandrel includes a second bridge portion having a second sidewall perpendicularly aligned to the corresponding first sidewall; and performing a second etch process after etching through the mandrel to cause the second bridge portion of the mandrel to be laterally recessed.

[0058] In an embodiment, the first and second spacers are substantially not etched in the second etching process. In an embodiment, the first etching process lasts for a first duration, and the second etching process lasts for a second duration, wherein the second duration is longer than the first duration. In an embodiment, in the second etching process, the mandrel has a first etching rate, the first and second spacers have a second etching rate, and wherein the ratio of the first etching rate to the second etching rate is greater than about 10. In an embodiment, the first and second etching processes are performed using the same process conditions.

[0059] In some embodiments, both the first and second etching processes are anisotropic etching processes. In some embodiments, the first and second etching processes are implemented using different process conditions. In some embodiments, the first and second etching processes are implemented using the same etching gas but different parameters. In some embodiments, the second etching process is more isotropic than the first etching process. In some embodiments, the first etching process is implemented using a first bias power, and the second etching process is implemented using a second bias power lower than the first bias power. In some embodiments, the first and second etching processes are implemented using different etching gases.

[0060] According to some embodiments, the method includes: forming a mandrel between a first spacer and a second spacer; forming an etching mask including: a first portion overlapping the first spacer; a second portion overlapping the second spacer; and a bridge portion overlapping the mandrel, wherein the mandrel includes a portion located between the first spacer and the second spacer, the portion of which is exposed through the etching mask; and etching the mandrel using the etching mask to define a pattern for the mandrel, wherein, after etching the mandrel, the remaining portion of the mandrel directly overlapping the bridge portion includes a first sidewall laterally recessed from a second sidewall of the bridge portion, and wherein, when the mandrel is etched, both the first sidewall and the second sidewall are exposed to an etching gas for etching.

[0061] In one embodiment, the first sidewall is recessed from the corresponding second sidewall by a recess distance greater than about 1 nm. In another embodiment, during the etching of the mandrel, additional sidewalls of the first and second spacers are also exposed to the etching gas, and wherein the first and second spacers have third sidewalls perpendicularly aligned with the corresponding fourth sidewall of the etching mask. In another embodiment, the method further includes: etching a mask layer located beneath the mandrel, the first spacer, and the second spacer, wherein a second portion of the mandrel, the first spacer, and the second spacer collectively serve as a second etching mask; transferring a pattern of the mask layer to a dielectric layer located beneath the mask layer; and filling the dielectric layer with a conductive material to form metal lines. In yet another embodiment, the method further includes: depositing a spacer layer on the top surface and opposite sidewalls of the mandrel; and performing an anisotropic etching process on the spacer layer to form the first and second spacers.

[0062] According to some embodiments, the method includes: forming a first spacer and a second spacer parallel to each other, wherein the first spacer and the second spacer are spaced apart; forming a mandrel including a bridging portion located between the first spacer and the second spacer, wherein the bridging portion includes first opposing sidewalls physically contacting the first spacer and the second spacer, and wherein the bridging portion has a first width measured in a direction perpendicular to the longitudinal direction of the first spacer; and using an etching gas to laterally recess the first opposing sidewalls of the mandrel such that the mandrel has a second width less than the first width, wherein during the lateral recess, the sidewalls of the first spacer and the second spacer are exposed to the etching gas, and wherein after the lateral recess, the first spacer and the second spacer are spaced apart. In an embodiment, forming the bridging portion of the mandrel includes a first anisotropic etching process. In an embodiment, the lateral recess includes a second anisotropic etching process. In an embodiment, the second anisotropic etching process has a duration longer than the first anisotropic etching process.

[0063] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming a semiconductor device, comprising: A first etching mask is formed to cover the mandrel, a first spacer, and a second spacer, wherein the first spacer and the second spacer are in contact with opposite sidewalls of the mandrel; The first etch mask is patterned, wherein, after patterning, the first etch mask comprises: The first part covers the first spacer; The second part covers the second spacer; and A bridge portion that connects the first portion to the second portion, wherein the bridge portion includes a first sidewall; A first etching process is performed on the mandrel using the first etching mask to define a pattern, wherein, after the first etching process, the mandrel includes a second bridge portion having a second sidewall perpendicularly aligned to the corresponding first sidewall; and After etching through the mandrel, a second etching process is performed to make the second bridge portion of the mandrel laterally recessed.

2. The method according to claim 1, wherein, In the second etching process, neither the first spacer nor the second spacer is etched.

3. The method according to claim 1, wherein, The first etching process lasts for a first duration, and the second etching process lasts for a second duration, wherein the second duration is longer than the first duration.

4. The method according to claim 1, wherein, In the second etching process, the mandrel has a first etching rate, the first spacer and the second spacer have a second etching rate, and wherein the ratio of the first etching rate to the second etching rate is greater than 10.

5. The method according to claim 1, wherein, The first etching process and the second etching process are carried out using the same process conditions.

6. The method according to claim 5, wherein, Both the first etching process and the second etching process are anisotropic etching processes.

7. The method according to claim 1, wherein, The first etching process and the second etching process are implemented using different process conditions.

8. The method according to claim 7, wherein, The first etching process and the second etching process are implemented using the same etching gas but different parameters.

9. The method according to claim 8, wherein, The second etching process is more isotropic than the first etching process.

10. The method according to claim 8, wherein, The first etching process is implemented using a first bias power, and the second etching process is implemented using a second bias power lower than the first bias power.

11. The method according to claim 7, wherein, The first etching process and the second etching process are carried out using different etching gases.

12. A method of forming a semiconductor device, comprising: A mandrel is formed between the first spacer and the second spacer; Forming an etching mask includes: The first part overlaps with the first spacer; The second part overlaps with the second spacer; and The bridge portion overlaps with the mandrel, wherein the mandrel includes a portion located between the first spacer and the second spacer, the portion being exposed by an etch mask; and The mandrel is etched using the etching mask to define a pattern for the mandrel, wherein, after etching the mandrel, the remaining portion of the mandrel that directly overlaps with the bridge portion includes a first sidewall that is laterally recessed from the second sidewall of the bridge portion, and wherein, when etching the mandrel, both the first sidewall and the second sidewall are exposed to the etching gas used for the etching.

13. The method according to claim 12, wherein, The first sidewall is recessed from the corresponding second sidewall by a recess distance greater than 1 nm.

14. The method according to claim 12, wherein, During the etching of the mandrel, additional sidewalls of the first and second spacers are also exposed to the etching gas, and wherein the first and second spacers have third sidewalls that are perpendicularly aligned with the corresponding fourth sidewall of the etching mask.

15. The method of claim 12, further comprising: Etching a mask layer located beneath the mandrel, the first spacer, and the second spacer, wherein the second portion of the mandrel, the first spacer, and the second spacer together serve as a second etching mask; The pattern of the mask layer is transferred to the dielectric layer located below the mask layer; and Conductive material is filled into the dielectric layer to form a metal wire.

16. The method of claim 12, further comprising: A spacer layer is deposited on the top surface and opposite sidewalls of the mandrel; as well as An anisotropic etching process is performed on the spacer layer to form the first spacer and the second spacer.

17. A method of forming a semiconductor device, comprising: A first spacer and a second spacer are formed that are parallel to each other, wherein the first spacer and the second spacer are spaced apart from each other; A mandrel is formed including a bridging portion located between the first spacer and the second spacer, wherein the bridging portion includes first opposing sidewalls physically contacting the first spacer and the second spacer, and wherein the bridging portion has a first width measured in a direction perpendicular to the longitudinal direction of the first spacer; and The first opposing sidewalls of the mandrel are laterally recessed using an etching gas, such that the mandrel has a second width less than the first width, wherein, during the lateral recess, the sidewalls of the first spacer and the second spacer are exposed to the etching gas, and wherein, after the lateral recess, the first spacer and the second spacer are spaced apart from each other.

18. The method according to claim 17, wherein, The bridging portion forming the mandrel includes a first anisotropic etching process.

19. The method according to claim 18, wherein, The lateral recess includes a second anisotropic etching process.

20. The method according to claim 19, wherein, The second anisotropic etching process has a longer duration than the first anisotropic etching process.

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