Semiconductor structure fabrication methods and semiconductor structures
By employing the self-alignment function of the mesa structure in Trench MOSFET fabrication, the etching process is simplified, the problem of difficult control of etching selectivity is solved, and the process flow is simplified and the cost is reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI DINGTAI JIANGXIN TECH CO LTD
- Filing Date
- 2023-04-12
- Publication Date
- 2026-07-03
AI Technical Summary
In the current technology for fabricating Trench MOSFETs, it is difficult to accurately control the etching selectivity during the contact hole formation process, requiring multiple etching processes, which results in a cumbersome process and high cost.
By forming spaced mesa structures on the substrate, the self-alignment function of the mesa structures is utilized to simplify the etching process. This includes forming a first oxide layer and a dielectric layer on the substrate, removing part of the substrate to form a gate trench, forming a second oxide layer on the surface of the gate structure and the mesa structure, and defining the location of the contact holes.
It simplifies the process flow, reduces process costs, improves the accuracy of etching selectivity, and reduces process steps.
Smart Images
Figure CN116246961B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology
[0002] With the development of semiconductor technology, trench metal-oxide-semiconductor field-effect transistors (Trench MOSFETs) have emerged. In the later stages of Trench MOSFET processing, an interlayer dielectric layer needs to be deposited on the semiconductor device first, then the interlayer dielectric layer is etched to form contact holes, and finally, metal material is filled into the contact holes to form metal interconnects to enable the device to work.
[0003] Currently, most inventions and practical processes in the industry typically employ self-aligned etching for contact hole formation. Furthermore, most existing technologies usually form the barrier structure after the gate (e.g., polysilicon) in the trench or after the source / drain formation, and then use these barrier structures to etch the interlayer dielectric layer to form the contact hole.
[0004] However, these methods need to consider the etching selectivity of various materials (typically SiO2, SIN, Poly, Silicon, etc.), making it difficult to accurately control the etching selectivity and potentially requiring multiple etching processes. Furthermore, trench MOSFETs require the growth of an oxygen layer as an etching stop layer, followed by removal of the oxygen layer after the barrier structure is formed. This process is quite complex, resulting in higher manufacturing costs. Summary of the Invention
[0005] Therefore, it is necessary to provide a method for fabricating a semiconductor structure and a semiconductor structure to address the problem of cumbersome process flow in the existing technology.
[0006] To achieve the above objectives, this application provides a method for fabricating a semiconductor structure, comprising:
[0007] Provide substrate;
[0008] A plurality of spaced-apart mesa structures are formed on the substrate; each mesa structure includes a first oxide layer located on the upper surface of the substrate and a first dielectric layer located on the sidewall of the first oxide layer; the height of the first dielectric layer in the thickness direction of the semiconductor structure is less than the height of the first oxide layer in the thickness direction.
[0009] Based on the mesa structure, a portion of the substrate is removed to form a gate trench;
[0010] A gate structure is formed within a gate trench located on the substrate;
[0011] A second oxide layer is formed on the surface of the gate structure and the surface of the mesa structure;
[0012] A plurality of contact holes are formed in the second oxide layer, at least one of the contact holes extending to the upper surface of the substrate and at least one of the contact holes extending to the gate structure; the position of each contact hole is defined by each mesa structure.
[0013] The above-described semiconductor structure fabrication method involves forming a plurality of spaced-apart mesa structures on a substrate. Each mesa structure includes a first oxide layer on the upper surface of the substrate and a first dielectric layer on the sidewalls of the first oxide layer. The height of the first dielectric layer in the thickness direction of the semiconductor structure is less than the height of the first oxide layer in the thickness direction. A portion of the substrate is removed based on the self-alignment function of the mesa structure to form a gate trench. A gate structure is formed within the gate trench on the substrate. A second oxide layer is formed on the surface of the gate structure and the surface of the mesa structure. A plurality of contact holes are formed within the second oxide layer. At least one contact hole extends to the upper surface of the substrate, and at least one contact hole extends to the gate structure. Again, utilizing the self-alignment function of the first dielectric layer included in the mesa structure, the position of each contact hole is defined by each mesa structure. Because the fabrication process of the mesa structure is simple, and the mesa structure enables two self-alignments, the process flow can be simplified, and the manufacturing cost reduced.
[0014] In one embodiment, forming a plurality of spaced-apart mesa structures on the substrate includes:
[0015] A first oxide layer is formed on the substrate;
[0016] A plurality of first openings are formed within the first oxide layer; the depth of the first openings in the thickness direction is less than the height of the first oxide layer in the thickness direction.
[0017] A first dielectric layer is formed at the bottom of the first opening, the sidewall of the first opening, and the top of the first oxide layer;
[0018] Remove the first dielectric layer located at the bottom of the first opening and the top of the first oxide layer, so as to retain the first dielectric layer located on the sidewall of the first opening;
[0019] A portion of the first oxide layer located at the bottom of the first opening and a portion of the first dielectric layer located on the sidewall of the first opening are removed to expose the upper surface of the substrate at the bottom of the first opening. The remaining first dielectric layer and the first oxide layer together constitute the mesa structure.
[0020] In one embodiment, removing a portion of the first oxide layer at the bottom of the first opening and a portion of the first dielectric layer on the sidewall of the first opening to expose the upper surface of the substrate at the bottom of the first opening includes:
[0021] A dry etching process is used to remove a portion of the first oxide layer located at the bottom of the first opening and a portion of the first dielectric layer located on the sidewall of the first opening so that the bottom of the first opening exposes the upper surface of the substrate; wherein, in the dry etching process, the etching rate of the first dielectric layer is greater than the etching rate of the first oxide layer.
[0022] In one embodiment, the substrate includes a silicon substrate, and the first oxide layer includes a tetraethyl silicon oxide layer; wherein, while removing a portion of the silicon substrate based on the mesa structure to form a gate trench, the method for fabricating the semiconductor structure further includes:
[0023] A portion of the tetraethyl silicon oxide layer is removed; wherein the remaining tetraethyl silicon oxide layer has a height in the thickness direction that is greater than the height of the first dielectric layer in the thickness direction.
[0024] In one embodiment, forming a gate structure within the gate trench includes:
[0025] A first gate oxide layer is formed at the bottom and sidewalls of the gate trench;
[0026] A gate material layer is formed within the gate trench and on the surface of the mesa structure;
[0027] A portion of the gate material layer is removed so that the upper surface of the remaining gate material layer is lower than the upper surface of the substrate.
[0028] In one embodiment, the gate material layer includes a polysilicon layer, the first oxide layer includes a tetraethyl silicon oxide layer, and the method for fabricating the semiconductor structure further includes removing a portion of the tetraethyl silicon oxide layer while removing a portion of the gate material layer, so that the upper surface of the tetraethyl silicon oxide layer is flush with the upper surface of the first dielectric layer.
[0029] In one embodiment, before forming a second oxide layer on the surface exposed by the gate structure and the surface of the mesa structure, the method for fabricating the semiconductor structure further includes:
[0030] A first ion implantation region and a second ion implantation region are formed adjacent to each of the gate trenches in the substrate, the first ion implantation region being located at the top of the substrate, and the second ion implantation region being located on the side of the first ion implantation region away from the upper surface of the substrate.
[0031] The first ion implantation region and the second ion implantation region are subjected to ion activation treatment using an annealing process.
[0032] In one embodiment, the formation of a plurality of contact holes within the second oxide layer, the contact holes exposing the upper surface of the substrate, includes:
[0033] Multiple contact holes are formed within the second oxide layer, the contact holes penetrating the first ion implantation region to expose the upper surface of the second ion implantation region.
[0034] In one embodiment, after forming a plurality of contact holes in the second oxide layer, the method for fabricating the semiconductor structure further includes:
[0035] A conductive plug is formed inside the contact hole, and the upper surface of the conductive plug is flush with the upper surface of the second oxide layer;
[0036] A metal interconnect layer is formed on the upper surface of the conductive plug and the upper surface of the second oxide layer.
[0037] On the other hand, this application also provides a semiconductor structure, which is fabricated using the semiconductor structure fabrication method described in any of the above embodiments. Because the mesa structure has a simple fabrication process and can achieve two self-alignments, the process flow can be simplified and the manufacturing cost reduced. Attached Figure Description
[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0039] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;
[0040] Figure 2This is a schematic cross-sectional view of the structure obtained in step S101 of the semiconductor structure fabrication method provided in one embodiment;
[0041] Figure 3 This is a flowchart of step S102 in a method for fabricating a semiconductor structure provided in one embodiment;
[0042] Figure 4 This is a schematic cross-sectional view of the structure obtained in step S1021 of the semiconductor structure fabrication method provided in one embodiment.
[0043] Figure 5 This is a schematic cross-sectional view of the structure obtained in step S1022 of the semiconductor structure fabrication method provided in one embodiment;
[0044] Figure 6 This is a schematic cross-sectional view of the structure obtained in step S1023 of the semiconductor structure fabrication method provided in one embodiment.
[0045] Figure 7 This is a schematic cross-sectional view of the structure obtained in step S1024 of the semiconductor structure fabrication method provided in one embodiment.
[0046] Figure 8 This is a schematic cross-sectional view of the structure obtained in step S1025 of the semiconductor structure fabrication method provided in one embodiment.
[0047] Figure 9 This is a schematic cross-sectional view of the structure obtained in step S103 of the semiconductor structure fabrication method provided in one embodiment.
[0048] Figure 10 This is a schematic cross-sectional view of the structure obtained in step S1025 of the semiconductor structure fabrication method provided in another embodiment;
[0049] Figure 11 This is a flowchart of step S104 in the method for fabricating a semiconductor structure provided in one embodiment;
[0050] Figure 12 This is a schematic cross-sectional view of the structure obtained in step S1041 of the semiconductor structure fabrication method provided in one embodiment.
[0051] Figure 13 This is a schematic cross-sectional view of the structure obtained in step S1042 of the semiconductor structure fabrication method provided in one embodiment.
[0052] Figure 14 This is a schematic cross-sectional view of the structure obtained in step S1043 of the semiconductor structure fabrication method provided in one embodiment.
[0053] Figure 15 This is a schematic cross-sectional view of the structure obtained in step S1043 of the semiconductor structure fabrication method provided in another embodiment;
[0054] Figure 16 This is a flowchart of the steps for forming a first ion implantation region and a second ion implantation region in a method for fabricating a semiconductor structure provided in one embodiment.
[0055] Figure 17 This is a schematic cross-sectional view of the structure obtained in step S1601 of the semiconductor structure fabrication method provided in one embodiment.
[0056] Figure 18 This is a schematic cross-sectional view of the structure obtained in step S1602 of the semiconductor structure fabrication method provided in one embodiment.
[0057] Figure 19 This is a schematic cross-sectional view of the structure obtained in step S105 of the semiconductor structure fabrication method provided in one embodiment.
[0058] Figure 20 This is a schematic cross-sectional view of the structure obtained in step S106 of the semiconductor structure fabrication method provided in one embodiment.
[0059] Figure 21 This is a flowchart of the steps in a semiconductor structure fabrication method provided in one embodiment, after step S106, to form a conductive plug and a metal interconnect layer.
[0060] Figure 22 This is a schematic cross-sectional view of the structure obtained in step S107 of the semiconductor structure fabrication method provided in one embodiment.
[0061] Figure 23 This is a schematic cross-sectional view of the structure obtained in step S108 of the semiconductor structure fabrication method provided in one embodiment.
[0062] Explanation of reference numerals in the attached figures: 10-substrate, 101-gate trench, 102-first ion implantation region, 103-second ion implantation region, 20-mesa structure, 201-first oxide layer, 2011-first opening, 202-first dielectric layer, 203-contact hole, 30-gate structure, 301-first gate oxide layer, 302-gate material layer, 303-second gate oxide layer, 40-second oxide layer, 401-first sub-oxide layer, 402-second sub-oxide layer, 50-conductive plug, 60-metal interconnect layer. Detailed Implementation
[0063] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0065] Please see Figure 1 The present invention provides a method for preparing a semiconductor structure, comprising the following steps S101 to S106.
[0066] S101: Provides a substrate;
[0067] S102: A plurality of mesa structures are formed on the substrate at intervals; the mesa structure includes a first oxide layer located on the upper surface of the substrate and a first dielectric layer located on the sidewall of the first oxide layer; the height of the first dielectric layer in the thickness direction of the semiconductor structure is less than the height of the first oxide layer in the thickness direction;
[0068] S103: Removing part of the substrate based on the mesa structure to form a gate trench;
[0069] S104: A gate structure is formed in the gate trench located in the substrate;
[0070] S105: A second oxide layer is formed on the surface of the gate structure and the surface of the mesa structure;
[0071] S106: A plurality of contact holes are formed in the second oxide layer, at least one contact hole extends to the upper surface of the substrate, and at least one contact hole extends to the gate structure; the position of each contact hole is defined by each mesa structure.
[0072] The above-described semiconductor structure fabrication method involves forming multiple spaced-apart mesa structures on a substrate. Each mesa structure includes a first oxide layer on the upper surface of the substrate and a first dielectric layer on the sidewalls of the first oxide layer. The height of the first dielectric layer in the thickness direction of the semiconductor structure is less than the height of the first oxide layer in the thickness direction. A portion of the substrate is removed based on the self-alignment function of the mesa structure to form a gate trench. A gate structure is formed within the gate trench on the substrate, and a second oxide layer is formed on the surface of the gate structure and the surface of the mesa structure. Multiple contact holes are formed within the second oxide layer, with at least one contact hole extending to the upper surface of the substrate and at least one contact hole extending to the gate structure. Again, utilizing the self-alignment function of the first dielectric layer included in the mesa structure, the position of each contact hole is defined by each mesa structure. Because the fabrication process of the mesa structure is simple, and the mesa structure enables two self-alignments, the process flow can be simplified, and the manufacturing cost reduced.
[0073] In step S101, as Figure 2 As shown, a substrate 10 is provided.
[0074] The substrate 10 can be any suitable substrate material known in the art, such as at least one of the following: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), silicon on insulator (SSOI), silicon on insulator (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI), or it can be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, quartz, or glass substrate, etc., which are not limited in this embodiment.
[0075] Optionally, the substrate 10 further includes a base and an epitaxial layer. The epitaxial layer is located on the upper surface of the base. The material of the epitaxial layer can be any suitable epitaxial layer material known in the art, such as one or a combination of gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), and indium gallium nitride (InGaN). This embodiment does not limit the material.
[0076] In step S102, as Figures 3-9As shown, a plurality of mesa structures 20 are formed on the substrate 10 at intervals; the mesa structure 20 includes a first oxide layer 201 located on the upper surface of the substrate 10 and a first dielectric layer 202 located on the sidewall of the first oxide layer 201; the height of the first dielectric layer 202 in the thickness direction of the semiconductor structure is less than the height of the first oxide layer 201 in the thickness direction.
[0077] In one embodiment, such as Figure 3 As shown, the above step S102 includes the following steps S1021 to S1025.
[0078] S1021: A first oxide layer is formed on the substrate;
[0079] S1022: A plurality of first openings are formed within the first oxide layer; the depth of the first openings in the thickness direction is less than the height of the first oxide layer in the thickness direction;
[0080] S1023: A first dielectric layer is formed at the bottom of the first opening, the sidewall of the first opening, and the top of the first oxide layer;
[0081] S1024: Remove the first dielectric layer located at the bottom of the first opening and the top of the first oxide layer, so as to retain the first dielectric layer located on the sidewall of the first opening;
[0082] S1025: Remove a portion of the first oxide layer located at the bottom of the first opening and a portion of the first dielectric layer located on the sidewall of the first opening, so that the bottom of the first opening exposes the upper surface of the substrate, and the remaining first dielectric layer and first oxide layer together constitute a mesa structure.
[0083] In step S1021, as Figure 4 As shown, a first oxide layer 201 can be formed on the substrate 10 using a deposition process.
[0084] The first oxide layer 201 may include a silicon oxide layer, a silicon carbide layer, a tetraethyl silicon oxide layer, etc.
[0085] Optionally, the thickness of the first oxide layer 201 can be 500 angstroms to 1500 angstroms. The thickness of the first oxide layer 201 along the thickness direction can be determined based on the specific material of the first oxide layer 201 to facilitate subsequent processes. For example, when the first oxide layer 201 is a tetraethyl silicon oxide layer, the thickness of the first oxide layer 201 can be 1000 angstroms; when the first oxide layer 201 is a silicon oxide layer, the thickness of the first oxide layer 201 can be 700 angstroms.
[0086] In step S1022, as Figure 5 As shown, a plurality of first openings 2011 are formed in the first oxide layer 201; the depth of the first openings 2011 in the thickness direction is less than the height of the first oxide layer 201 in the thickness direction.
[0087] Wherein, the thickness direction refers to the thickness direction of the semiconductor structure, for example, such as Figure 5 As shown, the thickness direction of the semiconductor structure is Figure 5 The thickness direction is vertical. Of course, in other application scenarios, the thickness direction of the semiconductor structure can be other suitable directions, and this embodiment does not impose any limitations on this.
[0088] Optionally, the depth of the first opening 2011 can be 500 angstroms to 1000 angstroms, and the depth of the first opening 2011 can be determined based on the height of the first oxide layer 201 in the thickness direction (i.e., the thickness of the first oxide layer 201). In actual process fabrication, it is necessary to ensure that the depth of the first opening 2011 in the thickness direction is less than the height of the first oxide layer 201 in the thickness direction, so as to ensure that a certain thickness of the first oxide layer 201 is still retained between the bottom of the first opening 2011 and the substrate 10 to meet the requirements of subsequent processes. For example, the thickness of the first oxide layer 201 can be 700 angstroms, and the depth of the first opening 2011 can be 500 angstroms, so that approximately 200 angstroms of the first oxide layer 201 is retained between the bottom of the first opening 2011 and the substrate 10 to facilitate subsequent processes. Of course, in actual fabrication processes, the depth of the first opening 2011 can also be other suitable depths, which are not limited in this embodiment.
[0089] In step S1023, as Figure 6 As shown, a first dielectric layer 202 is formed at the bottom of the first opening 2011, the sidewall of the first opening 2011, and the top of the first oxide layer 201.
[0090] The first dielectric layer 202 may include a silicon nitride layer, which may be formed by a deposition process. Optionally, the thickness of the first dielectric layer 202 may be 100 angstroms to 400 angstroms, for example, the thickness of the first dielectric layer 202 may be 200 angstroms.
[0091] In step S1024, as Figure 7 As shown, the first dielectric layer 202 located at the bottom of the first opening 2011 and the top of the first oxide layer 201 is removed, so as to retain the first dielectric layer 202 located on the sidewall of the first opening 2011.
[0092] Optionally, a dry etching process can be used to form the first dielectric layer 202 located on the sidewall of the first opening 2011. The dry etching process has the characteristics of anisotropic etching. During the dry etching process, the first dielectric layer 202 located at the bottom of the first opening 2011 and the top of the first oxide layer 201 is thinner along the thickness direction of the semiconductor structure and is therefore quickly removed. By controlling the etching endpoint, the dry etching process stops after removing the first dielectric layer 202 located at the bottom of the first opening 2011 and the top of the first oxide layer 201. As a result, the first dielectric layer 202 located on the sidewall of the first opening 2011 is thicker along the thickness direction and is thus retained.
[0093] In this embodiment, the first dielectric layer 202 located on the sidewall of the first opening 2011 is retained by using a dry etching process, thereby eliminating the need for photolithography alignment and simplifying the process flow.
[0094] In step S1025, as Figure 8 As shown, a portion of the first oxide layer 201 located at the bottom of the first opening 2011 and a portion of the first dielectric layer 202 located on the sidewall of the first opening 2011 are removed so that the bottom of the first opening 2011 exposes the upper surface of the substrate 10. The remaining first dielectric layer 202 and first oxide layer 201 together constitute the mesa structure 20.
[0095] In this embodiment, a first oxide layer 201 is formed on the substrate 10, and a plurality of first openings 2011 are formed within the first oxide layer. A first dielectric layer 202 is formed at the bottom and sidewalls of the first openings 2011 and at the top of the first oxide layer 201. The first dielectric layer located on the sidewalls of the first openings is retained through related processes. Subsequently, by removing a portion of the first oxide layer 201 and a portion of the first dielectric layer 202, a mesa structure 20 that meets the process requirements can be formed.
[0096] In one embodiment, a dry etching process is used to remove a portion of the first oxide layer 201 located at the bottom of the first opening 2011 and a portion of the first dielectric layer 202 located on the sidewall of the first opening 2011 so that the bottom of the first opening 2011 exposes the upper surface of the substrate 10; wherein, in the dry etching process, the etching rate of the first dielectric layer 202 is greater than the etching rate of the first oxide layer 201.
[0097] During the dry etching process, by controlling the etching selectivity ratio of the first dielectric layer 202 to the first oxide layer 201, the etching rate of the first dielectric layer 202 is made greater than that of the first oxide layer 201. This allows for the removal of a portion of the first dielectric layer 202 located on the sidewall of the first opening 2011 while removing the first oxide layer 201 located at the bottom of the first opening 2011, so that the morphology of the formed mesa structure 20 meets the expected process requirements.
[0098] For example, assuming the thickness of the first oxide layer 201 is 700 angstroms and the depth of the first opening 2011 is 500 angstroms, the thickness of the first dielectric layer 202 located on the sidewall of the first opening 2011 along the thickness direction of the semiconductor structure can be approximately 500 angstroms (comparable to the depth of the first opening 2011). In this case, during dry etching, the etching selectivity ratio of the first dielectric layer 202 to the first oxide layer 201 can be set to 1.5:1, and etching can be stopped after removing 200 angstroms of the first oxide layer 201 and 300 angstroms of the first dielectric layer 202. At this point, if... Figure 8 As shown, the remaining first oxide layer 201 has a thickness of 500 angstroms along the thickness direction, and the remaining first dielectric layer 202 has a thickness of 200 angstroms along the thickness direction. The first oxide layer 201 is 100 angstroms thicker than the first dielectric layer 202. Of course, in other suitable application scenarios, based on the specific materials and process requirements of the first dielectric layer 202 and the first oxide layer 201, the etching selectivity ratio of the first dielectric layer 202 to the first oxide layer 201 can also be other etching selectivity ratios, which are not limited in this embodiment.
[0099] In this embodiment, a portion of the first oxide layer 201 and a portion of the first dielectric layer 202 are removed by a dry etching process. During the dry etching process, the etching rate of the first dielectric layer 202 is controlled to be greater than that of the first oxide layer 201 by controlling the etching selectivity ratio, thereby forming a mesa structure 20 that meets the process requirements. Since no multi-step etching is required, the mesa structure 20 can be formed by only one dry etching, thereby further simplifying the process flow.
[0100] In step S103, as Figure 9 As shown, a portion of the substrate 10 is removed based on the mesa structure 20 to form a gate trench 101.
[0101] In the process of forming the gate trench 101 in step S103, a photolithography step can be eliminated, and a portion of the substrate 10 can be removed by self-alignment based on the mesa structure 20 to form the gate trench 101, thereby simplifying the process flow and reducing the manufacturing cost.
[0102] In one embodiment, the substrate 10 includes a silicon substrate 10, and the first oxide layer 201 includes a tetraethyl silicon oxide (TEOS) layer. Simultaneously with performing step S103, the semiconductor structure fabrication method further includes removing a portion of the tetraethyl silicon oxide layer; wherein the remaining tetraethyl silicon oxide layer has a greater height in the thickness direction than the first dielectric layer 202 in the thickness direction.
[0103] When the first oxide layer 201 is a tetraethyl silicon oxide layer, since TEOS itself is easily etched away, a deposition process is used in step S1021 to form a tetraethyl silicon oxide layer. This allows the tetraethyl silicon oxide layer to be made thicker, and the etching selectivity is appropriately considered in the subsequent etching process to avoid the tetraethyl silicon oxide layer being removed too much and failing to meet the process requirements.
[0104] For example, the thickness of the tetraethyl silicon oxide layer can be 1000 angstroms, the deposition thickness of the first dielectric layer 202 can be 200 angstroms, and the depth of the first opening 2011 can be 800 angstroms. After step S1024, the height of the first dielectric layer 202 remaining on the sidewall of the first opening 2011 along the thickness direction is approximately 800 angstroms, which is equivalent to the first opening 2011. Then, in step S1025, the etching selectivity ratio of the tetraethyl silicon oxide layer to the first dielectric layer 202 can be 3:1, such that 200 angstroms of the tetraethyl silicon oxide layer is removed, and 600 angstroms of the first dielectric layer 202 is removed. Thus, after step S1025, as... Figure 10 As shown, the height of the tetraethyl silicon oxide layer along the thickness direction is approximately 800 angstroms, and the remaining first dielectric layer 202 has a height of approximately 200 angstroms along the thickness direction. At this time, while performing step S103, the etching selectivity ratio of the silicon substrate 10 to the tetraethyl silicon oxide layer can be set to 3.3:1, resulting in the silicon substrate 10 being etched away by approximately 10,000 angstroms (i.e., the depth of each gate trench 101 formed within the substrate 10 along the thickness direction is approximately 10,000 angstroms), while the tetraethyl silicon oxide layer is etched away by approximately 300 angstroms, thereby forming a layer as shown in the diagram. Figure 9 The shape shown.
[0105] In this embodiment, since the tetraethyl silicon oxide layer is higher than the height of the first dielectric layer 202, no gaps or trenches will be formed between the tetraethyl silicon oxide layer and the first dielectric layer 202, thereby enabling the fabrication of a mesa structure 20 that meets the process requirements, so as to facilitate the subsequent processes.
[0106] In step S104, as Figures 11-15 As shown, a gate structure 30 is formed in the gate trench 101 located in the substrate 10.
[0107] In one embodiment, such as Figure 11As shown, the above step S104 includes steps S1041-S1043.
[0108] S1041: A first gate oxide layer is formed at the bottom and sidewalls of the gate trench;
[0109] S1042: A gate material layer is formed in the gate trench and on the surface of the mesa structure;
[0110] S1043: Remove part of the gate material layer so that the upper surface of the remaining gate material layer is lower than the upper surface of the substrate.
[0111] In step S1041, as Figure 12 As shown, a first gate oxide layer 301 is formed at the bottom and sidewalls of the gate trench 101.
[0112] Optionally, the first gate oxide layer 301 can be formed using a furnace tube process. During the furnace tube process, since the mesa structure 20 is mainly composed of the first oxide layer 201 and the first dielectric layer 202, the surface of the mesa structure 20 will not be oxidized. Thus, the furnace tube process can be used to form the first gate oxide layer 301 at the bottom and sidewall of the gate trench 101, thereby avoiding the formation of the first gate oxide layer 301 on the surface of the mesa structure 20.
[0113] In step S1042, as Figure 13 As shown, a gate material layer 302 can be formed within the gate trench 101 and on the surface of the mesa structure 20 using a deposition process. During the deposition process, as... Figure 13 As shown, since the height of the first dielectric layer 202 in the thickness direction is less than the height of the first oxide layer 201 in the thickness direction in the mesa structure 20 formed in step S102, no gap trench will be generated between the first dielectric layer 202 and the first oxide layer 201. Therefore, when the gate material layer 302 is formed in step S1042, the situation where the gate material layer 302 cannot be removed due to entering the gap can be avoided.
[0114] The gate material layer 302 can be made of any suitable gate material known in the art, such as polysilicon or other suitable metal gate materials, and this embodiment does not impose any limitations on it. Furthermore, the polysilicon can be P-type or N-type in terms of conductivity, and this embodiment does not impose any limitations on it.
[0115] In step S1043, as Figure 14 As shown, a portion of the gate material layer 302 is removed so that the upper surface of the remaining gate material layer 302 is lower than the upper surface of the substrate 10.
[0116] In this embodiment, during the formation of the gate structure 30, a first gate oxide layer 301 is formed at the bottom and sidewalls of the gate trench 101, and a gate material layer 302 is formed within the gate trench 101 and on the surface of the mesa structure 20. Since the height of the first dielectric layer 202 in the thickness direction in the mesa structure 20 is less than the height of the first oxide layer 201 in the thickness direction, no gap trench is generated between the first dielectric layer 202 and the first oxide layer 201. This avoids the situation where the gate material layer 302 cannot be removed due to entering a gap. Subsequently, the gate material layer 302 is partially removed, and the upper surface of the remaining gate material layer 302 is lower than the upper surface of the substrate 10, which ensures good reliability performance of the finally formed chip.
[0117] In one embodiment, the gate material layer 302 includes a polysilicon layer, and the first oxide layer 201 includes a tetraethyl silicon oxide layer. Simultaneously with the above step S1043, as... Figure 15 As shown, the method for fabricating the semiconductor structure further includes removing a portion of the tetraethyl silicon oxide layer so that the upper surface of the tetraethyl silicon oxide layer is flush with the upper surface of the first dielectric layer 202.
[0118] For example, such as Figure 13 As shown, assuming that in step S1042, the height of the tetraethyl silicon oxide layer along the thickness direction is 500 angstroms, and the height of the first dielectric layer 202 along the thickness direction is 200 angstroms, and the upper surface of the tetraethyl silicon oxide layer is 100 angstroms higher than the upper surface of the first dielectric layer 202, then when etching away the polysilicon layer, the etching selectivity ratio of the polysilicon layer to the tetraethyl silicon oxide layer can be set to 8:1 to remove 100 angstroms of the tetraethyl silicon oxide layer, thereby forming as shown in the figure. Figure 15 The diagram shows a morphology where the upper surface of the tetraethyl silicon oxide layer is flush with the upper surface of the first dielectric layer 202. This is because tetraethyl silicon oxide is easily etched away during the etching process, and therefore, by adjusting the etching selectivity, the upper surface of the tetraethyl silicon oxide layer can be made flush with the upper surface of the first dielectric layer 202. Of course, in other suitable applications, through appropriate process design, it is possible to make the height of the first oxide layer 201 along the thickness direction greater than the height of the first dielectric layer 202 along the thickness direction, or to make the upper surface of the first oxide layer 201 and the upper surface of the first dielectric layer 202 flush. This embodiment does not impose any limitations on this.
[0119] In one embodiment, such as Figure 16 As shown, prior to step S105 above, the method for fabricating the semiconductor structure further includes:
[0120] S1601: A first ion implantation region and a second ion implantation region are formed adjacent to each other in the substrate between the gate trenches. The first ion implantation region is located at the top of the substrate, and the second ion implantation region is located on the side of the first ion implantation region away from the upper surface of the substrate. Figure 17 As shown.
[0121] S1602: The first and second ion implantation regions are activated by annealing, such as... Figure 18 As shown.
[0122] In addition, such as Figure 18 As shown, during the annealing process, a small amount of oxygen is introduced, so a thin second gate oxide layer 303 can be formed on the exposed surface of the gate material layer 302.
[0123] In step S105, as Figure 19 As shown, a second oxide layer 40 is formed on the surface of the gate structure 30 and the surface of the mesa structure 20.
[0124] The material of the second oxide layer 40 may include one or more of silicon oxide, tetraethyl silicon oxide, and borophospho-silicate glass (BPSG).
[0125] Optional, such as Figure 19 As shown, the second oxide layer 40 includes a first sub-oxide layer 401 located on the surface of the gate structure 30 and the surface of the mesa structure 20, and a second sub-oxide layer 402 located on the upper surface of the first sub-oxide layer 401. For example, the first sub-oxide layer 401 may include a tetraethyl silicon oxide layer, and the second sub-oxide layer 402 may include a borosilicate glass layer, wherein the tetraethyl silicon oxide layer may be fabricated using a furnace tube process, and the borosilicate glass layer may be fabricated using a chemical vapor deposition (CVD) process.
[0126] Furthermore, the materials of the first sub-oxide layer 401 and the first oxide layer 201 can be the same. For example, both the first sub-oxide layer 401 and the first oxide layer 201 can be tetraethyl silicon oxide layers.
[0127] In step S106, as Figure 20 As shown, a plurality of contact holes 203 are formed in the second oxide layer 40, at least one contact hole 203 extends to the upper surface of the substrate 10, and at least one contact hole 203 extends to the gate structure 30; the position of each contact hole 203 is defined by each mesa structure 20.
[0128] Multiple contact holes 203 can be formed by a combination of photolithography and etching. A patterned photoresist layer can be formed on the surface of the second oxide layer 40 first. The photolithographic pattern of the patterned photoresist layer defines the shape and position of each contact hole 203. Then, the second oxide layer 40 is etched based on the patterned photoresist layer to form multiple contact holes 203.
[0129] Since both the first oxide layer 201 and the second oxide layer 40 are made of oxides, when etching to form the contact hole 203, an etching process capable of removing oxides can be used to remove both the first oxide layer 201 and the second oxide layer 40 simultaneously, thus forming a contact hole 203. Figure 20 The morphology shown. At the same time, as... Figure 20 As shown, during the formation of the contact hole 203, the first dielectric layer 202 included in the mesa structure 20 can correct the etching direction. When the contact hole 203 deviates due to photolithography misalignment or etching angle misalignment, the presence of the first dielectric layer 202 can promptly correct the etching direction, thereby achieving self-alignment again. Furthermore, the contact hole 203 formed based on self-alignment using the first dielectric layer 202 ensures that the distance between it and the gate trench 101 is equal. For example, as... Figure 20 As shown in box A, the contact hole 203 in box A already has a certain degree of deviation when forming the photolithographic pattern. Without the self-alignment function of the first dielectric layer 202, the aperture of the contact hole 203 in box A would be enlarged, and the distance between the contact hole 203 in box A and the gate trenches 101 on both sides would be difficult to keep consistent. There is even a risk that the contact hole 203 in box A could directly connect to the gate structure 30. However, due to the presence of the first dielectric layer 202, the etching direction of the contact hole 203 in box A is adjusted in a timely manner through the self-alignment function of the first dielectric layer 202. This ensures that the position of the contact hole 203 meets the process requirements, and the distance between the contact hole 203 and the gate trenches 101 on both sides also meets the process requirements, thereby ensuring that the morphology of the final semiconductor structure meets the process requirements.
[0130] In this embodiment, the mesa structure 20 can achieve two self-alignments. Specifically, in step S103, the entire mesa structure 20 can achieve one self-alignment to form the gate trench 101. In step S106, the first dielectric layer 202 included in the mesa structure 20 can achieve another self-alignment to correct the etching direction of the contact holes 203, thereby ensuring that each contact hole 203 meets the process requirements. Furthermore, since the mesa structure 20 is fabricated before the gate structure 30 is formed, its etching process involves fewer material types (only the first dielectric layer 202 and the first oxide layer 201), making the fabrication process simpler compared to existing technologies. Therefore, using the mesa structure 20 can simplify the process flow and reduce manufacturing costs.
[0131] Optional, such as Figure 20 As shown, during the etching process to form the contact hole 203, after the contact hole 203 exposes the surface of the substrate 10, the patterned photoresist layer can be removed first, and then an etching process capable of removing substrate material can be used to etch the substrate 10, thereby removing a portion of the substrate 10 to meet process requirements; alternatively, the substrate 10 can be etched directly based on the patterned photoresist layer using an etching process capable of removing substrate material, and after removing a portion of the substrate 10, the patterned photoresist can be removed. The semiconductor structure morphology formed by the latter process step is better than that formed by the former process step. Of course, the corresponding process steps can be arbitrarily selected according to different process requirements, and this embodiment does not impose any limitations.
[0132] In one embodiment, such as Figure 20 As shown, step S106 includes: forming a plurality of contact holes 203 in the second oxide layer 40, the contact holes 203 penetrating the first ion implantation region 102 to expose the upper surface of the second ion implantation region 103.
[0133] In one embodiment, such as Figure 21 As shown, after step S106, the method for fabricating the semiconductor structure further includes:
[0134] S107: A conductive plug is formed in the contact hole, and the upper surface of the conductive plug is flush with the upper surface of the second oxide layer.
[0135] S108: A metal interconnect layer is formed on the upper surface of the conductive plug and the upper surface of the second oxide layer.
[0136] In step S107, as Figure 22 As shown, a conductive plug 50 is formed in the contact hole 203, and the upper surface of the conductive plug 50 is flush with the upper surface of the second oxide layer 40.
[0137] Optionally, the conductive plug 50 may include a conductive barrier layer located at the bottom and sidewalls of the contact hole 203, and a metal filler layer filling the contact hole 203. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitrides such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof. The metal filler layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other metals.
[0138] In step S108, as Figure 23 As shown, a metal interconnect layer 60 is formed on the upper surface of the conductive plug 50 and the upper surface of the second oxide layer 40.
[0139] The material of the metal interconnect layer 60 may include metals such as copper, gold, titanium, silver, and aluminum, or it may include a multilayer metal composed of the above-mentioned metals, or a metal alloy, etc. This embodiment does not impose any limitations.
[0140] In this embodiment, the semiconductor structure can be powered by the formed conductive plug 50 and the metal interconnect layer 60, so that the prepared semiconductor structure can meet the process requirements.
[0141] Optionally, after step S108, a step of forming a passivation layer on the upper surface of the metal interconnect layer 60 by a deposition process may also be included.
[0142] This application also provides a semiconductor structure, which is fabricated using the semiconductor structure fabrication method described in any of the above embodiments. Because the mesa structure has a simple fabrication process and enables two self-alignments, the process flow can be simplified and manufacturing costs reduced.
[0143] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0144] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method of fabricating a semiconductor structure, characterized by, include: Provide substrate; A plurality of spaced-apart mesa structures are formed on the substrate; the mesa structure includes a first oxide layer located on the upper surface of the substrate and a first dielectric layer located on the sidewall of the first oxide layer; The height of the first dielectric layer in the thickness direction of the semiconductor structure is less than the height of the first oxide layer in the thickness direction. Based on the mesa structure, a portion of the substrate is removed to form a gate trench; A gate structure is formed within a gate trench located on the substrate; A second oxide layer is formed on the surface of the gate structure and the surface of the mesa structure; A plurality of contact holes are formed in the second oxide layer, at least one of the contact holes extending to the upper surface of the substrate and at least one of the contact holes extending to the gate structure; the position of each contact hole is defined by each mesa structure, wherein the mesa structure adjusts the etching direction of the contact hole based on the self-alignment function of the first dielectric layer, so as to at least make the position of the contact hole meet the process requirements.
2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The formation of a plurality of spaced-apart mesa structures on the substrate includes: A first oxide layer is formed on the substrate; A plurality of first openings are formed within the first oxide layer; the depth of the first openings in the thickness direction is less than the height of the first oxide layer in the thickness direction. A first dielectric layer is formed at the bottom of the first opening, the sidewall of the first opening, and the top of the first oxide layer; Remove the first dielectric layer located at the bottom of the first opening and the top of the first oxide layer, so as to retain the first dielectric layer located on the sidewall of the first opening; A portion of the first oxide layer located at the bottom of the first opening and a portion of the first dielectric layer located on the sidewall of the first opening are removed to expose the upper surface of the substrate at the bottom of the first opening. The remaining first dielectric layer and the first oxide layer together constitute the mesa structure.
3. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: The step of removing a portion of the first oxide layer located at the bottom of the first opening and a portion of the first dielectric layer located on the sidewall of the first opening, so that the bottom of the first opening exposes the upper surface of the substrate, includes: A dry etching process is used to remove a portion of the first oxide layer located at the bottom of the first opening and a portion of the first dielectric layer located on the sidewall of the first opening so that the bottom of the first opening exposes the upper surface of the substrate; wherein, in the dry etching process, the etching rate of the first dielectric layer is greater than the etching rate of the first oxide layer.
4. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: The substrate includes a silicon substrate, and the first oxide layer includes a tetraethyl silicon oxide layer; wherein, while removing a portion of the silicon substrate based on the mesa structure to form a gate trench, the method for fabricating the semiconductor structure further includes: A portion of the tetraethyl silicon oxide layer is removed; wherein the remaining tetraethyl silicon oxide layer has a height in the thickness direction that is greater than the height of the first dielectric layer in the thickness direction.
5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a gate structure within the gate trench includes: A first gate oxide layer is formed at the bottom and sidewalls of the gate trench; A gate material layer is formed within the gate trench and on the surface of the mesa structure; A portion of the gate material layer is removed so that the upper surface of the remaining gate material layer is lower than the upper surface of the substrate.
6. The method of claim 5, wherein the semiconductor structure is prepared by a method comprising: The gate material layer includes a polysilicon layer, and the first oxide layer includes a tetraethyl silicon oxide layer. While removing a portion of the gate material layer, the method for fabricating the semiconductor structure also includes removing a portion of the tetraethyl silicon oxide layer so that the upper surface of the tetraethyl silicon oxide layer is flush with the upper surface of the first dielectric layer.
7. The method of claim 5, wherein the step of forming the semiconductor structure is performed by a method comprising: Before forming a second oxide layer on the surface exposed by the gate structure and the surface of the mesa structure, the method for fabricating the semiconductor structure further includes: A first ion implantation region and a second ion implantation region are formed adjacent to each of the gate trenches in the substrate, the first ion implantation region being located at the top of the substrate, and the second ion implantation region being located on the side of the first ion implantation region away from the upper surface of the substrate. The first ion implantation region and the second ion implantation region are subjected to ion activation treatment using an annealing process.
8. The method of claim 7, wherein the semiconductor structure is prepared by a method comprising: The method of forming a plurality of contact holes within the second oxide layer, wherein the contact holes expose the upper surface of the substrate, includes: Multiple contact holes are formed within the second oxide layer, the contact holes penetrating the first ion implantation region to expose the upper surface of the second ion implantation region.
9. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: After forming a plurality of contact holes in the second oxide layer, the method for fabricating the semiconductor structure further includes: A conductive plug is formed inside the contact hole, and the upper surface of the conductive plug is flush with the upper surface of the second oxide layer; A metal interconnect layer is formed on the upper surface of the conductive plug and the upper surface of the second oxide layer.
10. A semiconductor structure, characterized by The semiconductor structure is prepared by the semiconductor structure preparation method described in any one of claims 1-9.