Method for preparing integrated power chip and chip

Abstract

The present application belongs to the field of semiconductor technology and provides a method for preparing an integrated power chip and a chip, wherein an N-type epitaxial layer is grown on the front surface of a semiconductor substrate, and then a medium- and low-voltage device is formed in a first preset area on the surface of the N-type epitaxial layer through an ion implantation process, and then a second P-type isolation layer is formed in a second preset area of the N-type epitaxial layer. The second P-type isolation layer is then divided into a first switch isolation area and a second switch isolation area by forming a voltage channel layer, an N-type connection area is formed on the voltage channel layer, and a first source doping layer, a second source doping layer and a plurality of alternating P-type doping structures and N-type channel structures are formed on both sides of the N-type connection area, and a gate layer is formed on the P-type doping structure, thereby preparing high-voltage devices and medium- and low-voltage devices in the same process flow, and the topological structures of various applications can be completed through appropriate connection, thereby achieving the purpose of taking into account both low cost and expansion of device application scenarios.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing an integrated power chip and the chip. Background Art

[0002] The breakdown voltage (BV) of power transistors is a crucial parameter. To increase BV while saving chip area, power transistors have transitioned from a planar to a vertical structure. The pursuit of high breakdown voltage, high current density, and a smaller device area remains the future development direction for power transistors.

[0003] However, with the demand for improved energy conversion efficiency, integrated power circuits have become a trend. In the highly competitive power device market, existing power transistors have the problem of being unable to simultaneously take into account low cost and functional expansion for multiple application scenarios. Summary of the Invention

[0004] In order to solve the above technical problems, the embodiments of the present application aim to provide a method for preparing an integrated power chip and a chip that can simultaneously take into account low cost and functional expansion of multiple application scenarios.

[0005] A first aspect of an embodiment of the present application provides a method for preparing an integrated power chip, the method comprising:

[0006] epitaxially growing an N-type epitaxial layer on the front side of the semiconductor substrate;

[0007] Implanting P-type dopant ions into a first predetermined area on the surface of the N-type epitaxial layer to form a first P-type isolation layer, and forming a P-type ion implantation region on the first P-type isolation layer; wherein the first P-type isolation layer is concave, and the P-type ion implantation region is located in the groove of the first P-type isolation layer;

[0008] forming an N-type drift region in a first device region on the P-type ion implantation region, and forming a P-type well region on the N-type drift region;

[0009] forming a first source doping region and a first drain doping region in a second device region on the P-type ion implantation region, respectively, forming a second drain doping region on the P-type well region, and forming a second source doping region on the N-type drift region; wherein the second source doping region and the P-type well region do not contact each other;

[0010] forming a dielectric layer on the P-type ion implantation region;

[0011] forming a second P-type isolation layer in a second predetermined area on the surface of the N-type epitaxial layer;

[0012] Performing N-type doping on a designated area of the second P-type isolation layer to form a voltage channel layer, so as to divide the second P-type isolation layer into a first switch isolation area and a second switch isolation area;

[0013] An N-type connection region is formed on the voltage channel layer, and a first source doping layer, a second source doping layer, and a plurality of alternating P-type doping structures and N-type channel structures are formed on both sides of the N-type connection region; wherein the first source doping layer is located on the first switch isolation region and is connected to the N-type connection region through the N-type channel structure, and the second source doping layer is located on the second switch isolation region and is connected to the N-type connection region through the N-type channel structure;

[0014] forming a first gate layer and a second gate layer on the dielectric layer, forming a third gate layer on the P-type doped structure, and forming a drain metal layer on the back side of the semiconductor substrate; wherein the third gate layer is insulated from the N-type channel structure, the first gate layer is located above the first source doped region and the first drain doped region, and the second gate layer is located above the P-type well region;

[0015] A shallow trench isolation structure is formed between the first preset area and the second preset area.

[0016] In one embodiment, the forming of an N-type connection region on the voltage channel layer, and forming a first source doping layer, a second source doping layer, and a plurality of alternating P-type doping structures and N-type channel structures on both sides of the N-type connection region include:

[0017] epitaxially growing an N-type channel layer on the voltage channel layer and the second P-type isolation layer;

[0018] Etching a first predetermined etched area on the N-type epitaxial layer to form a plurality of first etched deep grooves and a plurality of first N-type channel structures, and etching a second predetermined etched area on the N-type epitaxial layer to form a plurality of second etched deep grooves and a plurality of second N-type channel structures, so as to form the N-type connection region, the first source doping layer, and the second source doping layer on the voltage channel layer; wherein the first source doping layer and the N-type connection region are located on both sides of the first N-type channel structure, and the second source doping layer and the N-type connection region are located on both sides of the second N-type channel structure;

[0019] A first P-type doped structure contacting the first switch isolation region is formed in the etched grooves between the first N-type channel structures, and a second P-type doped structure contacting the second switch isolation region is formed in the etched grooves between the second N-type channel structures.

[0020] In one embodiment, the first preset etching region is located above the first P-type doped structure, the second preset etching region is located above the second P-type doped structure, and the N-type connection region is located between the first preset etching region and the second preset etching region.

[0021] In one embodiment, forming a first P-type doped structure in contact with the first switch isolation region in the etched groove between the first N-type channel structures includes:

[0022] A P-type semiconductor material is deposited between adjacent first N-type channel structures to form a first P-type doped structure; wherein the first source doped layer and the N-type connection region are located on both sides of the first P-type doped structure and are in contact with the first P-type doped structure.

[0023] In one embodiment, forming a second P-type doping structure in contact with the second switch isolation region in the etched groove between the second N-type channel structures includes:

[0024] A P-type semiconductor material is deposited between adjacent second N-type channel structures to form a second P-type doped structure; wherein the second source doped layer and the N-type connection region are located on both sides of the second P-type doped structure and are in contact with the second P-type doped structure.

[0025] In one embodiment, the forming of an N-type connection region on the voltage channel layer, and forming a first source doping layer, a second source doping layer, and a plurality of alternating P-type doping structures and N-type channel structures on both sides of the N-type connection region include:

[0026] epitaxially growing an N-type semiconductor material on the voltage channel layer and the second P-type isolation layer under the cover of the first photomask to form an N-type connection region, a first N-type channel structure, a second N-type channel structure, a first source doping layer, and a second source doping layer; wherein the first source doping layer and the N-type connection region are located on both sides of the first N-type channel structure, and the second source doping layer and the N-type connection region are located on both sides of the second N-type channel structure;

[0027] Under the cover of the second mask, a first P-type doping structure contacting the first switch isolation region is formed between adjacent first N-type channel structures, and a second P-type doping structure contacting the second switch isolation region is formed between adjacent second N-type channel structures.

[0028] In one embodiment, the preparation method further comprises:

[0029] N-type semiconductor material and P-type semiconductor material are alternately epitaxially grown using a first mask and a second mask to increase the thickness of the N-type connection area, the first N-type channel structure, the second N-type channel structure, the first source doping layer, the second source doping layer, the first P-type doping structure, and the second P-type doping structure.

[0030] In one embodiment, the doping concentration of the P-type ion implantation region is greater than the doping concentration of the first P-type isolation layer.

[0031] In one embodiment, the P-type well region and the second source doping region are respectively located on two sides of the N-type drift region.

[0032] A second aspect of an embodiment of the present application further provides a chip, wherein the chip integrates an integrated power chip prepared by any of the preparation methods described above.

[0033] The beneficial effects of the embodiments of the present application compared with the prior art are: by growing an N-type epitaxial layer on the front side of the semiconductor substrate, and then forming medium and low voltage devices through an ion implantation process in a first preset area on the surface of the N-type epitaxial layer, and then forming a second P-type isolation layer in a second preset area of the N-type epitaxial layer, and then dividing the second P-type isolation layer into a first switch isolation area and a second switch isolation area by forming a voltage channel layer, forming an N-type connection area on the voltage channel layer, and forming a first source doping layer, a second source doping layer and a plurality of alternating P-type doping structures and N-type channel structures on both sides of the N-type connection area, and forming a gate layer on the P-type doping structure, thereby preparing high voltage devices and medium and low voltage devices in the same process flow, and completing the topological structures of various applications through appropriate connection, thereby achieving the purpose of taking into account both low cost and expansion of device application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a schematic flow chart of a method for preparing an integrated power chip provided in one embodiment of the present application;

[0035] Figure 2 1 is a schematic diagram of forming a first P-type isolation layer 900 and a P-type ion implantation region 910 according to an embodiment of the present application;

[0036] Figure 3 1 is a schematic diagram of forming an N-type drift region 920 and a P-type well region 930 according to an embodiment of the present application;

[0037] Figure 4 Schematic diagram of forming a first source doping region 941 , a first drain doping region 951 , a second drain doping region 942 , and a second source doping region 952 according to one embodiment of the present application;

[0038] Figure 5 is a schematic diagram of forming a dielectric layer provided by one embodiment of the present application;

[0039] Figure 6 1 is a schematic diagram of forming a second P-type isolation layer 300 provided in one embodiment of the present application;

[0040] Figure 7 2 is a schematic diagram of forming a voltage channel layer 210 according to an embodiment of the present application;

[0041] Figure 8 is a schematic diagram of forming an N-type connection region 830 provided in one embodiment of the present application;

[0042] Figure 9 This is a schematic diagram of an epitaxial growth process provided by one embodiment of the present application on a voltage channel layer 210 and a P-type switch isolation layer;

[0043] Figure 10 3 is a schematic diagram of forming a first P-type doping structure 312 and a second P-type doping structure 322 according to an embodiment of the present application;

[0044] Figure 11 This is a working diagram of an integrated power chip provided in one embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0046] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0047] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0048] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means one or more, unless otherwise specifically defined.

[0049] References to "one embodiment," "some embodiments," or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in some other embodiments," "in some other embodiments," "in a specific embodiment," and "in a specific application" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner.

[0050] The battery voltage (BV) of power transistors is a crucial parameter. To increase BV while saving chip area, power transistors have transitioned from a planar to a vertical structure. Since the invention of the fin transistor (FINFET), it has successfully demonstrated the feasibility of CMOS processes at 14nm and even 3-5nm processes.

[0051] In order to balance low cost and functional expansion in multiple application scenarios, the present invention provides a method for preparing an integrated power chip for simultaneously preparing a fin-shaped high-voltage power device that can withstand high voltage, a medium-voltage LDMOS device, and a low-voltage MOS device using the same process flow. Figure 1 As shown, the preparation method in this embodiment includes steps S100 to S920.

[0052] Combine Figure 2 As shown, in step S100 , an N-type epitaxial layer 200 is epitaxially grown on the front surface of the semiconductor substrate 100 .

[0053] In this embodiment, the N-type epitaxial layer 200 is formed on the front side of the semiconductor substrate 100 by an epitaxial growth process. The semiconductor substrate 100 may be an N-type doped semiconductor material. The doping concentration of the N-type epitaxial layer 200 is greater than the concentration of N-type doping ions in the semiconductor substrate 100 .

[0054] In one embodiment, the semiconductor substrate 100 may be silicon carbide, silicon, or gallium nitride.

[0055] In step S200 , P-type dopant ions are implanted into a first predetermined region on the surface of the N-type epitaxial layer 200 to form a first P-type isolation layer 900 , and a P-type ion implantation region 910 is formed on the first P-type isolation layer 900 .

[0056] In this embodiment, the surface of the N-type epitaxial layer 200 can be divided into adjacent first preset areas and second preset areas. Among these two areas, the first preset area can be used to form medium-voltage LDMOS devices and low-voltage MOS devices, and the second preset area can be used to form high-voltage fin-shaped high-voltage power devices.

[0057] In this embodiment, a first P-type isolation layer 900 is formed by injecting P-type dopant ions in a first preset area, and then P-type dopant ions with a higher concentration are injected into a partial area of the first P-type isolation layer 900 to form a P-type ion injection area 910. At this time, the first P-type isolation layer 900 has a concave structure, and the P-type ion injection area 910 is located in the groove of the first P-type isolation layer 900. The first P-type isolation layer 900 isolates the P-type ion injection area 910 from contact with the N-type epitaxial layer 200.

[0058] Combine Figure 3 As shown, in step S300 , an N-type drift region 920 is formed in the first device region on the P-type ion implantation region 910 , and a P-type well region 930 is formed on the N-type drift region 920 .

[0059] In this embodiment, the P-type ion implantation region 910 can be divided into a first device region and a second device region. Specifically, N-type dopant ions are implanted into the first device region on its surface to form an N-type drift region 920 within the P-type ion implantation region 910 , and then P-type dopant ions are implanted into a partial region of the N-type drift region 920 to form a P-type well region 930 within the N-type drift region 920 .

[0060] In one embodiment, the P-type well region 930 is located at an edge region of the N-type drift region 920 and is close to the second device region on the surface of the P-type ion implantation region 910 .

[0061] In one embodiment, by injecting P-type dopant ions into an area near the edge of the surface of the N-type drift region 920, a P-type well region 930 is formed in the edge area of the N-type drift region 920. The N-type drift region 920 can be made into an L-shaped structure, and the P-type well region 930 is located on the horizontal portion of the N-type drift region 920, and the upper surface of the P-type well region 920 is flush with the upper surface of the vertical portion of the N-type drift region 920.

[0062] In one embodiment, P-type dopant ions are implanted into a portion of the N-type drift region 920 to form a P-type well region 930 within the N-type drift region 920 . Alternatively, the N-type drift region 920 may have a concave structure, with the P-type well region 930 located within the groove of the N-type drift region 920 .

[0063] In step S400 , a first source doping region 941 and a first drain doping region 951 are formed in the second device region on the P-type ion implantation region 910 , a second drain doping region 942 is formed on the P-type well region 930 , and a second source doping region 952 is formed on the N-type drift region 920 .

[0064] In this embodiment, the second device region of the P-type ion implantation region 910 can be used to form a low-voltage MOS device. Specifically, Figure 4 As shown, a mask is used to define the positions of the first source doping region 941 and the first drain doping region 951 in the second device area of the P-type ion implantation area 910, and a mask is used to define the position of the second drain doping region 942 on the P-type well area 930, and the position of the second source doping region 952 on the N-type drift area 920. Then, N-type doping ions are implanted into the surface of the device under the cover of the mask to form the first source doping region 941 and the first drain doping region 951 in the second device area of the P-type ion implantation area 910, the second drain doping region 942 in the P-type well area 930, and the second source doping region 952 in the N-type drift area 920.

[0065] In one embodiment, the second source doping region 952 and the P-type well region 930 do not contact each other, and the second source doping region 952 and the P-type well region 930 are respectively located on two sides of the N-type drift region 920 .

[0066] In step S500 , a dielectric layer is formed on the P-type ion implantation region 910 .

[0067] In one embodiment, combined Figure 5 As shown, a dielectric layer is formed on the P-type ion implantation region 910. The dielectric layer can be formed as a whole on the surface of the P-type ion implantation region 910, that is, the dielectric layer covers the surfaces of the first source doping region 941, the first drain doping region 951, the second drain doping region 942, the second source doping region 952 and the N-type drift region 920. It can also be divided into a first dielectric layer 961 and a second dielectric layer 962, so that the first dielectric layer 961 covers the first source doping region 941, the first drain doping region 951 and the surface of the P-type ion implantation region 910 therebetween, and the second dielectric layer 962 covers the second drain doping region 942, the P-type well region 930 and the surface of the N-type drift region 920.

[0068] In one embodiment, the first dielectric layer 961 and the second dielectric layer 962 may be silicon oxide or silicon nitride.

[0069] In step S600 , a second P-type isolation layer 300 is formed in a second predetermined region on the surface of the N-type epitaxial layer 200 .

[0070] In this embodiment, combined with Figure 6 As shown, the second P-type isolation layer 300 is formed in a second predetermined area on the surface of the N-type drift layer 200 , and is disposed adjacent to the first P-type isolation layer 900 and located on the same surface of the N-type drift layer 200 .

[0071] In a specific application embodiment, the preparation process of forming the second P-type isolation layer 300 in the second preset area in step S600 can be performed simultaneously with the preparation process of the first P-type isolation layer 900 in step S200 .

[0072] In step S700 , N-type doping is performed on a designated area of the second P-type isolation layer 300 to form a voltage channel layer 210 , so as to divide the second P-type isolation layer 300 into a first switch isolation region 311 and a second switch isolation region 321 .

[0073] In this embodiment, combined with Figure 7 As shown, N-type doping is performed on a designated area of the second P-type isolation layer 300 to form a voltage channel layer 210. The injection depth of the N-type doping ions is greater than the thickness of the second P-type isolation layer 300. The voltage channel layer 210 penetrates into the N-type epitaxial layer 200. The second P-type isolation layer 300 is divided into a first switch isolation area 311 and a second switch isolation area 321 through the voltage channel layer 210.

[0074] In one embodiment, by injecting N-type dopant ions into the central area of the second P-type isolation layer 300, a voltage channel layer 210 can be formed in the second P-type isolation layer 300, and the first switch isolation region 311 and the second switch isolation region 321 are respectively located on both sides of the voltage channel layer 210, and the first switch isolation region 311 and the second switch isolation region 321 do not contact each other.

[0075] In one embodiment, the first switch isolation region 311 and the second switch isolation region 321 are symmetrically arranged with the voltage channel layer 210 as a symmetry axis.

[0076] In step S800 , an N-type connection region 830 is formed on the voltage channel layer 210 , and a first source doping layer 810 , a second source doping layer 820 , and a plurality of alternating P-type doping structures and N-type channel structures are formed on both sides of the N-type connection region 830 .

[0077] In this embodiment, combined with Figure 9As shown, the N-type connection region 830 is located on the voltage channel layer 210, the first source doping layer 810 is located on the first switch isolation region 311, and the first source doping layer 810 is connected to the N-type connection region 830 through an N-type channel structure, and the second source doping layer 820 is located on the second switch isolation region 321, and the second source doping layer 820 is connected to the N-type connection region 830 through an N-type channel structure.

[0078] In one embodiment, the first source doping layer 810 is connected to the N-type connection region 830 via a plurality of first N-type channel structures 410 , and the second source doping layer 820 is connected to the N-type connection region 830 via a plurality of second N-type channel structures 420 .

[0079] In one embodiment, step S800 may include steps S811 to S813.

[0080] In step S811 , an N-type channel layer 400 is epitaxially grown on the voltage channel layer 210 and the P-type switch isolation layer.

[0081] In this embodiment, see Figure 8 As shown, an N-type channel layer 400 is epitaxially grown on the voltage channel layer 210 , the first switch isolation region 311 , and the second switch isolation region 321 by adopting an N-type semiconductor material epitaxial growth process.

[0082] In step S812, combined Figure 9 As shown, a first preset etching area on the N-type channel layer 400 is etched to form a plurality of first etching deep grooves 301, thereby forming a plurality of first N-type channel structures 410, and a first source doping layer 810 and an N-type connection region 830 are located on both sides of the plurality of first N-type channel structures 410, and a second preset etching area on the N-type channel layer 400 is etched to form a plurality of second etching deep grooves 302, thereby forming a plurality of second N-type channel structures 420, and a second source doping layer 820 and an N-type connection region 830 are located on both sides of the second N-type channel structure 420.

[0083] In one embodiment, the first etched deep trench 301 extends deep into the first switch isolation region 311 so that adjacent first N-type channel structures 410 do not contact each other, and the second etched deep trench 302 extends deep into the second switch isolation region 321 so that adjacent second N-type channel structures 420 do not contact each other.

[0084] In step S813, combined Figure 10 As shown, a first P-type doping structure 312 contacting the first switch isolation region 311 is formed in the first etched deep trench 301 , and a second P-type doping structure 322 contacting the second switch isolation region 321 is formed in the second etched deep trench 302 .

[0085] In one embodiment, combined Figure 10 As shown, the first preset etching area is used to determine the position of the first P-type doping structure 312 in the N-type channel layer 400, and the second preset etching area is used to determine the position of the second P-type doping structure 322 in the N-type channel layer 400. By determining the positions of the first P-type doping structure 312 and the second P-type doping structure 322, the structure between the first P-type doping structure 312 and the second P-type doping structure 322 is further used as the N-type connection area 830. Therefore, the first preset etching area is located above the first P-type doping structure 312, the second preset etching area is located above the second P-type doping structure 322, and the N-type connection area 830 is located between the first preset etching area and the second preset etching area.

[0086] In one embodiment, a plurality of first P-type doping structures 312 are arranged in parallel.

[0087] In one embodiment, the widths of the plurality of first P-type doping structures 312 are equal.

[0088] In one embodiment, a plurality of second P-type doping structures 322 are arranged in parallel.

[0089] In one embodiment, the widths of the plurality of second P-type doping structures 322 are equal.

[0090] In one embodiment, step S813 specifically includes: depositing a P-type semiconductor material in the first etched deep trench 301 to form a first P-type doped structure 312 .

[0091] In this embodiment, a first P-type doping structure 312 is formed by filling the first etched deep groove 301 with P-type doping material under the cover of a P-type doping mask. The first source doping layer 312 and the N-type connection region 830 are located on both sides of the first P-type doping structure 312, and the first source doping layer 312 and the N-type connection region 830 are both in contact with the first P-type doping structure 312.

[0092] In one embodiment, step S813 further includes: depositing a P-type semiconductor material in the second etched deep trench 302 to form a second P-type doped structure 322 .

[0093] In this embodiment, a second P-type doping structure 322 is formed by filling the second etched deep groove 302 with P-type doping material under the cover of a P-type doping mask. The second source doping layer 322 and the N-type connection region 830 are located on both sides of the second P-type doping structure 322, and the second source doping layer 322 and the N-type connection region 830 are both in contact with the second P-type doping structure 322.

[0094] In one embodiment, step S800 further includes step S821 and step S822.

[0095] In step S821, the positions of the N-type connection region 830, the first N-type channel structure 410, the second N-type channel structure 420, the first source doping layer 810 and the second source doping layer 820 are defined by a first mask, and then an N-type semiconductor material is deposited or epitaxially grown under the cover of the first mask, thereby forming an N-type connection region 830 on the voltage channel layer 210, forming a plurality of first N-type channel structures 410 and a first source doping layer 810 on the first switch isolation region 311, and forming a plurality of second N-type channel structures 420 and a second source doping layer 820 on the second switch isolation region 321.

[0096] In this embodiment, the first source doping layer 810 and the N-type connection region 830 are located on both sides of the first N-type channel structure 410 , and the second source doping layer 820 and the N-type connection region 830 are located on both sides of the second N-type channel structure 420 .

[0097] In one embodiment, the N-type semiconductor material may be N-type silicon carbide, N-type silicon, or N-type gallium nitride.

[0098] In step S822, a second mask is used to cover the positions of the N-type connection region 830, the first N-type channel structure 410, the second N-type channel structure 420, the first source doping layer 810 and the second source doping layer 820. By depositing P-type semiconductor material under the cover of the second mask, a first P-type doping structure 312 in contact with the first switch isolation region 311 is formed between adjacent first N-type channel structures 410, and a second P-type doping structure 322 in contact with the second switch isolation region 321 is formed between adjacent second N-type channel structures 420.

[0099] In one embodiment, the P-type semiconductor material may be P-type silicon carbide, P-type silicon, or P-type gallium nitride.

[0100] In one embodiment, the first and second photomasks are complementary in shape.

[0101] In one embodiment, in order to increase the thickness of the N-type connection region 830, the first N-type channel structure 410, the second N-type channel structure 420, the first source doping layer 810, and the second source doping layer 820, the above-mentioned step S821 and step S822 can be performed alternately, and the first mask and the second mask are used to alternately epitaxially grow N-type semiconductor material and P-type semiconductor material, thereby increasing the thickness of the N-type connection region 830, the first N-type channel structure 410, the second N-type channel structure 420, the first source doping layer 810, the second source doping layer 820, the first P-type doping structure 312, and the second P-type doping structure 322 through multiple epitaxial preparation processes.

[0102] In one embodiment, the first N-type channel structure 410 is located on both sides of the first P-type doping structure 312 , and the second N-type channel structure 420 is located on both sides of the second P-type doping structure 322 .

[0103] In one embodiment, the plurality of first N-type channel structures 410 and the plurality of second N-type channel structures 420 are disposed in a one-to-one correspondence.

[0104] In one embodiment, the first N-type channel structure 410 and the second N-type channel structure 420 have the same width.

[0105] In one embodiment, the device's withstand voltage can be increased by designing the wafer thickness, thereby increasing the device width to match the integrated power chip's switches, thereby achieving high current density and high breakdown voltage within the same chip area. While this design includes a connection region 830 compared to conventional device designs, technological advancements will allow for the introduction of more high-aspect-ratio technologies. Therefore, the integrated power chip of this embodiment has significant development potential.

[0106] In step S910 , a first gate layer 971 and a second gate layer 972 are formed on the dielectric layer, a third gate layer is formed on the P-type doping structure, and a drain metal layer is formed on the back side of the semiconductor substrate 100 .

[0107] In this embodiment, combined with Figure 11 As shown, a first gate layer 971 is formed on the first dielectric layer 961. The first gate layer 971 is located above the first dielectric layer 961 between the first source doping region 941 and the first drain doping region 951. The second gate layer 972 is located above the P-type well region 930 and the N-type drift region 920 between the second drain doping region 942 and the second source doping region 952.

[0108] In one embodiment, the first gate layer 971 and the second gate layer 972 may be polysilicon, and metal wires are led out from the first gate layer 971 and the second gate layer 972 respectively to serve as the first gate electrode and the second gate electrode.

[0109] In this embodiment, the third gate layer is formed on the first P-type doping structure 312 and the second P-type doping structure 322 , and the third gate layer is insulated from the first N-type channel structure 410 and the second N-type channel structure 420 .

[0110] In one embodiment, the third gate layer may include a first sub-gate 841 and a second sub-gate 842 . The first sub-gate 841 is formed on the first P-type doping structure 312 , and the second sub-gate 842 is formed on the second P-type doping structure 322 .

[0111] In one embodiment, in step S910 , a first interlayer dielectric layer may be formed between the first sub-gate 841 and the first P-type doped structure 312 , and a second interlayer dielectric layer may be formed between the second sub-gate 842 and the second P-type doped structure 322 .

[0112] In one embodiment, the first interlayer dielectric layer is further formed between the first sub-gate 841 and the first N-type channel structure 410 , and the second interlayer dielectric layer is further formed between the second sub-gate 842 and the second N-type channel structure 420 .

[0113] In this embodiment, combined with Figure 11 As shown, the drain metal layer 850 is formed on the back side of the semiconductor substrate 100 .

[0114] In one embodiment, the first P-type doped structure 312 and the first switch isolation region 311 are both P-type doped semiconductors, and the first N-type channel structure 410 and the first P-type doped structure 312 are alternately arranged to form a fin-shaped JFET structure. The first switch isolation region 311 is also used to isolate the first N-type channel structure 410 and the N-type drift layer 200. Taking the enhanced integrated power chip device as an example, a high voltage is connected to the first gate layer, which can make the depletion area of the JFET structure under the fin gate smaller, thereby turning on the device. If the voltage connected to the first gate layer is less than the turn-off threshold voltage, the depletion area of the JFET structure under the fin gate can be kept unchanged, thereby turning off the device.

[0115] In practical applications, if the transistor device is a depletion-type normally-on device, a negative voltage needs to be connected to the first gate layer to turn off the transistor.

[0116] Similarly, the fin-shaped JFET structure formed by the second switch isolation region 321 , the second source doping layer 820 , the N-type connection region 830 , the second P-type doping structure 322 and the second N-type channel structure 420 has the same working mechanism.

[0117] In step S920, combined Figure 11 As shown, a shallow trench isolation structure 980 is formed between the first predetermined area and the second predetermined area.

[0118] In this embodiment, the surface of the N-type epitaxial layer 200 can be divided into adjacent first predetermined regions and second predetermined regions, and the shallow trench isolation structure 980 is used to isolate the first predetermined region from the second predetermined region.

[0119] In one embodiment, the shallow trench isolation structure 980 extends deep into the N-type epitaxial layer 200 .

[0120] In one embodiment, the preparation process of steps S200 to S500 and steps S600 to S800 can be replaced, that is, first forming a high-voltage fin-shaped high-voltage power device in the second preset area on the surface of the N-type epitaxial layer 200, and then forming a medium-voltage LDMOS device and a low-voltage MOS device in the first preset area on the surface of the N-type epitaxial layer 200.

[0121] In one embodiment, in step S200 , the doping concentration of the P-type ion implantation region 910 is greater than the doping concentration of the first P-type isolation layer 900 .

[0122] In one embodiment, in step S400 , the P-type well region 930 and the second source doping region 952 are respectively located on two sides of the N-type drift region 920 .

[0123] In one embodiment, in step S910, a through hole can be formed on the dielectric layer and metal can be deposited to respectively lead out a first source electrode and a first drain electrode from the first source doping region 941 and the first drain doping region 951, and similarly, a second drain electrode and a second source electrode can be respectively led out from the second drain doping region 942 and the second source doping region 952.

[0124] In specific applications, by appropriately connecting the first source electrode, the first drain electrode, the second drain electrode, the second source electrode, the first gate layer 971, the second gate layer 972 and the third gate layer, that is, connecting the low-voltage device / medium-voltage device / high-voltage device, it can have a complete digital control circuit and power conversion function.

[0125] An embodiment of the present application further provides a chip, in which an integrated power chip prepared by any of the preparation methods described above is integrated.

[0126] The beneficial effects of the embodiments of the present application compared with the prior art are: by growing an N-type epitaxial layer on the front side of the semiconductor substrate, and then forming medium and low voltage devices through an ion implantation process in a first preset area on the surface of the N-type epitaxial layer, and then forming a second P-type isolation layer in a second preset area of the N-type epitaxial layer, and then dividing the second P-type isolation layer into a first switch isolation area and a second switch isolation area by forming a voltage channel layer, forming an N-type connection area on the voltage channel layer, and forming a first source doping layer, a second source doping layer and a plurality of alternating P-type doping structures and N-type channel structures on both sides of the N-type connection area, and forming a gate layer on the P-type doping structure, thereby preparing high voltage devices and medium and low voltage devices in the same process flow, and completing the topological structures of various applications through appropriate connection, thereby achieving the purpose of taking into account both low cost and expansion of device application scenarios.

[0127] Those skilled in the art will clearly understand that for the sake of convenience and brevity in description, only the division of the above-mentioned doping regions is used as an example. In actual applications, the above-mentioned functional areas can be allocated to different doping regions as needed, that is, the internal structure of the device can be divided into different doping regions to complete all or part of the functions described above.

[0128] The doping regions in the embodiment can be integrated into one functional region, or each doping region can exist physically separately, or two or more doping regions can be integrated into one functional region. The above-mentioned integrated functional regions can be implemented by using the same doping ion or by using multiple doping ions. In addition, the specific names of the doping regions are only for the convenience of distinguishing each other and are not used to limit the scope of protection of this application. The specific working process of the doping region in the preparation method of the above-mentioned device can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0129] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A method for preparing an integrated power chip, characterized in that: The preparation method comprises: epitaxially growing an N-type epitaxial layer on the front side of the semiconductor substrate; Implanting P-type dopant ions into a first predetermined area on the surface of the N-type epitaxial layer to form a first P-type isolation layer, and forming a P-type ion implantation region on the first P-type isolation layer; wherein the first P-type isolation layer is concave, and the P-type ion implantation region is located in the groove of the first P-type isolation layer; forming an N-type drift region in a first device region on the P-type ion implantation region, and forming a P-type well region on the N-type drift region; forming a first source doping region and a first drain doping region in a second device region on the P-type ion implantation region, respectively, forming a second drain doping region on the P-type well region, and forming a second source doping region on the N-type drift region; wherein the second source doping region and the P-type well region do not contact each other; forming a dielectric layer on the P-type ion implantation region; forming a second P-type isolation layer in a second predetermined area on the surface of the N-type epitaxial layer; Performing N-type doping on a designated area of the second P-type isolation layer to form a voltage channel layer, so as to divide the second P-type isolation layer into a first switch isolation area and a second switch isolation area; An N-type connection region is formed on the voltage channel layer, and a first source doping layer, a second source doping layer, and a plurality of alternating P-type doping structures and N-type channel structures are formed on both sides of the N-type connection region; wherein the first source doping layer is located on the first switch isolation region and is connected to the N-type connection region through the N-type channel structure, and the second source doping layer is located on the second switch isolation region and is connected to the N-type connection region through the N-type channel structure; forming a first gate layer and a second gate layer on the dielectric layer, forming a third gate layer on the P-type doped structure, and forming a drain metal layer on the back side of the semiconductor substrate; wherein the third gate layer is insulated from the N-type channel structure, the first gate layer is located above the first source doped region and the first drain doped region, and the second gate layer is located above the P-type well region; A shallow trench isolation structure is formed between the first preset area and the second preset area.

2. The preparation method according to claim 1, wherein The method comprises forming an N-type connection region on the voltage channel layer, and forming a first source doping layer, a second source doping layer, and a plurality of alternating P-type doping structures and N-type channel structures on both sides of the N-type connection region, including: epitaxially growing an N-type channel layer on the voltage channel layer and the second P-type isolation layer; Etching a first predetermined etched area on the N-type epitaxial layer to form a plurality of first etched deep grooves and a plurality of first N-type channel structures, and etching a second predetermined etched area on the N-type epitaxial layer to form a plurality of second etched deep grooves and a plurality of second N-type channel structures, so as to form the N-type connection region, the first source doping layer, and the second source doping layer on the voltage channel layer; wherein the first source doping layer and the N-type connection region are located on both sides of the first N-type channel structure, and the second source doping layer and the N-type connection region are located on both sides of the second N-type channel structure; A first P-type doped structure contacting the first switch isolation region is formed in the etched grooves between the first N-type channel structures, and a second P-type doped structure contacting the second switch isolation region is formed in the etched grooves between the second N-type channel structures.

3. The preparation method according to claim 2, wherein The first preset etching region is located above the first P-type doping structure, the second preset etching region is located above the second P-type doping structure, and the N-type connection region is located between the first preset etching region and the second preset etching region.

4. The preparation method according to claim 2, wherein The forming of a first P-type doping structure in contact with the first switch isolation region in the etched groove between the first N-type channel structures includes: A P-type semiconductor material is deposited between adjacent first N-type channel structures to form a first P-type doped structure; wherein the first source doped layer and the N-type connection region are located on both sides of the first P-type doped structure and are in contact with the first P-type doped structure.

5. The preparation method according to claim 2, wherein The forming of a second P-type doping structure in contact with the second switch isolation region in the etching groove between the second N-type channel structures includes: A P-type semiconductor material is deposited between adjacent second N-type channel structures to form a second P-type doped structure; wherein the second source doped layer and the N-type connection region are located on both sides of the second P-type doped structure and are in contact with the second P-type doped structure.

6. The preparation method according to claim 1, wherein The method comprises forming an N-type connection region on the voltage channel layer, and forming a first source doping layer, a second source doping layer, and a plurality of alternating P-type doping structures and N-type channel structures on both sides of the N-type connection region, including: epitaxially growing an N-type semiconductor material on the voltage channel layer and the second P-type isolation layer under the cover of a first photomask to form an N-type connection region, a first N-type channel structure, a second N-type channel structure, a first source doping layer, and a second source doping layer; wherein the first source doping layer and the N-type connection region are located on both sides of the first N-type channel structure, and the second source doping layer and the N-type connection region are located on both sides of the second N-type channel structure; Under the cover of the second mask, a first P-type doping structure contacting the first switch isolation region is formed between adjacent first N-type channel structures, and a second P-type doping structure contacting the second switch isolation region is formed between adjacent second N-type channel structures.

7. The preparation method according to claim 6, wherein The preparation method further comprises: The first mask and the second mask are used to alternately epitaxially grow N-type semiconductor material and P-type semiconductor material to increase the thickness of the N-type connection area, the first N-type channel structure, the second N-type channel structure, the first source doping layer, the second source doping layer, the first P-type doping structure and the second P-type doping structure.

8. The preparation method according to any one of claims 2 to 7, wherein The doping concentration of the P-type ion implantation region is greater than the doping concentration of the first P-type isolation layer.

9. The preparation method according to any one of claims 2 to 7, wherein: The P-type well region and the second source doping region are respectively located on both sides of the N-type drift region.

10. A chip, characterized in that: The chip is integrated with an integrated power chip prepared by the preparation method according to any one of claims 1 to 9.

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