High-power multi-channel multi-chip 3D vertical packaging structure based on HTCC process

Abstract

The present invention discloses a high-power multi-channel multi-chip 3D stereoscopic packaging structure based on the HTCC process, belonging to the field of radar and communication radio frequency front ends. It includes a multi-layer ceramic substrate which is integrally fabricated with a cavity by the HTCC process. On the front side of the substrate and / or in the front cavity, there are arranged first radio frequency devices with a peak power output greater than 3W in n transceiver channels. On the back side of the substrate and / or in the back cavity, there are arranged second radio frequency devices with a peak power output less than or equal to 3W in n transceiver channels. On the back side of the substrate, there are also arranged a level conversion chip and an OR gate. By separately arranging radio frequency devices with different functions and different output powers in multiple transceiver channels on two sides of the substrate and the cavity and vertically interconnecting them, high-power multi-channel multi-chip 3D stereoscopic packaging is achieved, the heat dissipation efficiency of the packaging structure is improved, miniaturized layout of multi-channel multi-chip packaging is realized, and a standardized and modular TR component with high-density integration at the board level is formed.

Description

Technical Field

[0001] The present invention relates to the field of radar and communication radio frequency front-ends, and particularly to a high-power multi-channel multi-chip 3D stereo packaging structure based on HTCC technology. Background Art

[0002] The networking application of detection satellite constellations and the one-arrow multi-satellite launch mode have put forward strict requirements on the volume and weight of a single satellite. As the main payload, the phased array radar must carry out miniaturization and lightweight design. If it is necessary to break the traditional radar antenna composition and realize the integrated design of components such as independent and separated antenna arrays and TR components, the AoB architecture is the main way to achieve high-density integration and low-cost manufacturing, and its core lies in the multi-channel and multi-functional multi-chip packaging and application. The AoB architecture has been widely used in satellite communication ground terminal antennas. However, since it mainly uses low-power transmitting chips or receiving chips with an output power not greater than 200 mW, the requirements for the area size and heat conduction ability of the packaging are not high. Therefore, a single-layer circuit planar layout packaging can meet the requirements.

[0003] Based on the TSV technology, multi-chip stacking can be realized to form a 3D layout structure. However, due to its use of silicon-based materials and semi-solid holes, the heat dissipation ability of chip packaging is poor, and it is mostly used for high-density packaging of multi-chips such as multi-channel low-power power amplifiers, low-noise amplifiers, and passive power dividers with an output power not greater than 500 mW.

[0004] In summary, the existing multi-chip packaging forms lack applicability in the field of radar detection with relatively large power or in military products and aerospace fields with relatively high environmental requirements. Therefore, multi-channel multi-chip packaging of high-power transmitting channels and receiving channels in phased array radar antennas to achieve a multi-chip high-density integration and 3D stereo miniaturization packaging form structure with smaller size and greater power, and solve the heat dissipation problem of the packaging, is of great significance for realizing a low-profile and lightweight payload phased array radar antenna and achieving large-scale networking applications based on this phased array antenna. Summary of the Invention

[0005] The purpose of the present invention is to overcome the problems of the prior art and provide a high-power multi-channel multi-chip 3D stereo packaging structure based on HTCC technology.

[0006] The object of the present invention is achieved by the following technical solutions: A high-power multi-channel multi-chip 3D stereoscopic packaging structure based on HTCC technology, which includes a double-sided substrate and cavities formed on the double-sided substrate; on the front side of the substrate and / or in the front cavity, there are arranged first radio frequency devices with a peak power output greater than 3W in n transceiver channels, and on the back side of the substrate and / or in the back cavity, there are arranged second radio frequency devices with a peak power output less than or equal to 3W in n transceiver channels; n is a positive integer greater than 1; on the substrate and / or in the cavity, there is also arranged a power management chip;

[0007] The first radio frequency device and the second radio frequency device in each transceiver channel are vertically interconnected through multi-layer vias of the substrate, and the power chip is interconnected with the first radio frequency device and / or the second radio frequency device, and the functional interfaces for the package to the outside are led to the bottom surface of the substrate;

[0008] There is a front cover plate on the front side of the substrate and a back cover plate on the back side of the substrate, thereby realizing the packaging of the devices in n transceiver channels;

[0009] There is also a level conversion chip and an OR gate on the back side of the substrate. The external control signal is transmitted to the radio frequency device after being converted by the level conversion chip, and the OR gate is connected to the first dual-channel power modulation chip and the second dual-channel power modulation chip for realizing the logic conversion of the control signal;

[0010] The substrate is a multi-layer ceramic substrate, and the multi-layer ceramic substrate and the cavity are integrally manufactured by HTCC technology.

[0011] In an example, the substrate is a ceramic substrate with a surrounding frame.

[0012] In an example, on the front side of the substrate, multiple sunken grooves are formed by multi-layer cavity opening to install the first radio frequency devices higher than the height of the surrounding frame, and the front cover plate and the front cavity are eutectically welded into one body; on the back side of the ceramic substrate, a cavity space is formed by a stepped multi-layer cavity opening to install the second radio frequency devices, and the back cover plate and the back cavity are eutectically welded into one body.

[0013] In an example, both the front cover plate and the back cover plate are kovar alloy metal cover plates.

[0014] In an example, the transmitting link of the transceiver channel includes a transmitting power amplifier chip; it also includes a double circulator for switching and isolation in the transceiver link, and the transmitting power amplifier chip is connected to the double circulator; it also includes a limiter chip, a receiving low-noise amplifier chip, and a receiving driver amplifier chip connected in sequence according to the receiving link, and the limiter chip is connected to the double circulator; it also includes a power management chip, and the power management chip is connected to the power supply ports of the transmitting power amplifier chip, the receiving low-noise amplifier chip, and the receiving driver amplifier chip;

[0015] The transmitting power amplifier chip, the dual circulator, the limiter chip, and the receiving low-noise amplifier chip are the first radio frequency devices, and the receiving driver amplifier chip is the second radio frequency device.

[0016] In one example, the transmitting power amplifier chip, the limiter chip, and the receiving low-noise amplifier chip are disposed on the front side of the substrate, and the dual circulator is disposed in the front cavity; the receiving driver amplifier chip and the power management chip are disposed in the back cavity.

[0017] In one example, the power management chip is a dual-channel power modulation chip.

[0018] In one example, the functional interface is led out to the bottom surface of the substrate in the form of BGA.

[0019] In one example, the area size of the 3D three-dimensional packaging structure meets the layout constraint limiting conditions determined by the element spacing of the phased array radar antenna without grating lobe beam scanning.

[0020] It should be further noted that the technical features corresponding to the above examples can be combined or replaced with each other to form a new technical solution.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0022] 1. In one example, by disposing high-power radio frequency devices with an output power greater than 3W on one side of the substrate, and at the same time disposing radio frequency devices with a smaller output power on the other side of the substrate, and vertically interconnecting the devices, a high-power multi-channel multi-chip 3D three-dimensional packaging is realized, which can avoid the risk of circuit non-conduction or short circuit caused by problems such as alignment accuracy and solder consumption during multi-substrate welding in planar packaging; at the same time, by separately disposing radio frequency devices with different output powers on both sides of the substrate, a temperature gradient is formed on both sides of the substrate, which is beneficial to heat conduction and improves the heat dissipation efficiency of the packaging structure; further, the 3D three-dimensional packaging of the present invention realizes a miniaturized layout of multi-channel multi-chip packaging, and is assembled and used to realize a standardized and modular TR component with high-density integration at the board level.

[0023] 2. In one example, an aluminum nitride ceramic integrated molding is used to manufacture the packaging substrate and the enclosure based on the HTCC process, combined with a metal can cover, which has excellent heat conduction performance; further, the heat dissipation of the high-power first radio frequency device is conducted through the shortest heat dissipation path of the substrate → enclosure → cover → component installation heat dissipation surface, and the second radio frequency device is conducted through the substrate according to the same path as above, so that the multi-chip packaging has high heat dissipation capacity, and the junction temperature of the power amplifier chip is much lower than the first-level derating condition, and it has excellent platform environment adaptability. Description of the Drawings

[0024] The following further elaborates on the specific embodiments of the present invention in conjunction with the accompanying drawings. The drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The same reference numerals are used in these drawings to represent the same or similar parts. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application.

[0025] Figure 1 It is a block diagram of a dual-channel multi-chip 3D stacked package in a preferred example of the present invention;

[0026] Figure 2 It is a schematic diagram of HTCC stacking and vertical interconnection of a dual-channel multi-chip 3D stacked package in a preferred example of the present invention;

[0027] Figure 3 It is a front view schematic diagram of the appearance of a dual-channel multi-chip 3D stacked package structure in a preferred example of the present invention;

[0028] Figure 4 It is a back view schematic diagram of the appearance of a dual-channel multi-chip 3D stacked package structure in a preferred example of the present invention;

[0029] Figure 5 It is a front layout schematic diagram of a dual-channel multi-chip 3D stacked package in a preferred example of the present invention;

[0030] Figure 6 It is a back layout schematic diagram of a dual-channel multi-chip 3D stacked package in a preferred example of the present invention;

[0031] Figure 7 It is a schematic diagram of the heat dissipation path of a dual-channel multi-chip 3D stacked package in a preferred example of the present invention.

[0032] In the figure: 1 - First transceiver channel, 11 - First transmitting power amplifier chip, 12 - First dual circulator, 13 - First limiter chip, 14 - First receiving low-noise amplifier chip, 15 - First receiving driver amplifier chip, 16 - First dual-channel power modulation chip, 2 - Second transceiver channel, 21 - Second transmitting power amplifier chip, 22 - Second dual circulator, 23 - Second limiter chip, 24 - Second receiving low-noise amplifier chip, 25 - Second receiving driver amplifier chip, 26 - Second dual-channel power modulation chip, 3 - Substrate, 41 - Front cover plate, 42 - Back cover plate, 5 - Frame, 6 - Chip capacitor, 7 - Level conversion chip, 8 - BGA ball, 9 - OR gate, 101 - Thermal conductive gasket, 102 - Heat sink, 103 - Hybrid pressure PCB board, 104 - First receiving feed terminal interface, 105 - First transmitting feed terminal interface, 106 - Second transmitting feed terminal interface, 107 - Second receiving feed terminal interface, 108 - First antenna terminal interface, 109 - Second antenna terminal interface. Specific Embodiments

[0033] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0034] In the description of the present invention, it should be noted that the directions or positional relationships indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings. This is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, the use of ordinal numbers (for example, "first and second", "first to fourth", etc.) is for distinguishing objects and is not limited to this order, and should not be construed as indicating or implying relative importance.

[0035] In the description of the present invention, it should be noted that unless otherwise clearly specified and defined, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0036] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0037] In one example, a high-power multi-channel multi-chip 3D three-dimensional packaging structure based on the HTCC process is located at the front end of a phased array radar antenna. The 3D three-dimensional packaging structure includes a substrate for arranging devices in the transceiver channels, preferably a stacked substrate. Through holes for realizing device wiring are formed on the substrate, and cavities are also formed on the substrate. Preferably, cavities are formed on both sides of the substrate to form a front cavity and a back cavity; on the front side of the substrate and in the front cavity, first radio frequency devices with an output peak power greater than 3W in n transceiver channels are arranged; in the back cavity, second radio frequency devices with an output peak power less than or equal to 3W in n transceiver channels are arranged, where n is a positive integer greater than 1; a power supply chip is also arranged on the substrate and / or in the cavity. The output power of the power supply chip for the high-power transmitting channels in the phased array radar antenna is generally less than 3W. And to effectively utilize the substrate area, that is, to fully arrange the devices in the transceiver channels on the limited substrate area, the power supply chip is generally arranged in the back cavity. Further, first basic elements and / or auxiliary chips for realizing the signal transceiver function of the transceiver channels can also be arranged on the front side of the substrate, and second basic elements and / or auxiliary chips for realizing the signal transceiver function of the transceiver channels can also be arranged on the back side of the substrate. The basic elements are capacitors, inductors, etc., and the auxiliary chips are logic gate chips, level conversion chips, etc.

[0038] Further, the first radio frequency devices and the second radio frequency devices in each transceiver channel are vertically interconnected through multi-layer through holes in the substrate, and at the same time, the power supply chip is interconnected with the first radio frequency devices and / or the second radio frequency devices; specifically, if both the first radio frequency devices and the second radio frequency devices need to be powered by the power supply chip, at this time, the radio frequency devices opposite to the power supply chip on the substrate are vertically interconnected with the power supply chip, and the radio frequency devices on the same side as the power supply chip on the substrate are directly horizontally interconnected with the power supply chip, so as to realize the signal transceiver and power supply functions of the transceiver channels. Of course, if basic elements need to be introduced to ensure the normal operation of the transceiver channels, at this time, the basic elements are generally arranged on the same side as the radio frequency devices they need to be connected to, so as to reduce the interconnection difficulty. Finally, the external function interfaces formed during the interconnection process between the devices in the transceiver channels are led to the bottom surface of the substrate, which is convenient for interconnection with external devices. Among them, the function interfaces include control interfaces, radio frequency interfaces, power supply interfaces, etc.

[0039] Further, a front cover plate is arranged on the front side of the substrate on which devices (such as the first radio frequency devices, the second radio frequency devices, the power supply chip, the basic elements, the auxiliary chips, etc.) are arranged, and a back cover plate is arranged on the back side of the substrate, thereby realizing a high-power multi-channel multi-chip 3D three-dimensional packaging, forming a standardized and modular TR component (transceiver component) with high-density integration at the board level. According to the array surface layout, it can be assembled and integrated with the antenna to be spliced into an ultra-large-scale phased array antenna, providing excellent radar power performance.

[0040] In one example, the substrate is a multi-layer ceramic substrate fabricated by the HTCC process. Preferably, aluminum nitride ceramic material is used as the packaging substrate, which has excellent thermal conductivity. More specifically, the multi-layer ceramic substrate and the cavity are integrally fabricated by the HTCC process, which not only ensures the reliability of cavity fabrication but also reduces the manufacturing process. Further, through the multi-layers of ceramics and vias in each layer fabricated by the HTCC process, vertical interconnection between layers is achieved. Basic components, radio frequency devices, power chips, and auxiliary chips are connected according to the link to form a 3D stereo circuit structure.

[0041] In one example, the substrate is a ceramic substrate with a surrounding frame. Preferably, the surrounding frame is only provided on the front side of the ceramic substrate. Further, the surrounding frame is an aluminum nitride ceramic surrounding frame and is fabricated by laminating and sintering with the ceramic substrate through the HTCC process, that is, the integrated preparation of the ceramic substrate and the surrounding frame is obtained, which ensures the alignment accuracy between the substrate and the surrounding frame and enables more continuous heat conduction, thus improving the heat dissipation performance.

[0042] In one example, when only the front side of the ceramic substrate is provided with a surrounding frame, a sunken groove, i.e., the front cavity, is formed on the front side of the ceramic substrate by using a multi-layer cavity opening method to install the first radio frequency device higher than the height of the surrounding frame. At the same time, other devices are arranged on the front side of the substrate. After all the front-side devices are installed, the front cover plate is eutectically welded to the surrounding frame as a whole. Preferably, it is eutectically welded to the aluminum nitride ceramic substrate surrounding frame by using a gold-tin solder to achieve hermetic packaging. A cavity space, i.e., the back cavity, is formed on the back side of the ceramic substrate by using a stepped multi-layer cavity opening method to install the second radio frequency device, and other devices (such as basic components) are installed on the back side of the substrate. After all the back-side devices are installed, the back cover plate is eutectically welded to the ceramic substrate as a whole. Preferably, it is eutectically welded to the aluminum nitride ceramic substrate by using a lead-tin solder to achieve hermetic packaging. As an option, both the front cover plate and the back cover plate are kovar alloy metal cover plates, which have good thermal conductivity and high mechanical strength.

[0043] In one example, the transmit link of the transceiver channel includes a transmit power amplifier chip; it also includes a dual circulator for switching and isolation in the transceiver link, and the transmit power amplifier chip is connected to the dual circulator; it further includes a limiter chip, a low-noise receive amplifier chip, and a receive driver amplifier chip connected in sequence according to the receive link. The limiter chip is connected to the dual circulator to achieve power amplification of the transmit signal of each channel, reception and low-noise amplification of the echo signal, time-division switching operation between transmission and reception, and isolation between transmission and reception; the transceiver channel also includes a power supply chip, and the power supply chip is connected to the power supply ports of the transmit power amplifier chip, the low-noise receive amplifier chip, and the receive driver amplifier chip. Among them, the dual circulator includes a first-stage circulator and a second-stage circulator connected to each other. The circulator is connected to the antenna, and the antenna is independently arranged outside the package structure of the present invention. The transmit power amplifier chip, the dual circulator, the limiter chip, and the low-noise receive amplifier chip are all first radio frequency devices with an output peak power greater than 3W, and are arranged on the front side and / or the front cavity of the substrate. Preferably, the transmit power amplifier chip, the limiter chip, and the low-noise receive amplifier chip are arranged on the front side of the substrate, and the dual circulator is arranged in the front cavity; the receive driver amplifier chip is a second radio frequency device and is arranged on the back side and / or the back cavity of the substrate. Preferably, the receive driver amplifier chip and the power management chip are arranged in the back cavity. Further, DC bias power supply required isolation capacitor chips are also arranged on the front side and the back side of the substrate.

[0044] Preferably, the power supply chip is a dual-channel power modulation chip. One channel provides the drain DC bias power supply for the transmit power amplifier chip to control the on / off of the transmit channel; the other channel provides the drain DC bias power supply for the low-noise receive amplifier chip and the receive driver amplifier chip to control the on / off of the receive channel; the two channels of power are independent of each other and provide different DC bias voltages. In this example, the heat dissipation of heat source chips such as the transmit power amplifier chip, the limiter chip, the low-noise receive amplifier chip, the receive driver amplifier chip, and the dual-channel power modulation chip is efficiently transmitted to the kovar alloy metal cover through the aluminum nitride ceramic substrate and the frame to achieve excellent heat conduction and heat dissipation; among them, the high-heat dissipation transmit power amplifier chip with an output peak power reaching more than 3W and arranged on the front side of the ceramic substrate has a shorter heat conduction path, improving the heat dissipation efficiency.

[0045] In one example, the high-power multi-channel multi-chip 3D stacked packaging structure of the present invention includes n transceiver channels. The on / off of each transceiver channel is independently controlled by the on / off of the power supply to the chips in the channel. The switching between the transmit channel and the receive channel in each transceiver channel is independently controlled by the on / off of the power supply to the chips in their respective channels, that is, the multi-channel operations are independent of each other, and the on / off of each transceiver channel and the switching of the transmit and receive operating states can be performed according to the control signal. Specifically, when working in the transmit state, the transceiver control signal causes the power modulation chip to output the operating voltage required by the transmit channel power amplifier chip, turning on the transmit channel while turning off the receive channel. The transmitted radio frequency signal is input, saturated and amplified by the power amplifier chip to the power required to meet the power requirement, and then output to the first-stage loop of the dual circulator and fed into the antenna. While being isolated from the receive channel, it ensures that the transmitted signal reflected from the antenna end is isolated from the transmit channel, protecting the power amplifier chip. When working in the receive state, the transceiver control signal causes the power modulation chip to output the operating voltages required by the receive channel low-noise amplifier chip and the receive drive amplifier chip, turning on the receive channel while turning off the transmit channel. The radio frequency signal received from the antenna end is input, passes through the two-stage loop of the dual circulator, is isolated from the transmit channel, enters the receive channel, and after passing through the limiter, low-noise amplifier chip and drive amplification, is output to the backend receive link.

[0046] In one example, the functional interface is led out to the bottom surface of the substrate in the form of BGA to form the external interface of the high-power multi-channel multi-chip 3D stacked packaging, including the radio frequency interface of n antenna terminals, the radio frequency interface of n feeding terminals, the transceiver control interface and the power supply interface; the interface pins adopt the BGA form to achieve low-loss transmission characteristics and miniaturized size.

[0047] In one example, the area size of the 3D stacked packaging structure meets the layout constraint conditions determined by the element spacing of the phased array radar antenna without grating lobes for beam scanning, so as to ensure the normal operation of the phased array radar antenna.

[0048] Combining the above examples, the preferred example of the present invention is obtained. Taking the 3D stacked packaging of high-power multi-channel multi-chips in the Ku-band spaceborne phased array radar antenna as an example for illustration:

[0049] The adjacent element spacing determined by the grating lobe-free beam scanning range of the Ku-band spaceborne phased array radar antenna is 9 mm. After removing the layout space for external circuits and devices, the area reserved for the front-end transceiver channels and other functional circuits is very compact. Therefore, a dual-channel multi-chip 3D stacked packaging is adopted to realize the integrated layout of the transceiver channel functional circuits of the standardized and modular TR components. The dual-channel multi-chip 3D stacked packaging realizes the power amplification of the transmitted signals of the two transceiver channels, the reception and low-noise amplification of the echo signals, and the time-division switching operation between transmission and reception, and the isolation between transmission and reception. The on / off of each transceiver channel is independently controlled by the on / off of the power supply to the chips in the channel, and the switching between the transmit channel and the receive channel in each transceiver channel is independently controlled by the on / off of the power supply to the chips in their respective channels.

[0050] As Figure 1 shown, the dual-channel multi-chip 3D stacked packaging includes a first transceiver channel 1 and a second transceiver channel 2. Among them, the transmit link of the first transceiver channel 1 includes a first transmit power amplifier chip 11; the first transceiver channel 1 further includes a first dual circulator 12 for switching and isolation in the transceiver link, and the first transmit power amplifier chip 11 is connected to the first dual circulator 12; the first transceiver channel 1 further includes a first limiter chip 13, a first receive low-noise amplifier chip 14, and a first receive driver amplifier chip 15 connected in sequence according to the receive link, and the first limiter chip 13 is connected to the first dual circulator 12; it also includes a first dual-channel power modulation chip 16, which is connected to the first transmit power amplifier chip 11, the first receive low-noise amplifier chip 14, and the first receive driver amplifier chip 15; the transmit link of the second transceiver channel 2 includes a second transmit power amplifier chip 21; the second transceiver channel 2 further includes a second dual circulator 22 for switching and isolation in the transceiver link, and the second transmit power amplifier chip 21 is connected to the second dual circulator 22; the second transceiver channel 2 further includes a second limiter chip 23, a second receive low-noise amplifier chip 24, and a second receive driver amplifier chip 25 connected in sequence according to the receive link, and the second limiter chip 23 is connected to the second dual circulator 22; it also includes a second dual-channel power modulation chip 26, which is connected to the second transmit power amplifier chip 21, the second receive low-noise amplifier chip 24, and the second receive driver amplifier chip 25. The on / off control of each transceiver channel is realized by a dual-channel power modulation chip. One path provides the drain DC bias power supply for the transmit power amplifier chip to control the on / off of the transmit channel; the other path provides the drain DC bias power supply for the receive low-noise amplifier chip and the receive driver amplifier chip to control the on / off of the receive channel; the two paths of power supply are independent of each other and provide different DC bias voltages.

[0051] The size of the dual-channel multi-chip 3D stacked package meets the layout constraint conditions determined by the element spacing for grating lobe-free beam scanning of the phased array radar antenna, with an area of 16 mm × 13 mm. For the size of a single device, the dual circulator is 6 mm × 5.8 mm × 2.5 mm, the power amplifier chip is 3.5 mm × 1.9 mm × 0.1 mm, the limiter chip is 1.0 mm × 0.6 mm × 0.1 mm, the receiving low-noise amplifier chip is 1.95 mm × 0.8 mm × 0.1 mm, the receiving driver amplifier chip is 1.6 mm × 0.85 mm × 0.1 mm, and the dual-channel power modulation chip is 2.0 mm × 1.1 mm × 0.1 mm. Considering other components such as chip capacitors and level shifters, it is impossible to arrange all the components and chips of two transceiver channels in a single-layer planar layout. Therefore, for the chip layout, an aluminum nitride ceramic material based on the HTCC process is used as the packaging substrate, and different components and chips are arranged on the front and back sides of the substrate; through the multi-layer ceramics fabricated by the HTCC process and the vias on each layer, vertical interconnection between layers is achieved, and the corresponding components and chips are connected according to the link, such as Figure 2 (Only the interconnection relationship of the devices in the first transceiver channel is shown, and the devices in the second transceiver channel are blocked by the devices in the first transceiver channel) as shown, including the RF connection from the input interface of the transmit channel at the bottom of the package to the front side of the substrate and the first transmit power amplifier chip 11, the RF connection between the first dual circulator 12 on the front side of the substrate and the interface from the bottom of the package to the antenna end, the RF connection between the first receiving low-noise amplifier chip 14 on the front side of the substrate and the first receiving driver amplifier chip 15 on the back side of the substrate, the RF connection between the first receiving driver amplifier chip 15 on the back side of the substrate and the output interface of the receive channel at the bottom of the package, the connection between the power supply and control interface at the bottom of the package and the first dual-channel power modulation chip 16 on the back side of the substrate, and the connection between the first dual-channel power modulation chip 16 on the back side of the substrate and the power supply for the first transmit power amplifier chip 11 and the first receiving low-noise amplifier chip 14 on the front side of the substrate, forming a 3D stacked circuit structure. Figure 2 In it, RF_Top represents the top RF layer; RF_Bot represents the bottom RF layer; GND represents the ground layer; POWER represents the power supply layer; SPI represents the control line layer; SL represents the stripline RF layer; NC represents not connected; L represents the trace layer. Among them, the vertical interconnection design has the characteristic of low insertion loss, ≤ 0.5 dB in the Ku band, enabling the single-channel transmit output power of the dual-channel multi-chip 3D stacked package to be ≥ 2.5 W and the single-channel receive noise figure to be ≤ 3 dB, with excellent RF and microwave performance.

[0052] Furthermore, the dual-channel multi-chip 3D stacked package is based on the multi-layer ceramics fabricated by the HTCC process, as Figure 3 shown. According to the heights of the first dual circulator and the second dual circulator on the front side, two dual circulators are assembled in a sunken manner using multi-layer cavity opening and stacking, and a ceramic packaging frame integrated with the substrate is realized; as Figure 4As shown, the cavity space for assembling the back chips and devices is realized through stepped multi-layer cavity opening and lamination on the back side; finally, the high-power multi-channel multi-chip 3D stereo packaging mechanism is formed in one step by the HTCC process, and a kovar alloy is used as the metal package shell, including a front cover plate and a back cover plate; the front cover plate is eutectically welded to the frame of the aluminum nitride ceramic substrate with a gold-tin solder to achieve the hermetic packaging of the front chips; the back cover plate is eutectically welded to the aluminum nitride ceramic substrate with a lead-tin solder to achieve the hermetic packaging of the back chips; as Figure 3 , Figure 5 shown, on the front side of the ceramic substrate, there are arranged a first dual circulator 12, a second dual circulator 22, a first transmitting power amplifier chip 11, a second transmitting power amplifier chip 21, a first limiter chip 13, a second limiter chip 23, a first receiving low-noise amplifier chip 14, a second receiving low-noise amplifier chip 24 and some chip capacitors 6; as Figure 4 , Figure 6 shown, on the back side of the ceramic substrate, there are arranged a first receiving drive amplifier chip 15, a second receiving drive amplifier chip 25, some chip capacitors 6, a first dual-channel power modulation chip 16 and a second dual-channel power modulation chip 26; on the back side of the ceramic substrate, there are also arranged a level conversion chip 7 and an OR gate 9. The external control signal is transmitted to the corresponding radio frequency device after being converted by the level conversion chip, and the OR gate is connected to the first dual-channel power modulation chip and the second dual-channel power modulation chip for realizing the logic conversion of the control signal. As Figure 6 shown, on the back side of the substrate, there are also arranged a first receiving feed terminal interface 104 in the first transceiver channel, a first transmitting feed terminal interface 105 in the first transceiver channel, a first antenna terminal interface 108 in the first transceiver channel, a second receiving feed terminal interface 107 in the second transceiver channel, a second transmitting feed terminal interface 106 in the second transceiver channel and a second antenna terminal interface 109 in the second transceiver channel. Further, the aluminum nitride ceramic material has high thermal conductivity, and the thermal conductivity of this material reaches 260 W / (m·k), which is more than 5 times higher than that of conventional alumina ceramics, and the thermal expansion coefficient (4.5×10 -6 / °C) is matched with that of Si (3.5 - 4×10 -6 / °C) and GaAs (6×10 -6 / °C). As Figure 7 shown, on the front cover plate, there are also successively arranged a thermal conductive gasket 101 and a heat sink 102, and the heat sink is preferably an aluminum alloy heat sink; on the back cover plate, there is also arranged a hybrid pressure PCB board 103, preferably a microwave multi-layer hybrid pressure board. It should be further noted that Figure 7The rectangular box filled with black in the middle is the heat source chip, and the arrow filled with black represents the heat dissipation path. It can be seen that the heat dissipation of heat source chips such as the transmitting power amplifier chip, limiter chip, receiving low-noise amplifier chip, receiving driver amplifier chip, and dual-channel power modulation chip is conducted through the aluminum nitride substrate → aluminum nitride enclosure → metal cover plate → thermal conductive gasket → heat dissipation surface of the heat sink. The receiving driver amplifier chip and dual-channel power modulation chip located on the reverse side of the substrate can also conduct heat dissipation through the aluminum nitride substrate in the same way, enabling the multi-chip package to have high-efficiency heat dissipation capacity. Among them, the high-heat-dissipation transmitting power amplifier chip with an output peak power of more than 3W, which is arranged on the front of the ceramic substrate, has a shorter heat conduction path.

[0053] Furthermore, the external interfaces of the dual-channel multi-chip 3D stereo package include 2 RF interfaces with the antenna end, 2 RF interfaces with the feeding end, a transceiver control interface, and a power supply interface. The interface pins adopt the BGA form to achieve low-loss transmission characteristics and miniaturized size, with a size of 16mm×13mm×5.2mm.

[0054] In this preferred example, for the limited layout space, the HTCC process is used to realize a multi-layer aluminum nitride ceramic substrate. The circulators, power amplifier chips, low-noise amplifier chips, limiter chips, driver amplifier chips, power splitter chips, and transceiver power modulation chips required for 2 transceiver channels are arranged on the front and back sides. Through the vertical interconnection in the substrate, a 3D stereo circuit structure is constructed to achieve a miniaturized layout of the multi-channel multi-chip package. After assembly and use, a standardized and modular TR component with high-density integration at the board level is realized. According to the array layout, it can be assembled and integrated with the antenna to form a super-large-scale phased array antenna, providing excellent radar power performance.

[0055] The above specific implementation manners are detailed descriptions of the present invention. It cannot be determined that the specific implementation manners of the present invention are only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions and substitutions can still be made, which should all be regarded as belonging to the protection scope of the present invention.

Claims

1. A high-power multi-channel multi-chip 3D stacked packaging structure based on the HTCC process, characterized in that: It includes a substrate and a cavity formed on the substrate. On the front side of the substrate and / or inside the front cavity, there are arranged first radio frequency devices, which are devices with an output peak power greater than 3W among the n transceiver channels. On the back side of the substrate and / or inside the back cavity, there are arranged second radio frequency devices, which are devices with an output peak power less than or equal to 3W among the n transceiver channels. n is a positive integer greater than 1. On the substrate and / or the cavity, there is also arranged a power management chip. The first radio frequency device and the second radio frequency device in each transceiver channel are vertically interconnected through multi-layer vias of the substrate. The power chip is interconnected with the first radio frequency device and / or the second radio frequency device, and leads the functional interfaces facing outward of the package to the bottom surface of the substrate. There is a front cover plate on the front side of the substrate and a back cover plate on the back side of the substrate, thereby realizing the packaging of the devices in the n transceiver channels. There is also a level conversion chip and an OR gate on the back side of the substrate. The external control signal is transmitted to the radio frequency device after being converted by the level conversion chip. The OR gate is connected to the first dual-channel power modulation chip and the second dual-channel power modulation chip, and is used to realize the logic conversion of the control signal. The substrate is a multi-layer ceramic substrate, and the multi-layer ceramic substrate and the cavity are integrally fabricated by the HTCC process.

2. The high-power multi-channel multi-chip 3D stacked packaging structure based on the HTCC process according to claim 1, wherein: The substrate is a ceramic substrate with a surrounding frame.

3. The high-power multi-channel multi-chip 3D three-dimensional packaging structure based on the HTCC process according to claim 2, wherein: On the front side of the substrate, multiple sunken grooves are formed by the multi-layer cavity opening method to install the first radio frequency devices higher than the height of the surrounding frame, and the front cover plate and the front cavity are eutectically welded into one body. On the back side of the ceramic substrate, a cavity space is formed by the stepped multi-layer cavity opening method to install the second radio frequency devices, and the back cover plate and the back cavity are eutectically welded into one body.

4. The high-power multi-channel multi-chip 3D stacked packaging structure based on the HTCC process according to claim 1, wherein: Both the front cover plate and the back cover plate are kovar alloy metal cover plates.

5. The high-power multi-channel multi-chip 3D stacked packaging structure based on the HTCC process according to claim 1, wherein: The transmitting link of the transceiver channel includes a transmitting power amplifier chip; it also includes a dual circulator for switching and isolation in the transceiver link, and the transmitting power amplifier chip is connected to the dual circulator; it also includes a limiter chip, a receiving low-noise amplifier chip, and a receiving driver amplifier chip connected in sequence according to the receiving link, and the limiter chip is connected to the dual circulator; it also includes a power management chip, and the power management chip is connected to the power supply ports of the transmitting power amplifier chip, the receiving low-noise amplifier chip, and the receiving driver amplifier chip. The transmitting power amplifier chip, the dual circulator, the limiter chip, and the receiving low-noise amplifier chip are the first radio frequency devices, and the receiving driver amplifier chip is the second radio frequency device.

6. The high-power multi-channel multi-chip 3D stereoscopic packaging structure based on the HTCC process according to claim 5, wherein: The transmitting power amplifier chip, the limiter chip, and the receiving low-noise amplifier chip are arranged on the front side of the substrate, and the dual circulator is arranged in the front cavity; the receiving driver amplifier chip and the power management chip are arranged in the back cavity.

7. The high-power multi-channel multi-chip 3D stacked packaging structure based on the HTCC process according to claim 5, characterized in that: The power management chip is a dual-channel power modulation chip.

8. The high-power multi-channel multi-chip 3D stereo packaging structure based on the HTCC process according to claim 1, wherein: The functional interfaces are led out to the bottom surface of the substrate in the form of BGA.

9. The high-power multi-channel multi-chip 3D stacked packaging structure based on the HTCC process according to claim 1, wherein: The area size of the 3D three-dimensional packaging structure meets the layout constraint limiting conditions determined by the element spacing for grating lobe-free beam scanning of the phased array radar antenna.

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