Hybrid access mechanism surround gate transistor and method of making the same

Abstract

The application provides a hybrid conduction mechanism surrounding gate transistor, which comprises a surrounding gate MOSFET device, a second source region and a second drain region; the surrounding gate MOSFET device comprises a substrate, a first source region and a first drain region; the first source region and the first drain region are doped with first ions; the second source region is formed between the substrate and the first source region, the second drain region is formed between the substrate and the first drain region, and the height of the second source region and the second drain region is not lower than the height of the substrate between the first source region and the first drain region; the second drain region is doped with the first ions, and the second source region is doped with second ions. The technical scheme solves the problem of bottom parasitic channel current leakage of the surrounding gate MOSFET device, and by additionally arranging the second source region and the second drain region, a tunneling field effect transistor (TFET) device structure is connected in parallel at the bottom of the traditional surrounding gate MOSFET device, so that the surrounding gate channel diffusion drift current and the bottom channel band-to-band tunneling current are hybridly conducted, and better super-steep switching characteristics are obtained.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a hybrid conduction mechanism gate-around transistor and its fabrication method. Background Technology

[0002] Since the birth of integrated circuits, microelectronic integration technology has been developing according to Moore's Law. With the shrinking size of complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs), the switching speed, density, functionality, and cost of microprocessors have significantly improved. However, device power consumption remains one of the major challenges in the miniaturization process. The main technical approach to reducing device power consumption is to enhance the gate control capability. Following fin transistors, gate-all-around nanowire / nanosheet FETs have become the next-generation mainstream logic device structure due to their superior channel gate control capability. Due to process variations, gate-all-around nanowire devices suffer from severe parasitic channel leakage at the bottom. Suppressing off-state leakage current has become one of the key challenges in optimizing gate-all-around devices.

[0003] Another effective way to reduce device power consumption is to decrease the supply voltage VDD. Traditional MOSFET devices have a theoretical limit of 60mV / dec at room temperature due to the thermodynamic distribution of kT / q, which prevents ULSI chips based on traditional MOSFETs from continuously reducing the supply voltage. Tunneling field-effect transistors (TFETs) have become one of the most promising devices for future ultra-low power integrated circuit applications due to their excellent subthreshold characteristics, low off-state leakage current, and low switching power consumption. Because their conduction mechanism is quantum mechanical band-to-band tunneling, tunneling transistors are not limited by thermodynamic temperature, and their subthreshold swing can break the 60mV / dec limit at room temperature. Therefore, developing a transistor that can effectively suppress bottom leakage current while significantly improving the device's subthreshold characteristics has become a key technical focus that those skilled in the art urgently need to address. Summary of the Invention

[0004] This invention provides a hybrid conduction mechanism gate-around transistor and its fabrication method to solve the problem of parasitic channel current leakage at the bottom of gate-around MOSFET devices.

[0005] According to a first aspect of the present invention, a hybrid conduction mechanism gate-around transistor is provided, comprising:

[0006] A gate-around MOSFET device includes a substrate, a first source region, and a first drain region; the first source region and the first drain region are arranged along a first direction; wherein the first source region and the first drain region are doped with a first ion; wherein the first direction is characterized as a direction parallel to the substrate.

[0007] A second source region and a second drain region are formed between the substrate and the first source region, and the second drain region is formed between the substrate and the first drain region, and the height of the second source region and the second drain region is not lower than the height of the substrate between the first source region and the first drain region;

[0008] The second drain region is doped with a first ion, and the second source region is doped with a second ion, wherein the type of the first ion is different from the type of the second ion.

[0009] Optionally, the thickness of the second source region and / or the second drain region is 5nm-50nm.

[0010] Optionally, the first ion is a P-type ion or an N-type ion.

[0011] Optionally, the second ion is a P-type ion or an N-type ion.

[0012] Optionally, the ion concentration doped in the second source region and / or the second drain region is 1E16cm-3-1E22cm-3.

[0013] Optionally, the material of the second source region and the material of the second drain region are binary or ternary compounds of the II-VI, III-V or IV-IV groups.

[0014] Optionally, the material of the second source region and the material of the second drain region are Si, SiGe, or Ge.

[0015] Optionally, the gate-around MOSFET device further includes:

[0016] A channel layer is formed between the first source region and the first drain region, and is spaced apart in a direction away from the substrate;

[0017] A gate dielectric layer and a control gate, wherein the gate dielectric layer partially encloses the surface of the channel layer; and the control gate encloses the surface of the gate dielectric layer.

[0018] Inner walls are formed on the surface of the channel layer between the first source region and the gate dielectric layer, and between the first drain region and the gate dielectric layer;

[0019] A source metal layer, a gate metal layer, and a drain metal layer; the source metal layer and the drain metal layer are respectively formed on the surfaces of the first source region and the first drain region, and respectively completely enclose the first source region and the second source region and the first drain region and the second drain region; the gate metal layer is formed at the top of the control gate;

[0020] An interlayer dielectric layer covers the surfaces of the source metal layer, the gate metal layer, the drain metal layer, and the inner sidewall;

[0021] A metal contact layer extends through the interlayer dielectric layer and connects the source metal layer, the gate metal layer, and the drain metal layer.

[0022] According to a second aspect of the present invention, a method for fabricating a hybrid conduction mechanism gate-around transistor is provided, for fabricating the hybrid conduction mechanism gate-around transistor as described in any one of the first aspects of the present invention, comprising:

[0023] The gate-all-around MOSFET device is formed with a second source region and a second drain region; wherein the gate-all-around MOSFET device includes the substrate, a first source region, and a first drain region; wherein the first source region and the first drain region are doped with the first ions; the second source region and the second drain region are respectively formed between the substrate and the first source region, and between the substrate and the first drain region, and the height of the second source region and the second drain region is not less than the height of the substrate between the first source region and the first drain region;

[0024] The second drain region is doped with the first ion, and the second source region is doped with the second ion.

[0025] Optionally, forming the gate-all-around MOSFET device and the second source region and the second drain region specifically includes:

[0026] Provide one of the aforementioned substrates;

[0027] A sacrificial layer and a channel layer are formed; the sacrificial layer and the channel layer are stacked on the substrate at intervals;

[0028] The sacrificial layer and the channel layer are etched to form a fin structure, and the substrate on both sides of the fin structure along the first direction is over-etched to form a first cavity and a second cavity; wherein the first cavity and the second cavity are arranged sequentially along the first direction;

[0029] A false gate structure is formed, and the two ends of the sacrificial layer along the first direction are etched to form an inner sidewall cavity;

[0030] The inner wall is formed; the inner wall is formed in the cavity of the inner wall;

[0031] The second source region and the second drain region are formed; the second source region is formed in the first cavity, and the second drain region is formed in the second cavity;

[0032] The first source region and the first drain region are formed; the first source region and the first drain region are respectively formed at the top of the second source region and the second drain region;

[0033] Remove the dummy gate structure and release the channel layer;

[0034] The gate dielectric layer, the control gate, the source metal layer, the gate metal layer, the drain metal layer, the interlayer dielectric layer, and the metal contact layer are formed.

[0035] Optionally, forming the second source region and the second drain region specifically includes:

[0036] A patterned first mask layer is formed; the patterned first mask layer covers the surfaces of the second cavity, the dummy gate structure, and the inner wall;

[0037] The material of the second source region is filled into the first cavity to form the second source region, and the patterned first mask layer is removed;

[0038] A patterned second mask layer is formed; the patterned second mask layer covers the surface of the second source region, the dummy gate structure, and the inner wall;

[0039] The material filling the second drain area in the second cavity forms the second drain area, and the patterned second mask layer is removed.

[0040] According to a third aspect of the present invention, an electronic device is provided, comprising a hybrid conduction mechanism gate-around transistor as described in any of the first aspects of the present invention.

[0041] According to a fourth aspect of the present invention, a method for manufacturing an electronic device is provided, comprising the method for manufacturing a hybrid conduction mechanism gate-around transistor as described in any of the second aspects of the present invention.

[0042] The present invention provides a hybrid conduction mechanism gate-all-around transistor, wherein a second source region and a second drain region are respectively disposed between a first source region and a substrate, and between a first drain region and a substrate. The second drain region is doped with a first ion, and the second source region is doped with a second ion, and the types of the first ion and the second ion are different, so as to form a reverse bias PIN channel at the bottom. This structure can significantly suppress the bottom parasitic channel leakage current of conventional gate-all-around MOSFET devices, thereby enhancing the current switching ratio of the device.

[0043] Furthermore, the hybrid conduction mechanism gate-all-around transistor structure provided by this invention, due to the addition of a second source region and a second drain region, is equivalent to a tunneling field-effect transistor (TFET) device structure connected in parallel at the bottom of a conventional gate-all-around MOSFET device. Therefore, it can achieve mixed conduction of the gate-all-around channel diffusion drift current and the bottom channel quantum mechanical band tunneling current, thereby obtaining an ultra-steep switching characteristic of less than 60mV / dec. Simultaneously, the conduction of the gate-all-around MOSFET device connected in parallel above can provide a large current to the device. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram of a hybrid conduction mechanism gate-around transistor according to an embodiment of the present invention;

[0046] Figure 2 This is a schematic flowchart of a method for fabricating a hybrid conduction mechanism gate-around transistor according to an embodiment of the present invention;

[0047] Figure 3-6 This is a schematic diagram of the device structure at different process stages fabricated according to a method for fabricating a hybrid conduction mechanism gate-around transistor, provided in an embodiment of the present invention.

[0048] Explanation of reference numerals in the attached figures:

[0049] 101-Substrate;

[0050] 102 - First Source Region;

[0051] 103 - First leak zone;

[0052] 104 - Second Source Region;

[0053] 105 - Second leak zone;

[0054] 106-channel layer;

[0055] 107 - Gate dielectric layer;

[0056] 108 - Control gate;

[0057] 109 - Drain metal layer;

[0058] 110 - Gate metal layer;

[0059] 111-Source metal layer;

[0060] 112 - Interlayer dielectric layer;

[0061] 113 - Metal interconnect layer;

[0062] 114 - Inner wall;

[0063] 115-Dummy gate structure;

[0064] 116 - Photoresist. Detailed Implementation

[0065] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0066] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0067] Since the birth of integrated circuits, microelectronic integration technology has been developing according to Moore's Law. With the shrinking size of complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs), the switching speed, density, functionality, and cost of microprocessors have significantly improved. However, device power consumption remains one of the major challenges in the miniaturization process. The main technical approach to reducing device power consumption is to enhance the gate control capability. Following fin transistors, gate-all-around nanowire / nanosheet FETs have become the next-generation mainstream logic device structure due to their superior channel gate control capability. Due to process variations, gate-all-around nanowire devices suffer from severe parasitic channel leakage at the bottom. Suppressing off-state leakage current has become one of the key challenges in optimizing gate-all-around devices.

[0068] Another effective way to reduce device power consumption is to decrease the supply voltage VDD. Traditional MOSFET devices have a theoretical limit of 60mV / dec at room temperature due to the thermodynamic distribution of kT / q, which prevents ULSI chips based on traditional MOSFETs from continuously reducing the supply voltage. Tunneling field-effect transistors (TFETs), with their excellent subthreshold characteristics, low off-state leakage current, and low switching power consumption, have become one of the most promising devices for future ultra-low power integrated circuit applications. Because their conduction mechanism is quantum mechanical band-to-band tunneling, which is not limited by thermodynamic temperature, the subthreshold swing of TFETs can break the 60mV / dec limit at room temperature.

[0069] In view of this, the inventors of this application have added a source region and a drain region to the bottom parasitic channel to form a structure similar to a tunneling transistor at the bottom of the gate-all-around nanowire / nanosheet field-effect transistor; the new structure of the hybrid conduction mechanism gate-all-around field-effect transistor combining the tunneling transistor and the gate-all-around nanowire / nanosheet field-effect transistor can effectively suppress the bottom leakage current and at the same time significantly improve the subthreshold characteristics of the device.

[0070] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0071] Please refer to Figures 1-6 According to an embodiment of the present invention, a hybrid conduction mechanism gate-around transistor is provided, comprising:

[0072] A gate-all-around MOSFET device includes a substrate 101, a first source region 102, and a first drain region 103; the first source region 102 and the first drain region 103 are arranged along a first direction; wherein the first source region 102 and the first drain region 103 are doped with first ions; wherein the first direction is characterized as a direction parallel to the substrate 101.

[0073] A second source region 104 and a second drain region 105 are formed between the substrate 101 and the first source region 102, and the second drain region 105 is formed between the substrate 101 and the first drain region 103. The height of the second source region 104 and the second drain region 105 is not lower than the height of the substrate 101 between the first source region 102 and the first drain region 103.

[0074] In this configuration, the second drain region 105 is doped with a first ion, and the second source region 104 is doped with a second ion, wherein the type of the first ion is different from the type of the second ion, such as... Figure 1 As shown.

[0075] The second source region and the second drain region can both be a single structural layer or multiple structural layers; the present invention is not limited to these.

[0076] The present invention provides a hybrid conduction mechanism gate-all-around transistor. Compared with existing gate-all-around MOSFET devices, a second source region and a second drain region are respectively disposed between the first source region and the substrate, and between the first drain region and the substrate. The second drain region is doped with a first ion, and the second source region is doped with a second ion. The types of the first ions and the second ions are different. In the off state, a reverse bias PIN channel is formed at the bottom. This structure can significantly suppress the bottom parasitic channel leakage current of traditional gate-all-around MOSFET devices, thereby enhancing the current switching ratio of the device.

[0077] Furthermore, the hybrid conduction mechanism gate-all-around transistor structure provided by this invention, due to the addition of a second source region and a second drain region, is equivalent to a parallel tunneling field-effect transistor (TFET) structure of a conventional gate-all-around MOSFET device. Therefore, in the on-state, the gate-all-around channel diffusion drift current and the bottom channel quantum mechanical band tunneling current can be mixed and conducted, thereby achieving an ultra-steep switching characteristic of less than 60mV / dec for the entire device. At the same time, in the on-state, the gate-all-around MOSFET device connected in parallel above conducts, providing a large current to the device.

[0078] In one embodiment, the first ion is a P-type ion or an N-type ion.

[0079] In one embodiment, the second ion is a P-type ion or an N-type ion.

[0080] Specifically, the P-type ions are: hydrides, fluorides, or chlorides of boron, specifically one or a combination of the following materials: B2H6, B4H10, B6H10, B10H14, B18H22, BF3, or BCl3; the N-type ions are: hydrides and fluorides of phosphorus and arsenic, specifically one or a combination of the following materials: phosphine, arsine, phosphorus pentafluoride, phosphorus trifluoride, arsenic pentafluoride, or arsenic trifluoride.

[0081] The channel region and the bottom Fin region (i.e., the substrate 101 between the second source region 104 and the second drain region 105) are undoped or lightly doped i-regions;

[0082] For the N-type device, the first source region 102 is N-type doped with a doping concentration of approximately 1E18cm⁻³-1E22cm⁻³, the first drain region 103 is N-type doped with a doping concentration of approximately 1E18cm⁻³-1E22cm⁻³, the second source region 104 is P-type doped with a doping concentration of approximately 1E18cm⁻³-1E22cm⁻³, and the second drain region 105 is N-type doped with a doping concentration of approximately 1E16cm⁻³-1E21cm⁻³.

[0083] For the P-type device, the first source region 102 is P-type doped with a doping concentration of approximately 1E18cm⁻³-1E22cm⁻³, the first drain region 103 is P-type doped with a doping concentration of approximately 1E18cm⁻³-1E20cm⁻³, the second source region 104 is N-type doped with a doping concentration of approximately 1E18cm⁻³-1E22cm⁻³, and the second drain region 105 is P-type doped with a doping concentration of approximately 1E16cm⁻³-1E21cm⁻³.

[0084] In the hybrid conduction mechanism gate-all-around transistor, the thickness and doping concentration of the second source and second drain regions are important parameters for device design. If the thickness of the second source or second drain region is too thin, the bottom tunneling field-effect transistor has a small impact on the total current, and the improvement on the subthreshold swing characteristics of the device is limited; if the thickness of the second source or second drain region is too thick, it will increase the difficulty of the process and lead to a decrease in device consistency and reliability. The doping concentration of the second source region cannot be too low. If the doping concentration is too low, the resistance of the second source region will increase, and the lower doping will reduce the tunneling probability of the bottom tunneling transistor, making band-to-band tunneling more difficult and the current will decrease. The doping concentration of the second drain region also needs to be controlled within a certain range. If the doping concentration is too low, the resistance of the bottom drain region will increase and the current will decrease; if the doping concentration is too high, the channel bipolar effect of the TFET device will be more significant. Therefore, in a preferred embodiment, the thickness of the second source region 104 and / or the second drain region 105 is 5nm-50nm. In a preferred embodiment, the doped ion concentration in the second source region 104 and / or the second drain region 105 is 1E16cm-3-1E22cm-3.

[0085] In one embodiment, the material of the second source region 104 and the material of the second drain region 105 are binary or ternary compounds of group II-VI, III-V or IV-IV.

[0086] In one embodiment, the material of the second source region 104 and the material of the second drain region 105 are Si, SiGe, or Ge.

[0087] In one embodiment, the gate-around MOSFET device further includes:

[0088] A channel layer 106 is formed between the first source region 102 and the first drain region 103, and is spaced apart along a direction away from the substrate 101;

[0089] A gate dielectric layer 107 and a control gate 108 are provided, wherein the gate dielectric layer 107 covers a portion of the surface of the channel layer 106; and the control gate 108 covers the surface of the gate dielectric layer 107.

[0090] Inner wall 114 is formed on the surface of the channel layer 106 between the first source region 102 and the gate dielectric layer 107, and between the first drain region 103 and the gate dielectric layer 107.

[0091] Source metal layer 111, gate metal layer 110 and drain metal layer 109;

[0092] In one embodiment, the source metal layer 111 and the drain metal layer 109 are respectively formed on the surfaces of the first source region 102 and the first drain region 103, and respectively completely cover the first source region 102 and the first drain region 103; the gate metal layer 110 is formed on the top of the control gate 108;

[0093] Since the additional parasitic resistance from the second source / drain region leads is detrimental to the steep subthreshold swing characteristics of the device, in a preferred embodiment, the source metal layer 111 and the drain metal layer 109 are respectively formed on the surfaces of the first source region 102 and the first drain region 103, and respectively completely enclose the first source region 102 and the second source region 104 and the first drain region 103 and the second drain region 105; the gate metal layer 110 is formed on the top of the control gate 108; the interlayer dielectric layer 112 covers the surfaces of the source metal layer 111, the gate metal layer 110, the drain metal layer 109, and the inner sidewall 114;

[0094] The metal contact layer 113 penetrates the interlayer dielectric layer 112 and is connected to the source metal layer 111, the gate metal layer 110 and the drain metal layer 109 respectively.

[0095] According to other embodiments of the present invention, a method for fabricating a hybrid conduction mechanism gate-around transistor is also provided, for fabricating the hybrid conduction mechanism gate-around transistor as described in any of the foregoing embodiments of the present invention, comprising:

[0096] The gate-all-around MOSFET device is formed with a second source region 104 and a second drain region 105; wherein the gate-all-around MOSFET device includes a substrate 101, a first source region 102, and a first drain region 103; wherein the first source region 102 and the first drain region 103 are doped with the first ions; the second source region 104 and the second drain region 105 are respectively formed between the substrate 101 and the first source region 102, and between the substrate 101 and the first drain region 103, and the height of the second source region 104 and the second drain region 105 is not lower than the height of the substrate 101 between the first source region 102 and the first drain region 103;

[0097] The second drain region 105 is doped with the first ion, and the second source region 104 is doped with the second ion.

[0098] In one embodiment, a schematic flowchart of the fabrication method of the gate-all-around MOSFET device, the second source region 104, and the second drain region 105, is shown below. Figure 2 As shown, the method specifically includes:

[0099] S11: Provide one of the substrates 101;

[0100] S12: Forming a sacrificial layer and the channel layer 106; the sacrificial layer and the channel layer 106 are stacked on the substrate 101 with a gap; specifically, the material of the sacrificial layer is SiGe, and the material of the channel layer 106 is Si; in a specific embodiment, the sacrificial layer and the channel layer 106 have the following crystal orientations: <100> The Si / SiGe stack has a thickness of approximately 10-20 nm per layer.

[0101] In one embodiment, the sacrificial layer and the channel layer 106 are lightly doped; specifically, the range of light doping in the Si / SiGe stack is 1E13cm-3 to 1E15cm-3.

[0102] In other embodiments, the sacrificial layer and the channel layer 106 are not doped with ions;

[0103] S13: Etch the sacrificial layer and the channel layer 106 to form a fin structure, the length of the control device channel is about 50nm-100nm, and over-etch the substrate 101 on both sides of the fin structure along the first direction to form a first cavity and a second cavity; wherein, the first cavity and the second cavity are arranged sequentially along the first direction;

[0104] Step S13, after forming the fin structure, further includes: using photolithography to perform STI isolation patterning to form an STI structure; wherein, the depth of photolithography is approximately 5nm-50nm, and the material of the STI structure is SiO2;

[0105] S14: Form a dummy gate structure 115 and etch the two ends of the sacrificial layer along the first direction to form an inner sidewall 114 cavity; specifically, the material of the dummy gate structure 115 is polycrystalline silicon; the method used to form the dummy gate structure 115 is: atomic layer deposition, chemical vapor deposition or physical vapor deposition; the thickness of the dummy gate structure 115 is 50nm;

[0106] S15: Forming the inner sidewall 114; the inner sidewall 114 is formed in the cavity of the inner sidewall 114; specifically, the material of the inner sidewall 114 is selected from SiO2, Si3N4 or other low-k dielectric materials; the method of forming the inner sidewall 114 is similar to the method of forming the dummy gate structure 115, and will not be described in detail here. Figure 3 As shown;

[0107] In one embodiment, step S16, the second source region 104 and the second drain region 105, specifically includes:

[0108] S161: Form a patterned first mask layer; the patterned first mask layer covers the surfaces of the second cavity, the dummy gate structure 115, and the inner sidewall 114;

[0109] S162: The material of the second source region 104 is filled into the first cavity to form the second source region 104, and the patterned first mask layer is removed, as follows. Figure 4 As shown;

[0110] In one embodiment, the second source region 104 is doped with B ions at a concentration of approximately 1E21cm⁻¹. -3 ;

[0111] S163: Form a patterned second mask layer; the patterned second mask layer covers the surfaces of the second source region 104, the dummy gate structure 115, and the inner sidewall 114; the second patterned mask layer and the first patterned mask layer are photoresist 116;

[0112] S164: The material filling the second drain area 105 in the second cavity forms the second drain area 105, and the patterned second mask layer is removed, as shown. Figure 5 As shown;

[0113] In one embodiment, the materials of the second source region 104 and the second drain region 105 are: SiGe and Si:C;

[0114] In particular, since the second source region 104 and the second drain region 105 of the device are SiGe / Si:C epitaxial, it is beneficial to increase the probability of band tunneling of the channel material.

[0115] In one embodiment, the second drain region 105 is doped with As ions at a concentration of approximately 1E18 cm⁻¹. -3 .

[0116] In one embodiment, the method used to form the second source region 104 or the second drain region 105 is: in-situ epitaxy, atomic layer deposition, or chemical vapor deposition.

[0117] In one embodiment, the method for highly doping the first source region 102 or the second source region 104 is selected from one of the following methods: in-situ doping, ion implantation, or solid-state source doping.

[0118] S16: Form the second source region 104 and the second drain region 105; the second source region 104 is formed in the first cavity, and the second drain region 105 is formed in the second cavity;

[0119] S17: Form the first source region 102 and the first drain region 103; the first source region 102 and the first drain region 103 are respectively formed at the top of the second source region 104 and the second drain region 105;

[0120] In one embodiment, the materials of the first source region 102 and the first drain region 103 are SiGe and Si:C.

[0121] In this embodiment, since the first source region 102 and the first drain region 103 of the device are SiGe / Si:C epitaxial, stress will be further applied to the gate-around nanowire / nanosheet channel, which is beneficial to increasing the carrier mobility of the channel material. In one specific embodiment, the first source region 102 and the first drain region 103 are in-situ doped with As ions at a concentration of approximately 1E21cm³. -3 The process after doping with ions also includes: a rapid high-temperature annealing and activation of the implanted impurities (1050℃, 10s).

[0122] S18: Remove the dummy gate structure 115 and release the channel layer 106, as follows. Figure 6 As shown;

[0123] S19: Form the gate dielectric layer 107, the control gate 108, the source metal layer 111, the gate metal layer 110, the drain metal layer 109, the interlayer dielectric layer 112, and the metal contact layer 113. Specifically, the material of the gate dielectric layer 107 is SiO2, Si3N4, or a high-k gate dielectric material; the material of the control gate 108 is selected from doped polysilicon, cobalt, nickel, and other metals or metal silicides.

[0124] The material of the gate dielectric layer 107 is grown by: conventional thermal oxidation, nitrogen-doped thermal oxidation, atomic layer deposition, or chemical vapor deposition.

[0125] In one specific embodiment, the gate dielectric layer 107 is made of HfO2 with a thickness of 1~5nm; the gate material is a TiN layer with a thickness of 50~200nm.

[0126] Secondly, according to an embodiment of the present invention, an electronic device is also provided, including a hybrid conduction mechanism gate-around transistor as described in any of the foregoing embodiments of the present invention.

[0127] In addition, according to an embodiment of the present invention, a method for manufacturing an electronic device is also provided, including the method for manufacturing a hybrid conduction mechanism gate-around transistor as described in any of the foregoing embodiments of the present invention.

[0128] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A hybrid turn-on mechanism surround gate transistor, comprising: include: A gate-around MOSFET device includes a substrate, a first source region, and a first drain region; the first source region and the first drain region are arranged along a first direction; wherein the first source region and the first drain region are doped with a first ion; wherein the first direction is a direction parallel to the substrate. A second source region and a second drain region are formed between the substrate and the first source region, and the second drain region is formed between the substrate and the first drain region, and the height of the second source region and the second drain region is not lower than the height of the substrate between the first source region and the first drain region; The second drain region is doped with a first ion, the second source region is doped with a second ion, and the type of the first ion is different from the type of the second ion. A channel layer is formed between the first source region and the first drain region, and is spaced apart along a direction away from the substrate; A gate dielectric layer and a control gate, wherein the gate dielectric layer covers a portion of the surface of the channel layer; and the control gate covers the surface of the gate dielectric layer.

2. The hybrid turn-on mechanism surround-gate transistor of claim 1, wherein, The thickness of the second source region and / or the second drain region is 5nm-50nm.

3. The hybrid pass-through gatekeeper transistor of claim 1, wherein, The first ion is a P-type ion or an N-type ion.

4. The hybrid conduction mechanism gate-around transistor according to claim 1, characterized in that, The second ion is a P-type ion or an N-type ion.

5. The hybrid pass-through gatekeeper transistor of claim 1, wherein, The ion concentration in the second source region and / or the second drain region is 1E16cm. -3 -1E22cm -3 .

6. The hybrid pass-through gatekeeper transistor of claim 1, wherein, The material of the second source region and the material of the second drain region are binary or ternary compounds of the II-VI, III-V or IV-IV groups.

7. The hybrid conduction mechanism gate-around transistor according to claim 6, characterized in that, The material of the second source region and the material of the second drain region are Si, SiGe, or Ge.

8. The hybrid pass-through gatekeeper transistor of claim 1, wherein, The gate-around MOSFET device further includes: Inner walls are formed on the surface of the channel layer between the first source region and the gate dielectric layer, and between the first drain region and the gate dielectric layer; A source metal layer, a gate metal layer, and a drain metal layer; the source metal layer and the drain metal layer are respectively formed on the surfaces of the first source region and the first drain region, and respectively completely enclose the first source region and the second source region and the first drain region and the second drain region; the gate metal layer is formed at the top of the control gate; An interlayer dielectric layer covers the surfaces of the source metal layer, the gate metal layer, the drain metal layer, and the inner sidewall; A metal contact layer extends through the interlayer dielectric layer and connects the source metal layer, the gate metal layer, and the drain metal layer.

9. A method for fabricating a hybrid conduction mechanism gate-all-around transistor, for fabricating the hybrid conduction mechanism gate-all-around transistor of any one of claims 1-8, the method comprising: include: ​ The gate-all-around MOSFET device is formed with a second source region and a second drain region; wherein the gate-all-around MOSFET device includes the substrate, a first source region, and a first drain region; wherein the first source region and the first drain region are doped with the first ions; the second source region and the second drain region are respectively formed between the substrate and the first source region, and between the substrate and the first drain region, and the height of the second source region and the second drain region is not less than the height of the substrate between the first source region and the first drain region; The second drain region is doped with the first ion, and the second source region is doped with the second ion.

10. The method of claim 9, wherein the step of forming the hybrid access mechanism surrounding gate transistor is performed by: The formation of the gate-all-around MOSFET device, the second source region, and the second drain region specifically includes: Provide one of the aforementioned substrates; A sacrificial layer and a channel layer are formed; the sacrificial layer and the channel layer are stacked on the substrate at intervals; The sacrificial layer and the channel layer are etched to form a fin structure, and the substrate on both sides of the fin structure along the first direction is over-etched to form a first cavity and a second cavity; wherein the first cavity and the second cavity are arranged sequentially along the first direction; A false gate structure is formed, and the two ends of the sacrificial layer along the first direction are etched to form an inner sidewall cavity; An inner sidewall is formed; the inner sidewall is formed in the cavity of the inner sidewall; The second source region and the second drain region are formed; the second source region is formed in the first cavity, and the second drain region is formed in the second cavity; The first source region and the first drain region are formed; the first source region and the first drain region are respectively formed at the top of the second source region and the second drain region; Remove the dummy gate structure and release the channel layer; The gate dielectric layer, control gate, source metal layer, gate metal layer, drain metal layer, interlayer dielectric layer, and metal contact layer are formed.

11. The method of claim 10, wherein: The formation of the second source region and the second drain region specifically includes: A patterned first mask layer is formed; the patterned first mask layer covers the surfaces of the second cavity, the dummy gate structure, and the inner wall; The material of the second source region is filled into the first cavity to form the second source region, and the patterned first mask layer is removed; A patterned second mask layer is formed; the patterned second mask layer covers the surface of the second source region, the dummy gate structure, and the inner wall; The material filling the second drain area in the second cavity forms the second drain area, and the patterned second mask layer is removed.

12. An electronic device, comprising: Includes the hybrid conduction mechanism gate-around transistor as described in any one of claims 1-8.

13. A method for manufacturing an electronic device, characterized in that, The method for fabricating a hybrid conduction mechanism gate-around transistor as described in any one of claims 9-11.

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