ESD protection circuit with stable discharge mechanism

Abstract

An electrostatic protection circuit with a stable discharge mechanism. A voltage divider circuit generates a detection signal based on a voltage input terminal, and a first inverter outputs an inverted detection signal. A first P-type and an N-type transistor circuit are connected in series between the voltage input terminal and the ground terminal through a first terminal. A second N-type transistor circuit is coupled between a second terminal and the ground terminal. The first P-type transistor control terminal is coupled to the second terminal, and the first and second N-type transistor control terminals receive an inverted detection signal and a detection signal, respectively. The resistor and capacitor of the capacitive circuit are connected in series between the voltage input terminal and the ground terminal through a control terminal, and the control terminal is coupled to the second terminal. The second inverter receives an inverted lift detection signal from the control terminal and outputs it inverted as a lift detection signal. The electrostatic discharge transistor is controlled by the lift detection signal to discharge the voltage input terminal when it is turned on.

Description

Technical Field

[0001] The present invention relates to electrostatic protection technology, and in particular to an electrostatic protection circuit with a stable discharge mechanism. Background Art

[0002] Electrostatic discharge (ESD) can cause permanent damage to electronic components and equipment, thereby affecting the circuit functions of integrated circuits and causing products to malfunction.

[0003] Electrostatic discharge (ESD) can occur during chip manufacturing, packaging, testing, storage, or transportation. To recreate and prevent ESD, integrated circuit products can incorporate ESD-protected components or circuits and incorporate testing to enhance their ESD protection capabilities, thereby improving the yield of electronic products. Summary of the Invention

[0004] In view of the problems of the prior art, one object of the present invention is to provide an electrostatic protection circuit with a stable discharge mechanism to improve the prior art.

[0005] The present invention includes an electrostatic protection circuit with a stable discharge mechanism, comprising: a voltage divider circuit, a first inverter, a voltage boost circuit, a capacitance circuit, a second inverter, and an electrostatic discharge transistor. The voltage divider circuit is electrically coupled to a voltage input terminal configured to receive a power supply signal to generate a detection signal at the voltage divider terminal. The first inverter is configured to receive the detection signal and invert it to output an inverted detection signal. The voltage boost circuit includes: a first P-type transistor circuit, a first N-type transistor circuit, and a second N-type transistor circuit. The first P-type transistor circuit and the first N-type transistor circuit are connected in series between the voltage input terminal and the ground terminal via a first terminal, and each circuit includes a first P-type transistor control terminal electrically coupled to the second terminal and a first N-type transistor control terminal configured to receive the inverted detection signal. The second N-type transistor circuit is electrically coupled between the second terminal and the ground terminal and includes a second N-type transistor control terminal configured to receive the detection signal. The capacitance circuit includes a resistor electrically coupled between the voltage input terminal and the control terminal, and a capacitor electrically coupled between the control terminal and the ground terminal, wherein the control terminal is electrically coupled to the second terminal. The second inverter is electrically coupled between the voltage input terminal and the ground terminal, and is configured to receive the inverted rise detection signal from the control terminal and invert it to output the rise detection signal. The electrostatic discharge transistor is electrically coupled between the voltage input terminal and the ground terminal, and is configured to be controlled by the rise detection signal to discharge the voltage input terminal when turned on.

[0006] The features, implementation and effects of the present invention are described in detail below with reference to the drawings for preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A circuit diagram showing an electrostatic protection circuit with a stable discharge mechanism according to an embodiment of the present invention; and

[0008] Figure 2 A circuit diagram showing an electrostatic protection circuit with a stable discharge mechanism in another embodiment of the present invention. DETAILED DESCRIPTION

[0009] One of the purposes of the present invention is to provide an electrostatic protection circuit with a stable discharge mechanism. By setting up a voltage divider circuit to directly detect voltage changes, a quick response can be achieved and a sufficiently long discharge time can be maintained, thereby stabilizing the discharge of the discharge transistor. The switching of the electrostatic discharge transistor is further stabilized by setting up a capacitive resistor circuit at the back end.

[0010] Please refer to Figure 1 . Figure 1 The following is a circuit diagram showing an ESD protection circuit 100 with a stable discharge mechanism according to an embodiment of the present invention. The ESD protection circuit 100 includes a voltage divider circuit 110, a first inverter 120, a voltage boost circuit 130, a capacitance circuit 140, a second inverter 150, and an ESD transistor 160.

[0011] The voltage divider circuit 110 is electrically coupled to a voltage input terminal IO configured to receive a power signal PS, so as to generate a detection signal DS at a voltage divider terminal DT.

[0012] In one embodiment, the voltage divider circuit 110 includes a first resistive circuit 115A and a second resistive circuit 115B, which are connected in series between the voltage input terminal IO and the ground terminal GND via the voltage divider terminal DT.

[0013] The first resistive circuit 115A includes a resistor, a diode, a diode-connected transistor, or a combination thereof. The number of the above elements can be one or more, and when the number is multiple, they can be connected in series. Figure 1 In the figure, the first resistive circuit 115A is exemplarily illustrated as a plurality of diode-connected P-type transistors, and the second resistive circuit 115B is exemplarily illustrated as a resistor. In other embodiments, the resistive circuit 115B may be implemented using other aforementioned elements, diode-connected N-type transistors, or a combination of the aforementioned elements. The present invention is not limited thereto.

[0014] In one embodiment, the ESD protection circuit 100 may be disposed in an electronic device (not shown) and receive a power signal PS through the voltage input terminal IO when the electronic device is operating. The ESD protection circuit 100 may generate a detection signal DS at the voltage divider terminal DT based on the resistance ratio between the first resistive circuit 115A and the second resistive circuit 115B.

[0015] The first inverter 120 operates based on a first voltage VDD1. The voltage boost circuit 130, the second inverter 150, and the ESD transistor 160 operate based on a second voltage VDD2. The first voltage VDD1 is lower than the second voltage VDD2. In one embodiment, the first voltage VDD1 is, for example, but not limited to, 0.9, 1.2, or 1.8 volts. The second voltage VDD2 is, for example, but not limited to, 3.3 volts.

[0016] In this embodiment, the second voltage VDD2 is generated based on the power signal PS. More specifically, in one embodiment, the voltage boost circuit 130, the second inverter 150, and the ESD transistor 160 can be electrically coupled to the voltage input terminal 10 to receive the power signal PS. Other circuit components can be included between these components and the voltage input terminal 10 without affecting the overall functionality of the ESD protection circuit 110.

[0017] In different embodiments, the first voltage VDD1 can be selectively generated by another independent power signal (not shown), or generated by voltage division of the power signal PS.

[0018] Therefore, the internal components (e.g., transistors) of the first inverter 120 have relatively low threshold voltages, while the internal components (e.g., transistors) of the voltage boosting circuit 130, the second inverter 150, and the ESD transistor 160 have relatively high threshold voltages. The first inverter 120 has a higher response speed than the voltage boosting circuit 130, the second inverter 150, and the ESD transistor 160.

[0019] The first inverter 120 is configured to receive the detection signal DS and invert the received signal to output an inverted detection signal IDS.

[0020] The voltage boost circuit 130 is configured to generate an inverted boosted detection signal IBDS according to the detection signal DS and the inverted detection signal IDS. In one embodiment, the voltage boost circuit 130 includes a first P-type transistor circuit 170A, a first N-type transistor circuit 170B, and a second N-type transistor circuit 180A.

[0021] exist Figure 1 In the embodiment, the first P-type transistor circuit 170A includes a P-type transistor MP1, the first N-type transistor circuit 170B includes two first N-type transistors MN1 and a second N-type transistor MN2 connected in series, and the second N-type transistor circuit 180A includes two first N-type transistors MN3 and a second N-type transistor MN4 connected in series.

[0022] The first P-type transistor circuit 170A and the first N-type transistor circuit 170B are connected in series between the voltage input terminal IO and the ground terminal GND through the first terminal T1, and respectively have a first P-type transistor control terminal electrically coupled to the second terminal T2 and a first N-type transistor control terminal configured to receive the inverted detection signal IDS.

[0023] In more detail, Figure 1 In the embodiment, the source of the P-type transistor MP1 is electrically coupled to the voltage input terminal IO, the drain is electrically coupled to the first terminal T1, and the gate serves as the first P-type transistor control terminal and is electrically coupled to the second terminal T2. The drain of the first N-type transistor MN1 is electrically coupled to the first terminal T1, and the source is electrically coupled to the drain of the N-type transistor MN2. The drain of the second N-type transistor MN2 is electrically coupled to the source of the N-type transistor MN1, and the source is electrically coupled to the ground terminal GND. The gates of the first N-type transistor MN1 and the second N-type transistor MN2 are electrically coupled and serve as the first N-type transistor control terminal to receive the inverted detection signal IDS.

[0024] The second N-type transistor circuit 180A is electrically coupled between the second terminal T2 and the ground terminal GND, and comprises a second N-type transistor control terminal configured to receive the detection signal DS.

[0025] In more detail, Figure 1 In the embodiment, the drain of the N-type transistor MN3 is electrically coupled to the second terminal T2, and the source is electrically coupled to the drain of the N-type transistor MN4. The drain of the N-type transistor MN4 is electrically coupled to the source of the N-type transistor MN3, and the source is electrically coupled to the ground terminal GND. The gates of the N-type transistors MN3 and MN4 are electrically coupled to each other and serve as the second N-type transistor control terminal to receive the detection signal DS.

[0026] In one embodiment, the first N-type transistors MN1 and MN3 are I / O devices with a relatively high voltage withstand capability (e.g., 3.3 volts), while the second N-type transistors MN2 and MN4 are core devices with a relatively low voltage withstand capability (0.9, 1.2, or 1.8 volts). This configuration allows for greater reliability of the first N-type transistor circuit 170B and the second N-type transistor circuit 180A.

[0027] In one embodiment, the first N-type transistor circuit 170B may be further optionally provided with an N-type transistor (not shown) connected in series with the first N-type transistor MN1 and the second N-type transistor MN2 and controlled by another control signal. When the first voltage VDD1 and the second voltage VDD2 have different sources, the first N-type transistor circuit 170B is enabled according to the control signal only after both the first voltage VDD1 and the second voltage VDD2 are powered on. This prevents the first N-type transistor circuit 170B from experiencing an unknown signal state due to power-on sequencing. Similarly, the second N-type transistor circuit 180A may also have the same configuration, which will not be further described here.

[0028] The capacitance-resistance circuit 140 includes a resistor R electrically coupled between the voltage input terminal IO and the control terminal CT, and a capacitor C electrically coupled between the control terminal CT and the ground terminal GND, wherein the control terminal TC is electrically coupled to the second terminal T2.

[0029] The second inverter 150 is electrically coupled between the voltage input terminal IO and the ground terminal GND, and is configured to receive the inverted rise detection signal IBDS from the control terminal TC and output the inverted rise detection signal BDS.

[0030] The ESD transistor 160 is electrically coupled between the voltage input terminal 10 and the ground terminal GND and is configured to be controlled by the boost detection signal BDS to discharge the voltage input terminal 10 when turned on. In this embodiment, the ESD transistor 160 is an N-type transistor. In other embodiments, the ESD protection circuit 100 may further include another inverter between the ESD transistor 150 and the second inverter 140, and implement the ESD transistor 150 as a P-type transistor. The present invention is not limited to this.

[0031] The following describes the normal operation mode and the discharge mode of the electrostatic protection circuit 100 according to the voltage level of the voltage input terminal IO. Figure 1 In the figure, the logic level of the voltage is determined by "1" as a high state level and "0" as a low state level. The logic levels in normal operation mode and discharge mode are marked in sequence at each circuit node.

[0032] When the voltage at the voltage input terminal IO does not exceed a predetermined level, for example, when only the power signal PS is received and no static input ES, such as that caused by actual static electricity generation or electrical overshoot (EOS), is received, the ESD protection circuit 100 operates in a normal operation mode. At this time, the detection signal DS generated by the voltage divider circuit 110 at the voltage divider terminal DT is at a low level (0), while the inverted detection signal IDS is at a high level (1) due to the operation of the first inverter 120.

[0033] According to the inverted detection signal IDS at a high level and the detection signal DS at a low level, the first N-type transistor circuit 170B is turned on, and the first P-type transistor circuit 170A and the second N-type transistor circuit 180A are turned off.

[0034] More specifically, the first N-type transistor MN1 and the second N-type transistor MN2 in the first N-type transistor circuit 170B are turned on by the inverted detection signal IDS at a high level, drawing current from the first terminal T1 and causing the voltage of the first terminal T1 to drop to a low level (0). The first N-type transistor MN3 and the second N-type transistor MN4 in the second N-type transistor circuit 180A are turned off by the detection signal DS at a low level.

[0035] The capacitor C in the capacitance-resistance circuit 140 receives the charge from the voltage input terminal IO through the resistor R, causing the voltage of the control terminal CT to rise to a high-state level (1). Since the second N-type transistor circuit 180A is turned off, the control terminal CT will not discharge through the second terminal T2. Therefore, the voltage of the second terminal T2 will rise to a high-state level (1) together with the control terminal CT, thereby turning off the P-type transistor MP1 in the first P-type transistor circuit 170A.

[0036] The inverted rise detection signal IBDS generated by the control terminal CT is therefore at a high level (1). The rise detection signal BDS is at a low level (0) due to the operation of the second inverter 150, thereby turning off the ESD transistor 160.

[0037] On the other hand, when the voltage at the voltage input terminal IO exceeds a predetermined level, for example, when the power signal PS is received and an electrostatic input ES with a momentary high voltage is received, the electrostatic protection circuit 100 operates in a discharge mode. At this time, the detection signal DS generated by the voltage divider circuit 110 at the voltage divider terminal DT is at a high level (1), and the inverted detection signal IDS is at a low level (0) due to the operation of the first inverter 120.

[0038] According to the inverted detection signal IDS at a low level and the detection signal DS at a high level, the first N-type transistor circuit 170B is turned off, and the first P-type transistor circuit 170A and the second N-type transistor circuit 180A are turned on.

[0039] More specifically, the first N-type transistor MN3 and the second N-type transistor MN4 in the second N-type transistor circuit 180A are turned on by the detection signal DS at a high level, drawing current from the second terminal T2, causing the voltage at the second terminal T2 to drop to a low level (0), thereby turning on the P-type transistor MP1 in the first P-type transistor circuit 170A. The first N-type transistor MN1 and the second N-type transistor MN2 in the first N-type transistor circuit 170B are turned off by the inverted detection signal IDS at a low level, causing the first terminal T1 to receive the current from the P-type transistor MP1, causing the voltage at the first terminal T1 to rise to a high level (1).

[0040] The capacitor C in the capacitance-resistance circuit 140 is discharged through the control terminal CT and the second terminal T2 when the second N-type transistor circuit 180A is turned on, so that the voltage of the control terminal CT drops to a low level (0).

[0041] The inverted rise detection signal IBDS generated by the second terminal T2 is therefore at a low level (0). The rise detection signal BDS is at a high level (1) due to the operation of the second inverter 150, thereby turning on the ESD transistor 160 to discharge the voltage input terminal IO.

[0042] In the above operation, the time constant of the capacitance circuit 140 (the product of the resistance value of the resistor R and the capacitance value of the capacitor C) determines the high-frequency response time of the ESD protection circuit 100, while the voltage divider circuit 110 and the first inverter 120 determine the low-frequency response time of the ESD protection circuit 100.

[0043] It should be noted that when the ESD transistor 150 discharges the voltage input terminal IO for a period of time, causing the voltage of the voltage input terminal IO to drop and the detection signal DS generated by the voltage division to return to the low level (0), the ESD protection circuit 110 will also return to the normal operation mode.

[0044] In some technologies, the ESD protection circuit uses a capacitive resistor connected to the ESD input, which in turn controls an inverter to determine whether to activate the discharge transistor. The capacitive resistor is configured to use the frequency of the ESD input as a criterion for whether to activate the ESD discharge mechanism. If the ESD input is not long enough or even sufficiently high, the fully charged capacitive resistor will cause the inverter to react more slowly, resulting in a delayed turn-on and an inability to maintain the discharge mechanism long enough. Furthermore, in such conditions, the discharge transistor often relies on a breakdown mechanism to operate, resulting in uneven conduction.

[0045] Therefore, the electrostatic protection circuit of the present invention can directly detect voltage changes through the setting of a voltage divider circuit to achieve a rapid response and maintain a sufficiently long discharge time, thereby stabilizing the discharge of the discharge transistor and making the switching of the electrostatic discharge transistor more stable through the capacitance circuit set at the back end.

[0046] It should be noted that the number of transistors included in the first P-type transistor circuit 170A, the first N-type transistor circuit 170B, and the second N-type transistor circuit 180A is merely an example. In other embodiments, the number of transistors included in the above circuits can be adjusted according to actual needs, and the present invention is not limited thereto.

[0047] Please refer to Figure 2 . Figure 2 A circuit diagram of an electrostatic protection circuit 200 with a stable discharge mechanism is shown in another embodiment of the present invention.

[0048] Similar to Figure 1 The electrostatic protection circuit 100, Figure 2 The ESD protection circuit 200 includes a voltage divider circuit 110, a first inverter 120, a voltage boost circuit 130, a second inverter 150, and an ESD transistor 160. Furthermore, the voltage boost circuit 130 also includes a first P-type transistor circuit 170A, a first N-type transistor circuit 170B, and a second N-type transistor circuit 180A. Therefore, components with the same structure and operation will not be described in detail here.

[0049] In this embodiment, the ESD protection circuit 100 further includes a second P-type transistor circuit 180B. The second P-type transistor circuit 180B includes a P-type transistor MP2 electrically coupled between the voltage input terminal 10 and the second terminal T2 to be connected in series with the second N-type transistor circuit 180A, and has a second P-type transistor control terminal electrically coupled to the first terminal T1.

[0050] When the ESD protection circuit 100 operates in a normal operation mode, since the first terminal T1 is at a low state level (0), the P-type transistor MP2 in the second P-type transistor circuit 170A will be turned on, causing the second terminal T2 to receive current, thereby increasing the voltage of the second terminal T2 to a high state level (1). Conversely, when the ESD protection circuit 100 operates in a discharge mode, since the first terminal T1 is at a high state level (1), the P-type transistor MP2 in the second P-type transistor circuit 170A will be turned off, causing the second terminal T2 to drop to a low state level (0) under the operation of the second N-type transistor circuit 180A drawing current.

[0051] It should be noted that the number of transistors included in the second P-type transistor circuit 180B is merely an example. In other embodiments, the number of transistors included in the second P-type transistor circuit 180B can be adjusted according to actual needs, and the present invention is not limited thereto.

[0052] It should be noted that the above-mentioned implementation is only an example. In other embodiments, those skilled in the art may make changes without departing from the spirit of the present invention.

[0053] In summary, the electrostatic protection circuit with a stable discharge mechanism in the present invention can directly detect voltage changes through the setting of a voltage divider circuit to achieve a rapid response and maintain a sufficiently long discharge time, thereby stabilizing the discharge of the discharge transistor, and making the switching of the electrostatic discharge transistor more stable through the capacitance circuit set at the back end.

[0054] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art may modify the technical features of this case based on the explicit or implicit content of this case. All such modifications may fall within the scope of the patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application defined in this specification.

[0055]

Explanation of symbols

[0056] 100: Electrostatic protection circuit

[0057] 110: Voltage divider circuit

[0058] 115A: First resistive circuit

[0059] 115B: Second resistive circuit

[0060] 120: First inverter

[0061] 130: Voltage boost circuit

[0062] 140: Capacitive resistance circuit

[0063] 150: Second inverter

[0064] 160: ESD transistor

[0065] 170A: First P-type transistor circuit

[0066] 170B: First N-type transistor circuit

[0067] 180A: Second N-type transistor circuit

[0068] 180B: Second P-type transistor circuit

[0069] 200: Electrostatic protection circuit

[0070] BDS: lift detection signal

[0071] C: Capacitor

[0072] CT: Control terminal

[0073] DS: Detection Signal

[0074] DT: voltage divider terminal

[0075] GND: Ground

[0076] IBDS: Inverter rise detection signal

[0077] IDS: Inverted Detection Signal

[0078] IO: voltage input terminal

[0079] MN1, MN3: first N-type transistor

[0080] MN2, MN4: second N-type transistor

[0081] MP1, MP2: P-type transistors

[0082] PS: Power signal

[0083] R: resistance

[0084] T1: First end

[0085] T2: Second end

[0086] VDD1: first voltage

[0087] VDD2: second voltage.

Claims

1. An electrostatic protection circuit with a stable discharge mechanism, comprising: a voltage divider circuit electrically coupled to a voltage input terminal configured to receive a power signal, so as to generate a detection signal at a voltage divider terminal; a first inverter configured to receive the detection signal and invert the received signal to output an inverted detection signal; A voltage boost circuit comprising: a first P-type transistor circuit and a first N-type transistor circuit, connected in series between the voltage input terminal and a ground terminal via a first terminal, each having a first P-type transistor control terminal electrically coupled to a second terminal and a first N-type transistor control terminal configured to receive the inverted detection signal; as well as a second N-type transistor circuit electrically coupled between the second terminal and the ground terminal, and having a second N-type transistor control terminal configured to receive the detection signal; a capacitance-resistance circuit comprising a resistor electrically coupled between the voltage input terminal and a control terminal, and a capacitor electrically coupled between the control terminal and a ground terminal, wherein the control terminal is electrically coupled to the second terminal; a second inverter electrically coupled between the voltage input terminal and the ground terminal, configured to receive an inverted rising detection signal from the control terminal and invert the inverted signal to output a rising detection signal; as well as An electrostatic discharge transistor is electrically coupled between the voltage input terminal and the ground terminal and is configured to be controlled by the rise detection signal to discharge the voltage input terminal when being turned on.

2. The electrostatic protection circuit according to claim 1, wherein the first inverter operates according to a first voltage, and the voltage boosting circuit, the second inverter, and the electrostatic discharge transistor operate according to a second voltage generated by the power signal, wherein the first voltage is less than the second voltage, and the first voltage is 0.9, 1.2, or 1.8 volts, and the second voltage is 3.3 volts. 3 . The electrostatic protection circuit according to claim 2 , wherein the second voltage is generated by the power signal, and the first voltage is generated by another independent power signal. 4 . The electrostatic protection circuit according to claim 2 , wherein the second voltage is generated by the power signal, and the first voltage is generated by a voltage division of the power signal.

5. The electrostatic protection circuit according to claim 1, wherein the voltage divider circuit comprises a first resistive circuit and a second resistive circuit, which are connected in series between the voltage input terminal and the ground terminal through the voltage divider terminal, wherein the first resistive circuit and the second resistive circuit respectively comprise a resistor, a diode, a diode-connected transistor, or a combination thereof.

6. The electrostatic protection circuit according to claim 1, wherein in a normal operation mode in which the voltage at the voltage input terminal does not exceed a preset level, the detection signal is at a low state level, the inverted detection signal is at a high state level, the first N-type transistor circuit is turned on and the first P-type transistor circuit and the second N-type transistor circuit are turned off, the inverted lift detection signal is at the high state level, and the lift detection signal is at the low state level, thereby turning off the electrostatic discharge transistor.

7. The electrostatic protection circuit according to claim 1, wherein in a discharge mode in which the voltage at the voltage input terminal exceeds a preset level due to receiving an electrostatic input, the detection signal is at a high state level, the inverted detection signal is at a low state level, the first N-type transistor circuit is turned off and the first P-type transistor circuit and the second N-type transistor circuit are turned on, the inverted lift detection signal is at the low state level, and the lift detection signal is at the high state level, thereby turning on the electrostatic discharge transistor.

8. The electrostatic protection circuit according to claim 1, wherein the first N-type transistor circuit and the second N-type transistor circuit respectively comprise a first N-type transistor and a second N-type transistor connected in series, wherein the first N-type transistor is an input / output device, and the second N-type transistor is a core device.

9. The electrostatic protection circuit according to claim 1 further comprises a second P-type transistor circuit electrically coupled between the voltage input terminal and the second terminal to be connected in series with the second N-type transistor circuit, and having a second P-type transistor control terminal electrically coupled to the first terminal. 10 . The ESD protection circuit according to claim 1 , wherein a time constant of the capacitance circuit determines a high-frequency response time of the ESD protection circuit, and the voltage divider circuit and the first inverter determine a low-frequency response time of the ESD protection circuit.

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