A secondary power supply circuit employing adaptive current compensation

Abstract

The application discloses a secondary power supply circuit with adaptive current compensation, comprising: a starting and current mirror generating module providing a reference current to a secondary power supply module, the secondary power supply module receiving the reference current to generate a secondary power supply, and the secondary power supply module providing a voltage to an output driving module; and an adaptive current compensation module providing a compensation current to the secondary power supply module. The secondary power supply circuit with adaptive current compensation is based on a CMOS process, and the output of a reference level is adaptively adjusted according to the condition of a power supply voltage, so that the output voltage is kept stable in a wider input voltage range; meanwhile, the output secondary level meets the working requirements of a signal transmission circuit under a low power supply voltage condition; and the transmission speed and the highest working frequency of an isolated DC / DC switching power supply are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of circuit design, and relates to a secondary power supply circuit adopting adaptive current compensation. BACKGROUND

[0002] The driver is an important component in an isolated DC / DC switching power supply, receives a pulse synchronization signal of a PWM controller, and outputs a signal for driving and controlling a switching tube and a freewheeling tube. A secondary power supply circuit applied in the driver supplies power to a logic part in the driver, so that a control system on a whole signal transmission link works at a lower working voltage and is not affected by a system power supply voltage. A traditional bandgap reference circuit needs to be designed based on a bipolar or BiCMOS process, and is affected by a bandgap reference structure, so that a working voltage range allowed by the traditional bandgap reference circuit is narrow, and a resistance trimming network needs to be additionally designed to ensure output voltage precision. SUMMARY

[0003] The application aims to solve the problem that a traditional bandgap reference circuit in the prior art needs to be designed based on a bipolar or BiCMOS process, is affected by a bandgap reference structure, so that a working voltage range allowed by the traditional bandgap reference circuit is narrow, and a resistance trimming network needs to be additionally designed to ensure output voltage precision, and provides a secondary power supply circuit adopting adaptive current compensation.

[0004] To achieve the above object, the application adopts the following technical scheme:

[0005] The secondary power supply circuit adopting adaptive current compensation comprises a start-up and current mirror generation module, a secondary power supply module, an output driving module and an adaptive current compensation module.

[0006] The start-up and current mirror generation module provides a reference current to the secondary power supply module, the secondary power supply module generates a secondary power supply by receiving the reference current, and the secondary power supply module provides a voltage to the output driving module; and the adaptive current compensation module provides a compensation current to the secondary power supply module.

[0007] Further, the start-up and current mirror generation module comprises a PMOS tube 1, a PMOS tube 2, a PMOS tube 3, a resistance R1, a resistance R2, a resistance R3, an NMOS tube 1, an NMOS tube 2, an NMOS tube 3 and an NMOS tube 4.

[0008] The drain of the PMOS tube 1, the drain of the PMOS tube 2 and the drain of the PMOS tube 3 are connected to each other, the gate of the PMOS tube 2 and the gate of the PMOS tube 3 are connected to each other; the source of the PMOS tube 3 is connected to one end of the resistor R1 and the drain of the NMOS tube 4; the gate of the PMOS tube 2, the gate of the PMOS tube 3, one end of the resistor R1 and the source of the PMOS tube 3 are connected to each other; the other end of the resistor R1 is connected to the drain of the NMOS tube 1; the gate of the NMOS tube 1 is connected to the drain of the NMOS tube 2 and the source of the PMOS tube 1; the gate of the NMOS tube 2 is connected to the gate of the PMOS tube 1 and the gate of the NMOS tube 3; the source of the PMOS tube 2 is connected to one end of the resistor R2; the other end of the resistor R2 is connected to the drain of the NMOS tube 3 and the gate of the NMOS tube 4 respectively; the gate of the NMOS tube 3 and the source of the NMOS tube 4 are connected to one end of the resistor R3; the other end of the resistor R3 is connected to the source of the NMOS tube 1, the source of the NMOS tube 2 and the source of the NMOS tube 3 respectively.

[0009] Further, the secondary power module comprises: the PMOS tube 4, the PMOS tube 5, the PMOS tube 6, the PMOS tube 7, the NMOS tube 5, the NMOS tube 14, the resistor R4, the diode Vbe and the voltage stabilizing diode Dz.

[0010] The drain of the PMOS tube 4, the drain of the PMOS tube 5, the drain of the PMOS tube 6, the drain of the PMOS tube 7 and the drain of the NMOS tube 14 are connected to the drain of the PMOS tube 3 in sequence; the source of the PMOS tube 4 is connected to the drain of the NMOS tube 5; the gate of the NMOS tube 5 is connected to the gate of the NMOS tube 4; one end of the resistor R4 is connected to the source of the NMOS tube 5, and the other end of the resistor R4 is connected to the other end of the resistor R3; the drain of the NMOS tube 5 is connected to the gate of the PMOS tube 4, the gate of the PMOS tube 5, the gate of the PMOS tube 6 and the gate of the PMOS tube 7; the source of the PMOS tube 7 is connected to the gate of the NMOS tube 14 and the positive electrode of the diode Vbe; the negative electrode of the diode Vbe and the negative electrode of the voltage stabilizing diode Dz; the positive electrode of the voltage stabilizing diode Dz is grounded.

[0011] Further, the output driving module comprises: the PMOS tube 9, the PMOS tube 10, the PMOS tube 11, the NMOS tube 6, the NMOS tube 7, the NMOS tube 8, the NMOS tube 9, the resistor R5 and the capacitor C1.

[0012] The drain of the PMOS tube 9, the drain of the PMOS tube 10 and the drain of the PMOS tube 11 are connected with the drain of the PMOS tube 7; the source of the PMOS tube 9 is connected with the drain of the NMOS tube 6 and the gate of the PMOS tube 11; the gate of the PMOS tube 9 and the gate of the PMOS tube 10 are connected with the source of the PMOS tube 10; the source of the PMOS tube 10 is connected with the drain of the NMOS tube 7; the source of the NMOS tube 7 and the source of the NMOS tube 6 are connected with the drain of the NMOS tube 8; the gate of the NMOS tube 6 is connected with the source of the NMOS tube 14; the source of the NMOS tube 8 is connected with the source of the NMOS tube 9 and one end of the resistor R5; the gate of the NMOS tube 8 is connected with the gate of the NMOS tube 9 and the drain of the NMOS tube 9; the drain of the NMOS tube 9 is connected with the second reference current Iref2 and the power supply VCC in sequence; the source of the PMOS tube 11 is connected with the other end of the resistor R5; the gate of the NMOS tube 7 and the gate of the PMOS tube 11 are connected with the capacitor C1; the gate of the NMOS tube 7 is connected with the output voltage Vout.

[0013] Further, the output driving module comprises: the PMOS tube 12, the PMOS tube 13, the PMOS tube 14, the PMOS tube 15, the NMOS tube 10, the NMOS tube 11, the NMOS tube 12, the NMOS tube 13 and the resistor R6.

[0014] The drain of the PMOS tube 12 and the drain of the PMOS tube 13 are connected; the gate of the PMOS tube 12, the gate of the PMOS tube 13 and the source of the PMOS tube 12 are connected; the source of the PMOS tube 12 is connected with the first reference current Iref1 and the ground in sequence; the source of the PMOS tube 13 is connected with the drain of the PMOS tube 14; the source of the PMOS tube 14 is connected with the gate of the PMOS tube 15 and the resistor R6; the resistor R6 is grounded; the gate of the PMOS tube 14 is connected with the gate of the NMOS tube 14; the source of the PMOS tube 15 is connected with the drain of the NMOS tube 13; the source of the NMOS tube 13 is connected with the source of the NMOS tube 12, the drain of the NMOS tube 12, the gate of the NMOS tube 12 and the gate of the NMOS tube 13 are connected; the drain of the NMOS tube 12 is connected with the source of the PMOS tube 6; the drain of the PMOS tube 15 is connected with the drain of the NMOS tube 11; the drain of the NMOS tube 11 is connected with the source of the PMOS tube 5 and the gate of the NMOS tube 11; the source of the NMOS tube 11 is connected with the source of the NMOS tube 10; the gate of the NMOS tube 10 is connected with the gate of the NMOS tube 11; the drain of the NMOS tube 10 is connected with the source of the NMOS tube 14.

[0015] Further, the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5 and the resistor R6 are of the same type.

[0016] Further, the first reference current Iref1 and the second reference current Iref2 have the same size.

[0017] Further, the voltage of the voltage stabilizing diode Dz is 6V.

[0018] Compared with the prior art, the present application has the following beneficial effects:

[0019] The present application adopts a secondary power supply circuit with adaptive current compensation based on CMOS process, and adaptively adjusts the output of the reference level according to the power supply voltage, so that the output voltage remains stable under a wider input voltage range; meanwhile, under the condition of low power supply voltage, the output secondary level meets the working requirements of the signal transmission circuit. The transmission speed and the highest working frequency of the isolated DC / DC switching power supply are greatly improved.

[0020] Further, the present application adaptively adjusts the output of the reference level according to the power supply voltage, so that the output voltage remains stable under a wider input voltage range; meanwhile, under the condition of low power supply voltage, the output secondary level meets the working requirements of the signal transmission circuit. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0022] Figure 1 The adaptive secondary power supply circuit diagram of the present application. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, not all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0025] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0026] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper," "lower," "horizontal," or "inner" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, terms such as "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0027] Furthermore, the use of the term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0028] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0029] The present invention will now be described in further detail with reference to the accompanying drawings:

[0030] See Figure 1 This invention discloses a secondary power supply circuit with adaptive current compensation, comprising: a startup and current mirror generation module 1, a secondary power supply module 2, an output drive module 3, and an adaptive current compensation module 4; the startup and current mirror generation module 1 provides a reference current to the secondary power supply module 2, the secondary power supply module 2 receives the reference current to generate a secondary power supply, and the secondary power supply module 2 provides voltage to the output drive module 3; the adaptive current compensation module 4 provides compensation current to the secondary power supply module 2.

[0031] The startup and current mirror generation module 1 includes: PMOS transistor 1, PMOS transistor 2, PMOS transistor 3, resistor R1, resistor R2, resistor R3, NMOS transistor 1, NMOS transistor 2, NMOS transistor 3 and NMOS transistor 4;

[0032] The drain of the PMOS tube 1, the drain of the PMOS tube 2 and the drain of the PMOS tube 3 are connected to each other, the gate of the PMOS tube 2 and the gate of the PMOS tube 3 are connected to each other; the source of the PMOS tube 3 is connected to one end of the resistor R1 and the drain of the NMOS tube 4; the gate of the PMOS tube 2, the gate of the PMOS tube 3, one end of the resistor R1 and the source of the PMOS tube 3 are connected to each other; the other end of the resistor R1 is connected to the drain of the NMOS tube 1; the gate of the NMOS tube 1 is connected to the drain of the NMOS tube 2 and the source of the PMOS tube 1; the gate of the NMOS tube 2 is connected to the gate of the PMOS tube 1 and the gate of the NMOS tube 3; the source of the PMOS tube 2 is connected to one end of the resistor R2; the other end of the resistor R2 is connected to the drain of the NMOS tube 3 and the gate of the NMOS tube 4 respectively; the gate of the NMOS tube 3 and the source of the NMOS tube 4 are connected to one end of the resistor R3; the other end of the resistor R3 is connected to the source of the NMOS tube 1, the source of the NMOS tube 2 and the source of the NMOS tube 3 respectively.

[0033] The secondary power module 2 comprises: a PMOS tube 4, a PMOS tube 5, a PMOS tube 6, a PMOS tube 7, an NMOS tube 5, an NMOS tube 14, a resistor R4, a diode Vbe and a voltage stabilizing diode Dz.

[0034] The drain of the PMOS tube 4, the drain of the PMOS tube 5, the drain of the PMOS tube 6, the drain of the PMOS tube 7 and the drain of the NMOS tube 14 are connected to the drain of the PMOS tube 3 in sequence; the source of the PMOS tube 4 is connected to the drain of the NMOS tube 5; the gate of the NMOS tube 5 is connected to the gate of the NMOS tube 4; the source of the NMOS tube 5 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the other end of the resistor R3; the drain of the NMOS tube 5 is connected to the gate of the PMOS tube 4, the gate of the PMOS tube 5, the gate of the PMOS tube 6 and the gate of the PMOS tube 7; the source of the PMOS tube 7 is connected to the gate of the NMOS tube 14 and the positive electrode of the diode Vbe; the negative electrode of the diode Vbe and the negative electrode of the voltage stabilizing diode Dz; the positive electrode of the voltage stabilizing diode Dz is grounded.

[0035] The output driving module 3 comprises: a PMOS tube 9, a PMOS tube 10, a PMOS tube 11, an NMOS tube 6, an NMOS tube 7, an NMOS tube 8, an NMOS tube 9, a resistor R5 and a capacitor C1.

[0036] The drain of the PMOS tube 9, the drain of the PMOS tube 10 and the drain of the PMOS tube 11 are connected with the drain of the PMOS tube 7; the source of the PMOS tube 9 is connected with the drain of the NMOS tube 6 and the gate of the PMOS tube 11; the gate of the PMOS tube 9 and the gate of the PMOS tube 10 are connected with the source of the PMOS tube 10; the source of the PMOS tube 10 is connected with the drain of the NMOS tube 7; the source of the NMOS tube 7 and the source of the NMOS tube 6 are connected with the drain of the NMOS tube 8; the gate of the NMOS tube 6 is connected with the source of the NMOS tube 14; the source of the NMOS tube 8 is connected with the source of the NMOS tube 9 and one end of the resistor R5; the gate of the NMOS tube 8 is connected with the gate of the NMOS tube 9 and the drain of the NMOS tube 9; the drain of the NMOS tube 9 is connected with the second reference current Iref2 and the power supply VCC in sequence; the source of the PMOS tube 11 is connected with the other end of the resistor R5; the capacitor C1 is connected between the gate of the NMOS tube 7 and the gate of the PMOS tube 11; the gate of the NMOS tube 7 is connected with the output voltage Vout.

[0037] The output driving module 4 comprises the PMOS tube 12, the PMOS tube 13, the PMOS tube 14, the PMOS tube 15, the NMOS tube 10, the NMOS tube 11, the NMOS tube 12, the NMOS tube 13 and the resistor R6.

[0038] The drain of the PMOS tube 12 and the drain of the PMOS tube 13 are connected; the gate of the PMOS tube 12, the gate of the PMOS tube 13 and the source of the PMOS tube 12 are connected; the source of the PMOS tube 12 is connected with the first reference current Iref1 and the ground in sequence; the source of the PMOS tube 13 is connected with the drain of the PMOS tube 14; the source of the PMOS tube 14 is connected with the gate of the PMOS tube 15 and the resistor R6; the resistor R6 is grounded; the gate of the PMOS tube 14 is connected with the gate of the NMOS tube 14; the source of the PMOS tube 15 is connected with the drain of the NMOS tube 13; the source of the NMOS tube 13 is connected with the source of the NMOS tube 12, the drain of the NMOS tube 12, the gate of the NMOS tube 12 and the gate of the NMOS tube 13 are connected; the drain of the NMOS tube 12 is connected with the source of the PMOS tube 6; the drain of the PMOS tube 15 is connected with the drain of the NMOS tube 11; the drain of the NMOS tube 11 is connected with the source of the PMOS tube 5 and the gate of the NMOS tube 11; the source of the NMOS tube 11 is connected with the source of the NMOS tube 10; the gate of the NMOS tube 10 is connected with the gate of the NMOS tube 11; the drain of the NMOS tube 10 is connected with the source of the NMOS tube 14.

[0039] The resistance R1, the resistance R2, the resistance R3, the resistance R4, the resistance R5 and the resistance R6 are of the same type. The first reference current Iref1 and the second reference current Iref2 are of the same size. The voltage of the voltage stabilizing diode Dz is 6V.

[0040] Referring to Figure 1 The application discloses a secondary power supply circuit with adaptive current compensation. When the power supply voltage gradually rises, the PMOS tube 1 is turned on due to the resistance R3, at this time, the NMOS tube 1 gate is lifted, the NMOS tube 1 is turned on, the PMOS tube 3 gate is pulled low, the PMOS tube 3 is turned on, and the circuit is started. At this time, the voltage at the upper end of the resistance R3 continuously increases, so that the inverter composed of the PMOS tube 1 and the NMOS tube 2 is reversed, the NMOS tube 1 is closed, and the circuit is normally started. The reference current I is formed in the NMOS tube 4.

[0041] A 6V voltage stabilizing diode Dz is adopted, a constant reverse bias current is added to the voltage stabilizing diode Dz, a stable reference voltage is output, a VBE is connected in series to the voltage stabilizing diode, the purpose is to increase the voltage and reduce the temperature coefficient of the reference voltage, and meanwhile, the voltage stabilizing value is improved, so as to leave enough margin for the overdrive voltage of a subsequent output tube.

[0042] The 5V reference level of the device is output through the source follower structure of the NMOS tube 14, a constant current is given to the NMOS tube, the VREF reference voltage is reduced to 5V, and the constant current can be calculated as follows:

[0043]

[0044] When the power supply voltage is higher than V DZ +V BE , the structure can stabilize the output voltage at 5V, at this time, one buffer output stage is added to the 5V voltage, and the driving capability of the output voltage Vout can be improved.

[0045] When the power supply voltage is lower than V DZ +V BE , the Zener voltage stabilizing diode does not break down, the reference voltage is consistent with the power supply voltage, at this time, if the above constant current source is still adopted, the secondary voltage obtained will be low, and even when the power supply voltage is 4.5V, the output voltage is lower than 3V. Since most of the low-voltage logic parts adopt 5V MOS devices, the working voltage range should be 3-5V, so that most application conditions can be met, and therefore the secondary voltage output should be designed to be 3V-5V under the condition of low input voltage.

[0046] The load current source of the source follower structure of the NMOS transistor 14 should be a variable current source varying with the Zener reference voltage. When the power supply voltage is low, the constant current source current should be reduced to reduce the voltage difference between the secondary power supply and the Zener reference voltage. When the power supply voltage is increased, the constant current source current is gradually increased so that the secondary power supply voltage does not exceed the design target of 5V. When the Zener tube is broken down, the constant current source remains stable, and the secondary power supply voltage is stable. Therefore, the constant current source should be related to the power supply voltage. Before the Zener tube is broken down, the Zener tube reference voltage is consistent with the power supply voltage. After the Zener tube is broken down, the reference voltage is a constant value, which is consistent with the trend of the constant current source. Therefore, the Zener reference voltage can be used as the control voltage of the constant current source.

[0047] When the Zener tube is not broken down, the PMOS transistor 14 is closed. At this time, the PMOS transistor 15 keeps open to shunt the constant current source, so that the constant current source is in a lower current range. When the Zener tube is broken down, the PMOS transistor 14 is open, the voltage on the resistor R6 is increased, and the PMOS transistor 15 stops shunting the constant current source. At this time, the constant current source keeps a constant value.

[0048] Here, due to the threshold voltage of the PMOS transistor 14, when the power supply voltage is less than V DZ +V BE +V THP , the transistor cannot be turned on in time, resulting in a small VGS of the source follower transistor and a secondary power supply higher than 5V. By adding the constant current source NMOS transistor 12\NMOS transistor 13 to the PMOS transistor 15, the opening current of the PMOS transistor 15 can be limited, and the secondary power supply voltage can be reduced. However, the reverse result is that the PMOS transistor 15 cannot draw too much current from the constant current source at low power supply voltage, resulting in a low secondary power supply output voltage. By adjusting and integrating, the final minimum output of the secondary power supply is 3.0V. Here, the relationship between the resistance, the power supply voltage and the constant current source current, and the secondary voltage can be listed. By adjusting the resistance R6, the variable constant current source can be fine-tuned.

[0049] The above is only a preferred embodiment of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A secondary power supply circuit employing adaptive current compensation, characterized by, The application relates to a starting and current mirror generating module (1), a secondary power supply module (2), an output driving module (3) and an adaptive current compensation module (4). The starting and current mirror generating module (1) provides a reference current for the secondary power supply module (2), the secondary power supply module (2) generates a secondary power supply by receiving the reference current, and the secondary power supply module (2) provides a voltage for the output driving module (3); the adaptive current compensation module (4) provides a compensation current for the secondary power supply module (2). The starting and current mirror generating module (1) comprises a PMOS tube 1, a PMOS tube 2, a PMOS tube 3, a resistor R1, a resistor R2, a resistor R3, an NMOS tube 1, an NMOS tube 2, an NMOS tube 3 and an NMOS tube 4. The drain of the PMOS tube 1, the drain of the PMOS tube 2 and the drain of the PMOS tube 3 are connected to each other and to a power supply VCC, the gate of the PMOS tube 2 and the gate of the PMOS tube 3 are connected to each other, the source of the PMOS tube 3 is connected to one end of the resistor R1 and the drain of the NMOS tube 4, the gate of the PMOS tube 2, the gate of the PMOS tube 3, one end of the resistor R1 and the source of the PMOS tube 3 are connected to each other, the other end of the resistor R1 is connected to the drain of the NMOS tube 1, the gate of the NMOS tube 1 is connected to the drain of the NMOS tube 2 and the source of the PMOS tube 1, the gate of the NMOS tube 2 is connected to the gate of the PMOS tube 1 and the gate of the NMOS tube 3, the source of the PMOS tube 2 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the drain of the NMOS tube 3 and the gate of the NMOS tube 4, the gate of the NMOS tube 3 and the source of the NMOS tube 4 are connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the source of the NMOS tube 1, the source of the NMOS tube 2 and the source of the NMOS tube 3. The secondary power supply module (2) comprises a PMOS tube 4, a PMOS tube 5, a PMOS tube 6, a PMOS tube 7, an NMOS tube 5, an NMOS tube 14, a resistor R4, a diode Vbe and a voltage stabilizing diode Dz. The drain of the PMOS tube 4, the drain of the PMOS tube 5, the drain of the PMOS tube 6, the drain of the PMOS tube 7 and the drain of the NMOS tube 14 are connected to the drain of the PMOS tube 3 in sequence, the source of the PMOS tube 4 is connected to the drain of the NMOS tube 5, the gate of the NMOS tube 5 is connected to the gate of the NMOS tube 4, the source of the NMOS tube 5 is connected to one end of the resistor R4, the other end of the resistor R4 is connected to the other end of the resistor R3, the drain of the NMOS tube 5 is connected to the gate of the PMOS tube 4, the gate of the PMOS tube 5, the gate of the PMOS tube 6 and the gate of the PMOS tube 7, the source of the PMOS tube 7 is connected to the gate of the NMOS tube 14 and the anode of the diode Vbe, the cathode of the diode Vbe and the cathode of the voltage stabilizing diode Dz are connected to each other, and the anode of the voltage stabilizing diode Dz is connected to the ground. ​ The output drive module (3) comprises PMOS 9, PMOS 10, PMOS 11, NMOS 6, NMOS 7, NMOS 8, NMOS 9, resistor R5 and capacitor C1; The drain of PMOS 9, the drain of PMOS 10 and the drain of PMOS 11 are connected with the drain of PMOS 7; the source of PMOS 9 is connected with the drain of NMOS 6 and the gate of PMOS 11; the gate of PMOS 9 and the gate of PMOS 10 are connected with the source of PMOS 10; the source of PMOS 10 is connected with the drain of NMOS 7; the source of NMOS 7 and the source of NMOS 6 are connected with the drain of NMOS 8; the gate of NMOS 6 is connected with the source of NMOS 14; the source of NMOS 8 is connected with the source of NMOS 9 and one end of resistor R5 and grounded; the gate of NMOS 8 is connected with the gate of NMOS 9 and the drain of NMOS 9; the drain of NMOS 9 is connected with second reference current Iref2 and power supply VCC in sequence; the source of PMOS 11 is connected with the other end of resistor R5; capacitor C1 is connected between the gate of NMOS 7 and the gate of PMOS 11; the gate of NMOS 7 is connected with output voltage Vout; The adaptive current compensation module (4) comprises PMOS 12, PMOS 13, PMOS 14, PMOS 15, NMOS 10, NMOS 11, NMOS 12, NMOS 13 and resistor R6; The drain of PMOS 12 and the drain of PMOS 13 are connected; the gate of PMOS 12 and the gate of PMOS 13 are connected with the source of PMOS 12; the source of PMOS 12 is connected with first reference current Iref1 and grounded in sequence; the source of PMOS 13 is connected with the drain of PMOS 14; the source of PMOS 14 is connected with the gate of PMOS 15 and resistor R6; resistor R6 is grounded; the gate of PMOS 14 is connected with the gate of NMOS 14; the source of PMOS 15 is connected with the drain of NMOS 13; the source of NMOS 13 is connected with the source of NMOS 12 and grounded, the drain of NMOS 12, the gate of NMOS 12 and the gate of NMOS 13 are connected with each other; the drain of NMOS 12 is connected with the source of PMOS 6; the drain of PMOS 15 is connected with the drain of NMOS 11; the drain of NMOS 11 is connected with the source of PMOS 5 and the gate of NMOS 11; the source of NMOS 11 is connected with the source of NMOS 10 and grounded; the gate of NMOS 10 is connected with the gate of NMOS 11; the drain of NMOS 10 is connected with the source of NMOS 14.

2. The secondary power supply circuit employing adaptive current compensation according to claim 1, characterized in that, The resistance R1, resistance R2, resistance R3, resistance R4, resistance R5 and resistance R6 are of the same type.

3. The secondary power supply circuit employing adaptive current compensation according to claim 1, wherein, The first reference current Iref1 and the second reference current Iref2 are of the same size.

4. The secondary power supply circuit employing adaptive current compensation of claim 1, wherein, The voltage of the voltage stabilizing diode Dz is 6V.

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