A high-precision PWM pulse generation circuit and chip

Abstract

This invention discloses a high-precision PWM pulse generation circuit and chip. The PWM pulse generation circuit includes a PWM pulse group unit, an output logic unit, and a precision control unit. A set of delayed clock signal input ports are connected to a set of input terminals of the PWM pulse group unit; a first control signal input port is connected to the control terminal of the PWM pulse group unit; and a set of output terminals of the PWM pulse group unit are connected to a first set of input terminals of the output logic unit. A second control signal input port is connected to the input terminal of the precision control unit; and a set of output terminals of the precision control unit are connected to a second set of input terminals of the output logic unit. The output terminal of the output logic unit is connected to the output terminal of the PWM pulse generation circuit. This PWM pulse generation circuit realizes the generation and adjustable output of a set of high-precision PWM pulse signals.

Description

Technical Field

[0001] This invention relates to a high-precision PWM pulse generation circuit, and also to an integrated circuit chip including the PWM pulse generation circuit, belonging to the field of integrated circuit technology. Background Technology

[0002] Pulse-Width Modulation (PWM) is a technique that modulates the width and duty cycle of a set of pulses to control the voltage, frequency, and other parameters of analog circuits. As an effective method for driving and control, PWM technology is widely used in fields such as communications, measurement, and power electronics. In PWM applications, the accuracy of the PWM pulse signal is a crucial performance indicator, directly determining the control precision of the system. Currently, the accuracy of the PWM pulse signal depends on the frequency of the system clock signal; when the system clock signal frequency cannot be increased, the accuracy of the PWM is limited.

[0003] Chinese invention patent CN 114420030B discloses a PWM generation circuit, a driver chip, and an electronic device. The PWM generation circuit includes a first device and a matching logic circuit. An initial clock signal is passed through the matching logic circuit to output a first PWM clock signal; a delayed clock signal is passed through the first device to output a second PWM clock signal. The logic path of the initial clock signal through the matching logic circuit is exactly the same as the logic path of the delayed clock signal in the first device. The delayed clock signal differs from the initial clock signal by F (0 ≤ F < 1) complete clock cycles. This PWM generation circuit can be used to eliminate unknown phase deviations between different clocks, thereby eliminating accuracy errors caused by unknown variables in PWM. Summary of the Invention

[0004] The primary technical problem to be solved by this invention is to provide a high-precision PWM pulse generation circuit.

[0005] Another technical problem to be solved by the present invention is to provide an integrated circuit chip including the PWM pulse generation circuit.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] According to a first aspect of the present invention, a high-precision PWM pulse generation circuit is provided. The PWM pulse generation circuit includes a PWM pulse group unit, an output logic unit, and a precision control unit; wherein,

[0008] The PWM pulse group unit is used to generate a set of PWM pulse signals according to a set of delayed clock signals and a first control signal, and the output terminal is connected to the output logic unit;

[0009] The precision control unit is used to generate a corresponding control signal according to the second control signal to control the opening and closing state of each output path in the output logic unit, and its control signal is output to the output logic unit.

[0010] The output logic unit is used to provide an output path for the PWM pulse signal according to the control of the precision control unit, and its output terminal is connected to the output terminal of the PWM pulse generation circuit.

[0011] Preferably, the PWM pulse group unit is composed of a group of PWM pulse units; the number of PWM pulse units is the same as the number of delayed clock signals; wherein...

[0012] The first input terminal of each PWM pulse unit is connected to the first control signal input terminal; the second input terminal of the first PWM pulse unit is connected to the original clock signal input terminal; the second input terminal of the second PWM pulse unit is connected to the first delayed clock signal input terminal; the second input terminal of the third PWM pulse unit is connected to the second delayed clock signal input terminal; the second input terminal of the fourth PWM pulse unit is connected to the third delayed clock signal input terminal; and so on, with the second input terminal of the last PWM pulse unit correspondingly connected to the last delayed clock signal input terminal.

[0013] Preferably, each PWM pulse unit consists of a first counter Count, a first comparator Comp, and a first register RS; wherein...

[0014] The clock signal input terminal is connected to the input terminal of the first counter Count and the clock terminal of the first register RS. The output terminal of the first counter Count is connected to the second input terminal of the first comparator Comp. The first control signal input terminal is connected to the first input terminal of the first comparator Comp. The output terminal of the first comparator Comp is connected to the input terminal of the first register RS. The output terminal of the first register RS ​​is connected to the output terminal of the PWM pulse unit.

[0015] Preferably, in the PWM pulse unit, when the first counter Count adopts an upward counting mode, the frequency f1 and duty cycle D of its output PWM pulse signal satisfy the following formulas:

[0016] f1 = F / Nmax

[0017] D = M / Nmax

[0018] Where F is the frequency of the input clock signal, Nmax is the maximum value of the counter; M is the given value of the first control signal, and M <Nmax。

[0019] Preferably, in the PWM pulse unit, when the first counter Count...

[0020] When using the down-counting method, the frequency f1 and duty cycle D of the output PWM pulse signal satisfy the following formulas:

[0021] f1 = F / Nmax

[0022] D = (Nmax - M) / Nmax

[0023] Where F is the frequency of the input clock signal; Nmax is the maximum value of the counter; M is the given value of the first control signal, and M <Nmax。

[0024] Preferably, in the PWM pulse unit, when the first counter Count...

[0025] When using the central counting method, the frequency f1 and duty cycle D of the output PWM pulse signal satisfy the following formulas:

[0026] f1 = F / (2Nmax)

[0027] D = M / Nmax

[0028] Where F is the input clock signal frequency; Nmax is the maximum value of the counter; M is the given value of the first control signal, and M <Nmax。

[0029] Preferably, the output logic unit consists of a set of AND gates and a first OR gate OR01, wherein the number of AND gates is the same as the number of PWM pulse units; wherein...

[0030] The set of control signal output terminals of the precision control unit are respectively connected to the first input terminals of the set of AND gates;

[0031] The output terminals of the PWM pulse group unit are respectively connected to the second input terminals of the AND gate.

[0032] The output terminals of the AND gate are respectively connected to a set of input terminals of the first OR gate OR01;

[0033] The output of the first OR gate OR01 is connected to the output of the output logic unit.

[0034] Preferably, the output logic unit consists of a set of AND gates and multiple levels of OR gates, each OR gate having two input terminals; wherein...

[0035] The number of AND gates is the same as the number of PWM pulse units; the number of first-stage OR gates is half the number of AND gates rounded up to the nearest integer; the number of second-stage OR gates is half the number of first-stage OR gates rounded up to the nearest integer; the number of third-stage OR gates is half the number of second-stage OR gates rounded up to the nearest integer; and so on, with the last-stage OR gate being a single OR gate;

[0036] The set of control signal output terminals of the precision control unit are respectively connected to the first input terminals of the set of AND gates;

[0037] The output terminals of the PWM pulse group unit are respectively connected to the second input terminals of the AND gate.

[0038] The output terminals of the AND gates are respectively connected to the input terminals of the first-stage OR gates;

[0039] The output terminals of the first-stage OR gate are respectively connected to the input terminals of the second-stage OR gate;

[0040] The output terminals of the second-stage OR gate are respectively connected to the input terminals of the third-stage OR gate;

[0041] Similarly, the output of the final OR gate is connected to the output of the output logic unit.

[0042] Preferably, when the frequency of the clock signal increases and / or the number of PWM pulse units in the PWM pulse group unit increases, the accuracy of the PWM pulse signal output by the PWM pulse generation circuit increases accordingly.

[0043] According to a second aspect of the present invention, an integrated circuit chip is provided, including the above-described high-precision PWM pulse generation circuit.

[0044] Compared with existing technologies, the high-precision PWM pulse generation circuit provided by this invention can generate PWM pulse signals with different frequencies and duty cycles. Furthermore, by increasing or decreasing the number of PWM pulse units, the precision of the output PWM pulse signal can be changed, thereby achieving the generation and adjustable output of a set of high-precision PWM pulse signals. This PWM pulse generation circuit can improve the precision of the output PWM pulse signal even when the system clock signal frequency cannot be increased. Therefore, the high-precision PWM pulse generation circuit provided by this invention has the advantages of high precision, flexible system adjustment, ingenious and reasonable structural design, and low design cost. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the high-precision PWM pulse generation circuit provided by the present invention;

[0046] Figure 2This is a circuit diagram of a high-precision PWM pulse generation circuit in the first embodiment of the present invention;

[0047] Figure 3 This is a circuit schematic diagram of the PWM pulse unit in the first embodiment of the present invention;

[0048] Figure 4 This is a timing comparison diagram of the PWM pulse unit using the first scheme in the first embodiment of the present invention;

[0049] Figure 5 This is a timing comparison diagram of the second scheme used in the first embodiment of the present invention;

[0050] Figure 6 This is a timing comparison diagram of the third scheme used in the first embodiment of the present invention;

[0051] Figure 7 This is a timing diagram of the output logic unit in the first embodiment of the present invention;

[0052] Figure 8 This is a circuit diagram of a high-precision PWM pulse generation circuit in the second embodiment of the present invention. Detailed Implementation

[0053] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0054] like Figure 1 As shown, the high-precision PWM pulse generation circuit provided by the present invention includes a PWM pulse group unit, an output logic unit, and a precision control unit. A set of delayed clock signal input ports are respectively connected to a set of input terminals of the PWM pulse group unit; a first control signal input port is connected to the control terminal of the PWM pulse group unit; and a set of output terminals of the PWM pulse group unit are respectively connected to a set of input terminals of the output logic unit. A second control signal input port is connected to the input terminal of the precision control unit; a set of output terminals of the precision control unit are respectively connected to a set of control terminals of the output logic unit; and the output terminal of the output logic unit is connected to the output terminal of the PWM pulse generation circuit.

[0055] The PWM pulse group unit consists of a set of PWM pulse units, which are used to generate a set of PWM pulse signals with sequentially increasing delay times based on a set of delayed clock signals and a first control signal.

[0056] The output logic unit consists of AND and OR gates, and is used to output multiple PWM pulse signals under the control of the precision control unit according to the second control signal.

[0057] The precision control unit is used to control the on and off states of each path in the output logic unit according to the second control signal.

[0058] In the first embodiment of the present invention, as Figure 2 As shown, the high-precision PWM pulse generation circuit includes a PWM pulse group unit 1, an output logic unit 2, and a precision control unit 3.

[0059] The PWM pulse group unit consists of 8 PWM pulse units. The first input terminal of each of the 8 PWM pulse units receives the first control signal. The second input terminal of the first PWM pulse unit receives the original clock signal, the second input terminal of the second PWM pulse unit receives the first delayed clock signal, the second input terminal of the third PWM pulse unit receives the second delayed clock signal, and so on, with the second input terminal of the eighth PWM pulse unit receiving the seventh delayed clock signal. Finally, the output terminal of the PWM pulse group unit can output 8 PWM pulse signals with sequentially increasing delay times.

[0060] like Figure 3 As shown, each PWM pulse unit consists of a first counter Count, a first comparator Comp, and a first register RS. The clock signal input is connected to the input of the first counter Count and the clock terminal CK of the first register RS. The output of the first counter Count is connected to the second input of the first comparator Comp. The first control signal input is connected to the first input of the first comparator Comp. The output of the first comparator Comp is connected to the input D of the first register RS. The output Q of the first register RS ​​is connected to the output of the PWM pulse unit.

[0061] In the PWM pulse unit, when the clock signal is input, the first counter Count starts counting. This count value is compared with the setpoint of the first control signal by the first comparator Comp, and the comparison result is input to the first register RS. Finally, a PWM pulse signal can be obtained at the output of the PWM pulse unit. Furthermore, by changing the setpoint of the first control signal and the counting mode and maximum count value of the first counter Count, PWM pulse signals with different frequencies and duty cycles can be obtained.

[0062] Based on different counting settings for the first counter Count, the first embodiment of the present invention provides a technical solution with three PWM pulse units. The details of the PWM pulse signal output by each PWM pulse unit in each technical solution are described below.

[0063] In the first scheme's PWM pulse unit, the first counter Count adopts an upward counting method. The timing of the PWM pulse unit is as follows: Figure 4As shown. When the clock signal is input, the first counter Count starts counting upwards from zero. When the count value is less than the given value of the first control signal, the first comparator Comp outputs a high-level signal, and the first register RS ​​outputs a high-level signal. When the count value of the first counter Count is equal to the given value of the first control signal, the first comparator Comp outputs a low-level signal, and the first register RS ​​also outputs a low-level signal in the next clock cycle. This continues until the first counter Count reaches its maximum value and overflows, at which point the first comparator Comp outputs a high-level signal, and the first register RS ​​also outputs a high-level signal in the next clock cycle, and the first counter Count restarts counting upwards from zero.

[0064] The frequency f1 and duty cycle D of the PWM pulse signal output by the PWM pulse unit in the first scheme are as follows:

[0065] f1=F / Nmax (1)

[0066] D = M / Nmax (2)

[0067] Where F is the clock signal frequency; Nmax is the maximum value of the counter (a positive integer); M is the given value of the first control signal, and M <Nmax。

[0068] Assuming the clock signal frequency is 100MHz, the setpoint of the first control signal is 3, and the maximum count value of the first counter is 7, then the frequency of the PWM pulse signal output by the PWM pulse unit of the first scheme is 100MHz / 7 = 14.28MHz, and the duty cycle is 3 / 7.

[0069] In the second scheme's PWM pulse unit, the first counter Count uses a downward counting method. The timing of the PWM pulse unit is as follows: Figure 5 As shown. When the clock signal is input, the first counter Count starts counting downwards from its maximum value. When the count value is greater than the given value of the first control signal, the first comparator Comp outputs a high-level signal, and the first register RS ​​outputs a high-level signal. When the count value of the first counter Count is equal to the given value of the first control signal, the first comparator Comp outputs a low-level signal, and the first register RS ​​also outputs a low-level signal in the next clock cycle. This continues until the first counter Count reaches zero, at which point the first comparator Comp outputs a high-level signal, and the first register RS ​​also outputs a high-level signal in the next clock cycle. The first counter Count then restarts counting downwards from its maximum value.

[0070] The frequency f1 and duty cycle D of the PWM pulse signal output by the PWM pulse unit in the second scheme are as follows:

[0071] f1=F / Nmax (3)

[0072] D=(Nmax -M) / Nmax (4)

[0073] Where F is the clock signal frequency; Nmax is the maximum value of the counter (a positive integer); M is the given value of the first control signal, and M <Nmax。

[0074] Assuming the clock signal frequency is 100MHz, the setpoint of the first control signal is 3, and the maximum count value of the first counter is 7, then the frequency of the PWM pulse signal output by the PWM pulse unit of the second scheme is 100MHz / 7 = 14.28MHz, and the duty cycle is 4 / 7.

[0075] In the third scheme's PWM pulse unit, the first counter Count adopts a central counting method. The timing of the PWM pulse unit is as follows: Figure 6 As shown. When the clock signal is input, the first counter Count starts counting upwards from zero. When the count value is less than the given value of the first control signal, the first comparator Comp outputs a high-level signal, and the first register RS ​​outputs a high-level signal. When the count value of the first counter Count equals the given value of the first control signal, the first comparator Comp outputs a low-level signal, and the first register RS ​​also outputs a low-level signal in the next clock cycle. When the count value of the first counter Count reaches its maximum value, it starts counting downwards from the maximum value. At this time, the outputs of the first comparator Comp and the first register RS ​​remain low. When the count value of the first counter Count again equals the given value of the first control signal, the first comparator Comp outputs a high-level signal, and the first register RS ​​also outputs a high-level signal in the next clock cycle. When the count value of the first counter Count reaches zero, it starts counting upwards from zero. At this time, the outputs of the first comparator Comp and the first register RS ​​remain high until the count value of the first counter Count again reaches the given value of the first control signal.

[0076] The frequency f1 and duty cycle D of the PWM pulse signal output by the PWM pulse unit in the third scheme are as follows:

[0077] f1=F / (2Nmax) (5)

[0078] D = M / Nmax (6)

[0079] Where F is the clock signal frequency; Nmax is the maximum value of the counter (a positive integer); M is the given value of the first control signal, and M <Nmax。

[0080] Assuming the clock signal frequency is 100MHz, the given value of the first control signal is 3, and the maximum count value of the first counter is 7, then the frequency of the PWM pulse signal output by the PWM pulse unit of the third scheme is 100MHz / (2*7)=7.14MHz, and the duty cycle is 3 / 7.

[0081] Compared to the first and second technical solutions, the third technical solution for the PWM pulse unit can generate PWM pulse signals with different frequencies and / or duty cycles more flexibly.

[0082] In summary, in a PWM pulse unit, the frequency of the input clock signal, the setpoint of the first control signal, the counting mode of the counter, and its maximum value determine the frequency and duty cycle of the output PWM pulse signal. Therefore, by changing the frequency of the input clock signal, the setpoint of the first control signal, and the counting mode and maximum value of the counter, the PWM pulse unit can generate PWM pulse signals with different frequencies and duty cycles. Specifically, as the maximum value of the counter increases, the frequency of the PWM pulse signal decreases.

[0083] The present invention provides a high-precision PWM pulse generation circuit, wherein the width of the high-precision PWM pulse signal output by the circuit consists of two parts: a main width and a precision width. The main width is generated by the pulse signal output by the first PWM pulse unit in the PWM pulse group unit according to the original clock signal and the first control signal. The precision width is generated by the output pulse signal of the remaining PWM pulse units in the PWM pulse group unit, controlled by the precision control unit according to the second control signal.

[0084] In the first embodiment of the present invention, the output logic unit is composed of a set of AND gates and a first OR gate OR01, and the number of AND gates is the same as the number of PWM pulse units. Specifically, a set of control signal output terminals of the precision control unit are respectively connected to the first input terminals of the set of AND gates; a set of output terminals of the PWM pulse unit are respectively connected to the second input terminals of the set of AND gates; the output terminals of the set of AND gates are respectively connected to a set of input terminals of the first OR gate (OR01); and the output terminal of the first OR gate (OR01) is connected to the output terminal of the output logic unit.

[0085] like Figure 2As shown, taking a PWM pulse group unit comprising 8 PWM pulse units as an example, the output logic unit consists of a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a fourth AND gate AND4, a fifth AND gate AND5, a sixth AND gate AND6, a seventh AND gate AND7, an eighth AND gate AND8, and a first OR gate OR01. The 8 output terminals of the PWM pulse group unit are respectively connected to the first input terminals of the first AND gate AND1, the second AND gate AND2, the third AND gate AND3...the eighth AND gate AND8; the 8 control signal output terminals of the precision control unit are respectively connected to the second input terminals of the first AND gate AND1, the second AND gate AND2, the third AND gate AND3...the eighth AND gate AND8; the output terminals of the first AND gate AND1, the second AND gate AND2, the third AND gate AND3...the eighth AND gate AND8 are respectively connected to the 8 input terminals of the first OR gate OR01; and the output terminal of the first OR gate OR01 is connected to the output terminal of the output logic unit.

[0086] When the system needs to output a high-precision PWM pulse signal, the precision control unit controls the corresponding high-level control signal according to the second control signal. This controls the number of AND gates AND1, AND2, AND3, ..., AND8 in the output logic unit to be turned on from front to back. The OR gates then superimpose the PWM pulse signals output by the PWM pulse units that are turned on, thereby obtaining a high-precision PWM pulse signal at the output of the first OR gate OR01.

[0087] Suppose that when the PWM pulse signals output by the first four PWM pulse units in the PWM pulse group unit need to be output, the precision control unit sends four high-level control signals, which are respectively input to the second input terminals of the first AND gate AND1, the second AND gate AND2, the third AND gate AND3, and the fourth AND gate AND4, opening the output paths of these four AND gates. After the output pulse signals of the first four PWM pulse units in the PWM pulse group unit are superimposed by the first OR gate OR01, a high-precision PWM pulse signal can be obtained at the output terminal of the PWM pulse generation circuit. Figure 7 As shown, the width of the high-precision PWM pulse signal includes the main width portion generated by the first PWM pulse unit in the PWM pulse group unit, and the precision width portion generated by the output logic unit controlled by the precision control unit and by the second, third, and fourth PWM pulse units in the PWM pulse group unit.

[0088] As the above analysis shows, the accuracy of the PWM pulse signal output by the PWM pulse generation circuit ultimately depends on the frequency of the clock signal and the number of PWM pulse units in the PWM pulse group unit. Assuming the clock signal frequency is 250MHz and the number of PWM pulse units in the PWM pulse group unit is 32, then the time delay between the sequential output pulse signals of the 32 PWM pulse units is 125ps, meaning the accuracy of the PWM pulse signal output by the PWM pulse generation circuit is 125ps.

[0089] On the other hand, when the output logic unit outputs PWM pulse signals, the AND and OR gates also generate a very small secondary delay time. Typically, the delay time of an AND gate is about 100 ps, ​​while the delay time of a multi-input OR gate, generated by synthesis tools, is uncertain from each input to the output, typically ranging from about 20 to 40 ps. Therefore, in the first embodiment of this invention, the maximum phase error between the PWM pulse signals output by each PWM pulse unit in the PWM pulse group unit through the output logic unit is about 20 ps.

[0090] In the second embodiment of the present invention, as Figure 8 As shown, the high-precision PWM pulse generation circuit includes a PWM pulse group unit 1, an output logic unit 2, and a precision control unit 3. The difference from the first embodiment lies in the output logic unit.

[0091] In a second embodiment of the present invention, the output logic unit consists of a set of AND gates and multiple OR gates, each OR gate having two input terminals. The number of AND gates is the same as the number of PWM pulse units; the number of first-stage OR gates is half the number of AND gates rounded up; the number of second-stage OR gates is half the number of first-stage OR gates rounded up; the number of third-stage OR gates is half the number of second-stage OR gates rounded up; and so on, with the final stage OR gate being a single OR gate.

[0092] A set of control signal output terminals of the precision control unit are respectively connected to the first input terminals of a set of AND gates; a set of output terminals of the PWM pulse group unit are respectively connected to the second input terminals of a set of AND gates; the output terminals of a set of AND gates are respectively connected to the input terminals of the first stage OR gate; the output terminals of the first stage OR gate are respectively connected to the input terminals of the second stage OR gate; the output terminals of the second stage OR gate are respectively connected to the input terminals of the third stage OR gate; and so on, with the output terminal of the final stage OR gate connected to the output terminal of the output logic unit.

[0093] Taking a PWM pulse group unit consisting of 8 PWM pulse units as an example, the output logic unit consists of AND gate 1, AND gate 2, AND gate 3, AND gate 4, AND gate 5, AND gate 6, AND gate 7, AND gate 8, and OR gates 11, 12, 13, 14, 21, 22, and 31. All OR gates have two input terminals. OR gates 11, 12, 13, and 14 form the first-stage OR gate, OR gates 15 and 22 form the second-stage OR gate, and OR gate 31 is the third-stage OR gate.

[0094] Specifically, the eight output terminals of the PWM pulse group unit are respectively connected to the first input terminals of the first AND gate AND1, the second AND gate AND2, the third AND gate AND3...the eighth AND gate AND8; the eight control signal output terminals of the precision control unit are respectively connected to the second input terminals of the first AND gate AND1, the second AND gate AND2, the third AND gate AND3...the eighth AND gate AND8; the output terminals of the first AND gate AND1, the second AND gate AND2, the third AND gate AND3...the eighth AND gate AND8 are respectively connected to the eight input terminals of the first-stage OR gate; the four output terminals of the first-stage OR gate are respectively connected to the four input terminals of the second-stage OR gate; the two output terminals of the second-stage OR gate are respectively connected to the two input terminals of the third-stage OR gate; and the output terminal of the third-stage OR gate is connected to the output terminal of the output logic unit.

[0095] When the system needs to output a high-precision PWM pulse signal, the precision control unit controls the corresponding high-level control signal according to the second control signal, and controls the number of AND gates AND1, AND2, AND3... AND8 in the output logic unit from front to back to be turned on. The PWM pulse signals output by the turned-on PWM pulse units are superimposed through three levels of OR gates, so that a high-precision PWM pulse signal is obtained at the output of the last level of OR gate.

[0096] In the second embodiment of the present invention, when the output logic unit outputs a PWM pulse signal, the AND gate and OR gate also generate a very small secondary delay time. Typically, the delay time of the AND gate is about 100 ps, ​​and the delay time from the two input terminals to the output terminal of the OR gate is about 10 ps. Since the pulse signal output by each PWM pulse unit follows the same path through the output logic unit, the phase error between the PWM pulse signals output by each PWM pulse unit in the PWM pulse group unit through the output logic unit is zero, eliminating the influence of the output logic unit itself on the accuracy of the PWM pulse signal.

[0097] In the second embodiment of the present invention, the circuit structure and working principle in other aspects are the same as those in the first embodiment, and therefore will not be described again.

[0098] This invention also provides an integrated circuit chip, which includes the aforementioned high-precision PWM pulse generation circuit for providing multiple PWM pulse signals to the system within the integrated circuit. The specific structure of the high-precision PWM pulse generation circuit in this integrated circuit chip will not be described in detail here.

[0099] In summary, compared with existing technologies, the high-precision PWM pulse generation circuit provided by this invention generates PWM pulse signals with different frequencies and duty cycles by employing different technical solutions for PWM pulse units. Simultaneously, the accuracy of the output PWM pulse signal can be changed by increasing or decreasing the number of PWM pulse units. This achieves the generation and adjustable output of a set of high-precision PWM pulse signals. This PWM pulse generation circuit can improve the accuracy of the output PWM pulse signal by increasing the number of PWM pulse units when the system clock signal frequency cannot be increased. Therefore, the high-precision PWM pulse generation circuit provided by this invention has the advantages of high accuracy, flexible system adjustment, ingenious and reasonable structural design, and low design cost.

[0100] The high-precision PWM pulse generation circuit and chip provided by this invention have been described in detail above. Any obvious modifications made by those skilled in the art without departing from the essence of this invention will fall within the scope of protection of this invention's patent rights.

Claims

1. A high-precision PWM pulse generation circuit, characterized in that It includes a PWM pulse group unit, an output logic unit, and an accuracy control unit; wherein, The PWM pulse group unit is composed of a group of PWM pulse units, and is used to generate a group of PWM pulse signals according to a group of delayed clock signals and a first control signal, and the output end is connected to the output logic unit; The accuracy control unit is used to generate corresponding control signals according to a second control signal, and control the on and off states of each output path in the output logic unit, and its control signals are output to the output logic unit; The output logic unit is used to provide an output path for the PWM pulse signal according to the control of the accuracy control unit, and its output end is connected to the output end of the PWM pulse generation circuit; the output logic unit is composed of a group of AND gates and multiple levels of OR gates, and each OR gate has two input ends; wherein, The number of the AND gates is the same as the number of the PWM pulse units; the number of the first-level OR gates is the ceiling of half of the number of the AND gates; the number of the second-level OR gates is the ceiling of half of the number of the first-level OR gates; the number of the third-level OR gates is the ceiling of half of the number of the second-level OR gates; and so on, the last-level OR gate is one OR gate; One group of control signal output ends of the accuracy control unit are respectively and correspondingly connected to the first input ends of the group of AND gates; One group of output ends of the PWM pulse group unit are respectively and correspondingly connected to the second input ends of the group of AND gates; The output ends of the group of AND gates are respectively and correspondingly connected to the input ends of the first-level OR gates; The output ends of the first-level OR gates are respectively and correspondingly connected to the input ends of the second-level OR gates; The output ends of the second-level OR gates are respectively and correspondingly connected to the input ends of the third-level OR gates; And so on, the output end of the last-level OR gate is connected to the output end of the output logic unit.

2. The high-accuracy PWM pulse generation circuit according to claim 1, wherein: The number of the PWM pulse units is the same as the number of the delayed clock signals; wherein, The first input end of each PWM pulse unit is respectively connected to the first control signal input end; the second input end of the first PWM pulse unit is connected to the original clock signal input end; the second input end of the second PWM pulse unit is connected to the first delayed clock signal input end; the second input end of the third PWM pulse unit is connected to the second delayed clock signal input end; the second input end of the fourth PWM pulse unit is connected to the third delayed clock signal input end; and so on, the second input end of the last PWM pulse unit is correspondingly connected to the last delayed clock signal input end.

3. The high-accuracy PWM pulse generation circuit according to claim 2, wherein: Each of the PWM pulse units is composed of a first counter (Count), a first comparator (Comp), and a first register (RS); wherein, The clock signal input terminal is connected to the input terminal of the first counter (Count) and the clock terminal of the first register (RS). The output terminal of the first counter (Count) is connected to the second input terminal of the first comparator (Comp). The first control signal input terminal is connected to the first input terminal of the first comparator (Comp). The output terminal of the first comparator (Comp) is connected to the input terminal of the first register (RS). The output terminal of the first register (RS) is connected to the output terminal of the PWM pulse unit.

4. The high-precision PWM pulse generation circuit according to claim 2 or 3, wherein: In the PWM pulse unit, when the first counter (Count) uses an up-counting method, the frequency f1 and duty cycle D of the output PWM pulse signal respectively satisfy the following formulas: f1 = F / Nmax D = M / Nmax Where, F is the frequency of the input clock signal, Nmax is the maximum value of the counter; M is the given value of the first control signal, and M < Nmax.

5. The high-precision PWM pulse generation circuit according to claim 2 or 3, wherein: In the PWM pulse unit, when the first counter (Count) uses a down-counting method, the frequency f1 and duty cycle D of the output PWM pulse signal respectively satisfy the following formulas: f1 = F / Nmax D = (Nmax - M) / Nmax Where, F is the frequency of the input clock signal; Nmax is the maximum value of the counter; M is the given value of the first control signal, and M < Nmax.

6. The high-precision PWM pulse generation circuit according to claim 2 or 3, wherein: In the PWM pulse unit, when the first counter (Count) uses a central counting method, the frequency f1 and duty cycle D of the output PWM pulse signal respectively satisfy the following formulas: f1 = F / (2Nmax) D = M / Nmax Where, F is the frequency of the input clock signal; Nmax is the maximum value of the counter; M is the given value of the first control signal, and M < Nmax.

7. The high-precision PWM pulse generation circuit according to claim 1, wherein: The output logic unit is composed of a group of AND gates and the first OR gate (OR01). The number of AND gates is the same as the number of PWM pulse units; wherein, A group of control signal output terminals of the precision control unit are respectively connected to the first input terminals of the group of AND gates correspondingly; A group of output terminals of the PWM pulse group unit are respectively connected to the second input terminals of the group of AND gates correspondingly; The output terminals of the group of AND gates are respectively connected to a group of input terminals of the first OR gate (OR01) correspondingly; The output terminal of the first OR gate (OR01) is connected to the output terminal of the output logic unit.

8. The high-precision PWM pulse generation circuit according to claim 1, wherein: When the frequency of the clock signal increases and / or the number of PWM pulse units in the PWM pulse group unit increases, the precision of the PWM pulse signal output by the PWM pulse generation circuit increases accordingly.

9. An integrated circuit chip, characterized in that The high-precision PWM pulse generation circuit according to any one of claims 1 to 8.

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