A digital-to-analog converter automatic adjustment system and adjustment method based on virtual instrument

Abstract

The present invention relates to a virtual instrument-based automatic tuning system and method for a digital-to-analog converter. The tuning system includes a power supply, a pattern generator, a multimeter, a DAC evaluation board to be tuned, and a host computer. The DAC evaluation board to be tuned includes a DAC chip to be tuned, a crystal oscillator, a clock source chip, a reference source circuit, and a relay. The tuning method controls the pattern generator via the host computer to generate the data code required to tune the DAC chip. Under the control of the host computer, the voltage output by the DAC chip is collected. A tuning code is calculated based on the collected output voltage. The tuning code is fed back to a tuning register corresponding to the DAC via the pattern generator, thereby achieving tuning. The tuning effect is determined by calculating the normalized mean square error of the applied tuning voltage until the tuning requirements are met. The present invention can effectively improve the accuracy and linearity of the digital-to-analog converter.

Description

Technical Field

[0001] The present invention relates to the technical field of high-precision digital-to-analog converters, and in particular to an automatic adjustment system and adjustment method for a high-precision digital-to-analog converter based on a virtual instrument. Background Art

[0002] As a key component connecting digital and analog signals, digital-to-analog converters (DACs) are widely used in a wide range of fields, including radio, digital communications, instrumentation, automatic control, radar, antennas, and more. The performance and accuracy of these components directly determine the quality of these products.

[0003] To improve chip accuracy and performance, current high-speed, high-precision DACs often use a segmented current steering structure that combines high-bit thermometer code with low-bit binary code. This structure improves circuit performance to a certain extent, but still cannot solve the problem of low chip linearity caused by inconsistent components.

[0004] In addition to requiring the use of too many peripheral devices, traditional DAC trimming systems sometimes require manual intervention during the trimming process, making it difficult to automate. Traditional DAC trimming methods often use chip linear error indicators as evaluation indicators, resulting in an excessively long trimming time and introducing greater uncertainty to the system. Summary of the Invention

[0005] The technology of the present invention aims at the defects and shortcomings of the existing technology and provides a digital-to-analog converter automatic adjustment system and adjustment method based on virtual instrument, which can effectively reduce the linear error of the digital-to-analog converter.

[0006] The technical solution of the present invention is:

[0007] A virtual instrument-based digital-to-analog converter automatic adjustment system includes a power supply, a pattern generator, a multimeter, a DAC evaluation board, and a host computer; the DAC evaluation board includes a DAC chip to be adjusted, a crystal oscillator, a clock source chip, a reference source circuit, and a relay;

[0008] The crystal oscillator on the DAC evaluation board is connected to the clock source chip to provide a reference clock for the clock source chip. The clock source chip is connected to the DAC chip to be adjusted to provide an operating clock for the DAC chip to be adjusted. The reference source circuit is connected to the DAC chip to be adjusted to provide a reference voltage. The relay input terminal on the evaluation board is connected to multiple analog output channels of the DAC chip to be adjusted, and the relay output terminal is connected to a multimeter.

[0009] The power supply uses a programmable NI board to power the DAC evaluation board, and the power supply is controlled by the host computer;

[0010] The pattern generator uses an NI board to generate SPI control codes, relay control codes, DAC digital codes, and trim codes.

[0011] The multimeter uses an NI board to collect the DAC output voltage;

[0012] The host computer is connected to the SPI interface and data interface of the DAC chip to be adjusted through the pattern generator, and controls the pattern generator to generate SPI control code, which is used to configure the working mode of the DAC chip to be adjusted and detect whether the read and write functions of the DAC chip register are normal;

[0013] On the DAC evaluation board, the analog output of the DAC chip to be adjusted is connected to the input of the relay to achieve channel switching;

[0014] The host computer is connected to the relay output terminal through a multimeter, and the voltage converted by the DAC chip to be adjusted is collected through the multimeter;

[0015] The host computer can control the code generator to generate corresponding data codes to write data to the DAC chip to be adjusted, and control the multimeter to collect the output voltage of the DAC chip to be adjusted, wherein the output voltage of the DAC chip to be adjusted includes the total voltage controlled by the low-segment binary decoding, the MSB voltage of each bit controlled by the middle-segment binary decoding, and the voltage of each bit controlled by the high-segment thermometer decoding;

[0016] The host computer calculates the trimming reference voltage and the least significant bit voltage based on the collected voltages, and calculates the trimming voltage and trimming code that need to be applied based on the trimming reference voltage. Based on this, the host computer controls the code generator to generate the trimming code to trim the DAC chip. After that, the trimming reference voltage and the least significant bit voltage of the DAC chip after trimming are remeasured, and the trimming effect is judged based on the mean square error of the trimming voltage that needs to be applied.

[0017] Furthermore, the host computer calculates the adjustment code of the DAC chip to be adjusted as follows:

[0018] (2.1) The code generator sends the total code of the low-segment data, which is measured by a multimeter and recorded as V L ;

[0019] (2.2) The MSB data code of each segment sent by the code generator is measured by a multimeter and recorded as V M1 、V M2 ,……,V MB , where B is the number of segment bits in the DAC chip;

[0020] (2.3) The code generator sends each bit of the high-level segment data code, which is measured by the multimeter and recorded as V H1 、V H2、……、 Where C is the number of high-segment bits of the DAC chip;

[0021] (2.4) The host computer calculates the reference voltage value V according to the voltage obtained by the above measurement REF And the least significant bit voltage V of the DAC chip to be adjusted LSB ;

[0022] (2.5) Based on the voltage values ​​obtained above and the reference voltage value, calculate the required adjustment voltage V ADJ The host computer calculates the voltage value that needs to be adjusted and the least significant bit voltage V LSB The ratio of is the analog value Z of each channel’s adjustment code;

[0023] (2.6) Converting each channel's adjustment code analog value into a signed binary code to obtain each channel's adjustment code;

[0024] (2.7) The host computer controls the code generator to generate the k-th channel adjustment code and write it into the k-th adjustment register, thereby achieving the adjustment of the DAC chip.

[0025] Furthermore, in step (2.4), the host computer calculates the reference voltage value V according to the following formula: REF And the least significant bit voltage V of the DAC chip to be adjusted LSB :

[0026]

[0027]

[0028] Among them, A is the low segmentation bit number of the DAC chip, B is the medium segmentation bit number of the DAC chip, and C is the high segmentation bit number of the DAC chip.

[0029] Furthermore, the adjustment voltage V ADJ It is calculated as follows:

[0030] The low segment needs to apply the adjustment voltage V ADJ,L for: Among them, A is the low segment number of the DAC chip, V L The voltage value measured by DAC under the low segment data total code;

[0031] The trimming voltage V that needs to be applied to each bit of the middle segment ADJ,Mi =V ADJ,Mi =2 i V REF -V Mi , where i is 1, 2, ..., B, B is the number of segments, V MiThe voltage value measured by the DAC under each MSB data code of the middle segment;

[0032] The adjustment voltage V that needs to be applied to each bit of the high segment ADJ,Hj =V ADJ,Hj =2 (B+1) V REF -(V Hj -V H(j-1) ), where j is 1, 2, ..., 2 C -1, C is the number of high segment, V Hj It is the voltage value measured by DAC under each data code of the high segment.

[0033] Furthermore, in step (2.5), the host computer calculates the analog value Z of each channel of the adjustment code according to the following formula:

[0034] Z=V ADJ / V LSB .

[0035] Furthermore, the method for judging the adjustment effect is as follows:

[0036] After the host computer completes a single adjustment of the DAC chip to be adjusted, it remeasures the adjustment reference voltage value and the least significant bit voltage. The host computer calculates the normalized mean square error S of the adjustment voltage to be applied based on the above two voltage values. 2 If the mean square error meets the preset range, it is judged that the adjustment effect meets the adjustment requirements. Otherwise, the adjustment does not meet the requirements and is repeated.

[0037] Furthermore, the normalized mean square error S of the voltage value to be adjusted is 2 Calculated by the following formula:

[0038]

[0039] in, The square of the adjustment voltage that needs to be applied to the low segment of the DAC chip, are the squares of the voltages that need to be applied to the middle segments, They are the squares of the trimming voltages required for the high segments.

[0040] Furthermore, the present invention also provides a tuning method, comprising:

[0041] (1) Install the DAC chip to be adjusted on the DAC evaluation board to be adjusted, and power it on by controlling the power module through the host computer;

[0042] (2) The host computer controls the code generator to generate an SPI control signal to reset the DAC chip to be adjusted, and reads and writes the register of the DAC chip to be adjusted through the SPI signal to determine whether the read and write function of the DAC chip register is normal. If it is normal, proceed to step (3), otherwise the adjustment is completed;

[0043] (3) For the DAC chip to be adjusted, the host computer controls the code generator to generate a relay control code to select the corresponding channel to enter the adjustment process;

[0044] (4) The host computer controls the code generator to generate an SPI control signal to configure the code of the DAC chip to be adjusted into a binary complement format;

[0045] (5) The host computer controls the pattern generator to generate an SPI control signal to configure the DAC chip to be adjusted to the external reference mode;

[0046] (6) The host computer controls the code generator to generate a data code and sends it to the DAC chip to be adjusted, and controls the multimeter to measure the output voltage of the corresponding data code, repeating the measurement multiple times to obtain the average;

[0047] (7) The host computer calculates the reference voltage value V according to the formula based on the voltage of each segment measured by the multimeter REF and the least significant bit voltage V LSB ;

[0048] (8) The host computer adjusts the reference voltage value V according to the output voltage value corresponding to each segment data code REF and the least significant bit voltage V LSB Calculate the adjustment code of the DAC chip to be adjusted;

[0049] (9) The host computer controls the code generator to generate the adjustment code of the DAC chip to be adjusted according to the adjustment code calculated in step (8) and writes it into the adjustment register;

[0050] (10) After the trimming chip completes a single trimming, re-measure the output voltage value corresponding to each segmented data code and the trimming reference voltage value V REF and the least significant bit voltage V LSB ;

[0051] (11) The upper computer judges the adjustment effect based on the normalized mean square error of the adjustment voltage to be applied. If the adjustment effect meets the pre-set index requirements, the process proceeds to step (12); otherwise, the process proceeds to step (6) and re-adjusts until the adjustment effect meets the requirements.

[0052] (12) Determine whether each channel of the DAC chip to be trimmed has been trimmed. If so, the trimming is completed. Otherwise, switch channels and go to step (3) to trim again.

[0053] Furthermore, the host computer calculates the reference voltage value V according to the following formula: REF And the least significant bit voltage V of the DAC chip to be adjusted LSB :

[0054]

[0055]

[0056] Among them, A is the low segmentation bit number of the DAC chip, B is the medium segmentation bit number of the DAC chip, and C is the high segmentation bit number of the DAC chip.

[0057] Furthermore, the analog value Z of each channel of the adjustment code is:

[0058] Z=V ADJ / V LSB

[0059] Among them, the adjustment voltage V ADJ It is calculated as follows:

[0060] The low segment needs to apply the adjustment voltage V ADJ,L for: Among them, A is the low segment number of the DAC chip, V L It is the voltage value measured by DAC under the low segment data total code.

[0061] The trimming voltage V that needs to be applied to each bit of the middle segment ADJ,Mi =V ADJ,Mi =2 i V REF -V Mi , where i is 1, 2, ..., B, B is the number of segments, V Mi It is the voltage value measured by DAC under the MSB data code of each segment.

[0062] The adjustment voltage V that needs to be applied to each bit of the high segment ADJ,Hj =V ADJ,Hj =2 (B+1) V REF -(V Hj -V H(j-1) ), where j is 1, 2, ..., 2 C -1, C is the number of high segment, V Hj The voltage value measured by DAC for each bit of high-segment data;

[0063] The analog value Z of each channel adjustment code is converted into a signed binary code, thereby obtaining each channel adjustment code. The beneficial effects of the present invention compared with the prior art are:

[0064] (1) The present invention is different from the traditional adjustment system that requires the cooperation of multiple peripheral devices. It can simplify the adjustment system to the greatest extent, which is conducive to the subsequent system expansion and maintenance.

[0065] (2) The present invention is different from the traditional adjustment system that requires manual cooperation. The entire system can be fully automated from power-on to the end of adjustment.

[0066] (3) The present invention uses the minimum mean square error criterion to judge the adjustment effect. Compared with the traditional method of judging by differential nonlinearity DNL and integral nonlinearity INL, it reduces the calculation of the above two parameters while ensuring the adjustment accuracy, greatly saving the adjustment time.

[0067] (4) Unlike the traditional trimming systems and methods that have the disadvantage of poor adaptability, the present invention can be applied to a variety of DAC circuits. The trimming systems and methods are highly adaptable and portable. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Figure 1 This is a structural diagram of a high-precision digital-to-analog converter automatic adjustment system based on virtual instruments of the present invention;

[0069] Figure 2 This is a flow chart of the adjustment method of the present invention. DETAILED DESCRIPTION

[0070] The present invention will be described in further detail below with reference to the accompanying drawings and specific examples.

[0071] In order to achieve high speed and high precision, modern digital-to-analog converters usually adopt the segmented current steering structure of A+B+C, in which the high segment C bit adopts thermometer decoding to control (2 C The DAC uses a -1)-bit thermometer-coded current source. The middle segment, bit B, uses binary decoding to control the binary-weighted current source for bit B. The low segment, bit A, uses binary decoding to control the binary-weighted current source for bit A. Due to manufacturing process limitations, variations in transistor threshold voltage, gate oxide thickness, channel length, and parasitic capacitance can occur during actual manufacturing. This can lead to mismatches in the current source arrays for each segment, affecting the linearity of the DAC.

[0072] The present invention provides a digital-to-analog converter automatic adjustment system and adjustment method based on virtual instrument, aiming to solve the problem of poor linearity of DAC chip caused by process condition limitations. Figure 1 As shown, the adjustment system includes a power supply, a pattern generator, a multimeter, a DAC evaluation board to be adjusted, and a host computer; the DAC evaluation board to be adjusted includes a DAC chip to be adjusted, a crystal oscillator, a clock source chip, a reference source circuit, and a relay;

[0073] The crystal oscillator on the DAC evaluation board to be adjusted is connected to the clock source chip to provide a reference clock for the clock source chip. The clock source chip is connected to the DAC to be adjusted to provide an operating clock for the DAC chip to be adjusted. The reference source circuit is connected to the DAC chip to be adjusted to provide a high-precision reference voltage for the DAC chip to be adjusted. The relay input terminal on the evaluation board is connected to multiple analog output channels of the DAC, and the output terminal is connected to a multimeter.

[0074] The power supply is used to power the DAC evaluation board to be adjusted, and the power supply can be controlled by the host computer;

[0075] The code generator is used to generate SPI control codes, relay control codes, DAC digital codes and trimming codes;

[0076] The multimeter is used to collect the DAC output voltage;

[0077] The host computer is connected to the SPI interface and data interface of the DAC chip to be adjusted through the pattern generator. It can control the pattern generator to generate SPI control code to configure the working mode of the chip to be adjusted. It can also detect the working status of the chip and whether the register read and write functions are normal.

[0078] The host computer can control the code generator to generate a data code to write data to the DAC chip to be adjusted, and can control the multimeter to collect the output voltage of the DAC chip to be adjusted, wherein the output voltage of the DAC chip to be adjusted includes the total voltage controlled by the low-segment binary decoding, the MSB voltage of each bit controlled by the middle-segment binary decoding, and the voltage of each bit controlled by the high-segment thermometer decoding;

[0079] Furthermore, the host computer calculates the trimming reference voltage based on the collected voltage, and calculates the trimming voltage and trimming code to be applied based on the trimming reference voltage, and controls the code generator to generate the trimming code to trim the DAC chip to be trimmed, and then judges the trimming effect according to the minimum mean square error criterion.

[0080] Furthermore, the host computer calculates the adjustment code of the DAC chip to be adjusted as follows:

[0081] (2.1) The code generator sends the total code of the low-segment data, which is measured by a multimeter and recorded as V L ;

[0082] (2.2) The MSB data code of each segment sent by the code generator is measured by a multimeter and recorded as V M1 、V M2 ,……,V MB ;

[0083] (2.3) The code generator sends each bit of the high-level segment data code, which is measured by the multimeter and recorded as VH1 、V H2 、……、 Where C is the number of high-segment bits of the DAC chip;

[0084] (2.4) The host computer calculates the reference voltage value V according to the voltage obtained by the above measurement REF And the least significant bit voltage V of the DAC chip to be adjusted LSB ;

[0085] The host computer calculates the reference voltage value V according to the following formula REF And the least significant bit voltage V of the DAC chip to be adjusted LSB :

[0086]

[0087]

[0088] Among them, A is the low segmentation bit number of the DAC chip, B is the medium segmentation bit number of the DAC chip, and C is the high segmentation bit number of the DAC chip.

[0089] (2.5) Based on the voltage values ​​obtained above and the reference voltage value, calculate the required adjustment voltage V ADJ The host computer calculates the voltage value that needs to be adjusted and the least significant bit voltage V LSB The ratio of is the analog value Z of each channel’s adjustment code;

[0090] The required adjustment voltage V ADJ It is calculated as follows:

[0091] The low segment needs to apply the adjustment voltage V ADJ,L for: Among them, A is the low segment number of the DAC chip, V L It is the voltage value measured by DAC under the low segment data total code.

[0092] The trimming voltage V that needs to be applied to each bit of the middle segment ADJ,Mi =V ADJ,Mi =2 i V REF -V Mi , where i is 1, 2, ..., B, B is the number of segments, V Mi It is the voltage value measured by DAC under the MSB data code of each segment.

[0093] The adjustment voltage V that needs to be applied to each bit of the high segment ADJ,Hj =V ADJ,Hj =2 (B+1) V REF -(V Hj -VH(j-1) ), where j is 1, 2, ..., 2 C -1, C is the number of high segment, V Hj It is the voltage value measured by DAC under each data code of the high segment.

[0094] The host computer calculates the analog value Z of each channel of adjustment code according to the following formula:

[0095] Z=V ADJ / V LSB

[0096] (2.6) Converting each channel's adjustment code analog value into a signed binary code to obtain each channel's adjustment code;

[0097] (2.7) The host computer controls the code generator to generate the k-th channel adjustment code and write it into the k-th adjustment register, thereby achieving the adjustment of the DAC chip.

[0098] Furthermore, the method for judging the adjustment effect is as follows:

[0099] After the host computer completes a single adjustment of the DAC chip to be adjusted, it remeasures the adjustment reference voltage value and the least significant bit voltage. The host computer calculates the normalized mean square error S of the adjustment voltage to be applied based on the above two voltage values. 2 If the mean square error meets the preset range, it is judged that the adjustment effect meets the adjustment requirements. Otherwise, the adjustment does not meet the requirements and is repeated.

[0100]

[0101] in, The square of the adjustment voltage that needs to be applied to the low segment of the DAC chip, are the squares of the voltages that need to be applied to the middle segments, They are the squares of the trimming voltages required for the high segments.

[0102] like Figure 2 As shown, the present invention provides a tuning method for a high-precision digital-to-analog converter automatic tuning system based on a virtual instrument, comprising the following steps:

[0103] (1) Install the DAC chip to be adjusted on the DAC evaluation board to be adjusted. After ensuring that all system modules are connected correctly, power on the entire system through the host computer control power module.

[0104] (2) The host computer controls the code generator to generate an SPI control signal to reset the chip, and reads and writes the DAC chip register to be adjusted through the SPI signal to determine whether the read and write function of the DAC chip register is normal. If it is normal, proceed to step (3), otherwise the adjustment is completed;

[0105] (3) For multi-channel DAC chips, the host computer controls the code generator to generate relay control codes to select the corresponding channel to enter the adjustment process;

[0106] (4) The host computer controls the code generator to generate an SPI control signal to configure the code of the DAC chip to be adjusted into a binary complement format;

[0107] (5) The host computer controls the pattern generator to generate an SPI control signal to configure the DAC chip to be adjusted to the external reference mode;

[0108] (6) The host computer controls the code generator to generate a data code and sends it to the DAC chip to be adjusted, and controls the multimeter to measure the output voltage of the corresponding data code, repeating the measurement multiple times to obtain the average;

[0109] (7) The host computer calculates the reference voltage value V according to the formula based on the voltage of each segment measured by the multimeter REF and the least significant bit voltage V LSB ;

[0110] (8) The host computer adjusts the reference voltage value V according to the output voltage value corresponding to each segment data code REF and the least significant bit voltage V LSB Calculate the adjustment code of the DAC chip to be adjusted;

[0111] (9) The host computer controls the code generator to generate the adjustment code of the DAC chip to be adjusted according to the adjustment code calculated in step (8) and writes it into the adjustment register;

[0112] (10) After the trimming chip completes a single trimming, re-measure the output voltage value corresponding to each segmented data code and the trimming reference voltage value V REF and the least significant bit voltage V LSB ;

[0113] (11) The upper computer judges the adjustment effect according to the minimum mean square error of the adjustment voltage applied as needed. If the adjustment effect meets the pre-set index requirements, it goes to step (12); otherwise, it goes to step (6) and re-adjusts until the adjustment effect meets the requirements;

[0114] (12) Determine whether each channel of the DAC chip to be trimmed has been trimmed. If so, the trimming is completed. Otherwise, switch channels and go to step (3) to trim again.

[0115] The high-precision digital-to-analog converter adjustment system and adjustment method based on virtual instruments of the present invention have short time consumption, good adjustment effect, high system automation level, and strong adaptability, and can be easily transplanted to other circuits.

[0116] Example:

[0117] A 16-bit, 1.25GSPS current-mode DAC with thermometer decoding for the upper 6 bits, binary decoding for the middle 4 bits, and binary decoding for the lower 6 bits is used as the DAC to be adjusted in the application example of the present invention. The static parameter requirements for this DAC chip are INL between [-4, 4] and DNL between [-2, 2]. The specific implementation process of the present invention is as follows:

[0118] The 16-bit, 1.25GSPS digital-to-analog converter (DAC) to be trimmed is mounted on an evaluation board. The DAC to be trimmed is powered by a 6V power supply and a 10MHz crystal oscillator. This power supply serves as the input reference clock for the clock source chip, which provides the operating clock for the DAC chip. An external reference source chip provides a 1.2V reference voltage for the DAC to be trimmed. A multimeter with 6.5-bit accuracy is selected. The host computer controls the power supply to power up the entire system. After powering up, the DAC to be trimmed is reset. The host computer then controls the pattern generator to generate SPI control codes to read and write to the DAC chip registers, testing the register read and write functionality of the trimming system. Once the system is properly connected and the register read and write functionality is functioning correctly, the host computer selects the corresponding channel to begin trimming and configures the channel via SPI, primarily setting the reference source to external reference mode and the DAC encoding mode to two's complement format.

[0119] In this example, the DAC structure to be adjusted adopts a 6+4+6 segmentation structure. According to the segmentation structure, a total of 68 current sources are controlled, that is, a total of 68 current sources need to be adjusted.

[0120] After the basic mode is configured, the host computer generates a data code by controlling the code generator, and controls the multimeter to collect the output voltage of the DAC chip under the data code. Each voltage is measured 10 times and averaged to obtain each voltage segment. Based on the measured voltage values, the adjustment reference voltage value V is calculated. REF And the least significant bit voltage V of the DAC chip to be adjusted LSB The trimming code can be calculated based on the two voltage values. The host computer converts the trimming code into a signed binary code and controls the pattern generator to generate the trimming code and write it into the trimming register of the DAC chip to be trimmed.

[0121] According to the required range of INL in this example, the mean square error S of the voltage to be adjusted can be calculated. 2 Should be less than 1.9145×10 -4 .

[0122] After the DAC chip was trimmed, the mean square error (MSE) was remeasured and found to meet the requirements. Finally, to further evaluate the effectiveness of the trimming method, the static parameters INL and DNL of the DAC were calculated after the trimming process. The results showed that INL and DNL improved from [-8, 8] and [-5, 5] before trimming to [-4, 4] and [-2, 2], respectively, meeting the trimming requirements.

[0123] The contents not described in detail in the specification of the present invention belong to the common knowledge of professionals in this field.

Claims

1. A digital-to-analog converter automatic adjustment system based on virtual instrumentation, characterized by: Includes power supply, pattern generator, multimeter, DAC evaluation board, and host computer; the DAC evaluation board includes the DAC chip to be adjusted, crystal oscillator, clock source chip, reference source circuit, and relay; The crystal oscillator on the DAC evaluation board is connected to the clock source chip to provide a reference clock for the clock source chip. The clock source chip is connected to the DAC chip to be adjusted to provide an operating clock for the DAC chip to be adjusted. The reference source circuit is connected to the DAC chip to be adjusted to provide a reference voltage. The relay input terminal on the evaluation board is connected to multiple analog output channels of the DAC chip to be adjusted, and the relay output terminal is connected to a multimeter. The power supply uses a programmable NI board to power the DAC evaluation board, and the power supply is controlled by the host computer; The pattern generator uses an NI board to generate SPI control codes, relay control codes, DAC digital codes, and trim codes. The multimeter uses an NI board to collect the DAC output voltage; The host computer is connected to the SPI interface and data interface of the DAC chip to be adjusted through the pattern generator, and controls the pattern generator to generate SPI control code, which is used to configure the working mode of the DAC chip to be adjusted and detect whether the read and write functions of the DAC chip register are normal; On the DAC evaluation board, the analog output of the DAC chip to be adjusted is connected to the input of the relay to achieve channel switching; The host computer is connected to the relay output terminal through a multimeter, and the voltage converted by the DAC chip to be adjusted is collected through the multimeter; The host computer can control the code generator to generate corresponding data codes to write data to the DAC chip to be adjusted, and control the multimeter to collect the output voltage of the DAC chip to be adjusted, wherein the output voltage of the DAC chip to be adjusted includes the total voltage controlled by the low-segment binary decoding, the MSB voltage of each bit controlled by the middle-segment binary decoding, and the voltage of each bit controlled by the high-segment thermometer decoding; The host computer calculates the trimming reference voltage and the least significant bit voltage based on the collected voltages, and calculates the trimming voltage and trimming code that need to be applied based on the trimming reference voltage. Based on this, the host computer controls the code generator to generate the trimming code to trim the DAC chip. After that, the trimming reference voltage and the least significant bit voltage of the DAC chip after trimming are remeasured, and the trimming effect is judged based on the mean square error of the trimming voltage that needs to be applied.

2. The automatic adjustment system for digital-to-analog converters based on virtual instruments according to claim 1, characterized in that: The host computer calculates the adjustment code of the DAC chip to be adjusted as follows: (2.1) The code generator sends the total code of the low-segment data, which is measured by a multimeter and recorded as V L ; (2.2) The MSB data code of each segment sent by the code generator is measured by a multimeter and recorded as V M1 、V M2 ,……,V MB , where B is the number of segment bits in the DAC chip; (2.3) The code generator sends each bit of the high-level segment data code, which is measured by the multimeter and recorded as V H1 、V H2 ,……,V H(2C-1) , where C is the number of high-segment bits of the DAC chip; (2.4) The host computer calculates the reference voltage value V according to the voltage obtained by the above measurement REF And the least significant bit voltage V of the DAC chip to be adjusted LSB ; (2.5) Based on the voltage values ​​obtained above and the reference voltage value, calculate the required adjustment voltage V ADJ The host computer calculates the voltage value that needs to be adjusted and the least significant bit voltage V LSB The ratio of is the analog value Z of each channel’s adjustment code; (2.6) Converting each channel's adjustment code analog value into a signed binary code to obtain each channel's adjustment code; (2.7) The host computer controls the code generator to generate the k-th channel adjustment code and write it into the k-th adjustment register, thereby achieving the adjustment of the DAC chip.

3. The automatic adjustment system for digital-to-analog converters based on virtual instruments according to claim 2, characterized in that: In step (2.4), the host computer calculates the reference voltage value V according to the following formula REF And the least significant bit voltage V of the DAC chip to be adjusted LSB : Among them, A is the low segmentation bit number of the DAC chip, B is the medium segmentation bit number of the DAC chip, and C is the high segmentation bit number of the DAC chip.

4. The automatic adjustment system for digital-to-analog converters based on virtual instruments according to claim 3, characterized in that: The required adjustment voltage V ADJ It is calculated as follows: The low segment needs to apply the adjustment voltage V ADJ,L for: Among them, A is the low segment number of the DAC chip, V L The voltage value measured by DAC under the low segment data total code; The trimming voltage V that needs to be applied to each bit of the middle segment ADJ,Mi =V ADJ,Mi =2 i V REF -V Mi , where i is 1, 2, ..., B, B is the number of segments, V Mi The voltage value measured by the DAC under each MSB data code of the middle segment; The adjustment voltage V that needs to be applied to each bit of the high segment ADJ,Hj =V ADJ,Hj =2 (B+1) V REF -(V Hj -V H(j-1) ), where j is 1, 2, ..., 2 C -1, C is the number of high-segment digits, V Hj It is the voltage value measured by DAC under each data code of the high segment.

5. The automatic adjustment system for digital-to-analog converters based on virtual instruments according to claim 4, characterized in that: In step (2.5), the host computer calculates the analog value Z of each channel of the adjustment code according to the following formula: Z=V ADJ / V LSB 。 6. The automatic adjustment system for digital-to-analog converters based on virtual instruments according to claim 2, characterized in that: The method for judging the effect of the adjustment is as follows: After the host computer completes a single adjustment of the DAC chip to be adjusted, it remeasures the adjustment reference voltage value and the least significant bit voltage. The host computer calculates the normalized mean square error S of the adjustment voltage to be applied based on the above two voltage values. 2 If the mean square error meets the preset range, it is judged that the adjustment effect meets the adjustment requirements. Otherwise, the adjustment does not meet the requirements and is repeated.

7. The automatic adjustment system for digital-to-analog converters based on virtual instruments according to claim 6, characterized in that: The normalized mean square error S of the voltage value that needs to be adjusted 2 Calculated by the following formula: in, The square of the adjustment voltage that needs to be applied to the low segment of the DAC chip, are the squares of the voltages that need to be applied to the middle segments, They are the squares of the trimming voltages required for the high segments.

8. A method for adjusting a digital-to-analog converter implemented by the automatic adjustment system according to any one of claims 1 to 7, characterized in that include: (1) Install the DAC chip to be adjusted on the DAC evaluation board to be adjusted, and power it on by controlling the power module through the host computer; (2) The host computer controls the code generator to generate an SPI control signal to reset the DAC chip to be adjusted, and reads and writes the register of the DAC chip to be adjusted through the SPI signal to determine whether the read and write function of the DAC chip register is normal. If it is normal, proceed to step (3), otherwise the adjustment is completed; (3) For the DAC chip to be adjusted, the host computer controls the code generator to generate a relay control code to select the corresponding channel to enter the adjustment process; (4) The host computer controls the code generator to generate an SPI control signal to configure the code of the DAC chip to be adjusted into a binary complement format; (5) The host computer controls the pattern generator to generate an SPI control signal to configure the DAC chip to be adjusted to the external reference mode; (6) The host computer controls the code generator to generate a data code and sends it to the DAC chip to be adjusted, and controls the multimeter to measure the output voltage of the corresponding data code, repeating the measurement multiple times to obtain the average; (7) The host computer calculates the reference voltage value V according to the formula based on the voltage of each segment measured by the multimeter REF and the least significant bit voltage V LSB ; (8) The host computer adjusts the reference voltage value V according to the output voltage value corresponding to each segment data code REF and the least significant bit voltage V LSB Calculate the adjustment code of the DAC chip to be adjusted; (9) The host computer controls the code generator to generate the adjustment code of the DAC chip to be adjusted according to the adjustment code calculated in step (8) and writes it into the adjustment register; (10) After the trimming chip completes a single trimming, re-measure the output voltage value corresponding to each segmented data code and the trimming reference voltage value V REF and the least significant bit voltage V LSB ; (11) The upper computer judges the adjustment effect based on the normalized mean square error of the adjustment voltage to be applied. If the adjustment effect meets the pre-set index requirements, the process proceeds to step (12); otherwise, the process proceeds to step (6) and re-adjusts until the adjustment effect meets the requirements. (12) Determine whether each channel of the DAC chip to be trimmed has been trimmed. If so, the trimming is completed. Otherwise, switch channels and go to step (3) to trim again.

9. The adjustment method according to claim 8, characterized in that: The host computer calculates the reference voltage value V according to the following formula REF And the least significant bit voltage V of the DAC chip to be adjusted LSB : Among them, A is the low segmentation bit number of the DAC chip, B is the medium segmentation bit number of the DAC chip, and C is the high segmentation bit number of the DAC chip.

10. The adjustment method according to claim 9, characterized in that: The analog value Z of each channel adjustment code: Z=V ADJ / V LSB Among them, the adjustment voltage V ADJ It is calculated as follows: The low segment needs to apply the adjustment voltage V ADJ,L for: Among them, A is the low segment number of the DAC chip, V L The voltage value measured by DAC under the low segment data total code; The trimming voltage V that needs to be applied to each bit of the middle segment ADJ,Mi =V ADJ,Mi =2 i V REF -V Mi , where i is 1, 2, ..., B, B is the number of segments, V Mi The voltage value measured by the DAC under each MSB data code of the middle segment; The adjustment voltage V that needs to be applied to each bit of the high segment ADJ,Hj =V ADJ,Hj =2 (B+1) V REF -(V Hj -V H(j-1) ), where j is 1, 2, ..., 2 C -1, C is the number of high-segment digits, V Hj The voltage value measured by DAC for each bit of high-segment data; The analog value Z of each trimming code is converted into a signed binary code, thereby obtaining each trimming code.

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