Display substrate and display device

Abstract

A display substrate includes a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of test circuit groups, a plurality of burn-in pin groups and a plurality of binding pin groups. The substrate includes a display area and a binding area located at one side of the display area. The plurality of sub-pixels are located in the display area. The plurality of data lines are electrically connected with the plurality of sub-pixels. The plurality of test circuit groups are arranged along a first direction and are electrically connected with the plurality of data lines. The plurality of burn-in pin groups and the plurality of binding pin groups are located in the binding area and are located at a side of the plurality of test circuit groups away from the display area. The plurality of binding pin groups are arranged along the first direction, and at least one burn-in pin group is arranged between two adjacent binding pin groups. Each binding pin group is configured to be bound with at least one circuit board. Each test circuit group is configured to be connected with at least one burn-in pin group in a test phase.

Description

TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, in particular to a display substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility and low cost. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0004] The embodiments of the present disclosure provide a display substrate and a display device.

[0005] In one aspect, the embodiments of the present disclosure provide a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of test circuit groups, a plurality of burn-in pin groups and a plurality of binding pin groups. The substrate comprises a display area and a binding area located on one side of the display area. The plurality of sub-pixels are located in the display area. The plurality of data lines are located in the display area and the binding area, and the plurality of data lines are electrically connected to the plurality of sub-pixels. The plurality of test circuit groups are arranged along a first direction, and the plurality of test circuit groups are electrically connected to the plurality of data lines. The plurality of burn-in pin groups and the plurality of binding pin groups are located in the binding area and on a side of the plurality of test circuit groups away from the display area. The plurality of binding pin groups are arranged along the first direction, and at least one burn-in pin group is arranged between any two adjacent binding pin groups. Each binding pin group is configured to be bound to at least one circuit board. Each test circuit group is configured to be connected to at least one burn-in pin group in a test phase.

[0006] In some example embodiments, the plurality of binding pin groups comprises n binding pin groups, n is a positive integer greater than or equal to 3, and the first binding pin group, the second binding pin group and the n-th binding pin group are sequentially arranged in the first direction. One burn-in pin group arranged between the first binding pin group and the second binding pin group comprises a plurality of first burn-in pins for transmitting gate driving control signals arranged continuously in the first direction. One burn-in pin group arranged between the n-th binding pin group and the n-1-th binding pin group comprises a plurality of first burn-in pins for transmitting gate driving control signals arranged continuously in the first direction.

[0007] In some example embodiments, the display substrate further comprises: a frame area located at the rest of the sides of the display area, the frame area being provided with a gate drive circuit, the gate drive circuit being configured to connect the first aging pins in the first and second aging pin groups and the n-th and (n-1)-th aging pin groups in the test phase.

[0008] In some example embodiments, one or two aging pin groups are provided between two adjacent binding pin groups.

[0009] In some example embodiments, each of the plurality of aging pin groups comprises: a plurality of second aging pins for transmitting direct current signals arranged continuously along the first direction.

[0010] In some example embodiments, at least one of the plurality of aging pin groups comprises: a plurality of first aging pins for transmitting gate drive control signals arranged continuously along the first direction and a plurality of second aging pins for transmitting direct current signals arranged continuously along the first direction, and the plurality of second aging pins are located on one side of the plurality of first aging pins close to the edge of the display substrate.

[0011] In some example embodiments, the first aging pins of at least one of the plurality of aging pin groups are configured to be electrically connected with the first aging pins of the rest of the aging pin groups for transmitting the same signals in the test phase.

[0012] In some example embodiments, the second aging pins of the plurality of aging pin groups for transmitting the same signals are configured to be electrically connected in the test phase.

[0013] In some example embodiments, the plurality of test circuit groups are connected through test circuit connection lines.

[0014] In some example embodiments, at least one of the plurality of test circuit groups is configured to be connected with two aging pin groups in the test phase, and the two aging pin groups are located on both sides of the at least one test circuit group.

[0015] In some example embodiments, the pins for transmitting the same signals in the aging pin groups electrically connected with different test circuit groups and arranged adjacently are configured to be electrically connected in the test phase.

[0016] In some example embodiments, the pins for transmitting the same signals in the aging pin groups electrically connected with the same test circuit group and arranged adjacently are configured to be electrically connected in the test phase.

[0017] In some example embodiments, the plurality of burn-in pin groups are arranged along the first direction, and the plurality of burn-in pin groups and the plurality of binding pin groups are arranged side by side in the first direction.

[0018] In some example embodiments, each of the plurality of binding pin groups comprises a plurality of access pins, at least one first power pin and at least one second power pin arranged along the first direction; the first power pin and the second power pin within each of the binding pin groups are configured to be used as burn-in pins in the burn-in phase, and each of the binding pin groups is configured to be bound with at least one circuit board after the burn-in phase.

[0019] In another aspect, the embodiments of the present disclosure provide a display device, comprising the display substrate as described above.

[0020] In another aspect, the embodiments of the present disclosure provide a display substrate, comprising a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of driving chip pin groups, a plurality of burn-in pin groups and a plurality of binding pin groups. The substrate comprises a display area and a binding area located at one side of the display area. The plurality of sub-pixels are located in the display area. The plurality of data lines are located in the display area and the binding area, and are electrically connected to the plurality of sub-pixels. The plurality of driving chip pin groups are located in the binding area and arranged along a first direction, and are connected to the plurality of data lines, and are configured to be bound with driving chips. The plurality of burn-in pin groups and the plurality of binding pin groups are located in the binding area and located at a side of the plurality of driving chip pin groups away from the display area, the plurality of binding pin groups are arranged along the first direction, and are connected to the plurality of driving chip pin groups through pin connection lines. At least one burn-in pin group is arranged between two adjacent binding pin groups.

[0021] In some example embodiments, the plurality of burn-in pin groups are arranged along the first direction, and the plurality of burn-in pin groups and the plurality of binding pin groups are arranged side by side in the first direction.

[0022] In some example embodiments, the plurality of binding pin groups and the plurality of driving chip pin groups are electrically connected one by one.

[0023] In some example embodiments, the plurality of driving chip pin groups comprises m driving chip pin groups, m is a positive integer greater than or equal to 3, and the plurality of driving chip pin groups comprises a first driving chip pin group, a second driving chip pin group and an mth driving chip pin group in the first direction. The display substrate further comprises a frame area located at the remaining side of the display area, and the frame area is provided with a gate drive circuit, and the gate drive circuit is configured to be electrically connected to the first driving chip pin group and the mth driving chip pin group through a first signal transmission line.

[0024] In some exemplary embodiments, one or two aging pin groups are provided between two adjacent bonded pin groups.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0027] Figure 1 This is a schematic diagram of the structure of a display device;

[0028] Figure 2 This is a planar schematic diagram of a display substrate;

[0029] Figure 3 This is a schematic diagram of a partial cross-sectional structure of the display area of ​​a display substrate;

[0030] Figure 4 This is a schematic diagram showing the arrangement of multiple display substrates in the motherboard.

[0031] Figure 5 This is a schematic diagram of the bonding area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0032] Figure 6 This is a partial schematic diagram of a display motherboard according to at least one embodiment of the present disclosure;

[0033] Figure 7A for Figure 6 A partial distribution diagram of the intermediate aging pin group 31g and the bonding pin group 41a;

[0034] Figure 7B for Figure 6 A partial distribution diagram of the intermediate aging pin group 31h and the bonding pin group 41d;

[0035] Figure 8A and Figure 8B for Figure 6 A partial schematic diagram of the pin-binding area and the first cutting area;

[0036] Figure 9A This is a schematic diagram of the bonding area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0037] Figure 9B for Figure 9A A partial schematic diagram of the bonding area of ​​the display substrate;

[0038] Figure 10A A schematic view of a binding area of a display substrate according to at least one embodiment of the present disclosure;

[0039] Figure 10B A partial schematic view of a binding area of a display substrate in Figure 10A

[0040] Figure 11A A schematic view of a binding area of a display substrate according to at least one embodiment of the present disclosure;

[0041] Figure 11B A partial schematic view of a binding area of a display substrate in Figure 11A

[0042] Figure 12A A schematic view of a binding area of a display substrate according to at least one embodiment of the present disclosure;

[0043] Figure 12B A partial schematic view of a binding area of a display substrate in Figure 12A

[0044] Figure 13 An equivalent circuit diagram of a test circuit according to at least one embodiment of the present disclosure;

[0045] Figure 14 A planar schematic view of a test circuit according to at least one embodiment of the present disclosure;

[0046] Figure 15A A partial schematic view of an aging pin group 31g and a binding pin group 41a in Figure 6

[0047] Figure 15B A partial schematic view of an aging pin group 31h and a binding pin group 41d in Figure 6

[0048] Figure 16 A partial schematic view of a binding pin area and a first cutting area in Figure 6

[0049] Figure 17 A schematic view of a binding area of a display substrate according to at least one embodiment of the present disclosure;

[0050] Figure 18 A partial schematic view of a display motherboard according to at least one embodiment of the present disclosure;

[0051] Figure 19 A partial schematic view of a binding pin area and a first cutting area in Figure 18

[0052] Figure 20 ​​​​​​​A schematic view of a binding area of a display substrate according to at least one embodiment of the present disclosure;

[0053] Figure 21 A partial schematic view of a display mother substrate according to at least one embodiment of the present disclosure;

[0054] Figure 22 A partial schematic view of a display mother substrate according to at least one embodiment of the present disclosure; Figure 21 A partial schematic view of a display mother substrate according to at least one embodiment of the present disclosure; DETAILED DESCRIPTION

[0055] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. The embodiments can be implemented in various forms. It is readily apparent to those skilled in the art that the embodiments and features thereof can be changed or replaced without departing from the gist of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other as long as there is no contradiction.

[0056] In the drawings, the size, the thickness, or the region of one or more constituent elements is sometimes exaggerated, and the like for the sake of explanation. Therefore, one embodiment of the present disclosure should not be interpreted as being limited to the drawings only. The pattern of the drawing is schematically shown, and one embodiment of the present disclosure is not limited to the shape or the value shown in the drawing.

[0057] In this specification, ordinal terms such as "first", "second", and "third" are used to avoid confusion among constituent elements, and are not used to constitute a limitation as to the number thereof. In the present disclosure, "a plurality of" means two or more.

[0058] In this specification, in order to facilitate the explanation of the position relationship of the constituent elements with reference to the drawings, the words of indicating the orientation or the positional relationship, such as "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are used, and are merely intended to facilitate the description of the specification and simplify the description, and therefore cannot be understood as indicating or implying that a specific orientation is required for the device or element to have a particular orientation, be constructed and operated, and therefore cannot be construed as limiting the present disclosure. The position relationship of the constituent elements is appropriately changed according to the direction of the described constituent elements. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0059] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", "connected" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or connected; it can be directly connected, or indirectly connected through an intermediate piece, or connected inside two elements. For those skilled in the art, the meaning of the above terms in this disclosure can be understood according to the situation.

[0060] In this specification, "electrically connected" includes the case where the constituent elements are connected together through an element having some electrical effect. The "element having some electrical effect" is not particularly limited as long as it can transmit electrical signals between the connected constituent elements. Examples of the "element having some electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0061] In this specification, a transistor refers to an element including at least three terminals of a gate, a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to a region where current mainly flows.

[0062] In this specification, the first pole can be a drain, and the second pole can be a source, or the first pole can be a source, and the second pole can be a drain. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in circuit operation, the functions of "source" and "drain" are sometimes exchanged with each other. Therefore, in this specification, "source" and "drain" can be interchanged. In addition, the gate can also be referred to as the control pole.

[0063] In this specification, "parallel" refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0064] In this specification, a circle, an ellipse, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly, and can be an approximate circle, an approximate ellipse, an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, or an approximate hexagon, etc. There can be some small deformations due to tolerances, such as a lead angle, an arc edge, and a deformation, etc.

[0065] In the present disclosure, "about" or "approximately" means not strictly limited to the boundary, allowing for a range of process and measurement errors. In the present disclosure, "about the same" means within 10% of the value.

[0066] In the present disclosure, A extending along B means that A can include a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment or a bar-shaped body, the main portion stretches along the B direction, and the length of the main portion stretching along the B direction is greater than the length of the secondary portion stretching along other directions. In the present disclosure, "A extending along B" means "the main portion of A extending along B".

[0067] Figure 1 A schematic structural diagram of a display device. In some examples, as shown in Figure 1 The display device can include a timing controller 21, a data driver 22, a scan driving circuit 23, a light emitting driving circuit 24, and a sub-pixel array 25. In some examples, the sub-pixel array 25 can include a plurality of sub-pixels PX arranged regularly. The scan driving circuit 23 can be configured to provide a scan signal to the sub-pixels PX along a scan line; the data driver 22 can be configured to provide a data voltage to the sub-pixels PX along a data line; the light emitting driving circuit 24 can be configured to provide a light emitting control signal to the sub-pixels PX along a light emitting control line; and the timing controller 21 can be configured to control the scan driving circuit 23, the light emitting driving circuit 24, and the data driver 22.

[0068] In some examples, as shown in Figure 1As shown, the timing controller 21 can provide grayscale values and control signals suitable for the specifications of the data driver 22 to the data driver 22; the timing controller 21 can provide a scan clock signal, a scan start signal, and the like suitable for the specifications of the scan driving circuit 23 to the scan driving circuit 23; the timing controller 21 can provide a light emission clock signal, a light emission start signal, and the like suitable for the specifications of the light emission driving circuit 24 to the light emission driving circuit 24. The data driver 22 can generate data voltages to be provided to the data lines D1 to Di using the grayscale values and the control signals received from the timing controller 21. For example, the data driver 22 can sample the grayscale values using the clock signal, and apply data voltages corresponding to the grayscale values to the data lines D1 to Di in units of sub-pixels. The scan driving circuit 23 can generate scan signals to be provided to the scan lines S1 to Sj by the scan clock signal, the scan start signal, and the like received from the timing controller 21. For example, the scan driving circuit 23 can sequentially provide scan signals having pulses of an on level to the scan lines. In some examples, the scan driving circuit 23 can include a shift register, and can generate the scan signals in a manner that sequentially transfers the scan start signal provided in the form of a pulse of the on level to a next stage circuit under the control of the scan clock signal. The light emission driving circuit 24 can generate light emission control signals to be provided to the light emission control lines E1 to Eo by the light emission clock signal, the light emission start signal, and the like received from the timing controller 21. For example, the light emission driving circuit 24 can sequentially provide light emission control signals having pulses of an off level to the light emission control lines. The light emission driving circuit 24 can include a shift register to generate the light emission control signals in a manner that sequentially transfers the light emission start signal provided in the form of a pulse of the off level to a next stage circuit under the control of the clock signal. Here, i, j, and o are each a natural number.

[0069] In some examples, the display apparatus can include a display substrate. The scan driving circuit and the light emission driving circuit can be directly disposed on the display substrate. For example, the scan driving circuit can be disposed on a left bezel of the display substrate, and the light emission driving circuit can be disposed on a right bezel of the display substrate; or, the left bezel and the right bezel of the display substrate can each be provided with the scan driving circuit and the light emission driving circuit. In some examples, the scan driving circuit and the light emission driving circuit can be formed together with the sub-pixels in a process of forming the sub-pixels.

[0070] In some examples, the data driver can be disposed on a separate chip or printed circuit board to connect to the sub-pixels through the signal access pins on the display substrate. For example, the data driver can be formed on the display substrate in a first bezel of the display substrate in a chip on glass, chip on plastic, chip on film, etc. to connect to the signal access pins. The timing controller can be disposed separately from the data driver or integrally with the data driver. However, the present embodiments are not limited thereto. In some examples, the data driver can be directly disposed on the display substrate.

[0071] Figure 2 FIG. 1 is a plan view of a display substrate, according to an example embodiment. Figure 2 As shown in FIG. 1, the display substrate can include a display area AA, a binding area B1 on one side of the display area AA, and a bezel area B2 on the other side of the display area AA. The binding area B1 can be, for example, a lower bezel of the display substrate, and the bezel area B2 can include an upper bezel, a left bezel, and a right bezel of the display substrate. In some examples, the display area AA can be a flat area including a plurality of sub-pixels PX constituting a pixel array, the plurality of sub-pixels PX being configured to display dynamic pictures or still images. The display area can be referred to as an active area. In some examples, the display substrate can be a flexible substrate, and thus the display substrate can be deformable, for example, rolled, bent, folded, or rolled up.

[0072] In some examples, the bezel area B2 can include, in order along a direction of the display area AA, a circuit region, a power line region, a crack dam region, and a cutting region. The circuit region can be connected to the display area AA and can include at least a plurality of cascaded gate driving circuits electrically connected to a plurality of gate lines in the display area AA. The power line region can be connected to the circuit region and can include at least a low-level power line extending along a direction parallel to an edge of the display area and connected to cathodes of the display area. The crack dam region can be connected to the power line region and can include at least a plurality of cracks provided on a composite insulating layer. The cutting region can be connected to the crack dam region and can include at least a cutting groove provided on the composite insulating layer, the cutting groove being configured to be cut along the cutting groove after all film layers of the display substrate are prepared.

[0073] In some examples, the binding area B1 and the bezel area B2 can be provided with a first isolation dam and a second isolation dam, the first isolation dam and the second isolation dam extending along a direction parallel to an edge of the display area, forming a ring structure surrounding the display area AA, the edge of the display area being an edge of the display area close to the binding area or the bezel area.

[0074] In some examples, as shown in FIG. 2, the display substrate can include a display area AA, a binding area B1 on one side of the display area AA, and a bezel area B2 on the other side of the display area AA. The binding area B1 can be, for example, a lower bezel of the display substrate, and the bezel area B2 can include an upper bezel, a left bezel, and a right bezel of the display substrate. In some examples, the display area AA can be a flat area including a plurality of sub-pixels PX constituting a pixel array, the plurality of sub-pixels PX being configured to display dynamic pictures or still images. The display area can be referred to as an active area. In some examples, the display substrate can be a flexible substrate, and thus the display substrate can be deformable, for example, rolled, bent, folded, or rolled up. Figure 2As shown, the display region AA can include at least a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL can extend along a first direction X, and the plurality of data lines DL can extend along a second direction Y. The orthogonal projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate substrate cross to form a plurality of sub-pixel regions, and one sub-pixel PX is arranged in each sub-pixel region. The plurality of data lines DL are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL can be configured to provide data signals to the plurality of sub-pixels PX. The plurality of data lines DL can extend to the bonding region B1. The plurality of gate lines GL are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL can be configured to provide gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signals can include scan signals and light-emitting control signals.

[0075] In some examples, as shown in FIG. 1A, the first direction X can be the extension direction (row direction) of the gate lines GL in the display region AA, and the second direction Y can be the extension direction (column direction) of the data lines DL in the display region AA. The first direction X and the second direction Y can be perpendicular to each other. Figure 2

[0076] In some examples, one pixel unit of the display region AA can include three sub-pixels, which are red sub-pixels, green sub-pixels, and blue sub-pixels, respectively. However, the present embodiments are not limited thereto. In some examples, one pixel unit can include four sub-pixels, which are red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, respectively.

[0077] In some examples, the shape of a sub-pixel can be rectangular, rhombic, pentagonal, or hexagonal. When one pixel unit includes three sub-pixels, the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular manner. When one pixel unit includes four sub-pixels, the four sub-pixels can be arranged in a horizontal parallel, vertical parallel, or square manner. However, the present embodiments are not limited thereto.

[0078] In some examples, one sub-pixel can include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit can include a plurality of transistors and at least one capacitor, for example, a 3T1C (i.e., 3 transistors and 1 capacitor) structure, a 7T1C (i.e., 7 transistors and 1 capacitor) structure, a 5T1C (i.e., 5 transistors and 1 capacitor) structure, an 8T1C (i.e., 8 transistors and 1 capacitor) structure, or an 8T2C (i.e., 8 transistors and 2 capacitors) structure, etc.

[0079] ​In some examples, the light emitting element can be any one of a light emitting diode (LED), an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light emitting element can be an OLED, which can emit red light, green light, blue light, or white light, etc. under the driving of the corresponding pixel circuit. The color of the light emitted by the light emitting element can be determined as needed. In some examples, the light emitting element can include an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode of the light emitting element can be electrically connected to the corresponding pixel circuit. However, the present embodiment is not limited in this regard.

[0080] Figure 3 A schematic diagram of a partial cross-sectional structure of a display area of a display substrate. Figure 3 The structure of three sub-pixels of the display substrate is illustrated. In some examples, as shown in Figure 3 In the direction perpendicular to the display substrate, the display substrate can include a substrate 101, and a circuit structure layer 102, a light emitting structure layer 103, an encapsulation structure layer 104, and an encapsulation cover plate 200 arranged in sequence on the substrate 101. In some possible implementations, the display substrate can include other film layers, such as a spacer, a touch structure layer, etc., which are not limited in the present disclosure.

[0081] In some examples, the substrate 101 can be a rigid substrate, for example, a glass substrate. However, the present embodiment is not limited in this regard. For example, the substrate can be a flexible substrate, for example, prepared from an insulating material such as resin. In addition, the substrate can be a single-layer structure or a multi-layer structure. When the substrate is a multi-layer structure, for example, inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride can be disposed between multiple layers in a single layer or multiple layers.

[0082] In some examples, the circuit structure layer 102 of each sub-pixel can include a plurality of transistors and a storage capacitor constituting a pixel circuit, Figure 3The illustration uses an example of each sub-pixel containing a transistor and a storage capacitor. In some possible implementations, the circuit structure layer 102 of each sub-pixel may include: an active layer disposed on a substrate 101; a first insulating layer 11 (or a first gate insulating layer) covering the active layer; a first gate metal layer (e.g., including the gate electrode and first capacitor electrode of a transistor) disposed on the first insulating layer 11; a second insulating layer 12 (or a second gate insulating layer) covering the first gate metal layer; a second gate metal layer (e.g., including a second capacitor electrode) disposed on the second insulating layer 12; a third insulating layer 13 (or an interlayer insulating layer) covering the second gate metal layer, wherein a plurality of first vias are formed on the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13, and the plurality of first vias can expose the active layer; a first source / drain metal layer (e.g., including the source electrode and drain electrode of a transistor) disposed on the third insulating layer 13, wherein the source electrode and drain electrode can be connected to the active layer through the first vias respectively; and a first planarization layer 14 covering the aforementioned structure, wherein a second via is formed on the first planarization layer 14, and the second via can expose the drain electrode. The active layer, gate electrode, source electrode, and drain electrode can form a transistor 105, and the first capacitor electrode and the second capacitor electrode can form a storage capacitor 106.

[0083] In some examples, such as Figure 3 As shown, the light-emitting structure layer 103 may include an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode layer may include the anode of the light-emitting element, which may be disposed on the first planarization layer 14 and electrically connected to the drain electrode of the transistor of the pixel circuit through a second via formed in the first planarization layer 14; the pixel definition layer is disposed on the anode layer and the first planarization layer, and the pixel definition layer has a pixel opening that exposes at least a portion of the surface of the anode; the organic light-emitting layer is at least partially disposed within the pixel opening and is connected to the anode; the cathode is disposed on the organic light-emitting layer and is connected to the organic light-emitting layer; the organic light-emitting layer emits light of the corresponding color under the drive of the anode and the cathode.

[0084] In some examples, such as Figure 3 As shown, the encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to ensure that external moisture cannot enter the light-emitting structure layer 103.

[0085] In some examples, the organic light-emitting layer may include at least a hole injection layer, a hole transport layer, a light-emitting layer, and a hole blocking layer stacked on the anode. In some examples, the hole injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the hole blocking layers may be a common layer connected together. However, this embodiment is not limited in this respect.

[0086] In some implementations, during the fabrication of the display substrate, a display motherboard can be prepared first, and then the display motherboard can be cut to divide the display motherboard into multiple display substrates, and a single display substrate can be used to form a single display device. Figure 4 This is a schematic diagram showing the arrangement of multiple display substrates within a display motherboard. (Example) Figure 4 As shown, the display motherboard 100 may include a plurality of substrate regions 300 arranged in a periodic and regular pattern, and a cutting region 400 located outside the substrate regions 300. The substrate regions 300 include at least a display region AA and a bonding region B1, and the bonding region B1 may include a bonding pin region located on one side of the display region AA. A first cutting track 701 and a second cutting track 702 may be provided within the cutting region 400. After all film layers of the display motherboard are prepared, the cutting equipment can perform rough cutting and fine cutting along the first cutting track 701 and the second cutting track 702, respectively.

[0087] In some implementations, multiple detections need to be performed during the preparation process of the display substrate, one of which is the cell test light-on, also known as ET light-on detection. The ET light-on detection is performed before the display substrate is bonded to the circuit board, in which a detection signal is input to the display substrate to make the sub-pixels present colors, and a defect detection device is used to check whether each sub-pixel is good or not, so as to confirm whether the display substrate has defects. Since the prepared light-emitting element has an interface not stable, another important process of the display substrate is the aging procedure. The aging procedure (or aging stage) is a necessary process before the display device is shipped, in which the light-emitting element is lighted by a certain size of current for a period of time, so as to age the interface not stable, reduce the brightness attenuation of the light-emitting element, and increase the service life of the light-emitting element. In the aging procedure, the signal input needs to be realized through the aging pins arranged on the display motherboard. However, with the improvement of the resolution of the display product and the introduction of the flexible multi-layer on cell (FMLOC) structure, the number of circuit boards bonded in the bonding area and the required bonding pins gradually increase, which leads to a smaller and smaller space for placing the aging pins in the bonding area. How to reasonably place the aging pins in the bonding area is a problem to be solved.

[0088] The display substrate provided in the embodiment includes a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of test circuit groups, a plurality of aging pin groups, and a plurality of bonding pin groups. The substrate includes a display area and a bonding area located on one side of the display area. The plurality of sub-pixels are located in the display area. The plurality of data lines are located in the display area and the bonding area, and the plurality of data lines are electrically connected to the plurality of sub-pixels. The plurality of test circuit groups are arranged along a first direction, and the plurality of test circuit groups are electrically connected to the plurality of data lines. The plurality of aging pin groups and the plurality of bonding pin groups are located in the bonding area and on a side of the plurality of test circuit groups away from the display area. The plurality of bonding pin groups are arranged along the first direction, and at least one aging pin group is arranged between adjacent bonding pin groups. Each bonding pin group is configured to be bonded to at least one circuit board. Each test circuit group is configured to be connected to at least one aging pin group in a test stage.

[0089] The display substrate provided in the embodiment can realize the arrangement of the aging pins in the bonding area by alternately arranging the aging pin groups between the plurality of bonding pin groups in the bonding area, so as to improve the insufficient arrangement space of the aging pins in the bonding area.

[0090] In the embodiment, one aging pin group can include a plurality of aging pins arranged continuously in the first direction, and one binding pin group can include a plurality of binding pins arranged continuously in the first direction. The aging pins are configured as pins used in the aging stage. The binding pins are configured as pins used for binding connection with the circuit board.

[0091] In some example embodiments, the plurality of binding pin groups can include n binding pin groups, n being a positive integer greater than or equal to 3, sequentially including a first binding pin group, a second binding pin group, and an n-th binding pin group in the first direction. One aging pin group included between the first binding pin group and the second binding pin group can include a plurality of first aging pins for transmitting a gate drive control signal arranged continuously in the first direction. One aging pin group included between the n-th binding pin group and an (n-1)-th binding pin group can include a plurality of first aging pins for transmitting a gate drive control signal arranged continuously in the first direction. In some examples, n can be 4. The first aging pins can be arranged between the first binding pin group and the second binding pin group and between the third binding pin group and the fourth binding pin group. The embodiment is not limited thereto. In some examples, the gate drive control signal can include a clock signal provided to the gate drive circuit, etc. In the preparation process of the display substrate, the EAC (EVEN After Cell) cutting process has a specific requirement for the distance between the aging pins and the rough cutting line (i.e. Figure 4 the first cutting lane), and the present example can improve the situation of insufficient aging pin arrangement space caused by being unable to be too close to the rough cutting line of the EAC by arranging the first aging pins between the first binding pin group and the second binding pin group and between the n-th binding pin group and the (n-1)-th binding pin group. Moreover, the arrangement mode of the first aging pins of the present example can also ensure the connection of the first aging pins with the gate drive circuit in the frame region.

[0092] In some example embodiments, two aging pin groups can be arranged between two adjacent binding pin groups or one aging pin group can be arranged. For example, by merging the plurality of aging pins between the adjacent binding pin groups into two groups or one group, the space occupied by the aging pin arrangement can be saved, thereby improving the situation of insufficient aging pin arrangement space in the binding area.

[0093] In some example embodiments, each of the plurality of aging pin groups can include a plurality of second aging pins arranged in series along the first direction for transmitting a direct current signal. In some examples, the direct current signal can include at least one of a high voltage signal and a low voltage signal provided to the gate drive circuit, an initial signal provided to the pixel circuit, a test control signal and a test data signal provided to the test circuit. The present embodiments are not limited thereto.

[0094] In some example embodiments, at least one of the plurality of aging pin groups can include a plurality of first aging pins arranged in series along the first direction for transmitting a gate drive control signal and a plurality of second aging pins arranged in series along the first direction for transmitting a direct current signal. The plurality of second aging pins in the aging pin group can be located on a side of the plurality of first aging pins close to the edge of the display substrate. The present example can arrange the plurality of first aging pins and the plurality of second aging pins in at least one of the aging pin groups, which can save space occupied by the arrangement of the aging pins by combining the aging pins, and the arrangement of the first aging pins and the second aging pins can facilitate optimization of the arrangement of the connection lines between the first aging pins and the second aging pins and other circuits and pins.

[0095] In some example embodiments, the first aging pins of at least one of the plurality of aging pin groups can be configured to be electrically connected to the first aging pins of the remaining aging pin groups for transmitting the same signal in the test phase. In this way, the consistency of the signal transmitted by the first aging pins can be ensured.

[0096] In some example embodiments, the second aging pins of the plurality of aging pin groups for transmitting the same signal can be configured to be electrically connected in the test phase. In this way, the consistency of the signal transmitted by the second aging pins can be ensured.

[0097] In some example embodiments, the plurality of test circuit groups can be connected by test circuit connection lines. In this way, the consistency of the signal received by the test circuit groups can be ensured.

[0098] In some example embodiments, at least one of the plurality of test circuit groups can be configured to be connected to two aging pin groups in the test phase, and the two aging pin groups are located on two sides of the at least one test circuit group. The present example can ensure the consistency of the signal received by the test circuit group by connecting the test circuit group to the aging pin groups.

[0099] In some example embodiments, the pins in the same aging pin group that are electrically connected to different test circuit groups and arranged adjacently are configured to be electrically connected in the test phase. The pins in the same aging pin group that are electrically connected to the same test circuit group and arranged adjacently are configured to be electrically connected in the test phase. This example can ensure consistency of signal transmission in the test phase by achieving electrical connection between the pins in the same aging pin group that transmit the same signal in the test phase.

[0100] In some example embodiments, the plurality of aging pin groups can be arranged in the first direction, and the plurality of aging pin groups and the plurality of binding pin groups can be arranged side by side in the first direction. This example can save the space occupied by the aging pin groups by arranging the aging pin groups and the binding pin groups side by side.

[0101] In some example embodiments, each of the plurality of binding pin groups can include a plurality of access pins arranged in the first direction, at least one first power pin, and at least one second power pin. The first power pin and the second power pin in each binding pin group are configured to be used as aging pins in the aging phase, and each binding pin group is configured to be bound to at least one circuit board after the aging phase. In some examples, for a display motherboard, a cutting process can be performed along an EAC cutting line to cut the display motherboard into a plurality of intermediate substrates (for example, an intermediate substrate can include a substrate area, a first cutting area, and a second cutting area), then, each intermediate substrate can be subjected to a lighting detection and an aging phase, after the detection and the aging phase, a cutting can be performed along a module (MDL) cutting line of the intermediate substrate, and then, a circuit board can be bound to the intermediate substrate. An edge cutting of the intermediate substrate on which the circuit board is bound can obtain a display substrate.

[0102] In some implementations, the connection position of the aging pin provided on the display motherboard and the wire of the display substrate adopts a two-layer different material punching interconnection at the module cutting line, for example, the aging pin can be located in a source-drain metal layer (for example, a first source-drain metal layer), and the source-drain metal layer can have a small resistance (for example, a titanium, aluminum, titanium stack structure is adopted); the wire of the display substrate at the module cutting line can be located in a gate metal layer (for example, a first gate metal layer or a second gate metal layer), and the gate metal layer can have a high resistance (for example, a metal material molybdenum is adopted). When the aging phase is performed, the detection current will pass through the source-drain metal layer and the gate metal layer. Since the test current of the first power voltage (VDD) and the second power voltage (VSS) of the large-size display substrate is relatively large, when a large current flows through the gate metal layer with large resistance, due to the high resistance, according to Q=I 2Rt, higher heat will be generated at the gate metal layer of the display substrate, thus causing burning loss to the display substrate. By sharing the first power pin and the second power pin in the binding pin group as the burn-in pin, the present example can reduce the current flowing through the module cutting line position, thus reducing the current flowing through the gate metal layer, and improving the burning loss to the display substrate. Moreover, without separately setting the burn-in pin for transmitting the first power voltage and the second power voltage, the space occupied by the burn-in pin can be reduced.

[0103] The scheme of the present embodiment is illustrated below by some examples. In the following examples, only the binding area of the display substrate and the cutting position of the display motherboard near the binding area of the display substrate are taken as examples for illustration.

[0104] Figure 5 A schematic diagram of the binding area of the display substrate of at least one embodiment of the present disclosure is shown. In some examples, as shown in Figure 5 along the direction away from the display area AA, the binding area B1 can include a sub-bezel area B11 and a binding pin area B10. The binding pin area B10 can be located on the side of the sub-bezel area B11 away from the display area AA.

[0105] In some examples, taking the display substrate as a flexible substrate as an example, along a direction away from the display area AA, the sub-bezel area B11 can include, in sequence, a first fan-out area, a bending area, a second fan-out area, a first circuit area, a third fan-out area, and a driving chip area. The first fan-out area can be connected to the display area and include at least a first power line, a second power line, and a plurality of data lines, the plurality of data lines being configured to extend from the data lines of the display area in a fan-out manner. The first power line of the first fan-out area can be configured to connect the high-level power line of the display area, and the second power line can be configured to connect the low-level power line of the bezel area. The bending area can be connected to the second fan-out area and can include a composite insulating layer provided with a groove, the groove being configured to bend the binding area B1 to the back of the display area AA. The second fan-out area can include a plurality of fan-out wires. The first circuit area can include at least an electrostatic circuit, which can be configured to prevent electrostatic damage to the display substrate by eliminating static electricity. The third fan-out area can include a plurality of fan-out wires. The driving chip area can be provided with a driving chip (IC, Integrated Circuit), which can be electrically connected to the data lines of the display area through the fan-out wires, and can be configured to generate driving signals required for driving the sub-pixels and provide the driving signals to the data lines of the display area. For example, the driving signals can be data signals for driving the luminance of the sub-pixels. In another example, taking the display substrate as a rigid substrate as an example, along a direction away from the display area AA, the sub-bezel area B11 can include, in sequence, a second circuit area and a fan-out wire area. The second circuit area can include a multiplexing circuit and an electrostatic discharge circuit. The multiplexing circuit can be configured to provide data signals to the plurality of data lines from one signal source. The fan-out wire area can include a plurality of fan-out wires extending to the binding area. However, the present embodiment is not limited to the structure of the sub-bezel area B11.

[0106] In some examples, as Figure 5As shown, the binding pin area B10 can include a plurality of burn-in pin groups (e.g., six burn-in pin groups 31a-31f) and a plurality of binding pin groups (e.g., four binding pin groups 41a-41d). The four binding pin groups 41a-41d are sequentially arranged along the first direction X, and the six burn-in pin groups 31a-31f are sequentially arranged along the first direction X. The plurality of burn-in pin groups and the plurality of binding pin groups can be alternately arranged along the first direction X. For example, two burn-in pin groups can be arranged between two adjacent binding pin groups. For example, the burn-in pin groups 31a and 31b can be arranged between the binding pin groups 41a and 41b, the burn-in pin groups 31c and 31d can be arranged between the binding pin groups 41b and 41c, and the burn-in pin groups 31e and 31f can be arranged between the binding pin groups 41c and 41d. Each burn-in pin group can include a plurality of burn-in pins sequentially arranged along the first direction X, and each binding pin group can include a plurality of binding pins sequentially arranged along the first direction X. Each binding pin group can be configured to be bound to at least one circuit board (e.g., a flexible printed circuit (FPC)). The burn-in pin groups can be configured to be used in a burn-in stage or a test stage, and after the burn-in stage and the test stage are completed and the binding pin groups are bound to the circuit board, the burn-in pin groups can be retained as invalid pins in the binding pin area B10.

[0107] Figure 6 A partial schematic view of a display mother board is shown for at least one embodiment of the present disclosure. In some examples, as shown, Figure 6 The display mother board can include at least one substrate area. The substrate area can include a display area AA and a binding area B1 located on one side of the display area AA. The cutting area can be located outside the substrate area. For example, the cutting area can include a first cutting area B31 located on a side of the binding area B1 away from the display area AA, and second cutting areas B32a and B32b located on opposite sides of the binding pin area of the binding area B1 along the first direction X. The present example omits the cutting areas on the remaining sides of the substrate area.

[0108] In some examples, for a display mother board, a cutting process can be performed along the EAC cutting line to cut the display mother board into a plurality of intermediate substrates (e.g., one intermediate substrate can include a substrate area, a first cutting area, and a second cutting area), then each intermediate substrate can be subjected to a lighting detection and burn-in procedure, after the detection and burn-in procedure is completed, cutting can be performed along the module (MDL) cutting line of the intermediate substrate, and then a circuit board can be bound to the intermediate substrate. The intermediate substrate on which the circuit board binding is completed can be edge cut to obtain a display substrate. Figure 6 A partial schematic view of a display mother board for obtaining a display substrate is shown. By performing a cutting process on the display mother board, a plurality of intermediate substrates can be obtained. Figure 5 A partial schematic view of a display mother board for obtaining a display substrate is shown. By performing a cutting process on the display mother board, a plurality of intermediate substrates can be obtained.Figure 6 The display motherboard shown can be cut to obtain Figure 5 The display substrate shown. Figure 6 The cutting line L1 in the display motherboard shown is the aforementioned module cutting line. After the lighting test and aging process are completed, the first cutting region B31 can be cut according to the cutting line L1. Subsequently, after the circuit board binding is completed, the second cutting regions B32a and B32b can be cut according to the cutting line L2.

[0109] In some examples, as shown in Figure 6 The first cutting region B31 is provided with a plurality of test pin groups 51. Each test pin group can include a plurality of test pins arranged along the first direction X. The test pins are configured as pins for signal transmission in the lighting test stage. The second cutting region B32a can be provided with an aging pin group 31g, and the second cutting region B32b can be provided with an aging pin group 31h. The aging pin groups 31g and 31h can be arranged side by side with a plurality of aging pin groups and a plurality of binding pin groups in the binding region in the first direction X.

[0110] Figure 7A For example, as shown in Figure 6 The local distribution diagram of the aging pin group 31g and the binding pin group 41a. Figure 7B For example, as shown in Figure 6 The local distribution diagram of the aging pin group 31h and the binding pin group 41d.

[0111] In some examples, taking the aging pin group 31g and the binding pin group 41a as an example, as shown in Figure 7A The alignment mark 35 can be provided between the aging pin group 31g and the binding pin group 41a. The normal projection of the alignment mark 35 on the substrate can be a cross. The aging pin group 31g can be located on the side of the cutting line L2 away from the binding pin group 41a. The binding pin group 41a can include a plurality of access pins 410, a first power pin 411, and a second power pin 412. The first power pin 411 can be configured to transmit a low-potential power signal VSS, and the second power pin 412 can be configured to transmit a high-potential power signal VDD. The first power pin 411 and the second power pin 412 can be arranged alternately between the plurality of access pins 410. In some examples, the plurality of aging pins in the aging pin group 31a, the plurality of pins in the binding pin group 41a, and the alignment mark 35 can be provided in the same layer, for example, all can be located in the first source-drain metal layer. In other examples, the plurality of aging pins and the binding pins can be a double-layer stacked structure, for example, can be a stacked structure of the first gate metal layer and the first source-drain metal layer, or a stacked structure of the second gate metal layer and the first source-drain metal layer. The pins in the aging pin group and the binding pin group in the present example can extend substantially along the second direction Y and be arranged along the first direction X.

[0112] In some examples, as shown in Figure 7A In some examples, as shown in

[0113] As described above in relation to the position relationship between the binding pin group 41d and the burn-in pin group 31h in FIG. 1, the description is not repeated here. Figure 7B Figure 7A

[0114] Figure 8A Figure 8B Figure 6 FIG. 6 is a partial schematic view of a binding pin region and a first cutting region in FIG. 1. In some examples, as shown in Figure 8A Figure 8B As shown in FIG. 6, the first cutting region B31 includes a plurality of test pin groups 51 arranged along the first direction X. Each test pin group 51 in the first cutting region B31 can include a plurality of test pins 511 arranged continuously along the first direction X. The plurality of test pins 511 can extend substantially along the second direction Y. The plurality of test pins 511 can be electrically connected to the plurality of pins in the binding pin groups in the binding pin region B10 through a plurality of first connection lines 36 to be configured to provide test signals. For example, one test pin 511 can be electrically connected to one binding pin through one first connection line 36. The plurality of first connection lines 36 can be located in the first cutting region B31 and on the side of the test pin groups 51 close to the binding pin region B10. The first connection line 36 may, for example, extend substantially along the second direction Y.

[0115] In some examples, as shown in Figure 8A ​​​​​As shown, the aging pin group 31a included between the first binding pin group 41a and the second binding pin group 41b can include a first aging pin group 311 and a second aging pin group 312. The first aging pin group 311 can include a plurality of first aging pins that transmit gate driving control signals in sequence along the first direction X. The second aging pin group 312 can include a plurality of second aging pins that transmit direct current signals in sequence along the first direction X. The second aging pin group 312 can be located on the side of the first aging pin group 311 close to the left side edge of the display substrate. In some examples, the second aging pin group 312 can include eight second aging pins, and the first aging pin group 311 can include nine first aging pins. For example, the second aging pin group 312 can include three test data pins, one test control pin, two power supply pins, and two initial signal pins arranged in sequence along the first direction X, wherein the three test data pins can be configured to provide test data signals to the test circuit in the test phase, the test control pin can be configured to provide a test control signal to the test circuit in the test phase, the two power supply pins can be configured to provide high voltage signals and low voltage signals to the gate driving circuit in the test phase, and the two initial signal pins can be configured to provide initial signals to the pixel circuit in the test phase. However, the present embodiment is not limited thereto. For example, the second aging pin group can include power supply pins that provide power supply signals to the gate driving circuit.

[0116] In some examples, as shown in FIG. 4, the aging pin group 31f included between the third binding pin group 41c and the fourth binding pin group 41d can include a first aging pin group 311 and a second aging pin group 312. The second aging pin group 312 can be located on the side of the first aging pin group 311 close to the right side edge of the display substrate. The pins in the first aging pin group 311 and the second aging pin group 312 can be described with reference to the foregoing embodiments, and thus will not be described again here. Figure 8B

[0117] In some examples, as shown in FIG. 4, the aging pin group 31f included between the third binding pin group 41c and the fourth binding pin group 41d can include a first aging pin group 311 and a second aging pin group 312. The second aging pin group 312 can be located on the side of the first aging pin group 311 close to the right side edge of the display substrate. The pins in the first aging pin group 311 and the second aging pin group 312 can be described with reference to the foregoing embodiments, and thus will not be described again here. Figure 8A ​As shown, the first aging pins in the first aging pin group 311 in the aging pin group 31a can be electrically connected with the gate drive circuit arranged in the frame area (e.g. the left frame) through the first adapter line 37a. The first aging pins in the first aging pin group 311 in the aging pin group 31f can be electrically connected with the gate drive circuit arranged in the frame area (e.g. the right frame) through the first adapter line 37b. The first adapter lines 37a and 37b can at least include a line segment extending along the first direction X and a line segment extending along the second direction Y, wherein the line segment extending along the first direction X can be located on the side of the test pin group 51 away from the binding pin area B10, and the line segment extending along the second direction Y can be located on the side of the test pin group 51 close to the edge of the display substrate in the first direction X. However, the present embodiment is not limited thereto.

[0118] In some examples, as shown in Figure 8A and Figure 8B The aging pin groups 31b, 31c, 31d and 31e can respectively include a plurality of second aging pins arranged continuously along the first direction X. As shown in Figure 7A and Figure 7B The aging pin groups 31g and 31h can respectively include a plurality of second aging pins arranged continuously along the first direction X. In some examples, the number of second aging pins in each aging pin group can be the same, for example, can be 8, and the number of first aging pins in the aging pin groups 31a and 31f can be 9. The present embodiment is not limited thereto. In the present example, the first aging pins can be arranged only between the first binding pin group 41a and the second binding pin group 41b, and between the third binding pin group 41c and the fourth binding pin group 41d.

[0119] In some examples, as shown in Figure 8A and Figure 8B The first aging pins in the first aging pin group 311 in the aging pin group 31a can be electrically connected with the first aging pins in the first aging pin group 311 in the aging pin group 31f transmitting the same signal through the second connection line 38. The second connection line 38 can at least include a line segment extending along the first direction X and a line segment extending along the second direction Y, wherein the line segment extending along the first direction X can be located on the side of the test pin group 51 away from the binding pin area B10. In some examples, the second connection line 38 can be electrically connected with the first adapter lines 37a and 37b to ensure signal transmission consistency.

[0120] In some examples, as shown in Figure 8A and Figure 8BAs shown, the second aging pins in the second aging pin group 312 in the aging pin group 31a can be electrically connected with the second aging pins in the remaining aging pin groups which transmit the same signal through the third connection lines 39. The third connection lines 39 can at least include a line segment extending along the first direction X and a line segment extending along the second direction Y, wherein the line segment extending along the first direction X can be located on the side of the test pin group 51 away from the binding pin region B10. In the present example, by electrically connecting the second aging pins which transmit the same signal, the signal transmission consistency can be ensured.

[0121] In some examples, the first transfer lines 37a and 37b, the second connection lines 38 and the third connection lines 39 can be located on the same conductive layer, for example, can be located on the first source-drain metal layer. When the first transfer lines 37a and 37b intersect with the second connection lines 38 and the third connection lines 39, the first transfer lines 37a and 37b can bypass the second connection lines 38 and the third connection lines 39 by using jumpers of different conductive layers (for example, located on the first gate metal layer or the second gate metal layer); or, the second connection lines 38 and the third connection lines 39 can bypass the first transfer lines 37a and 37b by using jumpers located on different conductive layers. The present embodiment is not limited thereto.

[0122] The following will be illustrated by taking the flexible display substrate as an example.

[0123] Figure 9A A schematic diagram of the binding region of the display substrate of at least one embodiment of the present disclosure. Figure 9B A schematic diagram of the binding region of the display substrate in Figure 9A A partial schematic diagram of the binding region of the display substrate in Figure 9A A partial schematic diagram of the binding region of the display substrate in Figure 9B The binding region of the display substrate, the plurality of test pin groups 51 arranged on the side of the binding region away from the display region, and the aging pin groups (for example, the aging pin groups 31g and 31h) located on the periphery of the binding region B1 along the first direction X are illustrated in

[0124] In some examples, as shown in Figure 9A A partial schematic diagram of the binding region of the display substrate in Figure 9BAs shown, the binding area B1 of the display substrate can include, sequentially arranged along a direction away from the display area AA, a first fan-out area B111, a bending area B112, a second fan-out area B113, a first circuit area B114, a third fan-out area B115, a driving chip area B116, and a binding pin area B10. The first fan-out area B111 can be connected to the display area AA. The bending area B112 is connected between the first fan-out area B111 and the second fan-out area B112, and can be configured to bend the binding area B1 to the back of the display area AA. The first circuit area B114 can include at least a plurality of test circuit groups (for example, including test circuit groups 42a, 42b, 42c, and 42d). The plurality of test circuit groups can be arranged side by side along the first direction X. Each test circuit group can include a plurality of test circuits, and the test circuits can be configured to be electrically connected to a plurality of data lines of the display area and provide test data signals to the plurality of data lines of the display area. The driving chip area B116 includes a plurality of driving chip pin groups (for example, including driving chip pin groups 61a, 61b, 61c, and 61d). The plurality of driving chip pin groups can be electrically connected to the plurality of data lines and configured to be bound with at least one driving chip. For example, each driving chip pin group can be configured to be bound with one driving chip. Figure 9A and Figure 9B The fan-out wires in the first fan-out area B111, the second fan-out area B113, and the third fan-out area B115 are omitted in FIGS. Figure 9A and Figure 9B The connection lines between the test circuit groups and the binding pin groups, and the connection lines between the binding pin groups and the test pin groups are shown in FIGS.

[0125] In some examples, as shown in Figure 9A and Figure 9B As shown, the binding area B1 can include a plurality of first power lines PL1 and a plurality of second power lines PL2. One binding pin group (for example, binding pin group 41a) in the binding pin area B10 can be electrically connected to two second power lines PL2 and one first power line PL1, and the first power line PL1 can be located between the two second power lines PL2 in the first direction X. The first power line PL1 can be electrically connected to the second power pins of the binding pin group in the binding pin area B10, and the second power lines PL2 can be electrically connected to the first power pins in the binding pin group. In some examples, the first power line PL1 and the second power line PL2 can be single-layer wires, for example, can be located in the first source-drain metal layer or the second source-drain metal layer; or, the first power line PL1 and the second power line PL2 can be double-layer wires, for example, can be a laminated structure wire of the first source-drain metal layer and the second source-drain metal layer. The present embodiment is not limited in this regard.

[0126] In some examples, as shown inFigure 9A and Figure 9B As shown, multiple driver chip pin groups within the driver chip area B116 can be arranged side-by-side along the first direction X. The number of driver chip pin groups within the driver chip area B116 can be the same as the number of bonded pin groups within the bonded pin area B10. Multiple driver chip pin groups and multiple bonded pin groups can be connected in a one-to-one correspondence. Pins within a driver chip pin group can be electrically connected to pins within a corresponding bonded pin group via pin connection lines 600. The pin connection lines 600 can extend approximately along the second direction Y and can be arranged sequentially along the first direction X. For example, driver chip pin group 61a is connected to bonded pin group 41a, driver chip pin group 61b is connected to bonded pin group 41b, driver chip pin group 61c is connected to bonded pin group 41c, and driver chip pin group 61d is connected to bonded pin group 41d. This embodiment is not limited in this respect.

[0127] In some examples, such as Figure 10A and Figure 10B As shown, the gate driving circuit located in the left frame of the frame region B2 can be electrically connected to the first signal transmission line 71a, which extends to the bonding region B1 via the lower left corner. Within the bonding region B1, the first signal transmission line 71a passes through the first fan-out area B111, the bend area B112, the second fan-out area B113, and the third fan-out area B115, and can be electrically connected to the pins in the driver chip pin group (e.g., driver chip pin group 61a) located in the driver chip region B116 closest to the left edge of the display substrate. The gate driving circuit located in the right frame of the frame region B2 is electrically connected to the first signal transmission line 71b, which extends to the bonding region B1 via the lower right corner. The first signal transmission line 71b passes through the first fan-out area B111, the bending area B112, the second fan-out area B113, and the third fan-out area B115 within the bonding area B1, and can be electrically connected to a pin in the driver chip pin group (e.g., driver chip pin group 61d) located in the driver chip area B116 closest to the right edge of the display substrate. In other words, the first signal transmission line 71a can be electrically connected to a pin in the first driver chip pin group 61a, and the first signal transmission line 71b can be electrically connected to a pin in the last driver chip pin group 61d.

[0128] In some examples, such as Figure 10A and Figure 10AAs shown, the first signal transmission line 71a can be electrically connected with the first adapter line 37a, and the first signal transmission line 71b can be electrically connected with the first adapter line 37b. The connection position of the first signal transmission line 71a and the first adapter line 37a can be located on the side of the first power line PL1 close to the driving chip pin group 61a. The connection position of the first signal transmission line 71b and the first adapter line 37b can be located on the side of the first power line PL1 close to the driving chip pin group 61d. The first adapter line 37a can be electrically connected with the first burn-in pin in the burn-in pin group 31a, and also can be electrically connected with the test pin in the test pin group 51 which transmits the same signal and is located on the side of the burn-in pin group 31a close to the left edge of the display substrate. The first adapter line 37b can be electrically connected with the first burn-in pin in the burn-in pin group 31f, and also can be electrically connected with the test pin in the test pin group 51 which transmits the same signal and is located on the side of the burn-in pin group 31f close to the right edge of the display substrate. The first adapter line 37a and the second adapter line 37b can be electrically connected through the second connection line 38. The second connection line 38 also can be electrically connected with the test pin in the plurality of test pin groups 51 which transmits the same signal. In the present example, the electrical connection between the first burn-in pin and the gate drive circuit can be realized by the electrical connection between the first adapter line 37a and the first signal transmission line 71a, and the electrical connection between the first adapter line 37b and the first signal transmission line 71b. In the test stage, the first signal transmission lines 71a and 71b are communicated through the first adapter lines 37a and 37b and the second connection line 38, which can ensure the uniformity of signal transmission. The signal transmitted to the first burn-in pin can include, for example, the clock signal provided to the gate drive circuit.

[0129] Figure 10B A schematic view of a binding area of a display substrate according to an embodiment of the present disclosure. Figure 10A A partial schematic view of a binding area of a display substrate in Figure 10B A partial schematic view of a binding area of a display substrate in Figure 10A A partial schematic view of a binding area of a display substrate in Figure 10B The connection relationship between the burn-in pin group and the test circuit group is shown in

[0130] In some examples, as shown in Figure 10A Figure 10B ​As shown, the first circuit region can include a plurality of test circuit groups (e.g., including test circuit groups 42a, 42b, 42c and 42d) arranged in sequence along the first direction X. The number of test circuit groups can be the same as the number of driving chip pin groups. Each test circuit group can be located near a side of the corresponding driving chip pin group close to the display area AA. The plurality of test circuit groups can be electrically connected through test circuit connection lines. For example, adjacent test circuit groups can be electrically connected through test circuit connection lines. In the present example, test circuit groups 42a and 42b can be electrically connected through test circuit connection line 72a, test circuit groups 42b and 42c can be electrically connected through test circuit connection line 72b, and test circuit groups 42c and 42d can be electrically connected through test circuit connection line 72c. Test circuit connection lines 72a, 72b and 72c can extend along the first direction X, for example. Test circuit connection lines 72a, 72b and 72c can be located near a side of the binding pin region close to the display area.

[0131] In some examples, as shown in Figure 11A and Figure 11B Test circuit group 42a can be configured to be connected with two aging pin groups 31a and 31g in the test phase, which can be located on both sides of test circuit group 42a. Test circuit group 42b can be configured to be connected with two aging pin groups 31b and 31c in the test phase, which can be located on both sides of test circuit group 42b. Test circuit group 42c can be configured to be connected with two aging pin groups 31d and 31e in the test phase, which can be located on both sides of test circuit group 42c. Test circuit group 42d can be configured to be connected with two aging pin groups 31f and 31h in the test phase, which can be located on both sides of test circuit group 42d.

[0132] In some examples, as shown in Figure 11A and Figure 11AAs shown, the test circuit group and the adjacent aging pin group can be electrically connected via the first test connection line 73. For example, the test circuit group 42a and the aging pin (e.g., the second aging pin) in the aging pin group 31a can be electrically connected via the first test connection line 73, and the test circuit group 42a and the aging pin in the aging pin group 31g can be electrically connected via the first test connection line 73. After one end of the first test connection line 73 is electrically connected to a test circuit group, it can extend approximately along the second direction Y to a test pin group 51 corresponding to the test circuit group. The first test connection line 73 can extend along the first direction X on the side of the test pin group 51 away from the display area AA, and after bypassing the test pin group 51, it can be electrically connected to an aging pin group. The first test connection line 73 can be used to electrically connect the pins in the test pin group 51 and the aging pin group that transmit the same signal, and also to the test circuit group. The two ends of a test circuit connection line can be electrically connected to two different first test connection lines 73. The remaining structure of the display substrate of this embodiment can be referred to the description of the foregoing embodiment, and will not be repeated here.

[0133] Figure 11B This is a schematic diagram of the bonding area of ​​a display substrate according to at least one embodiment of the present disclosure. Figure 11A for Figure 11B A partial schematic diagram of the bonding area of ​​the display substrate. Figure 12A and Figure 12B The diagram illustrates the connection relationships between the aging pin group and the test circuit group, as well as the connection relationships between the aging pin groups.

[0134] In some examples, such as Figure 12A and Figure 12A As shown, the first test connection line 73 electrically connected to test circuit group 42a and the first test connection line 73 electrically connected to test circuit group 42b can be electrically connected via the second test connection line 74. The first test connection line 73 electrically connected to test circuit group 42b and the first test connection line 73 electrically connected to test circuit group 42c can be electrically connected via the second test connection line 74. The first test connection line 73 electrically connected to test circuit group 42c and the first test connection line 73 electrically connected to test circuit group 42d can be electrically connected via the second test connection line 74. In this example, the first test connection lines electrically connected to adjacent test circuit groups can be electrically connected via the second test connection line. The second test connection line 74 can extend along a first direction X. The second test connection line 74 can be electrically connected to a segment of the first test connection line 73 extending along the first direction X. For example, the second test connection line 74 and the electrically connected first test connection line 73 can be a single unit.

[0135] In this example, aging pins that transmit the same test signal within adjacent aging pin groups electrically connected to different test circuit groups can be electrically connected via a first test connection line and a second test connection line, thereby achieving uniform signal transmission. The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0136] Figure 12B This is a schematic diagram of the bonding area of ​​a display substrate according to at least one embodiment of the present disclosure. Figure 12A for Figure 12B A partial schematic diagram of the bonding area of ​​the display substrate. Figure 13 and Figure 13 The diagram illustrates the connection between the aging pin group and the test circuit group, as well as another connection between the aging pin groups.

[0137] In some examples, such as Figure 14 and Figure 14 As shown, the first test connection line 73 electrically connected to two adjacent aging pin groups within the same test circuit group can be electrically connected via a third test connection line 75. For example, the first test connection line 73 electrically connected to aging pin group 31g and the first test connection line 73 electrically connected to aging pin group 31a can be electrically connected via the third test connection line 75; the first test connection line 73 electrically connected to aging pin group 31b and the first test connection line 73 electrically connected to aging pin group 31c can be electrically connected via the third test connection line 75; the first test connection line 73 electrically connected to aging pin group 31d and the first test connection line 73 electrically connected to aging pin group 31e can be electrically connected via the third test connection line 75; the first test connection line 73 electrically connected to aging pin group 31f and the first test connection line 73 electrically connected to aging pin group 31h can be electrically connected via the third test connection line 75. The third test connection line 75 can be electrically connected to a segment of the first test connection line 73 extending along the first direction X. For example, the third test connection line 75 can be an integral part of the electrically connected first test connection line 73.

[0138] In this example, aging pins that transmit the same test signal within adjacent aging pin groups and are electrically connected to different test circuit groups can be electrically connected via a first test connection line and a second test connection line; aging pins that transmit the same test signal within adjacent aging pin groups and are electrically connected to the same test circuit group can be electrically connected via a first test connection line and a third test connection line, thereby achieving uniform signal transmission. In this example, aging pins located within different aging pin groups and transmitting the same signal to the test circuit groups can be electrically connected via a first test connection line, a second test connection line, and a third test connection line, thereby ensuring uniform signal transmission. The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0139] In some examples, the third connection line 39 connected to the aging pin electrically connected to the test circuit group may include: a first test connection line and a second test connection line; or it may include a first test connection line and a third test connection line; or it may include a first test connection line, a second test connection line, and a third test connection line. This embodiment is not limited in this respect.

[0140] Figure 14 This is an equivalent circuit diagram of a test circuit according to at least one embodiment of the present disclosure. In some examples, the first circuit region of the bonding area includes multiple test circuit groups, each test circuit group may include multiple test circuits 40. Test circuit 40 may include multiple test transistors (e.g., including a first test transistor 44a, a second test transistor 44b, and a third test transistor 44c). Figure 15A As shown, the gates of the first test transistor 44a, the second test transistor 44b, and the third test transistor 44c are all connected to the same test control signal line 45. The first terminal of the first test transistor 44a is connected to the first test data line 46-1, the first terminal of the second test transistor 44b is connected to the second test data line 46-2, and the first terminal of the third test transistor 44c is connected to the third test data line 46-3. The second terminals of the first test transistor 44a, the second test transistor 44b, and the third test transistor 44c are respectively connected to different data lines DL in the display area. That is, the second terminal of the first test transistor 44a is connected to one data line DL, the second terminal of the second test transistor 44b is connected to another data line DL, and the second terminal of the third test transistor 44c is connected to yet another data line DL. In this way, the conduction of the three test transistors in the test circuit 40 can be controlled through the test control signal line 45, and the signals of different test data lines can be written to different data lines DL. During testing, a conduction signal is provided to the test control signal line 45, and the required test data signals are provided to multiple test data lines respectively, so that multiple data lines in the display area can obtain test data signals and achieve detection.

[0141] In some examples, the sub-pixels connected to each data line can be of the same color. During testing, the same test data signal is provided to the data lines corresponding to sub-pixels of the same color, which can make these sub-pixels display the same way. The color of the displayed image is used to determine whether there are any defective sub-pixels and to locate the defective sub-pixels.

[0142] Figure 6 This is a plan view of a test circuit according to at least one embodiment of the present disclosure. Figure 15B This illustrates two test circuits arranged along the first direction X. In some examples, such as... Figure 6As shown, the first test transistor 44a, the second test transistor 44b and the third test transistor 44c of the test circuit can be arranged in sequence along the second direction Y. The test control signal line 45, the first test data line 46-1, the second test data line 46-2 and the third test data line 46-3 can be arranged in sequence along the second direction Y and extend at least along the first direction X. The test control signal line 45, the first test data line 46-1, the second test data line 46-2 and the third test data line 46-3 can be located in the first source-drain metal layer. The active layers of the three test transistors of the test circuit and the active layers of the transistors of the pixel circuit of the sub-pixel can be in a same-layer structure. The gate of the first test transistor 44a, the gate of the second test transistor 44b and the gate of the third test transistor 44c of one test circuit can be in an integrated structure and located in the first gate metal layer, and can also be electrically connected to the test control signal line 45 located in the first source-drain metal layer. The first electrode of one first test transistor 44a can be electrically connected to the first test data line 46-1 located in the first source-drain metal layer, and the second electrode can be electrically connected to one data line DL3 located in the second gate metal layer through the connection electrode located in the first source-drain metal layer. The first electrode of one second test transistor 44b can be electrically connected to the second test data line 46-2 located in the first source-drain metal layer, and the second electrode can be electrically connected to one data line DL2 located in the first gate metal layer through the connection electrode located in the first source-drain metal layer. The first electrode of one third test transistor 44c can be electrically connected to the third test data line 46-3 located in the first source-drain metal layer, and the second electrode can be electrically connected to one data line DL1 located in the second gate metal layer through the connection electrode located in the first source-drain metal layer. The three test transistors of another test circuit can be electrically connected to the data lines DL4, DL5 and DL6 respectively.

[0143] In some examples, the test control signal line and the three test data lines electrically connected by the test circuit group can be respectively electrically connected to the burn-in pins in the burn-in pin group that transmit the same signal through the first test connection line. The test control signal line and the three test data lines electrically connected by the test circuit group can be respectively electrically connected to the test circuits in the adjacent test circuit group through the test circuit connection line.

[0144] Figure 16 For Figure 6 Another partial distribution diagram of the burn-in pin group 31g and the binding pin group 41a. Figure 15A For Figure 15B Another partial distribution diagram of the burn-in pin group 31h and the binding pin group 41d. Figure 16 For Figures 15A-16 Another partial distribution diagram of the binding pin area and the first cutting area.

[0145] In some examples, as Figures 7A-12B, Figure 17 and Figure 17 As shown, aging pin groups 31g and 31h may each include a first aging pin group 311 and a second aging pin group 312. The first aging pin group 311 may be located on the side of the second aging pin group 312 near the edge of the display substrate. In this example, the first aging pin group 311 may be disposed in aging pin groups 31g and 31h, and the remaining aging pin groups may only include the second aging pin group. The first aging pin in the aging pin group can be electrically connected to the first signal transmission line through a first adapter cable, and electrically connected to the gate driving circuit located in the bezel area through the first signal transmission line. Further descriptions of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0146] Figure 18 The example described above, by arranging the first aging pins at the left and right edges of the bonding region, facilitates the first aging pins providing signals to the gate drive circuitry within the bezel region (e.g., the left and right bezels). However, because the EAC dicing process has specific requirements on the distance between the aging pins and the coarse dicing line, it can easily lead to insufficient space at the left and right edges of the bonding pin region to accommodate a certain number (e.g., 17, 21, 25, or more) of pins. Therefore, Figure 18 In the example shown, by arranging the first aging pin between the first and second bonded pin groups and between the last two bonded pin groups within the bonded pin area, the problem of insufficient space at the left and right edges of the bonded pin area can be solved.

[0147] Figure 17 This is a schematic diagram of the bonding area of ​​a display substrate according to at least one embodiment of the present disclosure. In some examples, such as... Figure 18 As shown, the bonding pin region B10 may include multiple aging pin groups (e.g., three aging pin groups 32a to 32c arranged along the first direction X) and multiple bonding pin groups (e.g., four bonding pin groups 41a to 41d arranged along the first direction X). The multiple aging pin groups and the multiple bonding pin groups may be arranged alternately and side-by-side along the first direction X. For example, an aging pin group may be provided between two adjacent bonding pin groups. For instance, an aging pin group 32a may be provided between the first bonding pin group 41a and the second bonding pin group 41b, an aging pin group 32b may be provided between the second bonding pin group 41b and the third bonding pin group 41c, and an aging pin group 32c may be provided between the third bonding pin group 41c and the third bonding pin group 41d. However, this embodiment does not limit the number of bonding pin groups.

[0148] Figure 19 This is a partial schematic diagram of a display motherboard according to at least one embodiment of the present disclosure. Figure 18The mother panel shown can be obtained after being cut. Figure 19 The display substrate shown. In some examples, such as... Figure 18 As shown, the first cutting area B31 can be configured with multiple test pin groups 51. The second cutting area B32a can be configured with an aging pin group 32d, and the second cutting area B32b can be configured with an aging pin group 32e.

[0149] Figures 7A-12B for Figure 20 A partial schematic diagram of the pin-binding area and the first cut area. In some examples, such as... Figure 20 As shown, aging pin groups 32a and 32c may each include a first aging pin group 311 and a second aging pin group 312. The second aging pin 312 may be located on the side of the first aging pin group 311 near the edge of the display substrate. Aging pin group 32b may include the second aging pin group. Figure 21 As shown, aging pin groups 32d and 32e may include a second aging pin group. For example, aging pin groups 32a and 32c may each include 17 pins (e.g., including nine first aging pins and eight second aging pins), and aging pin groups 32b, 32d, and 32e may each include 8 pins (e.g., including eight second aging pins). This embodiment does not limit the number of pins. Further descriptions of the display substrate in this embodiment can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0150] Compared to Figure 22 As shown in the example, an aging pin group is set between adjacent bonded pin groups, which is equivalent to merging the two second aging pin groups in the previous example into one aging pin group. This can reduce the space occupied by the second aging pins in the bonded pin area, thereby improving the situation of insufficient space for aging pins in the bonded area.

[0151] Figure 21 This is a schematic diagram of the bonding area of ​​a display substrate according to at least one embodiment of the present disclosure. In some examples, such as... Figure 21 As shown, the bonding pin area B10 may include multiple bonding pin groups (e.g., four bonding pin groups 41a to 41d). The multiple bonding pin groups may be arranged side-by-side sequentially along a first direction X. Each bonding pin group may be configured to be bonded to a circuit board.

[0152] Figure 20 This is a partial schematic diagram of a display motherboard according to at least one embodiment of the present disclosure. Figure 21 for Figure 22 A partial schematic diagram of the pin-binding area and the first cutting area. Figure 21 The display motherboard shown can be obtained after cutting. Figure 22The display substrate is shown. In some examples, as ​ and ​ Each binding pin group can include a plurality of access pins 410, a first power pin 411 and a second power pin 412. The first power pin 411 and the second power pin 412 can be configured to be used as aging pins in the aging phase, so as to transmit power signals in the aging phase.

[0153] In some examples, as ​ and ​ The first cutting area B31 can be provided with a plurality of test pin groups 51. Each binding pin group can be electrically connected with a corresponding two test pin groups 51. For example, the binding pin group 41a is electrically connected with a corresponding two test pin groups 51. Each test pin group 51 can include a plurality of test pins 511. The plurality of test pins 511 can be divided into three parts, the first part pins can form a first aging pin group 311 as first aging pins, the second part pins can form a second aging pin group 312 as second aging pins, and the first part pins and the second part pins can be configured to be used in the test phase and the aging phase, and the third part pins can be configured to be used only in the test phase. The test pins 511 can be electrically connected with the corresponding binding pins through the first connecting lines 36. The pins transmitting the same signal in the plurality of first aging pin groups can be electrically connected through the second connecting lines 38, and the pins transmitting the same signal in the plurality of second aging pin groups can be electrically connected through the third connecting lines 39. The remaining description of this embodiment can refer to the description of the foregoing embodiments, and thus will not be described here.

[0154] In this example, sharing a part of the test pins in the test pin group as aging pins can reduce the occupation space of the aging pins in the binding pin area, and improve the situation that the space for arranging the aging pins in the binding pin area is insufficient.

[0155] In some example embodiments, the arrangement positions of the aging pins in the above-described embodiments can be combined. For example, a part of the aging pins can be arranged in the binding pin area, and another part can be arranged in the first cutting area and shared with the test pins. However, this embodiment is not limited thereto.

[0156] The embodiment also provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of drive chip pin groups, a plurality of aging pin groups, and a plurality of binding pin groups. The substrate comprises a display area and a binding area located at one side of the display area. The plurality of sub-pixels are located in the display area. The plurality of data lines are located in the display area and the binding area, and the plurality of data lines are electrically connected with the plurality of sub-pixels. The plurality of drive chip pin groups are located in the binding area and arranged along a first direction, and are connected with the plurality of data lines. The plurality of drive chip pin groups are configured to be bound with a drive chip. The plurality of aging pin groups and the plurality of binding pin groups are located in the binding area and located at a side of the plurality of drive chip pin groups away from the display area. The plurality of binding pin groups are arranged along the first direction and connected with the plurality of drive chip pin groups through pin connection lines. At least one aging pin group is arranged between two adjacent binding pin groups.

[0157] The display substrate provided by the embodiment can arrange aging pins in the binding area by arranging aging pin groups between the plurality of binding pins in the binding area, so as to improve the insufficient arrangement space of the aging pins in the binding area.

[0158] In some example embodiments, the plurality of aging pin groups can be arranged along a first direction, and the plurality of aging pin groups and the plurality of binding pin groups are arranged side by side in the first direction.

[0159] In some example embodiments, the plurality of binding pin groups and the plurality of drive chip pin groups can be electrically connected one by one. In this example, the number of binding pin groups can be the same as the number of drive chip pin groups.

[0160] In some example embodiments, the plurality of drive chip pin groups comprises m drive chip pin groups, m is a positive integer greater than or equal to 3, and the plurality of drive chip pin groups comprises a first drive chip pin group, a second drive chip pin group, and an mth drive chip pin group in the first direction. The display substrate further comprises a frame area located at the remaining side of the display area, and the frame area is provided with a gate drive circuit configured to be electrically connected with the first drive chip pin group and the mth drive chip pin group through a first signal transmission line. In some examples, m can be 4. For example, the gate drive circuit in the left frame can be connected with the pins in the first drive chip pin group through the first signal transmission line, and the gate drive circuit in the right frame can be connected with the pins in the fourth drive chip pin group through the first signal transmission line. The connection mode of the first signal transmission line in this example can avoid greater interference to other wires.

[0161] The structure of the display substrate provided by the embodiment can refer to the description of the foregoing embodiments, and thus will not be described here again.

[0162] The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.

[0163] The drawings in the present disclosure only relate to the structures involved in the present disclosure, and other structures can be referred to the general design. In the case of no conflict, the features in the embodiments of the present disclosure, i.e. the features in the embodiments, can be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of the present disclosure can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be covered in the scope of the claims of the present application.

Claims

1. A display substrate, characterized by, The display substrate comprises: a substrate comprising a display area and a binding area located on one side of the display area; a plurality of sub-pixels located in the display area; a plurality of data lines located in the display area and the binding area, the plurality of data lines being electrically connected with the plurality of sub-pixels; a plurality of test circuit groups arranged along a first direction, the plurality of test circuit groups being electrically connected with the plurality of data lines; a plurality of aging pin groups and a plurality of binding pin groups located in the binding area and located on a side of the plurality of test circuit groups away from the display area; the plurality of binding pin groups are arranged along the first direction, and at least one aging pin group is arranged between two adjacent binding pin groups; each binding pin group is configured to be bound to at least one circuit board, and each test circuit group is configured to be connected with at least one aging pin group in a test phase; each of the plurality of binding pin groups comprises a plurality of access pins arranged along the first direction, at least one first power pin and at least one second power pin; the first power pin and the second power pin in each binding pin group are configured to be used as aging pins in an aging phase, and each binding pin group is configured to be bound to at least one circuit board after the aging phase.

2. The display substrate of claim 1, wherein, The plurality of binding pin groups comprises n binding pin groups, n is a positive integer greater than or equal to 3, sequentially comprising a first binding pin group, a second binding pin group and an n-th binding pin group in the first direction, and an aging pin group arranged between the first binding pin group and the second binding pin group comprises a plurality of first aging pins for transmitting gate drive control signals arranged continuously along the first direction; an aging pin group arranged between the n-th binding pin group and the n-1-th binding pin group comprises a plurality of first aging pins for transmitting gate drive control signals arranged continuously along the first direction. 3.The display substrate of claim 2, wherein, The display substrate further comprises a frame area located on the remaining side of the display area, and the frame area is provided with a gate drive circuit configured to be connected with the first aging pins in the aging pin group between the first binding pin group and the second binding pin group and the aging pin group between the n-th binding pin group and the n-1-th binding pin group in the test phase.

4. The display substrate according to any one of claims 1 to 3, characterized in that, One or two aging pin groups are arranged between two adjacent binding pin groups.

5. The display substrate of claim 1, wherein, Each of the plurality of aging pin groups comprises a plurality of second aging pins for transmitting direct current signals arranged continuously along the first direction. 6.The display substrate of claim 1, wherein, At least one of the plurality of aging pin groups comprises a plurality of first aging pins for transmitting gate drive control signals arranged continuously along the first direction and a plurality of second aging pins for transmitting direct current signals arranged continuously along the first direction, and the plurality of second aging pins are located on a side of the plurality of first aging pins close to an edge of the display substrate.

7. The display substrate according to claim 2, 3 or 6, characterized in that, The first aging pins of at least one of the plurality of aging pin groups are configured to be electrically connected with the first aging pins of the remaining aging pin groups transmitting the same signals in the test phase. 8.The display substrate of claim 5 or 6, wherein, Second aging pins in the plurality of aging pin groups transmitting the same signal are configured to be electrically connected in the test phase. 9.The display substrate of claim 1, wherein, The plurality of test circuit groups are connected through test circuit connection lines. 10.The display substrate of claim 1, wherein, At least one test circuit group in the plurality of test circuit groups is configured to be connected with two aging pin groups in the test phase, and the two aging pin groups are located on two sides of the at least one test circuit group. 11.The display substrate of claim 10, wherein, Pins in aging pin groups that are electrically connected with different test circuit groups and arranged adjacently and transmit the same signal are configured to be electrically connected in the test phase. 12.The display substrate according to claim 10 or 11, characterized in that, Pins in aging pin groups that are electrically connected with the same test circuit group and arranged adjacently and transmit the same signal are configured to be electrically connected in the test phase. 13.The display substrate of claim 1, wherein, The plurality of aging pin groups are arranged along the first direction, and the plurality of aging pin groups and the plurality of binding pin groups are arranged side by side in the first direction.

14. A display device comprising: The display substrate includes any one of claims 1-13.

15. A display substrate, comprising: The display substrate includes: a substrate including a display area and a binding area located on one side of the display area; a plurality of sub-pixels located in the display area; a plurality of data lines located in the display area and the binding area, the plurality of data lines being electrically connected to the plurality of sub-pixels; a plurality of drive chip pin groups located in the binding area and arranged along a first direction, connected to the plurality of data lines, the plurality of drive chip pin groups being configured to be bound with a drive chip; a plurality of aging pin groups and a plurality of binding pin groups located in the binding area and located on a side of the plurality of drive chip pin groups away from the display area, the plurality of binding pin groups being arranged along the first direction and connected to the plurality of drive chip pin groups through pin connection lines, at least one aging pin group being provided between two adjacent binding pin groups. 16.The display substrate of claim 15, wherein, The plurality of aging pin groups are arranged along the first direction, and the plurality of aging pin groups and the plurality of binding pin groups are arranged side by side in the first direction. 17.The display substrate of claim 15, wherein, The plurality of binding pin groups and the plurality of drive chip pin groups are electrically connected one-to-one. 18.The display substrate of claim 15, wherein, The plurality of drive chip pin groups include m drive chip pin groups, m being a positive integer greater than or equal to 3, including a first drive chip pin group, a second drive chip pin group, and an mth drive chip pin group in the first direction; The display substrate further includes a bezel area located on the remaining sides of the display area, the bezel area being provided with a gate drive circuit, the gate drive circuit being configured to be electrically connected to the first drive chip pin group and the mth drive chip pin group through a first signal transmission line.

19. The display substrate according to any one of claims 15-18, wherein, One or two aging pin groups are provided between two adjacent binding pin groups.

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