Semiconductor device and semiconductor module

Abstract

The semiconductor device 1 includes: a semiconductor layer 40; a transistor 10 and a transistor 20 formed in the semiconductor layer 40; one or more first source pads 111 and a first gate pad 119 formed in a region S1 of an upper surface of the semiconductor layer 40, the first source pad being connected to a source of the transistor 10, and the first gate pad being connected to a gate; and one or more second source pads 121 and a second gate pad 129 formed in a region S2 of the upper surface of the semiconductor layer 40, the region S2 being adjacent to the region S1 in a plan view of the semiconductor layer 40, the second source pad being connected to a source of the transistor 20, and the second gate pad being connected to a gate; in the plan view of the semiconductor layer 40, an imaginary straight line 91 connecting a center of the first gate pad 119 and a center of the second gate pad 129 passes a center of the semiconductor layer 40, and an angle formed between each side of the semiconductor layer 40 and the imaginary straight line 91 is 45 degrees; and an upper surface boundary line 600 between the region S1 and the region S2 monotonously changes in a long side direction in which a long side of the semiconductor layer 40 extends and a short side direction in which a short side of the semiconductor layer 40 extends.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a semiconductor module using the same. BACKGROUND

[0002] Conventionally, a semiconductor device that is mounted on a mounting substrate and that switches the on state and the off state of a current path in the mounting substrate is known (for example, refer to Patent Literature 1).

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Publication No. 2019-129308 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] Conventionally, a current path in which a main current flows in a mounting substrate is designed so that the current flows efficiently (for example, so that the on resistance is reduced, or / and, for example, so that heat caused by the on current is effectively dissipated). Therefore, it is desirable that a semiconductor device that is mounted on a mounting substrate and that switches the on state and the off state of a current path in which a main current flows has a feature that enables current to flow efficiently in the current path in the mounting substrate. The greater the main current is, the more this is pursued.

[0008] Therefore, an object of the present disclosure is to provide a semiconductor device that has a feature that enables current to flow efficiently in a current path in a mounting substrate for mounting, and a semiconductor module that has a feature that enables current to flow efficiently in a current path in a mounting substrate.

[0009] MEANS FOR SOLVING THE PROBLEMS

[0010] A semiconductor device according to an aspect of the present disclosure is a chip size package type semiconductor device capable of face-down mounting, and includes: a semiconductor layer; a metal layer formed in contact with a back surface of the semiconductor layer; a first vertical MOS transistor formed in a first semiconductor layer inner region inside the semiconductor layer; a second vertical MOS transistor formed in a second semiconductor layer inner region inside the semiconductor layer adjacent to the first semiconductor layer inner region in a plan view of the semiconductor layer; one or more first source pads and a first gate pad formed in a first semiconductor layer upper surface region of an upper surface of the semiconductor layer, the first source pads being connected to source electrodes of the first vertical MOS transistor, and the first gate pad being connected to a gate electrode of the first vertical MOS transistor; and one or more second source pads and a second gate pad formed in a second semiconductor layer upper surface region of the upper surface adjacent to the first semiconductor layer upper surface region in the plan view of the semiconductor layer, the second source pads being connected to source electrodes of the second vertical MOS transistor, and the second gate pad being connected to a gate electrode of the second vertical MOS transistor. The first semiconductor layer inner region and the second semiconductor layer inner region are one of two equal halves of the semiconductor layer in area in the plan view of the semiconductor layer. The first semiconductor layer upper surface region and the second semiconductor layer upper surface region are one of two equal halves of the semiconductor layer in area in the plan view of the semiconductor layer. The semiconductor layer has a semiconductor substrate. The semiconductor substrate functions as a common drain region of the first vertical MOS transistor and the second vertical MOS transistor. The semiconductor layer is rectangular in the plan view of the semiconductor layer. A first imaginary straight line connecting a center of the first gate pad and a center of the second gate pad passes through a center of the semiconductor layer, and an angle formed by each side of the semiconductor layer is 45 degrees. A length of an upper surface boundary line between the first semiconductor layer upper surface region and the second semiconductor layer upper surface region is longer than a length of a long side of the semiconductor layer. The upper surface boundary line monotonically changes in a long side direction in which the long side extends and a short side direction in which a short side of the semiconductor layer extends.

[0011] A semiconductor device according to an aspect of the present disclosure is a chip size package type semiconductor device capable of face-down mounting, and includes: a semiconductor layer; a metal layer in contact with a back surface of the semiconductor layer; a first vertical MOS transistor formed in a first semiconductor layer inner region inside the semiconductor layer; a second vertical MOS transistor formed in a second semiconductor layer inner region inside the semiconductor layer adjacent to the first semiconductor layer inner region in a plan view of the semiconductor layer; one or more first source pads connected to source electrodes of the first vertical MOS transistor; a first gate pad connected to a gate electrode of the first vertical MOS transistor; one or more second source pads connected to source electrodes of the second vertical MOS transistor; and a second gate pad connected to a gate electrode of the second vertical MOS transistor. The first semiconductor layer inner region and the second semiconductor layer inner region are one of two equal halves of the semiconductor layer in area in the plan view of the semiconductor layer. The first semiconductor layer upper surface region and the second semiconductor layer upper surface region are one of two equal halves of the semiconductor layer in area in the plan view of the semiconductor layer. The semiconductor layer has a semiconductor substrate. The semiconductor substrate functions as a common drain region of the first vertical MOS transistor and the second vertical MOS transistor. The semiconductor layer is rectangular in the plan view of the semiconductor layer. A boundary line between the first semiconductor layer inner region and the second semiconductor layer inner region, i.e., an internal boundary line, monotonously changes in a long side direction in which a long side of the semiconductor layer extends and a short side direction in which a short side of the semiconductor layer extends. An angle formed by an imaginary straight line connecting a first end of one of the internal boundary lines and a second end of the other of the internal boundary lines and a side of the semiconductor layer that does not have the first end or the second end is 16 degrees or more.

[0012] A semiconductor module according to an aspect of the present disclosure includes: the first semiconductor device described above; and a mounting substrate on which the first semiconductor device is mounted face-down. The mounting substrate has a first through-hole through which a first conductor electrically connected to the first gate pad of the first semiconductor device passes, and a second through-hole through which a second conductor electrically connected to the second gate pad of the first semiconductor device passes.

[0013] The semiconductor module of the technical solution of the present disclosure has the first semiconductor device, the second semiconductor device, and a mounting substrate on which the first semiconductor device and the second semiconductor device are mounted face down on a first surface. In a plan view of the mounting substrate, the mounting substrate has a shape extending in a length direction with a certain width at least at a portion where the semiconductor devices are mounted. The second semiconductor device is mounted face down on the first surface in the same orientation as the first semiconductor device at a position after parallel movement in the extension direction of the length direction with respect to the first semiconductor device. The mounting substrate has a first metal wiring, a second metal wiring, and a third metal wiring arranged in the extension direction of the length direction on the first surface of the mounting substrate in sequence. The first metal wiring is connected to all of the one or more first source pads of the first semiconductor device. The second metal wiring is connected to all of the one or more second source pads of the first semiconductor device and all of the one or more first source pads of the second semiconductor device. The third metal wiring is connected to all of the one or more second source pads of the second semiconductor device.

[0014] The semiconductor module of the technical solution of the present disclosure has the first semiconductor device, the second semiconductor device, and a mounting substrate on which the first semiconductor device and the second semiconductor device are mounted face down on a first surface. In a plan view of the mounting substrate, the mounting substrate has a shape extending in a length direction with a certain width at least at a portion where the semiconductor devices are mounted. The second semiconductor device is mounted face down on the first surface in the same orientation as the first semiconductor device at a position after parallel movement in the extension direction of the length direction with respect to the first semiconductor device. The mounting substrate has a first metal wiring, a second metal wiring, and a third metal wiring arranged in the extension direction of the length direction on the first surface of the mounting substrate in sequence. The first metal wiring is connected to all of the one or more first source pads of the first semiconductor device. The second metal wiring is connected to all of the one or more second source pads of the first semiconductor device and all of the one or more first source pads of the second semiconductor device. The third metal wiring is connected to all of the one or more second source pads of the second semiconductor device.

[0015] Inventive Effects

[0016] The semiconductor device according to the technical solution of the present disclosure can provide a semiconductor device having a feature that can efficiently flow current in the current path of the mounting substrate to be mounted. In addition, the semiconductor module according to the technical solution of the present disclosure can provide a semiconductor module having a feature that can efficiently flow current in the current path of the mounting substrate. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a sectional view showing an example of the configuration of the semiconductor device of Embodiment 1.

[0018] Figure 2 is a plan view showing an example of the configuration of the semiconductor device of Embodiment 1.

[0019] Figure 3 is a plan view showing an example of the configuration of the semiconductor device of Embodiment 1.

[0020] Figure 4 is a plan view showing an example of the configuration of the semiconductor device of Embodiment 1.

[0021] Figure 5 is a plan view showing an example of the configuration of the semiconductor module of Embodiment 1.

[0022] Figure 6 is a schematic view showing a state in which the surface of the mounting substrate faces down and the semiconductor device of Embodiment 1 is mounted.

[0023] Figure 7 is a plan view showing an example of a variation of the arrangement positions of the first through-hole and the second through-hole of Embodiment 1.

[0024] Figure 8 is a list view showing a comparison result of comparing the semiconductor device of Embodiment 1 with the semiconductor device of the comparative example.

[0025] Figure 9 is a list view showing a comparison result of comparing the semiconductor device of Embodiment 1 with the semiconductor device of the comparative example.

[0026] Figure 10A is a plan view illustrating another arrangement example of the first source pad and the second source pad of Embodiment 1.

[0027] Figure 10B is a plan view illustrating another arrangement example of the first source pad and the second source pad of Embodiment 1.

[0028] Figure 10C is a plan view illustrating another arrangement example of the first source pad and the second source pad of Embodiment 1.

[0029] Figure 10D FIG. 1 is a plan view illustrating another configuration example of the first source pad and the second source pad of Embodiment 1.

[0030] Figure 11 FIG. 2 is a schematic view showing a state in which the semiconductor device of Embodiment 1 is mounted face down on a surface of a mounting substrate.

[0031] Figure 12 FIG. 3 is a plan view showing an example of the configuration of the semiconductor device of Embodiment 2.

[0032] Figure 13 FIG. 4 is a plan view showing an example of the configuration of the semiconductor device of Embodiment 2.

[0033] Figure 14 FIG. 5 is a plan view showing an example of the configuration of the semiconductor module of Embodiment 2.

[0034] Figure 15 FIG. 6 is a schematic view showing a state in which the semiconductor device of Embodiment 2 is mounted face down on a surface of a mounting substrate.

[0035] Figure 16 FIG. 7 is a plan view showing an example of the configuration of the semiconductor module of Embodiment 2.

[0036] Figure 17 FIG. 8 is a schematic view showing a state in which the semiconductor device of Embodiment 2 is mounted face down on a surface of a mounting substrate.

[0037] Figure 18 FIG. 9 is a graph showing a relationship between the degree of agreement and the improvement rate of the degree of agreement of Embodiment 2 compared to the past.

[0038] Figure 19A FIG. 10 is a plan view illustrating another configuration example of the first source pad and the second source pad of Embodiment 2.

[0039] Figure 19B FIG. 11 is a plan view illustrating another configuration example of the first source pad and the second source pad of Embodiment 2.

[0040] Figure 20 FIG. 12 is a plan view showing an example of the configuration of the semiconductor device of Embodiment 3.

[0041] Figure 21 FIG. 13 is a plan view showing an example of the configuration of the semiconductor device of Embodiment 3.

[0042] Figure 22 FIG. 14 is a plan view showing an example of the configuration of the semiconductor module of Embodiment 3.

[0043] Figure 23Ais a plan view of another configuration example of the first source pad and the second source pad of Embodiment 3.

[0044] Figure 23B is a plan view of another configuration example of the first source pad and the second source pad of Embodiment 3.

[0045] Figure 23C is a plan view of another configuration example of the first source pad and the second source pad of Embodiment 3.

[0046] Figure 23D is a plan view of another configuration example of the first source pad and the second source pad of Embodiment 3.

[0047] Figure 23E is a plan view of another configuration example of the first source pad and the second source pad of Embodiment 3.

[0048] Figure 24 is a plan view of an example of a configuration of a semiconductor device of Embodiment 4.

[0049] Figure 25 is a plan view of an example of a configuration of a semiconductor device of Embodiment 4.

[0050] Figure 26 is a plan view of an example of a configuration of a semiconductor module of Embodiment 4.

[0051] Figure 27 is a plan view of a semiconductor device of Embodiment 4.

[0052] Figure 28 is a graph showing a relationship between a ratio Z / X and angles θ2 and θ3.

[0053] Figure 29A is a plan view of another configuration example of the first source pad and the second source pad of Embodiment 4.

[0054] Figure 29B is a plan view of another configuration example of the first source pad and the second source pad of Embodiment 4.

[0055] Figure 30A is a plan view of an example of a configuration of a semiconductor module of Embodiment 5.

[0056] Figure 30B is a plan view of an example of a configuration of a semiconductor module of Embodiment 5.

[0057] Figure 30C is a plan view of an example of a configuration of a semiconductor module of Embodiment 5.

[0058] Figure 30D is a plan view showing an example of the configuration of the semiconductor module of Embodiment 5.

[0059] Figure 30E is a plan view showing an example of the configuration of the semiconductor module of Embodiment 5.

[0060] Figure 31A is a plan view showing an example of the configuration of the semiconductor module of Embodiment 6.

[0061] Figure 31B is a plan view showing an example of the configuration of the semiconductor module of Embodiment 6.

[0062] Figure 31C is a plan view showing an example of the configuration of the semiconductor module of Embodiment 6.

[0063] Figure 31D is a plan view showing an example of the configuration of the semiconductor module of Embodiment 6.

[0064] Figure 31E is a plan view showing an example of the configuration of the semiconductor module of Embodiment 6.

[0065] Figure 31F is a plan view showing an example of the configuration of the semiconductor module of Embodiment 6.

[0066] Figure 32A is a plan view showing an example of the configuration of the semiconductor module of Embodiment 7.

[0067] Figure 32B is a plan view showing an example of the configuration of the semiconductor module of Embodiment 7.

[0068] Figure 33 is a plan view showing an example of the configuration of the semiconductor device of Embodiment 8.

[0069] Figure 34A is a plan view showing an example of the configuration of the semiconductor module of Embodiment 8.

[0070] Figure 34B is a plan view showing an example of the configuration of the semiconductor module of Embodiment 8.

[0071] Figure 35A is a plan view showing an example of the configuration of the semiconductor module of Embodiment 8.

[0072] Figure 35B is a plan view showing an example of the configuration of the semiconductor module of Embodiment 8.

[0073] Figure 36 is a graph showing a relationship between the angle θ4 and the ratio of the resistance component of the metal layer of Embodiment 8.

[0074] Figure 37 is a graph showing a relationship between the angle θ4 and the ratio of the resistance component of the metal layer of Embodiment 8.

[0075] Figure 38 is a graph showing a relationship between the size of the semiconductor device and the offset between the semiconductor devices and the angle θ of Embodiment 8.

[0076] Figure 39 is a graph showing an example of a relationship between the size of the semiconductor device and the offset between the semiconductor devices and the angle θ of Embodiment 8, which the inventors of the present application consider to be preferable. DETAILED DESCRIPTION

[0077] (Procedure for obtaining a technical solution of the present disclosure)

[0078] In recent years, for example, in mobile devices such as smartphones, shortening of the charging time is an important aspect of competition, and large-currentization of charging of secondary batteries is desired.

[0079] The inventors of the present application have recognized that, in order to achieve large-current charging of a secondary battery, a semiconductor device that switches between an on state and an off state of a current path through which a large current flows at the time of large-current charging needs to have a feature that enables the current to flow in the current path efficiently, that is, as much as possible while suppressing heat generation due to energization.

[0080] Based on this recognition, the inventors of the present application have repeatedly conducted experiments and researches. As a result, the inventors of the present application have conceived the following semiconductor device and the like of the present disclosure.

[0081] A semiconductor device according to an aspect of the present disclosure is a chip size package type semiconductor device capable of face-down mounting, and includes: a semiconductor layer; a metal layer formed in contact with a back surface of the semiconductor layer; a first vertical MOS transistor formed in a first semiconductor layer inner region inside the semiconductor layer; a second vertical MOS transistor formed in a second semiconductor layer inner region inside the semiconductor layer adjacent to the first semiconductor layer inner region in a plan view of the semiconductor layer; one or more first source pads and a first gate pad formed in a first semiconductor layer upper surface region of an upper surface of the semiconductor layer, the first source pads being connected to source electrodes of the first vertical MOS transistor, and the first gate pad being connected to a gate electrode of the first vertical MOS transistor; and one or more second source pads and a second gate pad formed in a second semiconductor layer upper surface region of the upper surface adjacent to the first semiconductor layer upper surface region in the plan view of the semiconductor layer, the second source pads being connected to source electrodes of the second vertical MOS transistor, and the second gate pad being connected to a gate electrode of the second vertical MOS transistor. The first semiconductor layer inner region and the second semiconductor layer inner region are one of two equal halves of the semiconductor layer in area in the plan view of the semiconductor layer. The first semiconductor layer upper surface region and the second semiconductor layer upper surface region are one of two equal halves of the semiconductor layer in area in the plan view of the semiconductor layer. The semiconductor layer has a semiconductor substrate. The semiconductor substrate functions as a common drain region of the first vertical MOS transistor and the second vertical MOS transistor. The semiconductor layer is rectangular in the plan view of the semiconductor layer. A first imaginary straight line connecting a center of the first gate pad and a center of the second gate pad passes through a center of the semiconductor layer, and an angle formed by each side of the semiconductor layer is 45 degrees. A length of an upper surface boundary line between the first semiconductor layer upper surface region and the second semiconductor layer upper surface region is longer than a length of a long side of the semiconductor layer. The upper surface boundary line monotonically changes in a long side direction in which the long side extends and a short side direction in which a short side of the semiconductor layer extends.

[0082] According to the semiconductor device described above, in a case where two semiconductor devices of the same type described above are mounted with their faces downward on the front and back surfaces of a mounting substrate and simultaneously subjected to on-off driving, by overlapping the centers of the two semiconductor devices in a plan view of the mounting substrate and mounting the other semiconductor device so as to be oriented 90 degrees about a rotation axis perpendicular to the plane of the mounting substrate that passes through the center of the semiconductor device, the position of the first gate pad of one semiconductor device can be aligned with the position of the first gate pad of the other semiconductor device, and the position of the second gate pad of one semiconductor device can be aligned with the position of the second gate pad of the other semiconductor device.

[0083] Thus, in the mounting substrate in which the two semiconductor devices of the same type are mounted on the front and back surfaces, the wiring that controls the potential of both the first gate pad of one semiconductor device and the first gate pad of the other semiconductor device and the wiring that controls the potential of both the second gate pad of one semiconductor device and the second gate pad of the other semiconductor device can be made common, and the number of wirings (vias) that must be provided separately in the past can be reduced. Furthermore, the common wirings (vias) can be led out to the end of the mounting substrate so as not to interfere with the flow of main current.

[0084] Thus, the current path through which the main current flows in the mounting substrate can be ensured to be wide, and the on-resistance can be reduced.

[0085] Thus, according to the semiconductor device described above, a semiconductor device having features that can simplify the wiring that tends to complicate the mounting substrate and improve the ease of substrate design, and can efficiently flow current in the current path of the mounting substrate on which the semiconductor device is mounted can be provided.

[0086] Further, the semiconductor layer can be square in a plan view of the semiconductor layer.

[0087] Further, in a plan view of the semiconductor layer, the first gate pad can be disposed such that none of the one or more first source pads is sandwiched between the first gate pad and the closest first and second edges of the four edges of the semiconductor layer, and in a plan view of the semiconductor layer, the second gate pad can be disposed such that none of the one or more second source pads is sandwiched between the second gate pad and the closest third and fourth edges of the four edges of the semiconductor layer.

[0088] Further, it can also be that, in a case where the intersection of the upper surface boundary line and the first edge or the second edge is set as the first intersection point, and the intersection of the upper surface boundary line and the third edge or the fourth edge is set as the second intersection point, an angle formed by the first imaginary straight line and a second imaginary straight line connecting the first intersection point and the second intersection point in a plan view of the semiconductor layer is greater than 45 degrees and is 90 degrees or less.

[0089] Further, it can also be that the angle is 60 degrees or more and 90 degrees or less.

[0090] Further, it can also be that, in a case where the intersection of the upper surface boundary line and the first edge or the second edge is set as the first intersection point, and the intersection of the upper surface boundary line and the third edge or the fourth edge is set as the second intersection point, an angle formed by the first imaginary straight line and a second imaginary straight line connecting the first intersection point and the second intersection point in a plan view of the semiconductor layer is 0 degrees or more and less than 45 degrees.

[0091] Further, it can also be that the angle is 0 degrees or more and less than 22 degrees.

[0092] Further, it can also be that, in a plan view of the semiconductor layer, of the four edges of the semiconductor layer, an edge closest to the first gate pad and having an intersection with the upper surface boundary line is set as a first edge, an edge closest to the first gate pad and not having an intersection with the upper surface boundary line is set as a second edge, an edge closest to the second gate pad and having an intersection with the upper surface boundary line is set as a third edge, an edge closest to the second gate pad and not having an intersection with the upper surface boundary line is set as a fourth edge, a vertex formed by the first edge and the fourth edge is set as a first vertex, a vertex formed by the second edge and the third edge is set as a second vertex, the intersection of the upper surface boundary line and the first edge is set as a first intersection point, and the intersection of the upper surface boundary line and the third edge is set as a second intersection point, a distance between the first vertex and the first intersection point is 1 / N or more of the length of the edge of the semiconductor layer and is longer than the maximum diameter of the second gate pad, a distance between the second vertex and the second intersection point is 1 / N or more of the length of the edge of the semiconductor layer and is longer than the maximum diameter of the first gate pad, N is an integer of 3 or more, and the upper surface boundary line is formed by alternately connecting N-1 line segments parallel to the second edge and N-2 line segments parallel to the first edge.

[0093] Further, it can also be that N is any one of 3, 4, or 5.

[0094] Further, it can also be that the one or more first source pads are a plurality; in a plan view of the semiconductor layer, the one or more first source pads are each a rectangle or an oblong having a length direction in a direction parallel to the first side, and are formed in a strip shape in parallel to the first side; the one or more second source pads are a plurality; in a plan view of the semiconductor layer, the one or more second source pads are each a rectangle or an oblong having a length direction in a direction parallel to the first side, and are formed in a strip shape in parallel to the first side.

[0095] Further, it can also be that the one or more first source pads are one, and are disposed on substantially the entire surface of the first semiconductor layer upper surface region except for the region of the first gate pad; the one or more second source pads are one, and are disposed on substantially the entire surface of the second semiconductor layer upper surface region except for the region of the second gate pad.

[0096] Further, it can also be that the one or more first source pads are a plurality; the one or more first source pads are each a shape in which the edges opposite the other first source pads are edges orthogonal or parallel to the upper surface boundary line; the one or more second source pads are a plurality; the one or more second source pads are each a shape in which the edges opposite the other second source pads are edges orthogonal or parallel to the upper surface boundary line.

[0097] A semiconductor device according to one aspect of the present disclosure is a chip size package type semiconductor device capable of being mounted face down, and includes: a semiconductor layer; a metal layer formed in contact with a back surface of the semiconductor layer; a first vertical MOS transistor formed in a first semiconductor layer inner region inside the semiconductor layer; a second vertical MOS transistor formed in a second semiconductor layer inner region inside the semiconductor layer adjacent to the first semiconductor layer inner region in a plan view of the semiconductor layer; one or more first source pads connected to source electrodes of the first vertical MOS transistor and formed in a first semiconductor layer upper surface region of an upper surface of the semiconductor layer; and a first gate pad connected to gate electrodes of the first vertical MOS transistor and formed in the first semiconductor layer upper surface region. The semiconductor device also includes one or more second source pads connected to source electrodes of the second vertical MOS transistor and formed in a second semiconductor layer upper surface region of the upper surface adjacent to the first semiconductor layer upper surface region in the plan view of the semiconductor layer; and a second gate pad connected to gate electrodes of the second vertical MOS transistor and formed in the second semiconductor layer upper surface region. The first semiconductor layer inner region and the second semiconductor layer inner region are one of two equal halves of the semiconductor layer in area in the plan view of the semiconductor layer. The first semiconductor layer upper surface region and the second semiconductor layer upper surface region are one of two equal halves of the semiconductor layer in area in the plan view of the semiconductor layer. The semiconductor layer has a semiconductor substrate. The semiconductor substrate functions as a common drain region of the first vertical MOS transistor and the second vertical MOS transistor. The semiconductor layer is rectangular in the plan view of the semiconductor layer. A boundary line between the first semiconductor layer inner region and the second semiconductor layer inner region, i.e., an internal boundary line, monotonously changes in a long side direction in which a long side of the semiconductor layer extends and a short side direction in which a short side of the semiconductor layer extends in the plan view of the semiconductor layer. An angle formed by an imaginary straight line connecting a first end of one of the internal boundary lines and a second end of the other of the internal boundary lines and a side of the semiconductor layer that does not have the first end or the second end is 16 degrees or more.

[0098] According to the semiconductor device described above, the length of the internal boundary line is longer than that of a conventional semiconductor device in which the internal boundary line extends in a straight line in a direction orthogonal to or parallel to the long side direction of the semiconductor layer in the plan view of the semiconductor layer. Therefore, in a case where a current flows from the first source pad to the second source pad or from the second source pad to the first source pad, the current flowing in the horizontal direction in the metal layer has a larger current-carrying cross-sectional area.

[0099] Thus, compared with the past, it is possible to reduce the resistance value of the semiconductor device in the case where current flows from the first source pad to the second source pad or from the second source pad to the first source pad.

[0100] Thus, according to the semiconductor device having the above structure, it is possible to provide a semiconductor device having a feature that current can efficiently flow in the current path of the mounting substrate to be mounted.

[0101] Further, it can be that, in a plan view of the semiconductor layer, the first end of one side of the internal boundary line is located on the first long side of one side of the semiconductor layer, and the second end of the other side of the internal boundary line is located on the second long side of the other side of the semiconductor layer.

[0102] Further, it can be that the angle is 26 degrees or more.

[0103] Further, it can be that, in a plan view of the semiconductor layer, the first end of one side of the internal boundary line is located on the first long side of one side of the semiconductor layer, and the second end of the other side of the internal boundary line is located on the second long side of the other side of the semiconductor layer.

[0104] Further, it can be that the angle is 26 degrees or more.

[0105] Further, it can be that, in a plan view of the semiconductor layer, the semiconductor layer is a square, the distance between the first end of one side of the internal boundary line and a first vertex of the semiconductor layer closest to the first end is 1 / N or more of the length of the side of the semiconductor layer, the distance between the second end of the other side of the internal boundary line and a second vertex of the semiconductor layer closest to the second end is 1 / N or more of the length of the side of the semiconductor layer, N is an integer of 3 or more, and the internal boundary line is formed by alternately connecting N-1 line segments orthogonal to the side of the semiconductor layer on which the first end is located and N-2 line segments parallel to the side of the semiconductor layer on which the first end is located.

[0106] Further, it can be that, in a plan view of the semiconductor layer, the boundary line between the first semiconductor layer upper surface region and the second semiconductor layer upper surface region, that is, the upper surface boundary line, coincides with the internal boundary line.

[0107] The semiconductor module of the technical solution of the present disclosure has the above semiconductor device, and a mounting substrate on which the first semiconductor device faces downward is mounted. The mounting substrate has a first through hole through which a first conductor electrically connected to the first gate pad of the first semiconductor device passes, and a second through hole through which a second conductor electrically connected to the second gate pad of the first semiconductor device passes.

[0108] According to the semiconductor module having the above structure, the wiring of the mounting substrate that controls the potential of the first gate pad and the wiring of the mounting substrate that controls the potential of the second gate pad can be arranged to a region other than the surface on which the semiconductor devices are mounted face down. In particular, the wirings can be arranged near the end portion of the mounting substrate.

[0109] Therefore, the current path through which the main current flows in the mounting substrate can be ensured to be wider than in the past, and the design can be made so that the on-resistance is reduced.

[0110] Thus, according to the semiconductor module having the above structure, a semiconductor module having a feature that enables efficient current flow in the current path of the mounting substrate can be provided.

[0111] Further, it can be that, in a plan view of the mounting substrate, the center of the first via hole and the center of the second via hole are located on the first imaginary straight line of the first semiconductor device.

[0112] Further, it can be that the first semiconductor device is the above-described semiconductor device; in a plan view of the mounting substrate, the center of the first via hole is located at any one of the following positions of the first semiconductor device: (1) on the first imaginary straight line, (2) outside the first semiconductor device in the extension direction of the first side beyond the second side, and between the center of the first gate pad and the first side in the extension direction of the second side, or (3) outside the first semiconductor device in the extension direction of the second side beyond the first side, and between the center of the first gate pad and the second side in the extension direction of the first side; and the center of the second via hole is located at any one of the following positions of the first semiconductor device: (1) on the first imaginary straight line, (2) outside the first semiconductor device in the extension direction of the third side beyond the fourth side, and between the center of the second gate pad and the third side in the extension direction of the fourth side, or (3) outside the first semiconductor device in the extension direction of the fourth side beyond the third side, and between the center of the second gate pad and the fourth side in the extension direction of the third side.

[0113] Further, it can also be that the above-described first semiconductor device is the above-described semiconductor device; in a plan view of the mounting substrate, the mounting substrate is shaped so as to have a certain width at least at a portion where the above-described semiconductor device is mounted and extend in a length direction, on a first surface of the mounting substrate, there are provided a first metal wiring which is joined to all of the above-described one or more first source pads of the above-described first semiconductor device and extends in the above-described length direction, and a second metal wiring which is joined to all of the above-described one or more second source pads of the above-described first semiconductor device; and the above-described first semiconductor device is mounted on the first surface so as to face downward in an orientation in which an angle formed by the above-described second imaginary straight line and the extending direction of the length direction is 15 degrees or more and 75 degrees or less.

[0114] Further, it can also be that the above-described first semiconductor device is the above-described semiconductor device; in a plan view of the mounting substrate, the mounting substrate is shaped so as to have a certain width at least at a portion where the above-described semiconductor device is mounted and extend in a length direction, on a first surface of the mounting substrate, there are provided a first metal wiring which is joined to all of the above-described one or more first source pads of the above-described first semiconductor device and extends in the above-described length direction, and a second metal wiring which is joined to all of the above-described one or more second source pads of the above-described first semiconductor device; and the above-described first semiconductor device is mounted on the first surface so as to face downward in an orientation in which an angle formed by the above-described second imaginary straight line and the extending direction of the length direction is 15 degrees or more and 75 degrees or less.

[0115] Further, it can also be that the semiconductor device further includes the second semiconductor device; the first semiconductor device is mounted face down on the first surface in a direction in which the position of the first gate pad of the first semiconductor device is on the first extension direction side in the extension direction of the length direction; the second semiconductor device is mounted face down on the first surface in a direction in which the position of the first gate pad of the second semiconductor device is on the first extension direction side after being moved in parallel with respect to the first semiconductor device in a direction orthogonal to the extension direction of the second imaginary straight line of the first semiconductor device; the first metal wiring is further connected to all of the one or more first source pads of the second semiconductor device; the second metal wiring is further connected to all of the one or more second source pads of the second semiconductor device; and the second gate pad of the second semiconductor device is electrically connected to the second conductor.

[0116] Further, it can also be that the semiconductor device further includes the second semiconductor device; the first semiconductor device is mounted face down on the first surface in a direction in which the position of the first gate pad of the first semiconductor device is on the first extension direction side in the extension direction of the length direction; the second semiconductor device is mounted face down on the first surface in a direction in which the position of the first gate pad of the second semiconductor device is on the first extension direction side after being moved in parallel with respect to the first semiconductor device in a direction orthogonal to the extension direction of the second imaginary straight line of the first semiconductor device; the first metal wiring is further connected to all of the one or more first source pads of the second semiconductor device; the second metal wiring is further connected to all of the one or more second source pads of the second semiconductor device; and the second gate pad of the second semiconductor device is electrically connected to the second conductor.

[0117] Further, it can also be that the first semiconductor device is the semiconductor device described above; in a plan view of the mounting substrate, the mounting substrate has a shape extending in the length direction with a certain width at least at a portion where the semiconductor device is mounted, and has, on a first surface of the mounting substrate, a first metal wiring aligned in an extension direction of the length direction to be engaged with all of the one or more first source pads of the first semiconductor device, and a second metal wiring aligned in the extension direction of the length direction to be engaged with all of the one or more second source pads of the first semiconductor device; and the first semiconductor device is mounted face down on the mounting substrate in an orientation in which each side of the first semiconductor device forms a 45-degree angle with the extension direction of the length direction.

[0118] Further, it can also be that the first semiconductor device is the semiconductor device described above; in a plan view of the mounting substrate, the mounting substrate has a shape extending in the length direction with a certain width at least at a portion where the semiconductor device is mounted, and has, on a first surface of the mounting substrate, a first metal wiring aligned in an extension direction of the length direction to be engaged with all of the one or more first source pads of the first semiconductor device, and a second metal wiring aligned in the extension direction of the length direction to be engaged with all of the one or more second source pads of the first semiconductor device; and the first semiconductor device is mounted face down on the mounting substrate in an orientation in which each side of the first semiconductor device forms a 45-degree angle with the extension direction of the length direction.

[0119] Alternatively, it may also include the aforementioned second semiconductor device; in the plan view of the mounting substrate, the first semiconductor device is mounted face down on the first surface with the position of its first gate pad located on the first extension direction side of the length direction; the second semiconductor device, after being moved parallel to the first semiconductor device in a direction orthogonal to the length direction, is mounted face down on the first surface with the second imaginary line of the first semiconductor device parallel to the second imaginary line of the second semiconductor device; the first metal... The second metal wiring is also bonded to all of the first source pads of the second semiconductor device; the second metal wiring is also bonded to all of the first source pads of the second semiconductor device; the semiconductor substrate also has a third via through which a third conductor electrically connected to the first gate pad of the second semiconductor device passes, and a fourth via through which a fourth conductor electrically connected to the second gate pad of the second semiconductor device passes; the first via, the second via, the third via, and the fourth via are located between the first metal wiring and the second metal wiring in the extension direction of the mounting substrate in the length direction.

[0120] A semiconductor module according to the present disclosure includes: a first semiconductor device as described above; a second semiconductor device as described above; and a mounting substrate on which the first semiconductor device and the second semiconductor device are mounted facing downwards on a first surface; in a plan view of the mounting substrate, the mounting substrate has a shape that has a certain width at least at the portion where the semiconductor devices are mounted and extends in the length direction; the second semiconductor device, after being moved parallel to the first semiconductor device in the length direction, is mounted facing downwards on the first semiconductor device with the same orientation as the first semiconductor device. The first surface; the mounting substrate has a first metal wiring, a second metal wiring and a third metal wiring arranged sequentially on the first surface of the mounting substrate in the extension direction of the length direction, the first metal wiring being bonded to all of the one or more first source pads of the first semiconductor device, the second metal wiring being bonded to all of the one or more second source pads of the first semiconductor device and all of the one or more first source pads of the second semiconductor device, and the third metal wiring being bonded to all of the one or more second source pads of the second semiconductor device.

[0121] According to the semiconductor module with the above structure, the current path of the current flowing from the first metal wiring through the second metal wiring to the third metal wiring can be made straight.

[0122] Therefore, it is possible to design a current path through which a main current flows in the mounting substrate so as to reduce an on-resistance.

[0123] Thus, according to the semiconductor module of the above-described structure, it is possible to provide a semiconductor module having a feature that a current can efficiently flow in a current path of a mounting substrate.

[0124] The semiconductor module of the technical solution of the present disclosure has the first semiconductor device described above; the second semiconductor device described above; and a mounting substrate on which the first semiconductor device and the second semiconductor device are mounted face down in a first surface; in a plan view of the mounting substrate, the second semiconductor device is mounted face down in the first surface in the same orientation as the first semiconductor device after being moved substantially in parallel in a direction in which the imaginary straight line extends with respect to the first semiconductor device; the mounting substrate has a shape extending in a length direction with a certain width at least at a portion on which the semiconductor devices are mounted, and has a first metal wiring and a second metal wiring arranged in an extension direction of the length direction on the first surface of the mounting substrate, the first metal wiring is connected to all of the one or more first source pads of the first semiconductor device and all of the one or more first source pads of the second semiconductor device, and the second metal wiring is connected to all of the one or more second source pads of the first semiconductor device and all of the one or more second source pads of the second semiconductor device.

[0125] According to the semiconductor module of the above-described structure, the first semiconductor device and the second semiconductor device are arranged in a tilted positional relationship with respect to each edge of the first semiconductor device and each edge of the second semiconductor device.

[0126] Therefore, it is possible to effectively dissipate heat generated by the conduction current.

[0127] Therefore, it is possible to effectively dissipate heat generated by the conduction current.

[0128] Thus, according to the semiconductor module of the above-described structure, it is possible to provide a semiconductor module having a feature that a current can efficiently flow in a current path of a mounting substrate.

[0129] Hereinafter, a specific example of a semiconductor device of a technical solution of the present disclosure will be described with reference to the drawings. The embodiments shown here are intended to represent a specific example of the present disclosure. Thus, the numerical values, shapes, constituent elements, arrangement and connection modes of the constituent elements, and steps (procedures) and order of the steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. In addition, each drawing is a schematic view and is not necessarily strictly drawn. In each drawing, the same reference numerals are assigned to substantially identical structures, and repeated description will be omitted or simplified.

[0130] (Embodiment 1)

[0131] [1-1. Configuration of Semiconductor Device]

[0132] Hereinafter, the configuration of the semiconductor device of Embodiment 1 will be described. The semiconductor device of Embodiment 1 is a chip size package (CSP) type semiconductor device capable of face-down mounting, in which two longitudinal MOS (Metal Oxide Semiconductor) transistors are formed. The two longitudinal MOS transistors are power transistors, which are so-called trench type MOSFETs (Field Effect Transistors).

[0133] Figure 1 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 of Embodiment 1. Figure 2 is a plan view showing an example of the configuration of the semiconductor device 1. Figure 1 shows Figure 2 , Figure 3 , Figure 4 I-I cross section of Figure 3 is a plan view showing an example of the configuration of the semiconductor device 1, which is a plan view in a state where the configuration on the upper surface side than the portion 13 and the portion 23 described later is virtually removed from the upper surface of the semiconductor device 1, and the portion 13 and the portion 23 are virtually exposed. Figure 4 is a plan view showing an example of the configuration of the semiconductor device 1, which is a plan view in a state where the configuration on the upper surface side than the portion 17, the portion 68, the portion 27, and the portion 78 described later is virtually removed from the upper surface of the semiconductor device 1, and the portion 17, the portion 68, the portion 27, and the portion 78 are virtually exposed.

[0134] As shown in Figure 1 and Figure 4As shown, the semiconductor device 1 includes a semiconductor layer 40, a metal layer 30, a protective layer 35, a first vertical MOS transistor 10 (hereinafter also referred to as "transistor 10") formed in a first semiconductor layer inner region Al within the semiconductor layer 40, and a second vertical MOS transistor 20 (hereinafter also referred to as "transistor 20") formed in a second semiconductor layer inner region A2 within the semiconductor layer 40.

[0135] Here, as shown in FIG. 1, the first semiconductor layer inner region Al and the second semiconductor layer inner region A2 are adjacent to each other in a plan view of the semiconductor layer 40, and are one of the two halves of the semiconductor layer 40 in area. Figure 4 As shown in FIG. 1, the first semiconductor layer inner region Al and the second semiconductor layer inner region A2 are adjacent to each other in a plan view of the semiconductor layer 40, and are one of the two halves of the semiconductor layer 40 in area.

[0136] As shown in FIG. 1, the first semiconductor layer inner region Al and the second semiconductor layer inner region A2 are adjacent to each other in a plan view of the semiconductor layer 40, and are one of the two halves of the semiconductor layer 40 in area. Figures 1-4 As shown in FIG. 1, the semiconductor device 1 and the semiconductor layer 40 are rectangular in a plan view of the semiconductor layer 40.

[0137] Hereinafter, it is assumed that the semiconductor device 1 and the semiconductor layer 40 are square in a plan view of the semiconductor layer 40, and the description will be given. However, as will be described later, the semiconductor device 1 and the semiconductor layer 40 can be rectangular, and need not necessarily be a structure in which they are square.

[0138] Hereinafter, it is assumed that the boundary line, i.e., the internal boundary line 400, between the first semiconductor layer inner region Al and the second semiconductor layer inner region A2 in a plan view of the semiconductor layer 40 is a line segment connecting the midpoint of the first side 201 of the semiconductor layer 40 with the midpoint of the third side 203 of the semiconductor layer 40 opposite the first side 201, and the description will be given, i.e., it is assumed that the first semiconductor layer inner region Al and the second semiconductor layer inner region A2 are one of the two halves of the semiconductor layer 40 in area divided by a straight line connecting the midpoint of the first side 201 with the midpoint of the third side 203. However, the first semiconductor layer inner region Al and the second semiconductor layer inner region A2 can be one of the two halves of the semiconductor layer 40 in area divided by a straight line connecting the midpoint of the first side 201 with the midpoint of the third side 203, and need not necessarily be a structure in which they are one of the two halves of the semiconductor layer 40 in area divided by a straight line connecting the midpoint of the first side 201 with the midpoint of the third side 203. The internal boundary line 400 can coincide with the upper surface boundary line 600 described later in a plan view of the semiconductor layer 40.

[0139] The semiconductor layer 40 is configured by stacking the semiconductor substrate 32, the low-concentration impurity layer 33, and the oxide film 34.

[0140] The semiconductor substrate 32 is disposed on the lower surface side of the semiconductor layer 40 and is composed of silicon containing impurities of the first conductivity type.

[0141] The low-concentration impurity layer 33 is disposed on the upper surface side of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, and contains impurities of the first conductivity type at a lower concentration than the concentration of impurities of the first conductivity type of the semiconductor substrate 32. The low-concentration impurity layer 33 can be formed on the semiconductor substrate 32, for example, by epitaxial growth.

[0142] The oxide film 34 is disposed on the upper surface of the semiconductor layer 40 and is formed in contact with the low-concentration impurity layer 33.

[0143] The insulating film 36 is an insulating film that insulates the portion 17 of the first source electrode 11 described later and the portion 23 of the second source electrode 21 described later and insulates the portion 27 of the second source electrode 21 and the portion 13 of the first source electrode 11, is formed so as to cover the entire area in which the portion 17 of the first source electrode 11 and the portion 23 of the second source electrode 21 overlap each other in the plan view of the semiconductor layer 40 and the entire area in which the portion 27 of the second source electrode 21 and the portion 13 of the first source electrode 11 overlap each other, and is formed with the portion 17 and the portion 23 interposed therebetween and with the portion 27 and the portion 13 interposed therebetween. In addition, Figure 1 The cross-sectional view shown is a cross-sectional view of a portion in which the portion 17 and the portion 23 do not overlap each other in the plan view of the semiconductor layer 40, and thus the state in which the insulating film 36 is interposed between the portion 17 and the portion 23 and the state in which the insulating film 36 is interposed between the portion 27 and the portion 13 are not shown.

[0144] The protective layer 35 is formed on the upper surface of the semiconductor layer 40 and covers at least a portion of the upper surface of the semiconductor layer 40.

[0145] The metal layer 30 is formed in contact with the lower surface of the semiconductor substrate 32 and is composed of silver, copper, nickel, or an alloy thereof. In addition, in the metal layer 30, elements other than metals that are mixed as impurities in the manufacturing process of metal materials can be contained in a trace amount. The metal layer 30 can be formed, for example, in contact with the entire lower surface of the semiconductor substrate 32.

[0146] Further, as Figure 1 and Figure 2As shown, the semiconductor device 1 has one or more (here, seven) first source pads 111 (here, first source pads 111a, 111b, 111c, 111d, 111e, 111f, and 111g) and a first gate pad 119 in the first semiconductor layer upper surface region S1 on the upper surface of the semiconductor layer 40, which are bonded to the mounting substrate via bonding members when mounted face down. Furthermore, the semiconductor device 1 has one or more (here, seven) second source pads 121 (here, second source pads 121a, 121b, 121c, 121d, 121e, 121f, and 121g) and a second gate pad 129 in the second semiconductor layer upper surface region S2 on the upper surface of the semiconductor layer 40, which are bonded to the mounting substrate via bonding members when mounted face down.

[0147] Each of the first source pads 111 and each of the second source pads 121 is rectangular, oval, or circular in the plan view of the semiconductor layer 40. The first gate pad 119 and the second gate pad 129 are circular in the plan view of the semiconductor layer 40. Furthermore, in this specification, the end shapes of the rectangles and oval shapes are not limited to square (corresponding to a rectangle) or semi-circular (corresponding to an oval), and can also be polygonal.

[0148] Here, as Figure 2 As shown, the first semiconductor layer upper surface region S1 and the second semiconductor layer upper surface region S2 are adjacent to each other in the plan view of the semiconductor layer 40, and are one side and the other side that divide the semiconductor layer 40 into two equal areas. In this specification, the area comprising the portion constituting the first vertical MOS transistor 10 is defined as the first semiconductor layer upper surface region S1, and the area comprising the portion constituting the second vertical MOS transistor 20 is defined as the second semiconductor layer upper surface region S2.

[0149] like Figure 2 As shown, in the plan view of semiconductor layer 40, the boundary line between the upper surface region S1 of the first semiconductor layer and the upper surface region S2 of the second semiconductor layer, i.e., the upper surface boundary line 600, is the line segment connecting the first vertex 501 formed by the first side 201 and the fourth side 204 of semiconductor layer 40, and the second vertex 502 formed by the second side 202 and the third side 203 of semiconductor layer 40. That is, in the plan view of semiconductor layer 40, the upper surface region S1 of the first semiconductor layer and the upper surface region S2 of the second semiconductor layer are two sides of semiconductor layer 40 that are bisected in area by the line segment connecting the first vertex 501 and the second vertex 502. The inner boundary line 400 and the upper surface boundary line 600 may or may not be the same in the plan view of semiconductor layer 40.

[0150] like Figure 2As shown, in the plan view of the semiconductor layer 40, the first gate pad 119 and the second gate pad 129 are arranged at positions where a first imaginary straight line 91 connecting the center of the first gate pad 119 and the center of the second gate pad 129 passes through the center of the semiconductor layer 40 and the angle formed by each side of the semiconductor layer 40 is 45 degrees. Also, as shown in Figure 2 As shown, in the plan view of the semiconductor layer 40, the first gate pad 119 is arranged so that no part of the first source pad 111 is sandwiched between the first gate pad 119 and the first side 201 and the second side 202, and the second gate pad 129 is arranged so that no part of the second source pad 121 is sandwiched between the second gate pad 129 and the third side 203 and the fourth side 204.

[0151] In addition, in the present specification, the "angle" refers to the smaller one of the angles (including 90 degrees) formed by two straight lines.

[0152] Here, the center of the gate pad in the plan view of the semiconductor layer refers to the center of the shape of the gate pad in the plan view of the semiconductor layer. For example, in the case where the gate pad is a perfect circle, the center of the gate pad is the center of the perfect circle, for example, in the case where the gate pad is a rectangle, the center of the gate pad is the intersection of the two diagonal lines of the rectangle, and for example, in the case where the gate pad is an oblong, it is the intersection of a line segment that divides the length direction of the oblong into two and a line segment that divides the width direction of the oblong into two.

[0153] Here, the center of the semiconductor layer in the plan view of the semiconductor layer refers to the center of the shape of the semiconductor layer in the plan view of the semiconductor layer. For example, in the case where the semiconductor layer is a rectangle, the center of the semiconductor layer is the intersection of the two diagonal lines of the rectangle.

[0154] In addition, as described above, the present embodiment assumes that the semiconductor device 1 and the semiconductor layer 40 are square in the plan view of the semiconductor layer 40, and thus, as shown in Figure 2 As shown, the first imaginary straight line 91 becomes a straight line connecting the third vertex 503 and the fourth vertex 504 in the plan view of the semiconductor layer 40.

[0155] In addition, the number of the one or more first source pads 111 and the number of the one or more second source pads 121 are not necessarily limited to seven as exemplified in Figure 2 the above, but can be one or more numbers other than seven.

[0156] As shown in Figures 1-4As shown, in the region Al of the first semiconductor layer in the low concentration impurity layer 33, a first body region 18 including an impurity of a second conductivity type different from the first conductivity type is formed. In the first body region 18, a first source region 14, a first gate conductor 15, and a first gate insulating film 16 including an impurity of the first conductivity type are formed.

[0157] The first source electrode 11 includes a portion 17 formed in a region inside the semiconductor layer 40, and a portion 12 and a portion 13 formed in an upper surface region on an upper surface than the semiconductor layer 40, the portion 12 being connected to the first source region 14 and the first body region 18 via the portion 13 and the portion 17.

[0158] The portion 12 of the first source electrode 11 is a layer to be joined with solder at reflow in face-down mounting, and can be composed of a metal material including one or more of nickel, titanium, tungsten, and palladium as an example not to be limited. To an upper surface of the portion 12, a plating layer of gold or the like can be applied.

[0159] The portion 13 of the first source electrode 11 is a layer to connect the portion 12 and the portion 17, and can be composed of a metal material including one or more of aluminum, copper, gold, and silver as an example not to be limited.

[0160] The portion 17 of the first source electrode 11 is a layer to connect the portion 13 and the semiconductor layer 40, and can be composed of a metal material including one or more of aluminum, copper, gold, and silver as an example not to be limited.

[0161] The first gate electrode includes a portion 68 formed in the semiconductor layer 40, and a portion A (not shown) and a portion 69 formed in the upper surface region, the portion A being connected to the first gate conductor 15 via the portion 69 and the portion 68.

[0162] The portion A of the first gate electrode is a layer to be joined with solder at reflow in face-down mounting, and can be composed of a metal material including one or more of nickel, titanium, tungsten, and palladium as an example not to be limited. To an upper surface of the portion A, a plating layer of gold or the like can be applied.

[0163] The portion 69 of the first gate electrode is a layer to connect the portion A and the portion 68, and can be composed of a metal material including one or more of aluminum, copper, gold, and silver as an example not to be limited.

[0164] The portion 68 of the first gate electrode is a layer to connect the portion 69 and the first gate conductor 15, and can be composed of a metal material including one or more of aluminum, copper, gold, and silver as an example not to be limited, or can be polysilicon.

[0165] In the region A2 of the second semiconductor layer in the low concentration impurity layer 33, a second body region 28 including an impurity of the second conductivity type is formed. In the second body region 28, a second source region 24, a second gate conductor 25, and a second gate insulating film 26 including an impurity of the first conductivity type are formed.

[0166] The second source electrode 21 includes a portion 27 formed in the region of the semiconductor layer 40, and a portion 22 and a portion 23 formed in the upper surface region, the portion 22 being connected to the second source region 24 and the second body region 28 via the portion 23 and the portion 27.

[0167] The portion 22 of the second source electrode 21 is a layer which is joined with solder at reflow in the face-down mounting, and can be composed of a metal material including one or more of nickel, titanium, tungsten, and palladium as an example which is not limited. To the upper surface of the portion 22, a plating layer of gold or the like can be applied.

[0168] The portion 23 of the second source electrode 21 is a layer which connects the portion 22 and the portion 27, and can be composed of a metal material including one or more of aluminum, copper, gold, and silver as an example which is not limited.

[0169] The portion 27 of the second source electrode 21 is a layer which connects the portion 23 and the semiconductor layer 40, and can be composed of a metal material including one or more of aluminum, copper, gold, and silver as an example which is not limited.

[0170] The second gate electrode includes a portion 78 formed in the semiconductor layer 40, and a portion B (not shown) and a portion 79 formed in the upper surface region, the portion B being connected to the second gate conductor 25 via the portion 79 and the portion 78.

[0171] The portion B of the second gate electrode is a layer which is joined with solder at reflow in the face-down mounting, and can be composed of a metal material including one or more of nickel, titanium, tungsten, and palladium as an example which is not limited. To the upper surface of the portion B, a plating layer of gold or the like can be applied.

[0172] The portion 79 of the second gate electrode is a layer which connects the portion B and the portion 78, and can be composed of a metal material including one or more of aluminum, copper, gold, and silver as an example which is not limited.

[0173] The portion 78 of the second gate electrode is a layer which connects the portion 79 and the second gate conductor 25, and can be composed of a metal material including one or more of aluminum, copper, gold, and silver as an example which is not limited, or can be polysilicon.

[0174] With the above structure of the transistor 10 and the transistor 20, the low-concentration impurity layer 33 and the semiconductor substrate 32 function as a common drain region which is common to the first drain region of the transistor 10 and the second drain region of the transistor 20.

[0175] As shown in FIG. 1, the first body region 18 is covered with an oxide film 34 having an opening, and a portion 13 of the first source electrode 11 connected to the first source region 14 through the opening of the oxide film 34 is provided. The oxide film 34 and the portion 13 of the first source electrode 11 are covered with a protective layer 35 having an opening, and a portion 12 of the first source electrode 11 connected to the portion 13 through the opening of the protective layer 35 is provided. Figure 1 The second body region 28 is covered with the oxide film 34 having an opening, and a portion 23 of the second source electrode 21 connected to the second source region 24 through the opening of the oxide film 34 is provided. The oxide film 34 and the portion 23 of the second source electrode 21 are covered with the protective layer 35 having an opening, and a portion 22 of the second source electrode 21 connected to the portion 23 through the opening of the protective layer 35 is provided.

[0176] Thus, the one or more first source pads 111 and the one or more second source pads 121 each refer to a portion of the first source electrode 11 and the second source electrode 21, respectively, which is partially exposed on the upper surface of the semiconductor device 1, i.e., a terminal. Similarly, the first gate pad 119 and the second gate pad 129 each refer to a portion of the first gate electrode and the second gate electrode, respectively, which is partially exposed on the upper surface of the semiconductor device 1, i.e., a terminal. In this specification, the source pads and the gate pads are collectively referred to as "electrode pads".

[0177] Further, the upper surface boundary line 600 can be understood as an imaginary straight line along the center of the interval between the portion 13 of the first source electrode 11 in the first semiconductor layer upper surface region S1 and the portion 23 of the second source electrode 21 in the second semiconductor layer upper surface region S2, as a metal wiring called an EQR (Equipotential Ring) which is sometimes provided at the center and which does not have a function of passing current, or as the interval itself, although it has a limited width. In the case of the interval, it can be recognized as a line in the appearance under the naked eye or at a low magnification.

[0178]

[0179] ​Likewise, the internal boundary line 400 can be understood as an imaginary straight line along the center of the interval between the portion 17 of the first source electrode 11 in the first semiconductor layer inner region Al and the portion 27 of the second source electrode 21 in the second semiconductor layer inner region A2, as an EQR that is sometimes provided at the center, and as the interval itself, although of a limited width. In the case of the interval, it can be recognized as a line in the appearance under the naked eye or at a low magnification.

[0180] [1-2. Operation of semiconductor device]

[0181] In the semiconductor device 1, for example, the first conductive type can be set as N type, the second conductive type can be set as P type, the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 can be N-type semiconductors, and the first body region 18 and the second body region 28 can be P-type semiconductors.

[0182] Further, in the semiconductor device 1, for example, the first conductive type can be set as P type, the second conductive type can be set as N type, the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 can be P-type semiconductors, and the first body region 18 and the second body region 28 can be N-type semiconductors.

[0183] In the following description, it is assumed that the transistor 10 and the transistor 20 are so-called N-channel transistors in which the first conductive type is set as N type and the second conductive type is set as P type, and the on operation of the semiconductor device 1 is described.

[0184] In the semiconductor device 1, if a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21, and a voltage of the threshold value or more is applied to the second gate electrode (the second gate conductor 25) with the second source electrode 21 as a reference, a conduction channel is formed in the vicinity of the second gate insulating film 26 in the second body region 28. As a result, a main current flows in a path of the first source electrode 11 - the first body region 18 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 30 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the conduction channel formed in the second body region 28 - the second source region 24 - the second source electrode 21, and the semiconductor device 1 becomes in an on state. In addition, a PN junction exists at the contact surface between the first body region 18 and the low-concentration impurity layer 33 in the main current path, and functions as a body diode. Further, since the main current mainly flows in the horizontal direction through the metal layer 30, by making the metal layer 30 thicker, the cross-sectional area of the main current path is expanded, and the on resistance of the semiconductor device 1 can be reduced.

[0185] Similarly, in semiconductor device 1, if a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first source electrode 11, and a voltage above a threshold is applied to the first gate electrode (first gate conductor 15) with reference to the first source electrode 11, a conduction channel is formed near the first gate insulating film 16 in the first body region 18. As a result, a main current flows through the path of second source electrode 21 – second body region 28 – low-concentration impurity layer 33 – semiconductor substrate 32 – metal layer 30 – semiconductor substrate 32 – low-concentration impurity layer 33 – conduction channel formed in the first body region 18 – first source region 14 – first source electrode 11, and semiconductor device 1 becomes conductive. In addition, a PN junction exists at the contact surface between the second body region 28 and the low-concentration impurity layer 33 in this main current path, which functions as a body diode.

[0186] [1-3. Structure of a Semiconductor Module]

[0187] The structure of the semiconductor module in Embodiment 1 will be described below.

[0188] Figure 5 This is a plan view showing an example of the structure of the semiconductor module 5 in Embodiment 1.

[0189] like Figure 5 As shown, the semiconductor module 5 includes the aforementioned semiconductor device 1 and a mounting substrate 50 on which the semiconductor device 1 is mounted facing downwards. The mounting substrate 50 has a shape that has a certain width at least at the portion where the semiconductor device 1 is mounted and extends in the length direction. Figure 5 In the diagram, the semiconductor device 1 is represented by dashed lines as if it were transparent, so that the structure of the upper surface of the semiconductor device 1 and the surface of the mounting substrate 50, which are not actually visible to the naked eye, can be easily understood.

[0190] like Figure 5 As shown, with the surface of the mounting substrate 50 facing the positive z-axis, the semiconductor device 1 is mounted on the mounting substrate 50 with its upper surface facing the negative z-axis.

[0191] Figure 6 This is a schematic diagram showing the semiconductor device 1 mounted face down on the surface of the mounting substrate 50. Here, using... Figure 6 The example shown is an installation facing downwards, but this is just one example; even when using... Figure 6 In addition to the mounting example described, by mounting the upper surface of the semiconductor device 1 towards the negative z-axis with the surface of the mounting substrate 50 facing the positive z-axis, it is also possible to perform face-down mounting.

[0192] like Figure 6 As shown, Figure 2The orientation shown in the diagram is as follows: Figure 6 As shown in (a), the semiconductor device 1 with its upper surface facing the positive z-axis is flipped relative to the z-axis, becoming Figure 6 The state shown in diagram (b) is then rotated 90 degrees to the left about the z-axis, becoming... Figure 6 As shown in (c), the substrate is mounted onto the surface of the mounting substrate 50.

[0193] At this time, the semiconductor device 1 is mounted face down on the surface of the mounting substrate 50 in the following orientation: the second side 202 and the fourth side 204 extend parallel to the length direction of the mounting substrate 50. Figure 6 (in the x-axis direction), and the first gate pad 119 is located on the first extending direction side in the extending direction of the length direction of the mounting substrate 50 ...). Figure 6 (the negative x-axis).

[0194] Back to Figure 5 Continuing with the explanation of semiconductor module 5.

[0195] like Figure 5 As shown, the mounting substrate 50 has a shape that extends in the length direction and has a certain width at least at the location where the semiconductor device 1 is mounted in the plan view of the mounting substrate 50. The mounting substrate 50 has a first through-hole 61 through which a first conductor electrically connected to the first gate pad 119 (here, the metal wiring 55 electrically connected to the first gate pad 119, or the conductor connected to the metal wiring 55, described later) passes, and a second through-hole 62 through which a second conductor electrically connected to the second gate pad 129 (here, the metal wiring 56 electrically connected to the second gate pad 129, or the conductor connected to the metal wiring 56, described later) passes.

[0196] The mounting substrate 50 also has a first metal wiring 51, a second metal wiring 52, a metal wiring 55 and a metal wiring 56 on its surface.

[0197] The first metal wiring 51 and the second metal wiring 52 are separated by a gap 54 in the length direction of the mounting substrate 50. Figure 5 Arranged along the x-axis (in the image).

[0198] The first metal wiring 51 is bonded to all of one or more first source pads 111. The first metal wiring 51 is bonded to all of one or more first source pads 111, for example, via a conductive bonding member formed of solder or the like.

[0199] The second metal wiring 52 is bonded to all of one or more second source pads 121. The second metal wiring 52 is bonded to all of one or more second source pads 121, for example, via a conductive bonding member formed of solder or the like.

[0200] Therefore, as Figure 5 As shown, the semiconductor device 1 is mounted face down at a position spanning the first metal wiring 51 and the second metal wiring 52 with a gap 54 between them.

[0201] Metal wiring 55 is bonded to the first gate pad 119. Metal wiring 55 is bonded to the first gate pad 119, for example, via a conductive bonding member formed of solder or the like.

[0202] Metal wiring 56 is bonded to the second gate pad 129. Metal wiring 56 is bonded to the second gate pad 129, for example, via a conductive bonding element formed of solder or the like.

[0203] If a voltage exceeding a threshold voltage is applied to the second gate pad 129 via the second conductor passing through the second via 62, the second transistor 20 becomes conductive. Therefore, when the voltage on the first metal wiring 51 side is higher than that on the second metal wiring 52 side, by applying a voltage exceeding a threshold voltage to the second gate pad 129, such as... Figure 5 As shown by the arrow, the main current flows from the first metal wiring 51 side to the second metal wiring 52 side. Here, the main current is the current flowing in the power line of the mounting substrate 50 containing the semiconductor device 1.

[0204] If a voltage exceeding a threshold voltage is applied to the first gate pad 119 via the first conductor passing through the first via 61, the first transistor 10 becomes in the on state. Therefore, when the voltage on the second metal wiring 52 side is higher than that on the first metal wiring 51 side, by applying a voltage exceeding a threshold voltage to the first gate pad 119, the first transistor 10 becomes in the on state. Figure 5 The main current flows from the second metal wiring 52 side to the first metal wiring 51 side in the opposite direction of the arrow.

[0205] Figure 7 This is a plan view illustrating a variation of the configuration of the first through hole 61 and the second through hole 62.

[0206] like Figure 7 As shown, in the plan view of the mounting substrate 50, the center of the first via 61 is preferably located at any of the following positions: (1) a position on the first imaginary straight line 91 (e.g., Figure 7 (1) The center position of the first through hole 613 in the middle; (2) In the extension direction of the first side 201 ( Figure 7the first semiconductor device 1 beyond the second edge 202 in the extension direction of the second edge 202 (for example, the center of the second through-hole 622 in the plan view of the mounting substrate 50) ; or (3) the outside of the first semiconductor device 1 beyond the third edge 203 in the extension direction of the fourth edge 204 and between the center of the second gate pad 129 and the fourth edge 204 in the extension direction of the third edge 203 (for example, the center of the second through-hole 621 in the plan view of the mounting substrate 50). Figure 7 the center of the first through-hole 611 in the plan view of the mounting substrate 50) ; or (3) the outside of the first semiconductor device 1 beyond the first edge 201 in the extension direction of the second edge 202 and between the center of the first gate pad 119 and the second edge 202 in the extension direction of the first edge 201 (for example, the center of the first through-hole 612 in the plan view of the mounting substrate 50). Figure 7 the center of the first through-hole 611 in the plan view of the mounting substrate 50) ; or (3) the outside of the first semiconductor device 1 beyond the first edge 201 in the extension direction of the second edge 202 and between the center of the first gate pad 119 and the second edge 202 in the extension direction of the first edge 201 (for example, the center of the first through-hole 612 in the plan view of the mounting substrate 50). Figure 7 the center of the first through-hole 611 in the plan view of the mounting substrate 50) ; or (3) the outside of the first semiconductor device 1 beyond the first edge 201 in the extension direction of the second edge 202 and between the center of the first gate pad 119 and the second edge 202 in the extension direction of the first edge 201 (for example, the center of the first through-hole 612 in the plan view of the mounting substrate 50).

[0207] By arranging the center of the first through-hole 61 at such a position, the length of the metal wiring 55 can be made relatively short. Further, since the wiring (through-hole) can be made common to the front surface and the back surface when the positions of the gate pads are aligned by double-sided mounting, the substrate wiring can be simplified. Moreover, in the arrangement of (1), high versatility can be obtained regardless of whether the shape of the semiconductor device 1 is square or rectangular in the plan view of the semiconductor layer 40. Furthermore, in the arrangement of (2), since the through-hole does not hinder the main current flowing through the mounting substrate and the semiconductor device, the on-resistance can be reduced. Moreover, in the arrangement of (3), since it is not necessary to increase the width of the mounting substrate 40, space saving of the semiconductor module 5 can be achieved.

[0208] Here, the center of the through-hole in the plan view of the mounting substrate means the center of gravity of the shape of the through-hole in the plan view of the mounting substrate. For example, in the case where the through-hole is a perfect circle, the center of the through-hole is the center of the perfect circle.

[0209] As shown in FIG. 10, in the plan view of the mounting substrate 50, the center of the second through-hole 62 is preferably located at any one of the following positions: (1) a position on the first imaginary straight line 91 (for example, the center of the second through-hole 623 in the plan view of the mounting substrate 50) ; (2) the outside of the first semiconductor device 1 beyond the fourth edge 204 in the extension direction of the third edge 203 (for example, the center of the second through-hole 622 in the plan view of the mounting substrate 50) ; or (3) the outside of the first semiconductor device 1 beyond the third edge 203 in the extension direction of the fourth edge 204 and between the center of the second gate pad 129 and the fourth edge 204 in the extension direction of the third edge 203 (for example, the center of the second through-hole 621 in the plan view of the mounting substrate 50). Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 6

[0210] ​​​​​​By arranging the center of the second through-hole 62 at such a position, the length of the metal wiring 56 can be made relatively short. Further, since the wiring (through-hole) can be made common to the front surface and the back surface when aligning the positions of the gate pads by two-sided mounting, the substrate wiring can be simplified. Furthermore, in the arrangement of (1), high versatility can be obtained regardless of whether the shape of the semiconductor device 1 is square or rectangular in the plan view of the semiconductor layer 40. Furthermore, in the arrangement of (2), since the through-hole does not hinder the main current flowing through the mounting substrate and the semiconductor device, the on-resistance can be reduced. Furthermore, in the arrangement of (3), since it is not necessary to increase the width of the mounting substrate 40, space saving of the semiconductor module 5 can be achieved.

[0211] Here, the center of the through-hole in the plan view of the mounting substrate means the center of gravity of the shape of the through-hole in the plan view of the mounting substrate. For example, in the case where the through-hole is a perfect circle, the center of the through-hole is the center of the perfect circle thereof.

[0212] [1-4. Investigation]

[0213] According to the semiconductor device 1 of the above-described structure, in the case of a usage mode in which two semiconductor devices 1 of the same type are respectively mounted face down on the front surface and the back surface of the mounting substrate, and on-off driving is simultaneously performed, the two semiconductor devices 1 are mounted with the centers thereof overlapping in the plan view of the mounting substrate, and the other semiconductor device 1 is mounted with the orientation thereof relative to the one semiconductor device 1 being rotated 90 degrees about a rotation axis perpendicular to the plan of the mounting substrate and passing through the center of the semiconductor device 1, that is, the one semiconductor device 1 is mounted with the orientation thereof being Figure 6 (c) of (1), and the other semiconductor device 1 is mounted with the orientation thereof being Figure 6 (a) of (1), thereby the position of the first gate pad 119 of the one semiconductor device 1 and the position of the first gate pad 119 of the other semiconductor device 1 can be aligned, and the position of the second gate pad 129 of the one semiconductor device 1 and the position of the second gate pad 129 of the other semiconductor device 1 can be aligned.

[0214] Thus, in the mounting substrate in which the two semiconductor devices 1 of the same type are respectively mounted on the front surface and the back surface, the wiring for controlling the potential of both the first gate pad 119 of the one semiconductor device 1 and the first gate pad 119 of the other semiconductor device 1, and the wiring for controlling the potential of both the second gate pad 129 of the one semiconductor device 1 and the second gate pad 129 of the other semiconductor device 1 can be made common, respectively, so that the number of wirings (through-holes) is halved as compared with the case where they are separately provided.

[0215] Therefore, it is possible to ensure a current path through which a main current flows in the mounting substrate, and to design in a manner of reducing an on-resistance.

[0216] Thus, according to the semiconductor device 1 of the above-described structure, it is possible to provide a semiconductor device having a feature of efficiently causing a current to flow in a current path of a mounting substrate for mounting.

[0217] Further, according to Figure 6 in (a) and Figure 8 in (c), in a case where two semiconductor devices 1 of the same type are mounted face down to the front surface and the back surface of a mounting substrate, respectively, by overlapping the centers of the two semiconductor devices 1 in a plan view of the mounting substrate and mounting the other semiconductor device 1 so as to be oriented 90 degrees about a rotation axis perpendicular to the plane of the mounting substrate that passes through the center of the semiconductor device 1 with respect to the orientation of the one semiconductor device 1, it is possible to cause the first semiconductor layer upper surface regions S1 of the two semiconductor devices 1 and the second semiconductor layer upper surface regions S2 of the two semiconductor devices 1 to coincide completely across the front surface and the back surface of the mounting substrate in the plan view.

[0218] Thus, in the mounting substrate on which the two semiconductor devices 1 are mounted, it is possible to maximize the on-resistance of the current path, and to obtain an effect of reducing the on-resistance. Further, although not shown, the more the first semiconductor layer upper surface regions S1 overlap each other and the second semiconductor layer upper surface regions S2 overlap each other, the more effective the reduction of the on-resistance is, since it is possible to commonly provide the through holes related to the source.

[0219] In addition, the center of the semiconductor device 1 is the intersection of the diagonals of the semiconductor device 1 in a plan view of the semiconductor layer 40.

[0220] Figure 8 is a comparison result list of a comparison regarding the semiconductor device 1 and a conventional semiconductor device of a comparative example, indicating a comparison of the narrowness of the width of the mounting substrate, the on-resistance including the wiring of the mounting substrate, the commonality of the through holes, the ease of design of the gate wiring, and the bending strength of the mounting substrate in a case where the semiconductor device is mounted to the mounting substrate.

[0221] Here, Comparative Example 1 is a conventional semiconductor device in which the boundaries of the regions where one or more first source pads and one or more second source pads are disposed are orthogonal to the orientation of the first side and the third side opposite to it of the semiconductor device, and the first gate pad and the second gate pad are disposed at the corner of the semiconductor device. Comparative Example 2 is a conventional semiconductor device in which the boundaries of the regions where one or more first source pads and one or more second source pads are disposed are orthogonal to the orientation of the first side and the third side opposite to it of the semiconductor device, and the first gate pad and the second gate pad are disposed at the longitudinal center of the semiconductor device. Comparative Example 3 is a conventional semiconductor device in which the boundaries of the regions where one or more first source pads and one or more second source pads are disposed are orthogonal to the orientation of the first side and the third side opposite to it of the semiconductor device, and the first gate pad and the second gate pad are disposed at the transverse center of the semiconductor device.

[0222] like Figure 8 As shown, compared with Comparative Examples 1, 2 and 3, semiconductor device 1 has at least one superior performance in terms of wiring lead-out in the y-axis direction, ease of design of gate wiring, and wiring lead-out in the x-axis direction when the semiconductor device is mounted on a mounting substrate.

[0223] Furthermore, in Comparative Example 2, although it shares the same feature as this disclosure that it simplifies wiring through double-sided mounting, this disclosure allows wiring (vias) common on both the surface and back sides to be positioned close to the ends of the mounting substrate so as not to obstruct the main current (regarding...). Figure 9 The wiring leads in the y-axis direction have excellent performance.

[0224] Figure 9 This is a summary diagram showing the comparison results of semiconductor device 1, Comparative Example 1, Comparative Example 2 and Comparative Example 3, with the semiconductor devices mounted on mounting substrates of various structures, focusing on the width of the main current flow, the number of vias, the arrangement of vias, and the minimization of the width of the mounting substrate. Figure 9 The wiring configuration of each layer in the L1, L2, and L3 diagrams is virtually shown through the plan view viewed from the surface side.

[0225] like Figure 2 As shown, compared with Comparative Examples 1, 2 and 3, semiconductor device 1 has many superior performances, especially in terms of high current charging, even when mounted on a mounting substrate with various structures, in terms of the width of the main current flow, the number of vias, the arrangement of vias, and the minimization of the width of the mounting substrate.

[0226] Further, the semiconductor device 1 has superior characteristics in terms of the strength against bending of the mounting substrate because the gap of the mounting substrate is inclined with respect to the length direction.

[0227] Further, in Embodiment 1, as an example, the case where one or more first source pads 111 and one or more second source pads 121 are arranged as shown in FIG. 1A has been described, but as long as one or more first source pads 111 are arranged on the first semiconductor layer upper surface region S1 and one or more second source pads 121 are arranged on the second semiconductor layer upper surface region S2, it is not necessarily required to arrange them as shown in FIG. 1A. Figure 2 Figure 10A

[0228] Figure 10B Figure 10C Figure 10D Figure 10A are plan views illustrating other arrangement examples of one or more first source pads 111 and one or more second source pads 121.

[0229] As shown in FIG. 1A, one first source pad 111a can be arranged on the entire first semiconductor layer upper surface region S1 except for the region of the first gate pad 119, and one second source pad 121a can be arranged on the entire second semiconductor layer upper surface region S2 except for the region of the second gate pad 129. Figure 10B As shown in FIG. 1B, a plurality of first source pads 111b-111d can be arranged in parallel with the upper surface boundary line 600 on the first semiconductor layer upper surface region S1, and a plurality of second source pads 121b-121d can be arranged in parallel with the upper surface boundary line 600 on the second semiconductor layer upper surface region S2. Figure 10C As shown in FIG. 1C, a plurality of first source pads 111e-111g and a plurality of second source pads 121e-121g can be arranged in two divisions in parallel with the upper surface boundary line 600 on the first semiconductor layer upper surface region S1 and on the second semiconductor layer upper surface region S2, respectively. Figure 10D As shown in FIG. 1D, two first source pads 111h, 111i and two second source pads 121h, 121i can be arranged in two divisions in parallel with the upper surface boundary line 600 on the first semiconductor layer upper surface region S1 and on the second semiconductor layer upper surface region S2, respectively. Figure 11 As shown in FIG. 1E, two first source pads 111j, 111k and two second source pads 121j, 121k can be arranged in two divisions in parallel with the upper surface boundary line 600 on the first semiconductor layer upper surface region S1 and on the second semiconductor layer upper surface region S2, respectively, so that the opposing edges of the two first source pads 111j, 111k and the two second source pads 121j, 121k are orthogonal to the upper surface boundary line 600.

[0230] ​​​​​In addition, in Embodiment 1, the semiconductor device 1 and the semiconductor layer 40 are assumed to be square in plan view of the semiconductor layer 40 and are described. However, it is not necessarily required to be square. As for the semiconductor device 1 and the semiconductor layer 40, it is also possible to be rectangular other than square, as long as the first gate pad 119 and the second gate pad 129 are arranged in plan view of the semiconductor layer 40 so that a first imaginary straight line 91 connecting the center of the first gate pad 119 and the center of the second gate pad 129 passes through the center of the semiconductor layer 40 and forms an angle of 45 degrees with each side of the semiconductor layer 40.

[0231] Figure 11 is a schematic view showing a state in which the above-described rectangular semiconductor device 1 (hereinafter, also referred to as "rectangular semiconductor device") is mounted face down on the surface of the mounting substrate 50. Here, the rectangular semiconductor device 1 is mounted face down in a state in which the upper surface of the rectangular semiconductor device 1 faces the negative direction of the z-axis. Figure 11 An example of face-down mounting is described, but the description here is only an example, and even a method other than the mounting example described above can be used to mount the rectangular semiconductor device 1 face down in a state in which the upper surface of the rectangular semiconductor device 1 faces the positive direction of the z-axis. Figure 11

[0232] As shown in Figure 11 , the rectangular semiconductor device is mounted to the surface of the mounting substrate 50 in a state in which the upper surface of the rectangular semiconductor device faces the positive direction of the z-axis as shown in Figure 11 (a), is flipped over with respect to the z-axis to become a state shown in Figure 11 (b), and is further rotated 90 degrees to the left in a direction in which the z-axis is a rotation axis to become a state shown in Figure 11 (c).

[0233] Accordingly, according to the rectangular semiconductor device, in a case in which two rectangular semiconductor devices of the same type are mounted face down to the surface and the back of the mounting substrate, respectively, by overlapping the centers of the two rectangular semiconductor devices in plan view of the mounting substrate and mounting the other rectangular semiconductor device in a direction in which the orientation of the one rectangular semiconductor device is rotated 90 degrees about a rotation axis perpendicular to the plane of the mounting substrate and passing through the center of the rectangular semiconductor device, that is, by mounting the one rectangular semiconductor device in the orientation of Figure 11 (c) and mounting the other rectangular semiconductor device in the orientation of Figure 12 ​The mounting of (a) in the direction shown in the drawing enables the position of the first gate pad 119 of one rectangular semiconductor device to be aligned with the position of the first gate pad 119 of the other rectangular semiconductor device, and the position of the second gate pad 129 of one rectangular semiconductor device to be aligned with the position of the second gate pad 129 of the other rectangular semiconductor device.

[0234] Thus, in the mounting substrate in which the two rectangular semiconductor devices are mounted, the wiring that controls the potential of both the first gate pad 119 of one rectangular semiconductor device and the first gate pad 119 of the other rectangular semiconductor device, and the wiring that controls the potential of both the second gate pad 129 of one rectangular semiconductor device and the second gate pad 129 of the other rectangular semiconductor device, can be made into a relatively simple structure.

[0235] At this time, in the plan view of the mounting substrate 50, the center of the first through-hole 61 and the center of the second through-hole 62 are preferably positions on the first imaginary straight line 91. Thus, the length of the metal wiring 55 and the length of the metal wiring 56 can be made relatively short.

[0236] (Embodiment 2)

[0237] [2-1. Configuration of Semiconductor Device]

[0238] Hereinafter, the semiconductor device of Embodiment 2 will be described. The semiconductor device of Embodiment 2 is configured by changing a part of the structure of the semiconductor device 1 of Embodiment 1. Therefore, here, regarding the semiconductor device of Embodiment 2, for the same configuration elements as the semiconductor device 1, it is considered that the same description is given and the same reference numerals are assigned, and detailed description thereof is omitted, and description is made focusing on the points of difference from the semiconductor device 1.

[0239] Figure 13 is a plan view showing an example of the configuration of the semiconductor device 1a of Embodiment 2. Figure 12 is a plan view showing an example of the configuration of the semiconductor device 1a, and is a plan view in a state in which the configuration on the upper surface side of the part 13a and the part 23a described later is virtually removed from the upper surface of the semiconductor device 1a, and the part 13a and the part 23a are virtually exposed.

[0240] As Figure 13 and Figure 12As shown, the semiconductor device la changes the first semiconductor layer upper surface region Sl from the semiconductor device 1 of Embodiment 1 to a first semiconductor layer upper surface region Sl a, changes the second semiconductor layer upper surface region S2 to a second semiconductor layer upper surface region S2a, changes the upper surface boundary line 600 to an upper surface boundary line 600a, changes the one or more first source pads 111 to one or more first source pads 1111 (here, first source pads 1111a, 1111b, 1111c, 1111d, 1111e, and 1111f), changes the one or more second source pads 121 to one or more second source pads 1121 (here, second source pads 1121a, 1121b, 1121c, 1121d, 1121e, and 1121f), changes the portion 13 to a portion 13a, and changes the portion 23 to a portion 23a.

[0241] As shown in FIG. 6A, the upper surface boundary line 600a is formed by connecting N-1 line segments parallel to the second edge 202 and N-2 line segments parallel to the first edge 201 alternately in the plan view of the semiconductor layer 40, and the upper surface boundary line 600a monotonically changes in the extension direction of the second edge 202 and the extension direction of the first edge 201. Figure 12 As shown in FIG. 6A, the upper surface boundary line 600a is formed by connecting N-1 line segments parallel to the second edge 202 and N-2 line segments parallel to the first edge 201 alternately in the plan view of the semiconductor layer 40, and the upper surface boundary line 600a monotonically changes in the extension direction of the second edge 202 and the extension direction of the first edge 201.

[0242] In the present specification, monotonically changing refers to a function that monotonically increases in a broad sense or a function that monotonically decreases in a broad sense. That is, the function that monotonically increases in a broad sense refers to a function f(x) that becomes f(xl) < f(x2) in the case of xl < x2, and the function that monotonically decreases in a broad sense refers to a function f(x) that becomes f(xl) > f(x2) in the case of xl < x2.

[0243] Considering the main point of the invention (expanding the overlap between the upper surface regions S1a of the first semiconductor layer and the upper surface region S2a of the second semiconductor layer, which are aligned by mounting the gate pads on both sides), the pad layout in the upper surface region and the upper surface boundary line 600a preferably have point symmetry with the center of the semiconductor device 1a as the center of symmetry. In the case where the upper surface boundary line 600c is stepped, although strict point symmetry cannot be achieved, it is useful in the invention to slightly suppress the degree of deviation. A boundary shape where the center of the semiconductor device 1a is at the corner of the step does not allow this symmetry to hold. To improve point symmetry in the stepped upper surface boundary line 600a, the portion (segment) passing through the center of the semiconductor device 1a needs to have its center aligned with the center of the semiconductor device 1a, and thus, an equal number of portions (segments) are needed in the direction extending from the center to both sides of the segment. That is, preferably, it is a stepped shape consisting of an odd number of line segments in the direction of extension of the line segment passing through the center of the semiconductor device 1a, and an even number of line segments in the direction orthogonal to it. Therefore, it is preferable that the stepped boundary line is composed of N-1 and N-2 line segments, and passes through the center of the semiconductor device 1a in the direction where the number of line segments is odd.

[0244] The distance between the first vertex 501 and the first intersection point 601, which is the intersection of the upper surface boundary line 600a and the first side 201, is more than 1 / N of the length of the first side 201 and is longer than the maximum diameter of the second gate pad 129.

[0245] The distance between the second vertex 502 and the second intersection point 602, which is the intersection of the upper surface boundary line 600a and the third side 203, is more than 1 / N of the length of the third side 203 and is longer than the maximum diameter of the first gate pad 119.

[0246] Here, as Figure 12 As shown, the upper surface region S1a of the first semiconductor layer and the upper surface region S2a of the second semiconductor layer are adjacent to each other in the plan view of the semiconductor layer 40, and are one side and the other side that divide the semiconductor layer 40 into two equal areas.

[0247] Furthermore, in the planar view of semiconductor layer 40, the angle θ1 formed by the second imaginary line 92 connecting the first intersection point 601 and the second intersection point 602 and the first imaginary line 91 is greater than 45 degrees and less than 90 degrees.

[0248] like Figure 13As shown, the one or more first source pads 1111 are a plurality of first source pads 1111 each of which is a long rectangle or an oblong circle having a length direction in a direction parallel to the first side 201 in a plan view of the semiconductor layer 40, and formed in a strip shape in parallel to the first side 201. Further, the one or more second source pads 1121 are a plurality of second source pads 1121 each of which is a long rectangle or an oblong circle having a length direction in a direction parallel to the third side 203 in a plan view of the semiconductor layer 40, and formed in a strip shape in parallel to the third side 203.

[0249] Further, as the shape of the first semiconductor layer upper surface region S1a is changed from the shape of the first semiconductor layer upper surface region S1 of Embodiment 1, and the shape of the second semiconductor layer upper surface region S2a is changed from the shape of the second semiconductor layer upper surface region S2 of Embodiment 1, as shown in Figure 14 As shown, the shape of the portion 13a is changed from the shape of the portion 13 of Embodiment 1, and the shape of the portion 23a is changed from the shape of the portion 23 of Embodiment 1.

[0250] [2-2. Configuration of semiconductor module]

[0251] Hereinafter, the semiconductor module of Embodiment 2 will be described. The semiconductor module of Embodiment 2 is configured by changing a part of the structure of the semiconductor module 5 of Embodiment 1. Therefore, here, regarding the semiconductor module of Embodiment 2, for the same constituent elements as those of the semiconductor module 5, it is considered that the same description is given and the same reference numerals are assigned, and detailed description thereof is omitted, and the description is made focusing on the points different from those of the semiconductor module 5.

[0252] Figure 14 is a plan view showing an example of the configuration of the semiconductor module 5a of Embodiment 2.

[0253] As shown in Figure 14 , the semiconductor module 5a is configured by changing the semiconductor device 1 to the semiconductor device 1a and changing the mounting substrate 50 to the mounting substrate 50a from the semiconductor module 5 of Embodiment 1. In Figure 15 , the semiconductor device 1a is shown by a broken line as if it is transparent, so that the configuration of the upper surface of the semiconductor device 1a and the configuration of the surface of the mounting substrate 50a, which cannot actually be visually recognized, can be easily understood.

[0254] The mounting substrate 50a is configured by changing the first metal wiring 51 to the first metal wiring 51a and changing the second metal wiring 52 to the second metal wiring 52a from the mounting substrate 50.

[0255] Figure 15 is a schematic view showing a state in which the semiconductor device 1a is mounted face down on the surface of the mounting substrate 50a. As shown inFigure 15 (a) as shown, the semiconductor device la in a state where the upper surface faces the positive direction of the z-axis is flipped with respect to the z-axis to become a state shown in (b) as shown, and further, is rotated 90 degrees to the left with the z-axis as the rotation axis direction to become a state shown in (c) as shown, and is mounted to the surface of the mounting substrate 50a. Figure 15 Figure 15

[0256] At this time, the semiconductor device la is mounted face down on the surface of the mounting substrate 50a with the 2nd edge 202 and the 4th edge 204 parallel to the extension direction (x-axis direction in Figure 15 ) of the length direction of the mounting substrate 50a, and the 1st gate pad 119 on the 1st extension direction side (negative direction of the x-axis in Figure 14 ) in the extension direction of the length direction of the mounting substrate 50a.

[0257] Returning again to Figure 14 , the description of the semiconductor module 5a is continued.

[0258] As shown in Figure 14 , the 1st metal wiring 51a and the 2nd metal wiring 52a are arranged in the extension direction (x-axis direction in Figure 14 ) of the length direction of the mounting substrate 50a with the gap 54a therebetween.

[0259] The 1st metal wiring 51a is joined to all of the plurality of 1st source pads 1111. The 1st metal wiring 51a is joined to all of the plurality of 1st source pads 1111, for example, via a conductive joint member formed of solder or the like.

[0260] The 2nd metal wiring 52a is joined to all of the plurality of 2nd source pads 1121. The 2nd metal wiring 52a is joined to all of the plurality of 2nd source pads 1121, for example, via a conductive joint member formed of solder or the like.

[0261] Therefore, as shown in Figure 16 , the semiconductor device la is mounted face down at a position across the 1st metal wiring 51a and the 2nd metal wiring 52a with the gap 54a therebetween.

[0262] Figure 16 is a plan view showing an example of the configuration of the semiconductor module 5b of Embodiment 2.

[0263] As shown in Figure 16 , the semiconductor module 5b is configured by changing the semiconductor device 1 to the semiconductor device la and the mounting substrate 50 to the mounting substrate 50b from the semiconductor module 5 of Embodiment 1. In Figure 17 ​​In the middle, the semiconductor device 1a is indicated by a broken line as if it were transparent, so that the configuration of the upper surface of the semiconductor device 1a, which cannot actually be visually recognized, and the configuration of the surface of the mounting substrate 50b can be easily understood.

[0264] The mounting substrate 50b is configured by changing the first metal wiring 51 to the first metal wiring 51b, the second metal wiring 52 to the second metal wiring 52b, the first via 61 to the first via 61b, the second via 62 to the second via 62b, the metal wiring 55 to the metal wiring 55b, and the metal wiring 56 to the metal wiring 56b from the mounting substrate 50.

[0265] Figure 17 is a schematic view showing a state in which the semiconductor device 1a is mounted face down on the surface of the mounting substrate 50b. As shown in Figure 17 , as shown in Figure 17 (a), the semiconductor device 1a in a state in which the upper surface faces the positive direction of the z-axis is flipped with respect to the z-axis to become a state shown in Figure 17 (b), and further rotated 90 degrees to the left with the z-axis as the axis of rotation to become a state shown in Figure 17 (c), and mounted to the surface of the mounting substrate 50b.

[0266] At this time, the semiconductor device 1a is mounted face down to the surface of the mounting substrate 50b in an orientation in which the first edge 201 and the third edge 203 are parallel to the extension direction (x-axis direction) of the length direction of the mounting substrate 50b, and the first gate pad 119 is positioned on the first extension direction side (negative direction of the x-axis) of the extension direction of the length direction of the mounting substrate 50b. Figure 17 Figure 16

[0267] Returning again to Figure 16 , the description of the semiconductor module 5b is continued.

[0268] As shown in Figure 16 , the mounting substrate 50b has the first via 61b through which a first conductor (here, the metal wiring 55b to be described later that is electrically connected to the first gate pad 119 or a conductor connected to the metal wiring 55b) that is electrically connected to the first gate pad 119 passes, and the second via 62b through which a second conductor (here, the metal wiring 56b to be described later that is electrically connected to the second gate pad 129 or a conductor connected to the metal wiring 56b) that is electrically connected to the second gate pad 129 passes.

[0269] As shown in Figure 16 , the first metal wiring 51b and the second metal wiring 52b are separated by the gap 54b in the extension direction of the length direction of the mounting substrate 50b. Figure 16 ​​Arranged along the x-axis (in the image).

[0270] The first metal wiring 51b is bonded to all of the plurality of first source pads 1111. The first metal wiring 51b is bonded to all of the plurality of first source pads 1111, for example, via a conductive bonding member formed of solder or the like.

[0271] The second metal wiring 52b is bonded to all of the plurality of second source pads 1121. The second metal wiring 52b is bonded to all of the plurality of second source pads 1121, for example, via a conductive bonding member formed of solder or the like.

[0272] Metal wiring 55b is bonded to the first gate pad 119. Metal wiring 55b is bonded to the first gate pad 119, for example, via a conductive bonding element formed of solder or the like.

[0273] Metal wiring 56b is bonded to the second gate pad 129. Metal wiring 56b is bonded to the second gate pad 129, for example, via a conductive bonding element formed of solder or the like.

[0274] Therefore, as Figure 15 As shown, the semiconductor device 1a is mounted face down at a position that spans the first metal wiring 51b and the second metal wiring 52b across a gap 54b.

[0275] [2-3. Investigation]

[0276] According to the semiconductor device 1a with the above structure, in the usage mode where two identical semiconductor devices 1a are mounted face down on the surface and back of a mounting substrate respectively, and simultaneously driven to turn on and off, the centers of the two semiconductor devices 1a are overlapped in the plan view of the mounting substrate, and the orientation of one semiconductor device 1a relative to the other semiconductor device 1a is such that it is rotated 90 degrees around a rotation axis passing through the center of the semiconductor device 1a and perpendicular to the plane of the mounting substrate. That is, one semiconductor device 1a is mounted with... Figure 15 (c) is the orientation of the mounting, with the other semiconductor device 1a facing towards... Figure 17 The orientation of (a) in the image is used for mounting, or one of the semiconductor devices 1a is positioned such that... Figure 17 (c) is the orientation of the mounting, with the other semiconductor device 1a facing towards... Figure 15 The orientation of (a) in the figure is such that the position of the first gate pad 119 of one semiconductor device 1a can be aligned with the position of the first gate pad 119 of the other semiconductor device 1a, and the position of the second gate pad 129 of one semiconductor device 1a can be aligned with the position of the second gate pad 129 of the other semiconductor device 1a.

[0277] Thus, in the mounting substrate in which the two semiconductor devices 1a are mounted, the wiring that controls the potential of both the first gate pad 119 of one semiconductor device 1a and the first gate pad 119 of the other semiconductor device 1a and the wiring that controls the potential of both the second gate pad 129 of one semiconductor device 1a and the second gate pad 129 of the other semiconductor device 1a are each common, so the number of wirings (vias) is halved compared to the case in which they are separately provided.

[0278] Thus, the current path through which the main current flows in the mounting substrate can be ensured to be wide, and the current path can be designed in a manner that reduces the on-resistance.

[0279] Further, the wirings that control the potential of both the first gate pad 119 and the second gate pad 129 can be each common, and the number of wirings (vias) that must be separately provided in the past can be reduced. Thus, the complex wirings of the mounting substrate 50a and the mounting substrate 50b, which tend to be complicated, are simplified, and the ease of substrate design can be improved.

[0280] Thus, the current path through which the main current flows in the mounting substrate can be designed in a manner that reduces the on-resistance.

[0281] Thus, according to the semiconductor device 1a of the above-described structure, a semiconductor device having a feature that enables efficient current flow in the current path of the mounting substrate in which it is mounted can be provided.

[0282] Further, according to Figure 15 (a) and Figure 17 (c) and Figure 17 (a) and Figure 18 (c) in the case in which two semiconductor devices 1a are each mounted face down to the surface and the back of a mounting substrate, by overlapping the centers of the two semiconductor devices 1a in the plan view of the mounting substrate and mounting the other semiconductor device 1a so that the orientation thereof with respect to the orientation of one semiconductor device 1a is rotated 90 degrees about a rotation axis that is perpendicular to the plane of the mounting substrate and that passes through the center of the semiconductor device 1a, the first semiconductor layer upper surface region S1a of the two semiconductor devices 1a and the second semiconductor layer upper surface region S2a of the two semiconductor devices 1a can be overlapped in the plan view of the mounting substrate.

[0283] Thus, in the mounting substrate in which the two semiconductor devices 1a are mounted, the on-resistance of the current path can be reduced.

[0284] Figure 8This refers to (1) the degree of overlap between the areas of the first semiconductor layer upper surface region S1a of one semiconductor device 1a and the area of ​​the first semiconductor layer upper surface region S1a of the other semiconductor device 1a in the plan view of semiconductor layer 40 (i.e., the degree of overlap between the areas of the second semiconductor layer upper surface region S2a of one semiconductor device 1a and the area of ​​the second semiconductor layer upper surface region S2a of the other semiconductor device 1a), i.e., the consistency (hereinafter also referred to as "consistency"), and (2) in the... Figure 18 The graph shows the relationship between the improvement rate of consistency (hereinafter also referred to as "improvement rate of consistency compared to the past") when Comparative Example 1 is used as the previous baseline.

[0285] exist Figure 8 In the middle, the horizontal axis is... Figure 18 In Comparative Example 1, the position of the upper surface boundary line is the conventional reference. The second imaginary straight line 92 of semiconductor device 1a is tilted from the reference at an angle θ. The left vertical axis is the consistency, and the right vertical axis is the improvement rate of consistency compared to the conventional version.

[0286] exist Figure 8 In China, even as a previous benchmark ( Figure 18 In Comparative Example 1), the configuration of the upper surface boundary line (θ = 0°) also results in a consistency of 50%. If θ is increased, the consistency gradually increases from 50%, reaching a maximum of 100% at θ = 45°. The improvement in consistency compared to the past, based on θ = 0° (1.0), naturally becomes 2.0 at θ = 45°. Furthermore, an improvement in consistency of 1.1 times or more compared to the past is preferred. Therefore, as... Figure 15 As shown, it is preferable that the upper surface boundary line is inclined from the reference such that the angle θ is 11.3 degrees or more. Furthermore, considering the margin, it is preferable that the upper surface boundary line is inclined from the reference such that the angle θ is 15 degrees or more. If θ is associated with θ1, then θ1 = 45 degrees + θ, so it is preferable that θ1 is 60 degrees or more, and θ1 is preferably 60 degrees or more and 90 degrees or less.

[0287] When a semiconductor device 1a with an angle θ1 of 60 degrees or more and less than 90 degrees is used for mounting a semiconductor module 5a, the second imaginary straight line 92 extends along the length direction of the mounting substrate 50a. Figure 15 The angle between the imaginary straight line 92 and the x-axis direction (in the context of the semiconductor module 5b) is 45 degrees or more and 75 degrees or less. Furthermore, when a semiconductor device 1a with an angle θ1 of 60 degrees or more and 90 degrees or less is used for mounting a semiconductor module 5b, the second imaginary straight line 92 and the extension direction of the mounting substrate 50b (in the context of the semiconductor module 5b) are... Figure 12The angle formed by the second imaginary straight line 92 and the extension direction of the length direction of the mounting substrate 50a or 50b is 15 degrees or more and 45 degrees or less. In this way, in the case where the semiconductor device 1a in which the angle θ1 is 60 degrees or more and 90 degrees or less, which is a preferable angle, is used for the semiconductor module 5a or 5b, the angle formed by the second imaginary straight line 92 and the extension direction of the length direction of the mounting substrate 50a or 50b is 15 degrees or more and 75 degrees or less.

[0288] In addition, in Embodiment 2, as an example, it is assumed that one or more first source pads 1111 and one or more second source pads 1121 are arranged as shown in FIG. 10A, but as long as one or more first source pads 1111 are arranged on the first semiconductor layer upper surface region S1a and one or more second source pads 1121 are arranged on the second semiconductor layer upper surface region S2a, it is not necessary to arrange them as shown in FIG. 10A. Figure 12 Figure 19A

[0289] Figure 19B Figure 19A FIG. 11 is a plan view illustrating another arrangement example of one or more first source pads 1111 and one or more second source pads 1121.

[0290] As shown in FIG. 11, one first source pad 1111g can be arranged on substantially the entire surface of the first semiconductor layer upper surface region S1a except for the region of the first gate pad 119, and one second source pad 1121g can be arranged on substantially the entire surface of the second semiconductor layer upper surface region S2a except for the region of the second gate pad 129. As shown in FIG. 12, two first source pads 1111h, 1111i can be arranged on substantially the entire surface of the first semiconductor layer upper surface region S1a except for the region of the first gate pad 119 by being divided into two in a manner that the opposing sides thereof are parallel to each other, and two second source pads 1121h, 1121i can be arranged on substantially the entire surface of the second semiconductor layer upper surface region S2a except for the region of the second gate pad 129 by being divided into two in a manner that the opposing sides thereof are parallel to each other. Figure 19B Figure 20

[0291] (Embodiment 3)

[0292] [3-1. Configuration of Semiconductor Device]

[0293] Hereinafter, the semiconductor device of Embodiment 3 will be described. The semiconductor device of Embodiment 3 is configured by changing a part of the structure of the semiconductor device 1 of Embodiment 1. Therefore, here, regarding the semiconductor device of Embodiment 3, the same components as those of the semiconductor device 1 are considered to have been described and given the same reference numerals, and detailed description thereof will be omitted, and description will be made focusing on the points of difference from the semiconductor device 1.​​​​​

[0294] Figure 21 This is a plan view showing an example of the structure of the semiconductor device 1c according to Embodiment 3. Figure 20 This is a plan view showing an example of the structure of semiconductor device 1c. It is a plan view in which the structure on the upper surface side of the upper surface of semiconductor device 1c that is virtually removed from the upper surface of ...

[0295] like Figure 21 and Figure 20 As shown, the semiconductor device 1c is configured to change the upper surface region S1 of the first semiconductor layer to the upper surface region S1c of the first semiconductor layer, change the upper surface region S2 of the second semiconductor layer to the upper surface region S2c of the second semiconductor layer, change the upper surface boundary line 600 to the upper surface boundary line 600c, change one or more first source pads 111 to one or more first source pads 2111 (here, first source pads 2111a, 2111b, 2111c, 2111d and 2111e), change one or more second source pads 121 to one or more second source pads 2121 (here, second source pads 2121a, 2121b, 2121c, 2121d and 2121e), change part 13 to part 13c, and change part 23 to part 23c.

[0296] like Figure 21 As shown, in the plan view of semiconductor layer 40, the upper surface boundary line 600c, which serves as the boundary line between the upper surface region S1c of the first semiconductor layer and the upper surface region S2c of the second semiconductor layer, is a line segment connecting the third vertex 503 and the fourth vertex 504. That is, in the plan view of semiconductor layer 40, the upper surface region S1c of the first semiconductor layer and the upper surface region S2c of the second semiconductor layer are one and the other sides of semiconductor layer 40, which are bisected in area by the line segment connecting the third vertex 503 and the fourth vertex 504.

[0297] Furthermore, as the shape of the upper surface region S1c of the first semiconductor layer changes from the shape of the upper surface region S1 of the first semiconductor layer in Embodiment 1, and the shape of the upper surface region S2c of the second semiconductor layer changes from the shape of the upper surface region S2 of the second semiconductor layer in Embodiment 1, such as Figure 22 As shown, the shape of part 13c is changed from the shape of part 13 in Embodiment 1, and the shape of part 23c is changed from the shape of part 23 in Embodiment 1.

[0298] [3-2. Structure of a Semiconductor Module]

[0299] Hereinafter, the semiconductor module of Embodiment 3 will be described. The semiconductor module of Embodiment 3 is configured by changing a part of the semiconductor module 5 of Embodiment 1. Therefore, here, regarding the semiconductor module of Embodiment 3, the same reference numerals are given to the same constituent elements as those of the semiconductor module 5, and detailed description thereof will be omitted, and the description will be made focusing on the points different from those of the semiconductor module 5.

[0300] Figure 22 is a plan view showing an example of the configuration of the semiconductor module 5c of Embodiment 3.

[0301] As shown in Figure 22 , the semiconductor module 5c is configured by changing the semiconductor device 1 to the semiconductor device 1c and changing the mounting substrate 50 to the mounting substrate 50c from the semiconductor module 5 of Embodiment 1. In Figure 22 , the semiconductor device 1c is shown by a broken line as if it were transparent, so that the configuration of the upper surface of the semiconductor device 1c and the configuration of the surface of the mounting substrate 50c, which cannot actually be visually recognized, can be easily understood.

[0302] The mounting substrate 50c is configured by changing the first metal wiring 51 to the first metal wiring 51c, changing the second metal wiring 52 to the second metal wiring 52c, changing the first via 61 to the first via 61c, changing the second via 62 to the second via 62c, changing the metal wiring 55 to the metal wiring 55c, and changing the metal wiring 56 to the metal wiring 56c from the mounting substrate 50.

[0303] As shown in Figure 22 , in the plan view of the semiconductor layer 40, the semiconductor device 1c is mounted face down on the surface of the mounting substrate 50c in an orientation in which the angle formed by each side of the semiconductor device 1c and the extension direction of the length direction of the mounting substrate 50c is 45 degrees.

[0304] As shown in Figure 22 , the mounting substrate 50c has the first via 61c through which the first conductor (here, the metal wiring 55c to be described later that is electrically connected to the first gate pad 119 or the conductor connected to the metal wiring 55c) that is electrically connected to the first gate pad 119 passes, and the second via 62c through which the second conductor (here, the metal wiring 56c to be described later that is electrically connected to the second gate pad 129 or the conductor connected to the metal wiring 56c) that is electrically connected to the second gate pad 129 passes.

[0305] As shown in Figure 22 , the first metal wiring 51c and the second metal wiring 52c are arranged in the extension direction of the length direction of the mounting substrate 50c (x-axis direction in Figure 22 ) with the gap 54c therebetween.

[0306] The first metal wiring 51c is joined to all of the plurality of first source pads 2111. The first metal wiring 51c is joined to all of the plurality of first source pads 2111, for example, via a conductive joint formed of solder or the like.

[0307] The second metal wiring 52c is joined to all of the plurality of second source pads 2121. The second metal wiring 52c is joined to all of the plurality of second source pads 2121, for example, via a conductive joint formed of solder or the like.

[0308] The metal wiring 55c is joined to the first gate pad 119. The metal wiring 55c is joined to the first gate pad 119, for example, via a conductive joint formed of solder or the like.

[0309] The first via 61c is disposed within the gap 54c. Also, the first gate pad 119 is disposed within the gap 54c. Therefore, the metal wiring 55c is also disposed within the gap 54c.

[0310] The metal wiring 56c is joined to the second gate pad 129. The metal wiring 56c is joined to the second gate pad 129, for example, via a conductive joint formed of solder or the like.

[0311] The second via 62c is disposed within the gap 54c. Also, the second gate pad 129 is disposed within the gap 54c. Therefore, the metal wiring 56c is also disposed within the gap 54c.

[0312] Therefore, as shown in FIG. 1C, the semiconductor device 1c is mounted face down at a position straddling the first metal wiring 51c and the second metal wiring 52c across the gap 54c. Figure 22

[0313] [3-3. Investigation]

[0314] According to the semiconductor device 1c of the above-described structure, as shown in FIG. 1C, the semiconductor device 1c is mounted face down at a position straddling the first metal wiring 51c and the second metal wiring 52c across the gap 54c. Figure 22 ​As illustrated, in the plan view of the semiconductor layer 40, the above surface boundary line 600c, that is, the first imaginary straight line 91, is orthogonal to the direction of the length direction of the mounting substrate 50c, and the semiconductor device 1c is mounted with the surface facing downward on the surface of the mounting substrate, whereby the width of the mounting substrate can be used most effectively, and the metal wiring of the mounting substrate and the source pads of the semiconductor device 1c are joined. Further, in the case where the internal boundary line 400 and the above surface boundary line 600c coincide in the plan view of the semiconductor layer 20, in the semiconductor device 1c, even if it is a square of the same shape and the same area as in Embodiment 1 or Embodiment 2, due to the shape of the above surface boundary line 600c and the position of the gate pad of the semiconductor device 1c, the inside thereof can be used as a conduction path most widely in width. That is, Embodiment 3 is suitable for causing a large current to flow, and can lower the conduction resistance of the conduction path including the substrate wiring and the semiconductor device 1c. Further, in the case where the semiconductor device 1c is used as illustrated in Figure 20 , the current flowing from the first metal wiring 51c can flow from both sides of the semiconductor device 1c, and further, the current flowing to the second metal wiring 52c can flow from both sides of the semiconductor device 1c, and thus is very suitable for causing a large current to flow.

[0315] Therefore, the current path in which a large current flows in the mounting substrate can be designed in a manner to reduce the conduction resistance.

[0316] Thus, according to the semiconductor device 1c having the above structure, a semiconductor device having a feature that a current can efficiently flow in a current path of a mounting substrate for mounting can be provided.

[0317] Further, in Embodiment 3, as an example, it is assumed that one or more first source pads 2111 and one or more second source pads 2121 are arranged as illustrated in Figure 20 , but as long as one or more first source pads 2111 are arranged on the first semiconductor layer upper surface region S1c and one or more second source pads 2121 are arranged on the second semiconductor layer upper surface region S2c, it is not necessary to necessarily arrange them as illustrated in Figure 23A .

[0318] Figure 23B , Figure 23C , Figure 23D , Figure 23E , Figure 23A are plan views of other arrangement examples of one or more first source pads 2111 and one or more second source pads 2121.

[0319] may be arranged as illustrated in Figure 23BAs shown in FIG. 1C, one first source pad 2111f is arranged on the entire surface of the first semiconductor layer upper surface region S1c except for the region of the first gate pad 119, and one second source pad 2121f is arranged on the entire surface of the second semiconductor layer upper surface region S2c except for the region of the second gate pad 129. As shown in FIG. 1D, a plurality of first source pads 2111g to 2111h are arranged on the first semiconductor layer upper surface region S1c in parallel with the upper surface boundary line 600c, and a plurality of second source pads 2121g to 2121h are arranged on the second semiconductor layer upper surface region S2c in parallel with the upper surface boundary line 600c. As shown in FIG. 1E, a plurality of first source pads 2111i to 2111l are arranged on the first semiconductor layer upper surface region S1c in two divisions in parallel with the upper surface boundary line 600c, and a plurality of second source pads 2121i to 2121l are arranged on the second semiconductor layer upper surface region S2c in two divisions in parallel with the upper surface boundary line 600c. As shown in FIG. 1F, two first source pads 2111m and 2111n are arranged on the entire surface of the first semiconductor layer upper surface region S1c in two divisions in such a manner that the opposing sides are orthogonal to the upper surface boundary line 600c, and two second source pads 2121m and 2121n are arranged on the entire surface of the second semiconductor layer upper surface region S2c in two divisions in such a manner that the opposing sides are orthogonal to the upper surface boundary line 600c. As shown in FIG. 1G, a plurality of first source pads 2111o to 2111q are arranged on the first semiconductor layer upper surface region S1c, and a plurality of second source pads 2121o to 2121q are arranged on the second semiconductor layer upper surface region S2c, in such a manner that the semiconductor device 1c becomes the shape in which the first source pad 2111p, the first source pad 2111q, the second source pad 2121q, and the second source pad 2121p overlap and the first gate pad 119, the first source pad 2111o, the second gate pad 129, and the second source pad 2121o overlap every 90 degrees of rotation of the semiconductor device 1c with the center of the semiconductor device 1c as the axis of rotation in the plan view of the semiconductor layer 40. Figure 23C Figure 23D Figure 23E Figure 24

[0320] (Embodiment 4)

[0321] [4-1. Configuration of Semiconductor Device]

[0322] ​​​​The semiconductor device of Embodiment 4 will now be described. The semiconductor device of Embodiment 4 is constructed by modifying a portion of the structure of the semiconductor device 1 of Embodiment 1. Therefore, here, for the semiconductor device of Embodiment 4, the same reference numerals are given to the same constituent elements as those of semiconductor device 1 as have already been described, and detailed descriptions are omitted. The description will focus on the differences from semiconductor device 1.

[0323] Figure 25 This is a plan view showing an example of the structure of the semiconductor device 1d according to Embodiment 4. Figure 24 This is a plan view showing an example of the structure of semiconductor device 1d. It is a plan view in which the structure on the upper surface side of the upper surface of semiconductor device 1d, which is more than the upper surface side of the portion 13d and the portion 23d described later, is virtually removed, and the portion 13d and the portion 23d are virtually exposed.

[0324] like Figure 25 and Figure 24 As shown, the semiconductor device 1d is configured to change the upper surface region S1 of the first semiconductor layer to the upper surface region S1d of the first semiconductor layer, change the upper surface region S2 of the second semiconductor layer to the upper surface region S2d of the second semiconductor layer, change the upper surface boundary line 600 to the upper surface boundary line 600d, change one or more first source pads 111 to one or more first source pads 3111 (here, first source pads 3111a, 3111b, 3111c, 3111d and 3111e), change one or more second source pads 121 to one or more second source pads 3121 (here, second source pads 3121a, 3121b, 3121c, 3121d and 3121e), change part 13 to part 13d, and change part 23 to part 23d.

[0325] like Figure 24 As shown, in the planar view of semiconductor layer 40, N-1 line segments (N is an integer greater than 3; here, N is 4) parallel to the first side 201 and N-2 line segments parallel to the second side 202 are alternately connected to form an upper surface boundary line 600d, which serves as the boundary line between the upper surface region S1d of the first semiconductor layer and the upper surface region S2d of the second semiconductor layer. Furthermore, the upper surface boundary line 600d monotonically changes in the extension direction of the second side 202 and the extension direction of the first side 201.

[0326] The distance between the third vertex 503 and the first intersection point 601d, which is the intersection of the upper surface boundary line 600d and the second side 202, is more than 1 / N of the length of the second side 202 and is longer than the maximum diameter of the first gate pad 119.

[0327] The distance between the 4th vertex 504 and the 2nd intersection point 602d which is the intersection point of the upper surface boundary line 600d and the 4th side 204 is 1 / N or more of the length of the 4th side 204, and is shorter than the maximum diameter of the 2nd gate pad 129.

[0328] Here, as shown in Figure 24 the 1st semiconductor layer upper surface region S1d and the 2nd semiconductor layer upper surface region S2d are one and the other which are adjacent to each other in a plan view of the semiconductor layer 40 and bisect the semiconductor layer 40 in area.

[0329] Further, in the plan view of the semiconductor layer 40, the angle θ2 formed by the 2nd imaginary straight line 92d connecting the 1st intersection point 601d and the 2nd intersection point 602d and the 1st imaginary straight line 91 is 0 degrees or more and less than 45 degrees.

[0330] As shown in Figure 25 the 1st source pad 3111 is a plurality of one or more, and the 1st source pad 3111 is a rectangle or an oblong in a plan view of the semiconductor layer 40, respectively, having a length direction in a direction parallel to the 2nd side 202, and is formed in a bar shape in parallel to the 2nd side 202. Further, the 2nd source pad 3121 is a plurality of one or more, and the 2nd source pad 3121 is a rectangle or an oblong in a plan view of the semiconductor layer 40, respectively, having a length direction in a direction parallel to the 4th side 204, and is formed in a bar shape in parallel to the 4th side 204.

[0331] Further, as the shape of the 1st semiconductor layer upper surface region S1d is changed from the shape of the 1st semiconductor layer upper surface region S1 of Embodiment 1 and the shape of the 2nd semiconductor layer upper surface region S2d is changed from the shape of the 2nd semiconductor layer upper surface region S2 of Embodiment 1, as shown in Figure 26 the shape of the portion 13d is changed from the shape of the portion 13 of Embodiment 1, and the shape of the portion 23d is changed from the shape of the portion 23 of Embodiment 1.

[0332] [4-2. Configuration of semiconductor module]

[0333] Hereinafter, the semiconductor module of Embodiment 4 will be described. The semiconductor module of Embodiment 4 is configured by changing a part of the structure from the semiconductor module 5c of Embodiment 3. Therefore, here, regarding the semiconductor module of Embodiment 4, for the same configuration elements as the semiconductor module 5c, it is considered that the same reference numerals are given to the same configuration elements and detailed description thereof is omitted, and the description is made focusing on the difference from the semiconductor module 5c.

[0334] Figure 26 is a plan view showing an example of the configuration of the semiconductor module 5d of Embodiment 4.

[0335] like Figure 26 As shown, the semiconductor module 5d is constructed by changing the semiconductor device 1c to a semiconductor device 1d and the mounting substrate 50c to a mounting substrate 50d, which is different from the semiconductor module 5c in Embodiment 3. Figure 26 In the diagram, the semiconductor device 1d is represented by dashed lines as if it were transparent, so that the structure of the upper surface of the semiconductor device 1d, which is not actually visible to the naked eye, and the structure of the surface of the mounting substrate 50d can be easily understood.

[0336] The mounting substrate 50d is constructed by changing the first metal wiring 51 to the first metal wiring 51d and the second metal wiring 52 to the second metal wiring 52d from the mounting substrate 50.

[0337] like Figure 26 As shown, the first metal wiring 51d and the second metal wiring 52d are separated by a gap 54d in the length direction of the mounting substrate 50d. Figure 26 Arranged along the x-axis (in the image).

[0338] The first metal wiring 51d is bonded to all of the plurality of first source pads 3111. The first metal wiring 51d is bonded to all of the plurality of first source pads 3111, for example, via a conductive bonding member formed of solder or the like.

[0339] The second metal wiring 52d is bonded to all of the plurality of second source pads 3121. The second metal wiring 52d is bonded to all of the plurality of second source pads 3121, for example, via a conductive bonding member formed of solder or the like.

[0340] Therefore, as Figure 26 As shown, the semiconductor device 1d is mounted face down at a position spanning the first metal wiring 51d and the second metal wiring 52d across a gap 54d.

[0341] [4-3. Investigation]

[0342] According to the above-described structure, the semiconductor device 1d, such as Figure 26As exemplified, the semiconductor device Id is mounted with the face down on the surface of the mounting substrate in the orientation in which the first imaginary straight line 91 is orthogonal to the extension direction of the length direction of the mounting substrate 50d, and thus the metal wiring of the mounting substrate can be joined to the source pad of the semiconductor device Id while efficiently using the width of the mounting substrate. Further, in the case where the internal boundary line 400 and the upper surface boundary line 600d coincide in the plan view of the semiconductor layer 20, the semiconductor device Id has the following feature: even if it is a square of the same shape and the same area as in Embodiments 1 or 2, the inside thereof can be used as a conduction path with the maximum width due to the shape of the upper surface boundary line 600d and the position of the gate pad of the semiconductor device Id. That is, Embodiment 4 is suitable for causing a large current to flow, and can lower the conduction resistance of the conduction path including the substrate wiring and the semiconductor device Id. Further, in the case where the semiconductor device Id is used as exemplified in Figure 27 Thus, the current flowing from the first metal wiring 51d can flow from both sides of the semiconductor device Id, and further, the current flowing to the second metal wiring 52d can flow from both sides of the semiconductor device Id, and thus it is suitable for causing a large current to flow.

[0343] Thus, the current flowing from the first metal wiring 51d can flow from both sides of the semiconductor device Id, and further, the current flowing to the second metal wiring 52d can flow from both sides of the semiconductor device Id, and thus it is suitable for causing a large current to flow.

[0344] Thus, the current flowing from the first metal wiring 51d can flow from both sides of the semiconductor device Id, and further, the current flowing to the second metal wiring 52d can flow from both sides of the semiconductor device Id, and thus it is suitable for causing a large current to flow.

[0345] Next, a preferable range of the angle θ2 is examined. Here, the case where the semiconductor device Id is a square in the plan view of the semiconductor layer 40 and the upper surface boundary line 600d coincides with the internal boundary line 400 is examined.

[0346] Figure 27 is a plan view of the semiconductor device Id.

[0347] In Figure 27 , the first control region 71 is a region of a square in which each side has a length Z in which the first gate pad 119 is arranged, and the second control region 72 is a region of a square in which each side has a length Z in which the second gate pad 129 is arranged.

[0348] In the semiconductor module 5d, in order to reduce the conduction resistance of the semiconductor device Id as much as possible, it is preferable that the length of the opposing line segment 93, which is a line segment of a portion of the second imaginary straight line 92 of the upper surface of the semiconductor device Id other than the first control region 71 and the second control region 72, be longer than the length X of each side of the semiconductor layer 40.

[0349] Figure 27 Line segment 94 in the diagram is an imaginary line segment of length X that connects the boundary of the first control region 71 to the boundary of the second control region 72.

[0350] like Figure 28 As shown, in order for the opposite line segment 93 to be longer than line segment 94, the angle θ2 needs to be larger than the angle θ3 formed by line segment 94 and the first imaginary line 91.

[0351] Figure 28 It is a graph showing the relationship between the length X of each side of the semiconductor device 1d and the ratio Z / X (hereinafter also referred to as "ratio Z / X") of the length Z of each side of the control region (first control region 71 and second control region 72) and the angles θ2 and θ3.

[0352] exist Figure 28 In the diagram, the horizontal axis is Z / X, the first vertical axis is the angle (tilt angle) of angles θ2 and θ3, and the second vertical axis is the angle (difference of tilt angle) of the absolute value of the difference between angles θ2 and θ3, |θ2-θ3|.

[0353] like Figure 28 As shown, if the ratio Z / X increases, the difference between angles θ2 and θ3 decreases, and the absolute values ​​of both angles θ2 and θ3 increase. This weakens the effect of effectively utilizing the width of the mounting substrate to bond the metal wiring of the mounting substrate to the source pad of the semiconductor device 1d.

[0354] The inventors of this invention conducted repeated experiments and research, and as a result, obtained the following understanding: If it is Figure 28 Regions with a Z / X ratio smaller than 0.29 are preferred from the viewpoint of achieving the aforementioned effect. This is in Figure 28 The region where |θ2-θ3| is less than 2 degrees. Originally, the opposing line segment 93 was the upper surface boundary line 600, which inherently has a finite width in the planar view. When a hypothetical line segment is drawn from the center of the semiconductor device 1d to the intersection of the outer perimeter of the semiconductor device 1d and the upper surface boundary line 600, there is a fluctuation of approximately 2 degrees in this hypothetical line segment, corresponding to the finite width of the upper surface boundary line 600. Therefore, if |θ2-θ3| is less than 2 degrees, it is practically difficult to distinguish between the opposing line segment 93 and line segment 94; therefore, |θ2-θ3| is preferably 2 degrees or more. Figure 24 As shown, the regions where the ratio Z / X is less than 0.29 are those where θ2 is between 0 degrees and 22 degrees.

[0355] Therefore, the preferred angle θ2 is between 0 degrees and 22 degrees.

[0356] Furthermore, in embodiment 4, as an example, it is assumed that one or more first source pads 3111 and one or more second source pads 3121 are used as follows: Figure 24The configuration as shown has been described, but as long as one or more first source pads 3111 are arranged on the first semiconductor layer upper surface region S1d and one or more second source pads 3121 are arranged on the second semiconductor layer upper surface region S2d, it is not necessary to arrange them as shown. Figure 29A

[0357] Figure 29B Figure 29A is a plan view illustrating another configuration example of one or more first source pads 3111 and one or more second source pads 3121.

[0358] As shown in Figure 29B , one first source pad 3111f can be arranged on substantially the entire first semiconductor layer upper surface region S1d except for the region of the first gate pad 119, and one second source pad 3121f can be arranged on substantially the entire second semiconductor layer upper surface region S2d except for the region of the second gate pad 129. As shown in Figure 30A , two first source pads 3111g, 3111h can be arranged in two halves on substantially the entire first semiconductor layer upper surface region S1d except for the region of the first gate pad 119, with the opposing edges parallel to each other, and two second source pads 3121g, 3121h can be arranged in two halves on substantially the entire second semiconductor layer upper surface region S2d except for the region of the second gate pad 129, with the opposing edges parallel to each other.

[0359] (Embodiment 5)

[0360] [5-1. Configuration of Semiconductor Module]

[0361] Hereinafter, the configuration of the semiconductor module of Embodiment 5 will be described.

[0362] Figure 30A is a plan view showing an example of the configuration of the semiconductor module 5ea of Embodiment 5.

[0363] As shown in Figure 30A , the semiconductor module 5ea has two semiconductor devices 1 (hereinafter, in order to distinguish between the two, one will be referred to as semiconductor device 1ea and the other will be referred to as semiconductor device 1eb), and a mounting substrate 50ea on which the semiconductor device 1ea and the semiconductor device 1eb are mounted face down in the surface. In Figure 30A , the semiconductor device 1ea and the semiconductor device 1eb are shown by broken lines as if they are transparent, so that the configuration of the upper surface of the semiconductor device 1ea, the configuration of the upper surface of the semiconductor device 1eb, and the configuration of the surface of the mounting substrate 50ea can be easily understood.​​

[0364] like Figure 30A As shown, regarding the semiconductor device 1ea, in the plan view of the mounting substrate 50ea, the position of the first gate pad 119 is located in the extension direction of the length direction of the mounting substrate 50ea. Figure 30A The first gate pad 119 is mounted face down on the surface of the mounting substrate 50ea, facing the first extending direction (x-axis direction). Furthermore, regarding the semiconductor device 1eb, after being moved parallel to the second extending direction (opposite to the first extending direction) in the length direction of the mounting substrate 50ea relative to the semiconductor device 1ea, it is mounted face down on the surface of the mounting substrate 50ea, with the upper surface boundary line 600 of the semiconductor device 1ea parallel to the upper surface boundary line 600 of the semiconductor device 1eb, and the position of the first gate pad 119 located in the first extending direction direction.

[0365] like Figure 30A As shown, the mounting substrate 50ea has a shape that extends in the length direction and has a certain width at least at the location where the semiconductor device 1 is mounted in the plan view of the mounting substrate 50ea. The mounting substrate 50ea has a first through-hole 61ea through which a first conductor electrically connected to the first gate pad 119 of the semiconductor device 1ea (here, the metal wiring 55ea electrically connected to the first gate pad 119 of the semiconductor device 1ea, or the conductor connected to the metal wiring 55ea, described later) passes, and a second through-hole through which a second conductor electrically connected to the second gate pad 129 of the semiconductor device 1ea (here, the metal wiring 56ea electrically connected to the second gate pad 129 of the semiconductor device 1ea, or the conductor connected to the metal wiring 56ea, described later) passes. 62ea, a third via 63ea through which a third conductor electrically connected to the first gate pad 119 of the semiconductor device 1eb (here described later as metal wiring 57ea electrically connected to the first gate pad 119 of the semiconductor device 1eb or a conductor connected to metal wiring 57ea) passes, and a fourth via 64ea through which a fourth conductor electrically connected to the second gate pad 129 of the semiconductor device 1eb (here described later as metal wiring 58ea electrically connected to the second gate pad 129 of the semiconductor device 1eb or a conductor connected to metal wiring 58ea) passes.

[0366] The mounting substrate 50ea also has a first metal wiring 51ea, a second metal wiring 52ea, a third metal wiring 53ea, a metal wiring 55ea, a metal wiring 56ea, a metal wiring 57ea and a metal wiring 58ea on its surface.

[0367] The first metal wiring 51ea and the second metal wiring 52ea are separated by a gap 54ea and extend along the length direction of the mounting substrate 50ea.Figure 30A Arranged along the x-axis (in the image).

[0368] The second metal wiring 52ea and the third metal wiring 53ea are arranged in the extension direction of the mounting substrate 50ea with a gap 54eb between them.

[0369] The first metal wiring 51ea is bonded to all of the first source pads 111 of the semiconductor device 1ea. The first metal wiring 51ea is bonded to all of the first source pads 111 of the semiconductor device 1ea, for example, via a conductive bonding member formed of solder or the like.

[0370] The second metal wiring 52ea is bonded to all of one or more second source pads 121 of semiconductor device 1ea and all of one or more first source pads 111 of semiconductor device 1eb. The second metal wiring 52ea is bonded to all of one or more second source pads 121 of semiconductor device 1ea and all of one or more first source pads 111 of semiconductor device 1eb, for example, via a conductive bonding member formed of solder or the like.

[0371] The third metal wiring 53ea is bonded to all of the second source pads 121 of the semiconductor device 1eb. The third metal wiring 53ea is bonded to all of the second source pads 121 of the semiconductor device 1eb, for example, via a conductive bonding member formed of solder or the like.

[0372] Therefore, as Figure 30B As shown, semiconductor device 1ea is mounted face down at a position spanning the first metal wiring 51ea and the second metal wiring 52ea across a gap 54ea, and semiconductor device 1eb is mounted face down at a position spanning the second metal wiring 52ea and the third metal wiring 53ea across a gap 54eb.

[0373] Metal wiring 55ea is bonded to the first gate pad 119 of semiconductor device 1ea. Metal wiring 55ea is bonded to the first gate pad 119 of semiconductor device 1ea, for example, via a conductive bonding member formed of solder or the like.

[0374] Metal wiring 56ea is bonded to the second gate pad 129 of semiconductor device 1ea. Metal wiring 56ea is bonded to the second gate pad 129 of semiconductor device 1ea, for example, via a conductive bonding member formed of solder or the like.

[0375] Metal wiring 57ea is bonded to the first gate pad 119 of semiconductor device 1eb. Metal wiring 57ea is bonded to the first gate pad 119 of semiconductor device 1eb, for example, via a conductive bonding element formed of solder or the like.

[0376] The metal wiring 58ea is joined with the second gate pad 129 of the semiconductor device 1eb. The metal wiring 58ea is joined with the second gate pad 129 of the semiconductor device 1eb, for example, via a conductive joint formed of solder or the like.

[0377] Figure 30B is a plan view that shows an example of the configuration of the semiconductor module 5eb of Embodiment 5.

[0378] As shown in Figure 30B , the semiconductor module 5eb is configured by changing the two semiconductor devices 1 (the semiconductor device 1ea and the semiconductor device 1eb) of the semiconductor module 5ea to the two semiconductor devices la (hereinafter, in order to distinguish between the two, one will also be referred to as the semiconductor device laea and the other will also be referred to as the semiconductor device laeb), and changing the mounting substrate 50ea to the mounting substrate 50eb. In Figure 30B , the semiconductor device laea and the semiconductor device laeb are shown in broken lines as if they are transparent, so that the configuration of the upper surface of the semiconductor device laea, the configuration of the upper surface of the semiconductor device laeb, and the configuration of the surface of the mounting substrate 50eb can be easily understood.

[0379] As shown in Figure 30B , the semiconductor device laea is mounted face down on the surface of the mounting substrate 50eb in a direction in which the position of the first gate pad 119 is on the first extension direction side in the extension direction of the length direction of the mounting substrate 50eb (the x-axis direction in Figure 30B , and the semiconductor device laeb is mounted face down on the surface of the mounting substrate 50eb in a direction in which the position of the first gate pad 119 is on the first extension direction side, in parallel with the second imaginary straight line 92 of the semiconductor device laea and the second imaginary straight line 92 of the semiconductor device laeb, and in the second extension direction opposite to the first extension direction in the extension direction of the length direction of the mounting substrate 50eb with respect to the semiconductor device laea.

[0380] The mounting substrate 50eb is configured by changing the first metal wiring 51ea to the first metal wiring 51eb, changing the second metal wiring 52ea to the second metal wiring 52eb, and changing the third metal wiring 53ea to the third metal wiring 53eb from the mounting substrate 50ea.

[0381] The first metal wiring 51eb and the second metal wiring 52eb are arranged in the extension direction of the length direction of the mounting substrate 50eb (the x-axis direction in Figure 30B ).

[0382] The second metal wiring 52eb and the third metal wiring 53eb are arranged in the extension direction of the mounting substrate 50eb with a gap 54ed between them.

[0383] The first metal wiring 51eb is fully bonded to one or more first source pads 1111 of the semiconductor device 1aea. The first metal wiring 51eb is fully bonded to one or more first source pads 1111 of the semiconductor device 1aea, for example, via a conductive bonding member formed of solder or the like.

[0384] The second metal wiring 52eb is bonded to all of one or more second source pads 1121 of semiconductor device 1aea and all of one or more first source pads 1111 of semiconductor device 1aeb. The second metal wiring 52eb is bonded to all of one or more second source pads 1121 of semiconductor device 1aea and all of one or more first source pads 1111 of semiconductor device 1aeb, for example, via a conductive bonding member formed of solder or the like.

[0385] The third metal wiring 53eb is bonded to all of the second source pads 1121 of the semiconductor device 1aeb. The third metal wiring 53eb is bonded to all of the second source pads 1121 of the semiconductor device 1aeb, for example, via a conductive bonding member formed of solder or the like.

[0386] Therefore, as Figure 30C As shown, semiconductor device 1aea is mounted face down at a position spanning the first metal wiring 51eb and the second metal wiring 52eb across a gap 54ec, and semiconductor device 1aeb is mounted face down at a position spanning the second metal wiring 52eb and the third metal wiring 53eb across a gap 54ed.

[0387] Figure 30C This is a plan view showing an example of the structure of the semiconductor module 5ec in Embodiment 5.

[0388] like Figure 30C As shown, the semiconductor module 5ec includes two semiconductor devices 1a (hereinafter, for distinction, one will be referred to as semiconductor device 1aec and the other as semiconductor device 1aed), and a mounting substrate 50ec on which semiconductor devices 1aec and 1aed are mounted face down. Figure 30CIn the diagram, semiconductor devices 1aec and 1aed are represented by dashed lines as if they were transparent, so that the structure of the upper surface of semiconductor device 1aec, the upper surface of semiconductor device 1aed, and the surface of mounting substrate 50ec, which are not actually visible to the naked eye, can be easily understood and illustrated.

[0389] like Figure 30C As shown in the plan view of the mounting substrate 50ec, the mounting substrate 50ec has a shape that has a certain width at least at the location where the semiconductor device 1a is mounted and extends in the length direction. The mounting substrate 50ec has a first through-hole 61ec through which a first conductor electrically connected to the first gate pad 119 of the semiconductor device 1aec (here, the metal wiring 55ec electrically connected to the first gate pad 119 of the semiconductor device 1aec, or the conductor connected to the metal wiring 55ec, described later) passes, and a second through-hole 61ec through which a second conductor electrically connected to the second gate pad 129 of the semiconductor device 1aec (here, the metal wiring 56ec electrically connected to the second gate pad 129 of the semiconductor device 1aec, or the conductor connected to the metal wiring 56ec, described later) passes. 2ec, a third via 63ec through which a third conductor electrically connected to the first gate pad 119 of the semiconductor device 1aed (here described later as the metal wiring 57ec electrically connected to the first gate pad 119 of the semiconductor device 1aed, or a conductor connected to the metal wiring 57ec) passes, and a fourth via 64ec through which a fourth conductor electrically connected to the second gate pad 129 of the semiconductor device 1aed (here described later as the metal wiring 58ec electrically connected to the second gate pad 129 of the semiconductor device 1aed, or a conductor connected to the metal wiring 58ec) passes.

[0390] The mounting substrate 50ec also has a first metal wiring 51ec, a second metal wiring 52ec, a third metal wiring 53ec, a metal wiring 55ec, a metal wiring 56ec, a metal wiring 57ec, and a metal wiring 58ec on its surface.

[0391] like Figure 30C As shown, the first metal wiring 51ec and the second metal wiring 52ec are separated by a gap 54ee in the length direction of the mounting substrate 50ec. Figure 30C Arranged along the x-axis (in the image).

[0392] The second metal wiring 52ec and the third metal wiring 53ec are arranged in the extension direction of the mounting substrate 50ec with a gap 54ef between them.

[0393] The first metal wiring 51ec is bonded to all of one or more first source pads 1111 of the semiconductor device 1aec. The first metal wiring 51ec is bonded to all of one or more first source pads 1111 of the semiconductor device 1aec, for example, via a conductive bonding member formed of solder or the like.

[0394] The second metal wiring 52ec is bonded to all of one or more second source pads 1121 of semiconductor device 1aec and all of one or more first source pads 1111 of semiconductor device 1aed. The second metal wiring 52ec is bonded to all of one or more second source pads 1121 of semiconductor device 1aec and all of one or more first source pads 1111 of semiconductor device 1aed, for example, via a conductive bonding member formed of solder or the like.

[0395] The third metal wiring 53ec is bonded to all of one or more second source pads 1121 of the semiconductor device 1aed. The third metal wiring 53ec is bonded to all of one or more second source pads 1121 of the semiconductor device 1aed, for example, via a conductive bonding member formed of solder or the like.

[0396] Therefore, as Figure 30D As shown, semiconductor device 1aec is mounted face down at a position spanning the first metal wiring 51ec and the second metal wiring 52ec across a gap 54ee, and semiconductor device 1aed is mounted face down at a position spanning the second metal wiring 52ec and the third metal wiring 53ec across a gap 54ef.

[0397] Metal wiring 55ec is bonded to the first gate pad 119 of semiconductor device 1aec. Metal wiring 55ec is bonded to the first gate pad 119 of semiconductor device 1aec, for example, via a conductive bonding member formed of solder or the like.

[0398] Metal wiring 56ec is bonded to the second gate pad 129 of semiconductor device 1aec. Metal wiring 56ec is bonded to the second gate pad 129 of semiconductor device 1aec, for example, via a conductive bonding member formed of solder or the like.

[0399] Metal wiring 57ec is bonded to the first gate pad 119 of semiconductor device 1aed. Metal wiring 57ec is bonded to the first gate pad 119 of semiconductor device 1aed, for example, via a conductive bonding member formed of solder or the like.

[0400] Metal wiring 58ec is bonded to the second gate pad 129 of semiconductor device 1aed. Metal wiring 58ec is bonded to the second gate pad 129 of semiconductor device 1aed, for example, via a conductive bonding member formed of solder or the like.

[0401] Figure 30D is a plan view showing an example of the configuration of the semiconductor module 5ed of Embodiment 5.

[0402] As shown in Figure 30D , the semiconductor module 5ed has two semiconductor devices 1c (hereinafter, in order to distinguish between the two, one will be referred to as semiconductor device 1cea and the other will be referred to as semiconductor device 1ceb) and a mounting substrate 50ed on which the semiconductor device 1cea and the semiconductor device 1ceb are mounted facing downward in the surface. In Figure 30D , the semiconductor device 1cea and the semiconductor device 1ceb are shown by broken lines as if they are transparent, so that the configuration of the upper surface of the semiconductor device 1cea, the configuration of the upper surface of the semiconductor device 1ceb and the configuration of the surface of the mounting substrate 50ed can be easily understood.

[0403] As shown in Figure 30D , in the plan view of the mounting substrate 50ed, the mounting substrate 50ed is in a shape extending in the length direction with a certain width at least at the portion where the semiconductor device 1c is mounted. The mounting substrate 50ed has a first through-hole 61ed through which a first conductor (here, a metal wiring 55ed to be described later that is electrically connected to the first gate pad 119 of the semiconductor device 1cea, or a conductor connected to the metal wiring 55ed) that is electrically connected to the first gate pad 119 of the semiconductor device 1cea, a second through-hole 62ed through which a second conductor (here, a metal wiring 56ed to be described later that is electrically connected to the second gate pad 129 of the semiconductor device 1cea, or a conductor connected to the metal wiring 56ed) that is electrically connected to the second gate pad 129 of the semiconductor device 1cea, a third through-hole 63ed through which a third conductor (here, a metal wiring 57ed to be described later that is electrically connected to the first gate pad 119 of the semiconductor device 1ceb, or a conductor connected to the metal wiring 57ed) that is electrically connected to the first gate pad 119 of the semiconductor device 1ceb, and a fourth through-hole 64ed through which a fourth conductor (here, a metal wiring 58ed to be described later that is electrically connected to the second gate pad 129 of the semiconductor device 1ceb, or a conductor connected to the metal wiring 58ed) that is electrically connected to the second gate pad 129 of the semiconductor device 1ceb.

[0404] The mounting substrate 50ed also has a first metal wiring 51ed, a second metal wiring 52ed, a third metal wiring 53ed, a metal wiring 55ed, a metal wiring 56ed, a metal wiring 57ed and a metal wiring 58ed on the surface thereof.

[0405] As shown in Figure 30DAs shown, the first metal wiring 51ed and the second metal wiring 52ed are separated by a gap 54eg in the length direction of the mounting substrate 50ed. Figure 30D Arranged along the x-axis (in the image).

[0406] The second metal wiring 52ed and the third metal wiring 53ed are arranged in the extension direction of the mounting substrate 50ed with a gap 54eh between them.

[0407] The first metal wiring 51ed is bonded to all of the first source pads 2111 of the semiconductor device 1cea. The first metal wiring 51ed is bonded to all of the first source pads 2111 of the semiconductor device 1cea, for example, via a conductive bonding member formed of solder or the like.

[0408] The second metal wiring 52ed is bonded to all of the second source pads 2121 of one or more of the semiconductor device 1cea and all of the first source pads 2111 of one or more of the semiconductor device 1ceb. The second metal wiring 52ed is bonded to all of the second source pads 2121 of one or more of the semiconductor device 1cea and all of the first source pads 2111 of one or more of the semiconductor device 1ceb, for example, via a conductive bonding member formed of solder or the like.

[0409] The third metal wiring 53ed is bonded to all of the second source pads 2121 of the semiconductor device 1ceb. The third metal wiring 53ed is bonded to all of the second source pads 2121 of the semiconductor device 1ceb, for example, via a conductive bonding member formed of solder or the like.

[0410] Therefore, as Figure 30E As shown, semiconductor device 1cea is mounted face down at a position spanning the first metal wiring 51ed and the second metal wiring 52ed across a gap 54eg, and semiconductor device 1ceb is mounted face down at a position spanning the second metal wiring 52ed and the third metal wiring 53ed across a gap 54eh.

[0411] Metal wiring 55ed is bonded to the first gate pad 119 of semiconductor device 1cea. Metal wiring 55ed is bonded to the first gate pad 119 of semiconductor device 1cea, for example, via a conductive bonding member formed of solder or the like.

[0412] The first via 61ed is disposed within the gap 54eg. Furthermore, the first gate pad 119 of the semiconductor device 1cea is also disposed within the gap 54eg. Therefore, the metal wiring 55ed is also disposed within the gap 54eg.

[0413] Metal wiring 56ed is bonded to the second gate pad 129 of semiconductor device 1cea. Metal wiring 56ed is bonded to the second gate pad 129 of semiconductor device 1cea, for example, via a conductive bonding member formed of solder or the like.

[0414] The second via 62ed is disposed within the gap 54eg. Furthermore, the second gate pad 129 of the semiconductor device 1cea is also disposed within the gap 54eg. Therefore, the metal wiring 56ed is also disposed within the gap 54eg.

[0415] Metal wiring 57ed is bonded to the first gate pad 119 of semiconductor device 1ceb. Metal wiring 57ed is bonded to the first gate pad 119 of semiconductor device 1ceb, for example, via a conductive bonding member formed of solder or the like.

[0416] The third via 63ed is disposed within the gap 54eh. Furthermore, the first gate pad 119 of the semiconductor device 1ceb is also disposed within the gap 54eh. Therefore, the metal wiring 57ed is also disposed within the gap 54eh.

[0417] Metal wiring 58ed is bonded to the second gate pad 129 of semiconductor device 1ceb. Metal wiring 58ed is bonded to the second gate pad 129 of semiconductor device 1ceb, for example, via a conductive bonding member formed of solder or the like.

[0418] The fourth via 64ed is disposed within the gap 54eh. Furthermore, the second gate pad 129 of the semiconductor device 1ceb is also disposed within the gap 54eh. Therefore, the metal wiring 58ed is also disposed within the gap 54eh.

[0419] Figure 30E This is a plan view showing an example of the structure of the semiconductor module 5ee in Embodiment 5.

[0420] like Figure 30E As shown, semiconductor module 5ee is constructed by changing two semiconductor devices 1c (semiconductor devices 1cea and 1ceb) from semiconductor module 5ed to two semiconductor devices 1d (hereinafter, for the purpose of distinguishing the two, one will also be referred to as semiconductor device 1dea and the other as semiconductor device 1deb), and changing the mounting substrate 50ed to mounting substrate 50ee. Figure 30E In the diagram, semiconductor devices 1dea and 1deb are represented by dashed lines as if they were transparent, so that the structure of the upper surface of semiconductor device 1dea, the upper surface of semiconductor device 1deb, and the surface of mounting substrate 50ee, which are not actually visible to the naked eye, can be easily understood.

[0421] The mounting substrate 50ee is constructed by changing the first metal wiring 51ed to the first metal wiring 51ee, the second metal wiring 52ed to the second metal wiring 52ee, and the third metal wiring 53ed to the third metal wiring 53ee from the mounting substrate 50ed.

[0422] The first metal wiring 51ee and the second metal wiring 52ee are separated by a gap 54ei in the length direction of the mounting substrate 50ee. Figure 30E Arranged along the x-axis (in the image).

[0423] The second metal wiring 52ee and the third metal wiring 53ee are arranged in the extension direction of the mounting substrate 50ee with a gap 54ej between them.

[0424] The first metal wiring 51ee is bonded to all of the first source pads 3111 of the semiconductor device 1dea. The first metal wiring 51ee is bonded to all of the first source pads 3111 of the semiconductor device 1dea, for example, via a conductive bonding member formed of solder or the like.

[0425] The second metal wiring 52ee is bonded to all of the first source pads 3111 of one or more of the semiconductor device 1dea and one or more of the semiconductor device 1deb. The second metal wiring 52ee is bonded to all of the first source pads 3111 of one or more of the semiconductor device 1dea and one or more of the semiconductor device 1deb via, for example, a conductive bonding member formed of solder or the like.

[0426] The third metal wiring 53ee is bonded to all of the second source pads 3121 of the semiconductor device 1deb. The third metal wiring 53ee is bonded to all of the second source pads 3121 of the semiconductor device 1deb, for example, via a conductive bonding member formed of solder or the like.

[0427] Therefore, as Figure 31A As shown, semiconductor device 1dea is mounted face down at a position spanning the first metal wiring 51ee and the second metal wiring 52ee across a gap 54ei, and semiconductor device 1deb is mounted face down at a position spanning the second metal wiring 52ee and the third metal wiring 53ee across a gap 54ej.

[0428] [5-2. Investigation]

[0429] According to the semiconductor module 5ea to the semiconductor module 5ee described above, the current path of the current flowing from the first metal wiring (the first metal wiring 51ea to the first metal wiring 51ee) to the third metal wiring (the third metal wiring 53ea to the third metal wiring 53ee) via the second metal wiring (the second metal wiring 52ea to the second metal wiring 52ee) can be made linear. Further, the first via hole 61ea, 61ec, 61ed, the second via hole 62ea, 62ec, 62ed, the third via hole 63ea, 63ec, 63ed, the fourth via hole 64ea, 64ec, 64ed can be provided close to the end portion of the mounting substrate, so the current path of the main current flowing in the mounting substrate and the semiconductor device is not hindered.

[0430] Therefore, the current path of the main current flowing in the mounting substrate can be designed in a manner to reduce the on-resistance.

[0431] Thus, according to the semiconductor module 5ea to the semiconductor module 5ee described above, a semiconductor module having a feature that enables efficient current flow in the current path of the mounting substrate can be provided.

[0432] (Embodiment 6)

[0433] [6-1. Configuration of Semiconductor Module]

[0434] Hereinafter, the configuration of the semiconductor module of Embodiment 6 will be described.

[0435] Figure 31A is a plan view showing an example of the configuration of the semiconductor module 5fa of Embodiment 6.

[0436] As shown in Figure 31A , the semiconductor module 5fa includes two semiconductor devices 1 (hereinafter, in order to distinguish between the two, one will be referred to as the semiconductor device 1fa and the other will be referred to as the semiconductor device 1fb), and a mounting substrate 50fa on which the semiconductor device 1fa and the semiconductor device 1fb are mounted facing downward in the surface. In Figure 31A , the semiconductor device 1fa and the semiconductor device 1fb are shown by broken lines as if they are transparent, so that the configuration of the upper surface of the semiconductor device 1fa, the configuration of the upper surface of the semiconductor device 1fb, and the configuration of the surface of the mounting substrate 50fa can be easily understood.

[0437] As shown in Figure 31A , in the plan view of the mounting substrate 50fa, the semiconductor device 1fa is positioned such that the position of the first gate pad 119 is located in the extension direction of the length direction of the mounting substrate 50fa (the direction of the arrow A1 in Figure 31AThe semiconductor device 1fb is mounted face down on the surface of the mounting substrate 50fa, with the first extension direction side facing downwards (in the x-axis direction). Furthermore, the semiconductor device 1fb is positioned after being moved parallel to the semiconductor device 1fa in a direction orthogonal to the extension direction of the mounting substrate 50fa, such that the upper surface boundary line 600 of the semiconductor device 1fa is perpendicular to the upper surface boundary line 600 of the semiconductor device 1fb, and the first gate pad 119 is mounted face down on the surface of the mounting substrate 50fa with the first extension direction side facing downwards.

[0438] like Figure 31A As shown in the plan view of the mounting substrate 50fa, the mounting substrate 50fa is a shape that has a certain width at least at the part where the semiconductor device 1 is mounted and extends in the length direction. Mounting substrate 50fa includes a first via 61fa through which a first conductor electrically connected to the first gate pad 119 of semiconductor device 1fa (here described later as metal wiring 55fa electrically connected to the first gate pad 119 of semiconductor device 1fa, or a conductor connected to metal wiring 55fa) passes; a second via 62fa through which a second conductor electrically connected to the second gate pad 129 of semiconductor device 1fa and the second gate pad 129 of semiconductor device 1fb (here described later as metal wiring 56fa electrically connected to the second gate pad 129 of semiconductor device 1fa and the second gate pad 129 of semiconductor device 1fb, or a conductor connected to metal wiring 56fa) passes; and a third via 63fa through which a third conductor electrically connected to the first gate pad 119 of semiconductor device 1fb (here described later as metal wiring 57fa electrically connected to the first gate pad 119 of semiconductor device 1fb, or a conductor connected to metal wiring 57fa) passes.

[0439] The mounting substrate 50fa also has a first metal wiring 51fa, a second metal wiring 52fa, a metal wiring 55fa, a metal wiring 56fa and a metal wiring 57fa on its surface.

[0440] The first metal wiring 51fa and the second metal wiring 52fa are separated by a gap 54fa and extend along the length of the mounting substrate 50fa. Figure 31A Arranged along the x-axis (in the image).

[0441] The first metal wiring 51fa is bonded to all of the first source pads 111 of one or more of the semiconductor device 1fa and all of the first source pads 111 of the semiconductor device 1fb. The first metal wiring 51fa is bonded to all of the first source pads 111 of the semiconductor device 1fa and all of the first source pads 111 of the semiconductor device 1fb, for example, via a conductive bonding member formed of solder or the like.

[0442] The second metal wiring 52fa is bonded to all of the second source pads 121 of one or more of the semiconductor device 1fa and all of the second source pads 121 of the semiconductor device 1fb. The second metal wiring 52fa is bonded to all of the second source pads 121 of the semiconductor device 1fa and all of the second source pads 121 of the semiconductor device 1fb, for example, via a conductive bonding member formed of solder or the like.

[0443] Therefore, as Figure 31B As shown, semiconductor devices 1fa and 1fb are mounted face down at a position that spans the first metal wiring 51fa and the second metal wiring 52fa across a gap 54fa.

[0444] Metal wiring 55fa is bonded to the first gate pad 119 of semiconductor device 1fa. Metal wiring 55fa is bonded to the first gate pad 119 of semiconductor device 1fa, for example, via a conductive bonding member formed of solder or the like.

[0445] Metal wiring 56fa is bonded to the second gate pad 129 of semiconductor device 1fa and the second gate pad 129 of semiconductor device 1fb. Metal wiring 56fa is bonded to the second gate pad 129 of semiconductor device 1fa and the second gate pad 129 of semiconductor device 1fb, for example, via a conductive bonding member formed of solder or the like.

[0446] Metal wiring 57fa is bonded to the first gate pad 119 of semiconductor device 1fb. Metal wiring 57fa is bonded to the first gate pad 119 of semiconductor device 1fb, for example, via a conductive bonding member formed of solder or the like.

[0447] Figure 31B This is a plan view showing an example of the structure of the semiconductor module 5fb in Embodiment 6.

[0448] like Figure 31B As shown, the semiconductor module 5fb includes two semiconductor devices 1 (hereinafter, for distinction, one will be referred to as semiconductor device 1fc and the other as semiconductor device 1fd), and a mounting substrate 50fb on which semiconductor devices 1fc and 1fd are mounted face down. Figure 31B In the diagram, semiconductor devices 1fc and 1fd are represented by dashed lines as if transparent, so as to make it easy to understand the structure of the upper surface of semiconductor device 1fc, the upper surface of semiconductor device 1fd, and the surface of mounting substrate 50fb, which are not actually visible to the naked eye.

[0449] like Figure 31BAs shown in the plan view of the mounting substrate 50fb, the semiconductor device 1fc is positioned such that the location of the first gate pad 119 is in the extension direction of the mounting substrate 50fb along its length. Figure 31B The first gate pad 119 is mounted face down on the surface of the mounting substrate 50fb, facing the first extending direction side (x-axis direction). Furthermore, the semiconductor device 1fd, after being moved approximately parallel to the extending direction of the upper surface boundary line 600 of the semiconductor device 1fc relative to the semiconductor device 1fc, is mounted face down on the surface of the mounting substrate 50fb, such that the upper surface boundary line 600 of the semiconductor device 1fc and the upper surface boundary line 600 of the semiconductor device 1fd are on the same straight line, and the position of the first gate pad 119 is located facing the first extending direction side.

[0450] like Figure 31B As shown in the plan view of the mounting substrate 50fb, the mounting substrate 50fb has a shape that has a certain width at least at the location where the semiconductor device 1 is mounted and extends in the length direction. The mounting substrate 50fb includes a first via 61fb through which a first conductor electrically connected to the first gate pad 119 of the semiconductor device 1fc (here, the metal wiring 55fb electrically connected to the first gate pad 119 of the semiconductor device 1fc, or a conductor connected to the metal wiring 55fb, described later) passes, and a second via 61fb through which a second conductor electrically connected to the second gate pad 129 of the semiconductor device 1fc (here, the metal wiring 56fb electrically connected to the second gate pad 129 of the semiconductor device 1fc, or a conductor connected to the metal wiring 56fb, described later) passes. 2fb, a third via 63fb through which a third conductor electrically connected to the first gate pad 119 of the semiconductor device 1fd (here described later as metal wiring 57fb electrically connected to the first gate pad 119 of the semiconductor device 1fd, or a conductor connected to metal wiring 57fb) passes, and a fourth via 64fb through which a fourth conductor electrically connected to the second gate pad 129 of the semiconductor device 1fd (here described later as metal wiring 58fb electrically connected to the second gate pad 129 of the semiconductor device 1fd, or a conductor connected to metal wiring 58fb) passes.

[0451] The mounting substrate 50fb also has a first metal wiring 51fb, a second metal wiring 52fb, a metal wiring 55fb, a metal wiring 56fb, a metal wiring 57fb and a metal wiring 58fb on its surface.

[0452] The first metal wiring 51fb and the second metal wiring 52fb are separated by a gap 54fb in the length direction of the mounting substrate 50fb. Figure 31B Arranged along the x-axis (in the image).

[0453] The first metal wiring 51fb is joined to all of the one or more first source pads 111 of the semiconductor device 1fc and all of the one or more first source pads 111 of the semiconductor device 1fd. The first metal wiring 51fb is joined to all of the one or more first source pads 111 of the semiconductor device 1fc and all of the one or more first source pads 111 of the semiconductor device 1fd, for example, via a conductive joining member formed of solder or the like.

[0454] The second metal wiring 52fb is joined to all of the one or more second source pads 121 of the semiconductor device 1fc and all of the one or more second source pads 121 of the semiconductor device 1fd. The second metal wiring 52fb is joined to all of the one or more second source pads 121 of the semiconductor device 1fc and all of the one or more second source pads 121 of the semiconductor device 1fd, for example, via a conductive joining member formed of solder or the like.

[0455] Therefore, as shown in FIG. 6, the semiconductor device 1fc and the semiconductor device 1fd are mounted face down at positions straddling the first metal wiring 51fb and the second metal wiring 52fb across the gap 54fb. Figure 31C

[0456] The metal wiring 55fb is joined to the first gate pad 119 of the semiconductor device 1fc. The metal wiring 55fb is joined to the first gate pad 119 of the semiconductor device 1fc, for example, via a conductive joining member formed of solder or the like.

[0457] The metal wiring 56fb is connected to the second gate pad 129 of the semiconductor device 1fc. The metal wiring 56fb is joined to the second gate pad 129 of the semiconductor device 1fc, for example, via a conductive joining member formed of solder or the like.

[0458] The metal wiring 57fb is joined to the first gate pad 119 of the semiconductor device 1fd. The metal wiring 57fb is joined to the first gate pad 119 of the semiconductor device 1fd, for example, via a conductive joining member formed of solder or the like.

[0459] The metal wiring 58fb is connected to the second gate pad 129 of the semiconductor device 1fd. The metal wiring 58fb is joined to the second gate pad 129 of the semiconductor device 1fd, for example, via a conductive joining member formed of solder or the like.

[0460] Figure 31C is a plan view showing an example of the configuration of the semiconductor module 5fc of Embodiment 6.

[0461] As shown in FIG. 6, the semiconductor device 1fc and the semiconductor device 1fd are mounted face down at positions straddling the first metal wiring 51fb and the second metal wiring 52fb across the gap 54fb. Figure 31C ​As shown, semiconductor module 5fc is constructed by changing two semiconductor devices 1 (semiconductor device 1fa and semiconductor device 1fb) from semiconductor module 5fa to two semiconductor devices 1a (hereinafter, for the purpose of distinguishing the two, one will also be referred to as semiconductor device 1afa and the other as semiconductor device 1afb), and changing the mounting substrate 50fa to mounting substrate 50fc. Figure 31C In the diagram, semiconductor devices 1afa and 1afb are represented by dashed lines as if they were transparent, so that the structure of the upper surface of semiconductor device 1afa, the upper surface of semiconductor device 1afb, and the surface of mounting substrate 50fc, which are not actually visible to the naked eye, can be easily understood and illustrated.

[0462] like Figure 31C As shown in the plan view of the mounting substrate 50fc, the semiconductor device 1afa is positioned such that the location of the first gate pad 119 is in the extension direction of the length direction of the mounting substrate 50fc. Figure 30B The first gate pad 119 is mounted face down on the surface of the mounting substrate 50fc, facing the first extending direction (x-axis direction). Furthermore, the semiconductor device 1afb is moved parallel to the extending direction orthogonal to the length direction of the mounting substrate 50fc relative to the semiconductor device 1afa, such that the second imaginary line 92 of the semiconductor device 1afa is perpendicular to the second imaginary line 92 of the semiconductor device 1afb, and the first gate pad 119 is mounted face down on the surface of the mounting substrate 50fc, facing the first extending direction.

[0463] The mounting substrate 50fc is constructed by changing the first metal wiring 51fa to the first metal wiring 51fc and the second metal wiring 52fa to the second metal wiring 52fc from the mounting substrate 50fa.

[0464] The first metal wiring 51fc and the second metal wiring 52fc are separated by a gap 54fc in the length direction of the mounting substrate 50fc. ​ Arranged along the x-axis (in the image).

[0465] The first metal wiring 51fc is bonded to all of the first source pads 1111 of one or more of the semiconductor device 1afa and all of the first source pads 1111 of the semiconductor device 1afb. The first metal wiring 51fc is bonded to all of the first source pads 1111 of the semiconductor device 1afa and all of the first source pads 1111 of the semiconductor device 1afb, for example, via a conductive bonding member formed of solder or the like.

[0466] The second metal wiring 52fc is joined to all of the one or more second source pads 1121 of the semiconductor device 1afa and all of the one or more second source pads 1121 of the semiconductor device 1afb. The second metal wiring 52fc is joined to all of the one or more second source pads 1121 of the semiconductor device 1afa and all of the one or more second source pads 1121 of the semiconductor device 1afb, for example, via a conductive joint formed of solder or the like.

[0467] Therefore, as FIG. 31C shown, the semiconductor device 1afa and the semiconductor device 1afb are mounted face down at positions straddling the first metal wiring 51fc and the second metal wiring 52fc across the gap 54fc.

[0468] FIG. 31D is a plan view showing an example of the configuration of the semiconductor module 5fd of Embodiment 6.

[0469] As FIG. 31D shown, the semiconductor module 5fd includes two semiconductor devices 1a (hereinafter, in order to distinguish between the two, one will be referred to as the semiconductor device 1afc and the other will be referred to as the semiconductor device 1afd), and a mounting substrate 50fd on which the semiconductor device 1afc and the semiconductor device 1afd are mounted face down in the surface. In FIG. 31D , the semiconductor device 1afc and the semiconductor device 1afd are shown in broken lines as if they are transparent, so that the configuration of the upper surface of the semiconductor device 1afc, the configuration of the upper surface of the semiconductor device 1afd, and the configuration of the surface of the mounting substrate 50fd can be easily understood.

[0470] As FIG. 31D shown, in the plan view of the mounting substrate 50fd, the semiconductor device 1afc is mounted face down on the surface of the mounting substrate 50fd in an orientation in which the position of the first gate pad 119 is on the first extension direction side in the extension direction (the x-axis direction in FIG. 31D ) of the length direction of the mounting substrate 50fd. Also, the semiconductor device 1afd is mounted face down on the surface of the mounting substrate 50fd in an orientation in which the position of the first gate pad 119 is on the first extension direction side after moving approximately in parallel to the extension direction of the second imaginary straight line 92 of the semiconductor device 1afc with respect to the semiconductor device 1afc, and in which the second imaginary straight line 92 of the semiconductor device 1afc and the second imaginary straight line 92 of the semiconductor device 1afd are in parallel.

[0471] As FIG. 31DAs shown, in a plan view of the mounting substrate 50fd, the mounting substrate 50fd is elongated in a length direction (x-axis direction in FIG. 1) with a certain width at least at a portion where the semiconductor device laa is mounted. The mounting substrate 50fd has a first via 61fd through which a first conductor (here, a metal wiring 55fd to be described later that is electrically connected to the first gate pad 119 of the semiconductor device laf, or a conductor connected to the metal wiring 55fd) that is electrically connected to the first gate pad 119 of the semiconductor device laf, a second via 62fd through which a second conductor (here, a metal wiring 56fd to be described later that is electrically connected to the second gate pad 129 of the semiconductor device laf, or a conductor connected to the metal wiring 56fd) that is electrically connected to the second gate pad 129 of the semiconductor device laf, a third via 63fd through which a third conductor (here, a metal wiring 57fd to be described later that is electrically connected to the first gate pad 119 of the semiconductor device lafd, or a conductor connected to the metal wiring 57fd) that is electrically connected to the first gate pad 119 of the semiconductor device lafd, and a fourth via 64fd through which a fourth conductor (here, a metal wiring 58fd to be described later that is electrically connected to the second gate pad 129 of the semiconductor device lafd, or a conductor connected to the metal wiring 58fd) that is electrically connected to the second gate pad 129 of the semiconductor device lafd.

[0472] The mounting substrate 50fd also has the first metal wiring 51fd, the second metal wiring 52fd, the metal wiring 55fd, the metal wiring 56fd, the metal wiring 57fd, and the metal wiring 58fd on a surface thereof.

[0473] The first metal wiring 51fd and the second metal wiring 52fd are arranged in the length direction of the mounting substrate 50fd (x-axis direction in FIG. 1) with the gap 54fd therebetween. FIG. 31D

[0474] The first metal wiring 51fd is joined to all of the one or more first source pads 1111 of the semiconductor device laf and all of the one or more first source pads 1111 of the semiconductor device lafd. The first metal wiring 51fd is joined to all of the one or more first source pads 1111 of the semiconductor device laf and all of the one or more first source pads 1111 of the semiconductor device lafd, for example, via a conductive joining member formed of solder or the like.

[0475] ​The second metal wiring 52fd is bonded to all of the first or more second source pads 1121 of the semiconductor device 1afc and all of the first or more second source pads 1121 of the semiconductor device 1afd. The second metal wiring 52fd is bonded to all of the first or more second source pads 1121 of the semiconductor device 1afc and all of the first or more second source pads 1121 of the semiconductor device 1afd, for example, via a conductive bonding member formed of solder or the like.

[0476] Therefore, as FIG. 31D As shown, semiconductor device 1afc and semiconductor device 1afd are mounted face down at a position spanning the first metal wiring 51fd and the second metal wiring 52fd across a gap 54fd.

[0477] Metal wiring 55fd is bonded to the first gate pad 119 of semiconductor device 1afc. Metal wiring 55fd is bonded to the first gate pad 119 of semiconductor device 1afc, for example, via a conductive bonding member formed of solder or the like.

[0478] Metal wiring 56fd is connected to the second gate pad 129 of semiconductor device 1afc. Metal wiring 56fd is bonded to the second gate pad 129 of semiconductor device 1afc, for example, via a conductive bonding member formed of solder or the like.

[0479] Metal wiring 57fd is bonded to the first gate pad 119 of semiconductor device 1afd. Metal wiring 57fd is bonded to the first gate pad 119 of semiconductor device 1afd, for example, via a conductive bonding member formed of solder or the like.

[0480] Metal wiring 58fd is connected to the second gate pad 129 of semiconductor device 1afd. Metal wiring 58fd is bonded to the second gate pad 129 of semiconductor device 1afd, for example, via a conductive bonding member formed of solder or the like.

[0481] FIG. 31E This is a plan view showing an example of the structure of the semiconductor module 5fe in Embodiment 6.

[0482] like FIG. 31E As shown, the semiconductor module 5fe includes two semiconductor devices 1c (hereinafter, for distinction, one will be referred to as semiconductor device 1cfa and the other as semiconductor device 1cfb), and a mounting substrate 50fe on which semiconductor devices 1cfa and 1cfb are mounted face down. FIG. 31EIn the diagram, semiconductor devices 1cfa and 1cfb are represented by dashed lines as if transparent, so as to make it easy to understand the structure of the upper surface of semiconductor device 1cfa, the upper surface of semiconductor device 1cfb, and the surface of mounting substrate 50fe, which are not actually visible to the naked eye.

[0483] like FIG. 31E As shown in the plan view of the mounting substrate 50fe, the mounting substrate 50fe has a shape that has a certain width at least at the location where the semiconductor device 1c is mounted and extends in the length direction. The mounting substrate 50fe has a first through-hole 61fe through which a first conductor electrically connected to the first gate pad 119 of the semiconductor device 1cfa (here, the metal wiring 55fe electrically connected to the first gate pad 119 of the semiconductor device 1cfa, or the conductor connected to the metal wiring 55fe, described later) passes, and a second through-hole 61fe through which a second conductor electrically connected to the second gate pad 129 of the semiconductor device 1cfa (here, the metal wiring 56fe electrically connected to the second gate pad 129 of the semiconductor device 1cfa, or the conductor connected to the metal wiring 56fe, described later) passes. 2fe, a third via 63fe through which a third conductor electrically connected to the first gate pad 119 of the semiconductor device 1cfb (here described later as metal wiring 57fe electrically connected to the first gate pad 119 of the semiconductor device 1cfb, or a conductor connected to metal wiring 57fe) passes, and a fourth via 64fe through which a fourth conductor electrically connected to the second gate pad 129 of the semiconductor device 1cfb (here described later as metal wiring 58fe electrically connected to the second gate pad 129 of the semiconductor device 1cfb, or a conductor connected to metal wiring 58fe) passes.

[0484] The mounting substrate 50fe also has a first metal wiring 51fe, a second metal wiring 52fe, a metal wiring 55fe, a metal wiring 56fe, a metal wiring 57fe and a metal wiring 58fe on its surface.

[0485] The first metal wiring 51fe and the second metal wiring 52fe are separated by a gap 54fe in the length direction of the mounting substrate 50fe. FIG. 31E Arranged along the x-axis (in the image).

[0486] The first metal wiring 51fe is bonded to all of the first source pads 2111 of one or more of the semiconductor device 1cfa and all of the first source pads 2111 of one or more of the semiconductor device 1cfb. The first metal wiring 51fe is bonded to all of the first source pads 2111 of one or more of the semiconductor device 1cfa and all of the first source pads 2111 of one or more of the semiconductor device 1cfb, for example, via a conductive bonding member formed of solder or the like.

[0487] The second metal wiring 52fe is bonded to all of the second source pads 2121 of one or more of the semiconductor device 1cfa and all of the second source pads 2121 of the semiconductor device 1cfb. The second metal wiring 52fe is bonded to all of the second source pads 2121 of one or more of the semiconductor device 1cfa and all of the second source pads 2121 of the semiconductor device 1cfb, for example, via a conductive bonding member formed of solder or the like.

[0488] Therefore, as FIG. 31E As shown, semiconductor devices 1cfa and 1cfb are mounted face down at a position spanning the first metal wiring 51fe and the second metal wiring 52fe across a gap 54fe.

[0489] Metal wiring 55fe is bonded to the first gate pad 119 of semiconductor device 1cfa. Metal wiring 55fe is bonded to the first gate pad 119 of semiconductor device 1cfa, for example, via a conductive bonding member formed of solder or the like.

[0490] The first via 61fe is disposed within the gap 54fe. Furthermore, the first gate pad 119 of the semiconductor device 1cfa is also disposed within the gap 54fe. Therefore, the metal wiring 55fe is also disposed within the gap 54fe.

[0491] Metal wiring 56fe is bonded to the second gate pad 129 of semiconductor device 1cfa. Metal wiring 56fe is bonded to the second gate pad 129 of semiconductor device 1cfa, for example, via a conductive bonding member formed of solder or the like.

[0492] The second via 62fe is disposed within the gap 54fe. Furthermore, the second gate pad 129 of the semiconductor device 1cfa is also disposed within the gap 54fe. Therefore, the metal wiring 56fe is also disposed within the gap 54fe.

[0493] Metal wiring 57fe is bonded to the first gate pad 119 of semiconductor device 1cfb. Metal wiring 57fe is bonded to the first gate pad 119 of semiconductor device 1cfb, for example, via a conductive bonding member formed of solder or the like.

[0494] The third via 63fe is disposed within the gap 54fe. Furthermore, the first gate pad 119 of the semiconductor device 1cfb is also disposed within the gap 54fe. Therefore, the metal wiring 57fe is also disposed within the gap 54fe.

[0495] The metal wiring 58fe is joined with the second gate pad 129 of the semiconductor device 1cfb. The metal wiring 58fe is joined with the second gate pad 129 of the semiconductor device 1cfb, for example, via a conductive joint formed of solder or the like.

[0496] The fourth via hole 64fe is arranged in the gap 54fe. Further, the second gate pad 129 of the semiconductor device 1cfb is also arranged in the gap 54fe. Therefore, the metal wiring 58fe is also arranged in the gap 54fe.

[0497] FIG. 31F is a plan view that shows an example of the configuration of the semiconductor module 5ff of Embodiment 6.

[0498] As shown in FIG. 31F , the semiconductor module 5ff is configured by changing the two semiconductor devices 1c (semiconductor device 1cfa and semiconductor device 1cfb) of the semiconductor module 5fe to two semiconductor devices 1d (hereinafter, in order to distinguish between the two, one will be referred to as semiconductor device 1dfa and the other will be referred to as semiconductor device 1dfb), and changing the mounting substrate 50fe to the mounting substrate 50ff. In FIG. 31F , the semiconductor device 1dfa and the semiconductor device 1dfb are shown in dotted lines as if they are transparent, so that the configuration of the upper surface of the semiconductor device 1dfa, the configuration of the upper surface of the semiconductor device 1dfb, and the configuration of the surface of the mounting substrate 50ff can be easily understood.

[0499] The mounting substrate 50ff is configured by changing the first metal wiring 51fe to the first metal wiring 51ff and changing the second metal wiring 52fe to the second metal wiring 52ff from the mounting substrate 50fe.

[0500] The first metal wiring 51ff and the second metal wiring 52ff are arranged in the extension direction of the length direction of the mounting substrate 50ff (x-axis direction in FIG. 31F ).

[0501] The first metal wiring 51ff is joined with all of the one or more first source pads 3111 of the semiconductor device 1dfa and all of the one or more first source pads 3111 of the semiconductor device 1dfb. The first metal wiring 51ff is joined with all of the one or more first source pads 3111 of the semiconductor device 1dfa and all of the one or more first source pads 3111 of the semiconductor device 1dfb, for example, via a conductive joint formed of solder or the like.

[0502] The second metal wiring 52ff is joined to all of the one or more second source pads 3121 of the semiconductor device 1dfa and all of the one or more second source pads 3121 of the semiconductor device 1dfb. The second metal wiring 52ff is joined to all of the one or more second source pads 3121 of the semiconductor device 1dfa and all of the one or more second source pads 3121 of the semiconductor device 1dfb, for example, via a conductive joining member formed of solder or the like.

[0503] Therefore, as shown in FIG. 1 1A, the semiconductor device 1dfa and the semiconductor device 1dfb are mounted face down at positions straddling the first metal wiring 51 ff and the second metal wiring 52ff across the gap 54ff. FIG. 31F

[0504] The metal wiring 55fe is joined to the first gate pad 119 of the semiconductor device 1dfa. The metal wiring 55fe is joined to the first gate pad 119 of the semiconductor device 1dfa, for example, via a conductive joining member formed of solder or the like.

[0505] The metal wiring 56fe is joined to the second gate pad 129 of the semiconductor device 1dfa. The metal wiring 56fe is joined to the second gate pad 129 of the semiconductor device 1dfa, for example, via a conductive joining member formed of solder or the like.

[0506] The metal wiring 57fe is joined to the first gate pad 119 of the semiconductor device 1dfb. The metal wiring 57fe is joined to the first gate pad 119 of the semiconductor device 1dfb, for example, via a conductive joining member formed of solder or the like.

[0507] The metal wiring 58fe is joined to the second gate pad 129 of the semiconductor device 1dfb. The metal wiring 58fe is joined to the second gate pad 129 of the semiconductor device 1dfb, for example, via a conductive joining member formed of solder or the like.

[0508] [6-2. Investigation]

[0509] According to the semiconductor module 5fa of the above structure, the through hole for passing a conductor for applying a voltage to the second gate pad 129 of the semiconductor device 1fa and the through hole for passing a conductor for applying a voltage to the second gate pad 129 of the semiconductor device 1fb can be implemented with only one second through hole 62fa.

[0510] Therefore, the current path through which the main current flows in the mounting substrate 50fa can be designed in a manner that reduces on-resistance.

[0511] ​Similarly, according to the semiconductor module 5fc of the above structure, the through hole through which the conductor for applying a voltage to the second gate pad 129 of the semiconductor device 1afa passes and the through hole through which the conductor for applying a voltage to the second gate pad 129 of the semiconductor device 1afb passes can be realized with only one second through hole 62fa. Further, since the common through holes can be arranged near the end portion of the mounting substrate, the current path of the main current flowing in the mounting substrate and the semiconductor devices is not hindered.

[0512] Therefore, the current path of the main current flowing in the mounting substrate 50fc can be designed in a manner to reduce the on-resistance.

[0513] Thus, according to the semiconductor module 5fa and the semiconductor module 5fc of the above structure, a semiconductor module having a feature that the current can efficiently flow in the current path of the mounting substrate can be provided.

[0514] The semiconductor module 5fa to the semiconductor module 5fd of the above structure can arrange the through holes at positions that do not hinder the main current flowing in the mounting substrate and the semiconductor devices. Further, in the semiconductor module 5fa and the semiconductor module 5fc, a part of the through holes can be common. Therefore, a design to reduce the on-resistance of the mounting substrate can be realized.

[0515] Similarly, the semiconductor module 5fe and the semiconductor module 5ff of the above structure can arrange the through holes at positions that do not hinder the main current flowing in the mounting substrate and the semiconductor devices on the gap. Therefore, a design to reduce the on-resistance of the mounting substrate can be realized.

[0516] (Embodiment 7)

[0517] [7-1. Configuration of Semiconductor Module]

[0518] Hereinafter, the configuration of the semiconductor module of Embodiment 7 will be described.

[0519] FIG. 32A is a plan view showing an example of the configuration of the semiconductor module 5ga of Embodiment 7.

[0520] As shown in FIG. 32A , the semiconductor module 5ga has two semiconductor devices 1 (hereinafter, in order to distinguish between the two, one will be referred to as a semiconductor device 1ga and the other will be referred to as a semiconductor device 1gb), and a mounting substrate 50ga on which the semiconductor device 1ga is mounted face down in a surface (hereinafter, also referred to as a "first surface") and the semiconductor device 1gb is mounted face down in a back surface (hereinafter, also referred to as a "second surface"). In FIG. 32A , in FIG. 32A , the semiconductor module 5ga has two semiconductor devices 1 (hereinafter, in order to distinguish between the two, one will be referred to as a semiconductor device 1ga and the other will be referred to as a semiconductor device 1gb), and a mounting substrate 50ga on which the semiconductor device 1ga is mounted face down in a surface (hereinafter, also referred to as a "first surface") and the semiconductor device 1gb is mounted face down in a back surface (hereinafter, also referred to as a "second surface"). Inpart of (a), the semiconductor device 1ga is indicated by a broken line as if transparent, to make it easy to understand the configuration of the upper surface of the semiconductor device 1ga and the configuration of the first surface of the mounting substrate 50ga, which are virtually invisible. Further, in the part of (b), the constituent elements other than the semiconductor device 1gb are indicated by a broken line as if transparent, and the semiconductor device 1gb is indicated by a solid line, to make it easy to understand the configuration of the upper surface of the semiconductor device 1gb. FIG. 32A

[0521] As shown in (a) and (b), the semiconductor device 1ga is mounted on the first surface of the mounting substrate 50ga, and the semiconductor device 1gb is mounted on the second surface of the mounting substrate 50ga. FIG. 32A In the plan view of the mounting substrate 50ga, the semiconductor device 1ga is mounted with the first gate pad 119 positioned on the first extension direction side in the extension direction (x-axis direction in (a)) of the mounting substrate 50ga. Further, in the plan view of the mounting substrate 50ga, the semiconductor device 1gb is mounted with the semiconductor device 1ga and the first gate pad 119 of the semiconductor device 1ga overlapping the semiconductor device 1gb and the first gate pad 119 of the semiconductor device 1gb, respectively. FIG. 32A

[0522] Therefore, in the plan view of the mounting substrate 50ga, the first semiconductor layer upper surface region S1 of the semiconductor device 1ga and the first semiconductor layer upper surface region S1 of the semiconductor device 1gb overlap by 100%, and the second semiconductor layer upper surface region S2 of the semiconductor device 1ga and the second semiconductor layer upper surface region S2 of the semiconductor device 1gb overlap by 100%.

[0523] As shown in (a) and (b), the semiconductor device 1ga is mounted on the first surface of the mounting substrate 50ga, and the semiconductor device 1gb is mounted on the second surface of the mounting substrate 50ga. FIG. 32A ​​As shown in a plan view of the mounting substrate 50ga, the mounting substrate 50ga is elongated in a length direction with a certain width at least at a portion where the semiconductor device 1 is mounted. The mounting substrate 50ga has a first via 61ga through which a first conductor (here, a metal wiring 55ga to be described later that is electrically connected to the first gate pad 119 of the semiconductor device 1ga or a conductor connected to the metal wiring 55ga, and a metal wiring 55gb that is electrically connected to the first gate pad 119 of the semiconductor device 1gb or a conductor connected to the metal wiring 55gb) that electrically connects the first gate pad 119 of the semiconductor device 1ga and the first gate pad 119 of the semiconductor device 1gb, and a second via 62ga through which a second conductor (here, a metal wiring 56ga that is electrically connected to the second gate pad 129 of the semiconductor device 1ga or a conductor connected to the metal wiring 56ga, and a metal wiring 56gb that is electrically connected to the second gate pad 129 of the semiconductor device 1gb or a conductor connected to the metal wiring 56gb) that electrically connects the second gate pad 129 of the semiconductor device 1ga and the second gate pad 129 of the semiconductor device 1gb.

[0524] The mounting substrate 50ga has a first metal wiring 51ga, a second metal wiring 52ga, the metal wiring 55ga, and the metal wiring 56ga on the first surface thereof.

[0525] The first metal wiring 51ga and the second metal wiring 52ga are arranged in a direction in which the mounting substrate 50ga is elongated (an x-axis direction in FIG. 6) with the gap 54ga therebetween. FIG. 32A

[0526] The first metal wiring 51ga is joined to all of the one or more first source pads 111 of the semiconductor device 1ga. The first metal wiring 51ga is joined to all of the one or more first source pads 111 of the semiconductor device 1ga, for example, via a conductive joining member formed of solder or the like.

[0527] The second metal wiring 52ga is joined to all of the one or more second source pads 121 of the semiconductor device 1ga. The second metal wiring 52ga is joined to all of the one or more second source pads 121 of the semiconductor device 1ga, for example, via a conductive joining member formed of solder or the like.

[0528] Accordingly, as shown in FIG. 6, the semiconductor device 1ga is mounted face down at a position across the first metal wiring 51ga and the second metal wiring 52ga with the gap 54ga therebetween. FIG. 32A

[0529] ​​The metal wiring 55ga is joined with the first gate pad 119 of the semiconductor device 1ga. The metal wiring 55ga is joined with the first gate pad 119 of the semiconductor device 1ga, for example, via a conductive joint formed of solder or the like.

[0530] The metal wiring 56ga is joined with the second gate pad 129 of the semiconductor device 1ga. The metal wiring 56ga is joined with the second gate pad 129 of the semiconductor device 1ga, for example, via a conductive joint formed of solder or the like.

[0531] The mounting substrate 50ga also has a first metal wiring 51gb, a second metal wiring 52gb, a metal wiring 55gb, and a metal wiring 56gb on the second surface thereof.

[0532] The first metal wiring 51gb and the second metal wiring 52gb are arranged in the direction of extension of the length of the mounting substrate 50ga (x-axis direction in FIG. 17) with the gap 54gb therebetween. FIG. 32A

[0533] The first metal wiring 51gb is joined with all of the one or more first source pads 111 of the semiconductor device 1gb. The first metal wiring 51gb is joined with all of the one or more first source pads 111 of the semiconductor device 1gb, for example, via a conductive joint formed of solder or the like.

[0534] The second metal wiring 52gb is joined with all of the one or more second source pads 121 of the semiconductor device 1gb. The second metal wiring 52gb is joined with all of the one or more second source pads 121 of the semiconductor device 1gb, for example, via a conductive joint formed of solder or the like.

[0535] Accordingly, as shown in FIG. 18, the semiconductor device 1gb is mounted face down at a position straddling the first metal wiring 51gb and the second metal wiring 52gb with the gap 54gb therebetween. FIG. 32B

[0536] The metal wiring 55gb is joined with the first gate pad 119 of the semiconductor device 1gb. The metal wiring 55gb is joined with the first gate pad 119 of the semiconductor device 1gb, for example, via a conductive joint formed of solder or the like.

[0537] The metal wiring 56gb is joined with the second gate pad 129 of the semiconductor device 1gb. The metal wiring 56gb is joined with the second gate pad 129 of the semiconductor device 1gb, for example, via a conductive joint formed of solder or the like.

[0538] FIG. 32B FIG. 19 is a plan view showing an example of the configuration of the semiconductor module 5gb of Embodiment 7. ​​

[0539] As FIG. 32B shown, the semiconductor module 5gb is configured by changing the semiconductor device 1ga to the semiconductor device 1aga, changing the semiconductor device 1gb to the semiconductor device 1agb, and changing the mounting substrate 50ga to the mounting substrate 50gb from the semiconductor module 5ga. In FIG. 32B part (a) of FIG. 15, the semiconductor device 1aga is indicated by a broken line as if transparent, so that the configuration of the upper surface of the semiconductor device 1aga and the configuration of the first surface of the mounting substrate 50gb can be easily understood. In FIG. 32B part (b) of FIG. 15, the semiconductor device 1agb is indicated by a solid line, and the other constituent elements are indicated by broken lines as if transparent, so that the configuration of the upper surface of the semiconductor device 1agb can be easily understood. FIG. 32B As

[0540] shown in FIG. 16, in the plan view of the mounting substrate 50gb, the semiconductor device 1aga is mounted face down on the first surface of the mounting substrate 50gb so that the position of the first gate pad 119 is located on the first extension direction side in the extension direction (x-axis direction in FIG. 16) of the length direction of the mounting substrate 50gb. Also, in the plan view of the mounting substrate 50gb, the semiconductor device 1agb is mounted face down on the second surface of the mounting substrate 50gb so that the semiconductor device 1aga overlaps the semiconductor device 1agb, and the position of the first gate pad 119 of the semiconductor device 1aga overlaps the position of the first gate pad 119 of the semiconductor device 1agb. FIG. 32B FIG. 32B As

[0541] As described above, in the semiconductor device 1aga and the semiconductor device 1agb, the angle θ1 formed by the second imaginary straight line 92 and the first imaginary straight line is larger than 45 degrees and is 90 degrees or less. Therefore, in the plan view of the mounting substrate 50gb, the first semiconductor layer upper surface region S1a of the semiconductor device 1agb overlaps the first semiconductor layer upper surface region S1a of the semiconductor device 1aga by more than 50%, and the second semiconductor layer upper surface region S2a of the semiconductor device 1aga overlaps the second semiconductor layer upper surface region S2a of the semiconductor device 1agb by more than 50%.

[0542] The mounting substrate 50gb is configured by changing the first metal wiring 51ga to the first metal wiring 51gc, changing the second metal wiring 52ga to the second metal wiring 52gc, changing the first metal wiring 51gb to the first metal wiring 51gd, and changing the second metal wiring 52gb to the second metal wiring 52gd from the mounting substrate 50ga. ​

[0543] The first metal wiring 51gc and the second metal wiring 52gc are separated by a gap 54gc in the length direction of the mounting substrate 50gb. FIG. 32B Arranged along the x-axis (in the image).

[0544] The first metal wiring 51gc is bonded to all of the first source pads 1111 of the semiconductor device 1aga. The first metal wiring 51gc is bonded to all of the first source pads 1111 of the semiconductor device 1aga, for example, via a conductive bonding member formed of solder or the like.

[0545] The second metal wiring 52gc is bonded to all of one or more second source pads 1121 of the semiconductor device 1aga. The second metal wiring 52gc is bonded to all of one or more second source pads 1121 of the semiconductor device 1aga, for example, via a conductive bonding member formed of solder or the like.

[0546] Therefore, as FIG. 32B As shown, the semiconductor device 1aga is mounted face down at a position spanning the first metal wiring 51gc and the second metal wiring 52gc across a gap 54gc.

[0547] The first metal wiring 51gd and the second metal wiring 52gd are separated by a gap 54gd in the length direction of the mounting substrate 50gb. FIG. 32A Arranged along the x-axis (in the image).

[0548] The first metal wiring 51gd is fully bonded to one or more first source pads 1111 of the semiconductor device 1agb. The first metal wiring 51gd is fully bonded to one or more first source pads 1111 of the semiconductor device 1agb, for example, via a conductive bonding member formed of solder or the like.

[0549] The second metal wiring 52gd is bonded to all of one or more second source pads 1121 of the semiconductor device 1agb. The second metal wiring 52gd is bonded to all of one or more second source pads 1121 of the semiconductor device 1agb, for example, via a conductive bonding member formed of solder or the like.

[0550] Therefore, as FIG. 32B As shown, the semiconductor device 1agb is mounted face down at a position spanning the first metal wiring 51gd and the second metal wiring 52gd across a gap 54gd.

[0551] [7-2. Investigation]

[0552] According to the semiconductor module 5ga of the above structure, the through hole for passing a conductor for applying a voltage to the first gate pad 119 of the semiconductor device 1ga and the through hole for passing a conductor for applying a voltage to the first gate pad 119 of the semiconductor device 1gb can be implemented with only one first through hole 61ga, and the through hole for passing a conductor for applying a voltage to the second gate pad 129 of the semiconductor device 1ga and the through hole for passing a conductor for applying a voltage to the second gate pad 129 of the semiconductor device 1gb can be implemented with only one second through hole 62ga.

[0553] Further, since the first through hole 61ga and the second through hole 62ga can be provided close to the end portion of the mounting substrate, the current path of the main current flowing in the mounting substrate and the semiconductor devices is not hindered.

[0554] Thus, in mounting the two semiconductor devices of the same type in the mounting substrate on the front surface and the back surface, respectively, the wiring (through hole) for controlling the potential of both the first gate pad of one semiconductor device and the first gate pad of the other semiconductor device and the wiring (through hole) for controlling the potential of both the second gate pad of one semiconductor device and the second gate pad of the other semiconductor device can be commonly used, respectively, and the number of wirings (through holes) that had to be provided separately in the past can be reduced, so the design easiness can be improved by simplifying the wirings that tend to complicate the mounting substrate.

[0555] Further, as shown in FIG. 33 , FIG. 33 , the gate pad of the semiconductor device of the present disclosure is provided near the corner portion of the semiconductor device, whereby the commonly used wirings (through holes) can be led out to the end portion of the mounting substrate without hindering the flow of the main current. Therefore, it is suitable for ensuring the current path of the main current flowing in the mounting substrate widely, and can be mounted in a manner of reducing the on-resistance.

[0556] Therefore, the current path of the main current flowing in the mounting substrate 50ga can be designed in a manner of reducing the on-resistance.

[0557] Further, according to the semiconductor module 5ga of the above structure, in the plan view of the mounting substrate 50ga, the first semiconductor layer upper surface region S1 of the semiconductor device 1ga and the first semiconductor layer upper surface region S1 of the semiconductor device 1gb, and the second semiconductor layer upper surface region S2 of the semiconductor device 1ga and the second semiconductor layer upper surface region S2 of the semiconductor device 1gb can be made to coincide completely with each other across the mounting substrate 50ga.

[0558] Thus, in the mounting substrate 50ga, the on-resistance of the current path can be reduced.

[0559] Therefore, the current path through which the main current flows in the mounting substrate 50ga can be designed in a manner to reduce the on-resistance.

[0560] Similarly, according to the semiconductor module 5gb of the above-described structure, the through hole through which the conductor for applying a voltage to the first gate pad 119 of the semiconductor device 1aga passes and the through hole through which the conductor for applying a voltage to the first gate pad 119 of the semiconductor device 1agb passes can be implemented with only one first through hole 61ga, and the through hole through which the conductor for applying a voltage to the second gate pad 129 of the semiconductor device 1aga passes and the through hole through which the conductor for applying a voltage to the second gate pad 129 of the semiconductor device 1agb passes can be implemented with only one second through hole 62ga.

[0561] Further, since the first through hole 61ga and the second through hole 62ga can be disposed near the end portion of the mounting substrate, the current path of the main current flowing in the mounting substrate and the semiconductor device is not hindered.

[0562] Therefore, as in the case of the mounting substrate 50ga, the current path through which the main current flows in the mounting substrate 50gb can be designed in a manner to reduce the on-resistance.

[0563] Further, according to the semiconductor module 5gb of the above-described structure, in the plan view of the mounting substrate 50gb, the first semiconductor layer upper surface region Sla of the semiconductor device 1aga and the first semiconductor layer upper surface region Sla of the semiconductor device 1agb, and the second semiconductor layer upper surface region S2a of the semiconductor device 1aga and the second semiconductor layer upper surface region S2a of the semiconductor device 1agb can be made to overlap by 50% or more, respectively, with the mounting substrate 50ga interposed therebetween.

[0564] Thus, in the mounting substrate 50gb, the on-resistance of the current path can be made relatively large.

[0565] (Embodiment 8)

[0566] [8-1. Configuration of Semiconductor Device]

[0567] Hereinafter, the semiconductor device of Embodiment 8 will be described. The semiconductor device of Embodiment 8 is configured by changing a part of the structure of the semiconductor device 1a of Embodiment 2. Therefore, here, regarding the semiconductor device of Embodiment 8, the same components as those of the semiconductor device 1a are considered to have been described and given the same reference numerals, and detailed description thereof will be omitted, and description will be made focusing on the points of difference from the semiconductor device 1a.

[0568] FIG. 33is a plan view showing an example of the configuration of the semiconductor device 1e of Technical Solution 8, and is a plan view in a state in which the configuration on the upper surface side of the first body region 18e and the second body region 28e described later is removed from the upper surface of the semiconductor device 1e, and the first body region 18e and the second body region 28e are virtually exposed.

[0569] As shown in FIG. 33 , the semiconductor device 1e is configured by changing the first body region 18 to the first body region 18e, changing the second body region 28 to the second body region 28e, changing the first semiconductor layer inner region Al to the first semiconductor layer inner region Al e, and changing the second semiconductor layer inner region A2 to the second semiconductor layer inner region A2e from the semiconductor device 1a of Embodiment 2.

[0570] As shown in FIG. 33 , the first body region 18e, the second body region 28e, the first semiconductor layer inner region Al e, and the second semiconductor layer inner region A2e are configured by changing the shape of the first body region 18, the second body region 28, the first semiconductor layer inner region Al, and the second semiconductor layer inner region A2, respectively.

[0571] Here, as shown in FIG. 34A , the first semiconductor layer inner region Al e and the second semiconductor layer inner region A2e are one and the other that bisect the semiconductor layer 40 in area in the plan view of the semiconductor layer 40, and are adjacent to each other.

[0572] As shown in FIG. 34A , in the plan view of the semiconductor layer 40, the internal boundary line 400e as the boundary line of the first semiconductor layer inner region Al e and the second semiconductor layer inner region A2e is formed by alternately connecting N-1 (N is an integer of 3 or more. Here, N is 4) line segments orthogonal to the fourth edge 204 where the first end 401 on one side of the internal boundary line 400e is located and N-2 line segments parallel to the fourth edge 204, and the internal boundary line 400e monotonically changes in the extension direction of the second edge 202 and the extension direction of the first edge 201.

[0573] The distance of the first vertex 501 from the first end 401 is 1 / N or more of the length of the fourth edge 204.

[0574] The distance of the second vertex 502 from the second end 402 on the other side of the internal boundary line 400e is 1 / N or more of the length of the second edge 202.

[0575] Further, in the plan view of the semiconductor layer 40, the angle θ4 formed by the third imaginary straight line 95 connecting the first end 401 and the second end 402 and the first edge 201 is 16 degrees or more.

[0576] Further, in a plan view of the semiconductor layer 40, the internal boundary line 400e does not necessarily coincide with the upper surface boundary line 600a, but can coincide therewith.

[0577] Further, here, the semiconductor layer 40 is described assuming that it is a square, but the semiconductor layer 40 can also be a rectangular shape other than a square. In this case, the first end 401 is located on a first long side of the semiconductor layer 40, and the second end 402 is located on a second long side of the semiconductor layer 40. Alternatively, the first end 401 is located on a first short side of the semiconductor layer 40, and the second end 402 is located on a second short side of the semiconductor layer 40.

[0578] [8-2. Configuration of semiconductor module]

[0579] Hereinafter, the semiconductor module of Embodiment 8 will be described. The semiconductor module of Embodiment 8 is configured by changing a part of the structure of the semiconductor module 5ea or 5eb of Embodiment 5, or the semiconductor module 5fb or 5fd of Embodiment 6. Therefore, here, regarding the semiconductor module of Embodiment 8, for the same constituent elements as the semiconductor module 5ea or 5eb, or the semiconductor module 5fb or 5fd, it is considered that the same description is given and the same reference numerals are assigned, and detailed description thereof is omitted, and description is made focusing on the points of difference from the semiconductor module 5ea or 5eb, or the semiconductor module 5fb or 5fd.

[0580] FIG. 34B is a plan view showing an example of the configuration of the semiconductor module 5ha of Embodiment 8.

[0581] As shown in FIG. 34B , the semiconductor module 5ha is configured by changing the semiconductor device 1ea to the semiconductor device 1eha which is one of the semiconductor devices 1e of Embodiment 5, and changing the semiconductor device 1eb to the semiconductor device 1ehb which is the other of the semiconductor devices 1e of Embodiment 5.

[0582] Here, the semiconductor device 1eha and the semiconductor device 1ehb are the semiconductor devices 1e whose shapes of the upper surfaces are the same as the shape of the upper surface of the semiconductor device 1.

[0583] FIG. 35A is a plan view showing an example of the configuration of the semiconductor module 5hb of Embodiment 8.

[0584] As shown in FIG. 35AAs shown, the semiconductor module 5hb is configured by changing the semiconductor device 1aea to the semiconductor device 1ehc as one of the semiconductor devices 1e and changing the semiconductor device 1aeb to the semiconductor device 1ehd as the other semiconductor device 1e from the semiconductor module 5eb of Embodiment 5.

[0585] Here, the semiconductor device 1ehc and the semiconductor device 1ehd are the semiconductor devices 1e whose shapes of the upper surfaces are the same as the shape of the upper surface of the semiconductor device 1a, and are the semiconductor devices 1e in which the inner boundary line 400e coincides with the upper surface boundary line 600a in the plan view of the semiconductor layer 40.

[0586] FIG. 35B is a plan view showing an example of the configuration of the semiconductor module 5ia of Embodiment 8.

[0587] As shown, FIG. 35B the semiconductor module 5ia is configured by changing the semiconductor device 1fc to the semiconductor device 1ehe as one of the semiconductor devices 1e and changing the semiconductor device 1fd to the semiconductor device 1ehf as the other semiconductor device 1e from the semiconductor module 5fb of Embodiment 6.

[0588] Here, the semiconductor device 1ehe and the semiconductor device 1ehf are the semiconductor devices 1e whose shapes of the upper surfaces are the same as the shape of the upper surface of the semiconductor device 1.

[0589] FIG. 36 is a plan view showing an example of the configuration of the semiconductor module 5ib of Embodiment 8.

[0590] As shown, FIG. 37 the semiconductor module 5ib is configured by changing the semiconductor device 1afc to the semiconductor device 1ehg as one of the semiconductor devices 1e and changing the semiconductor device 1afd to the semiconductor device 1ehh as the other semiconductor device 1e from the semiconductor module 5fd of Embodiment 6.

[0591] Here, the semiconductor device 1ehg and the semiconductor device 1ehh are the semiconductor devices 1e whose shapes of the upper surfaces are the same as the shape of the upper surface of the semiconductor device 1a, and are the semiconductor devices 1e in which the inner boundary line 400e coincides with the upper surface boundary line 600a in the plan view of the semiconductor layer 40.

[0592] [8-3. Investigation]

[0593] According to the semiconductor device 1e having the above structure, in a plan view of the semiconductor layer 40, the length of the internal boundary line 400e is longer than that of a conventional semiconductor device in which the internal boundary line extends in a straight line in a direction orthogonal to or parallel to the long side direction of the semiconductor layer. Therefore, in a case where a current flows from the first source pad 1111 to the second source pad 1121 or from the second source pad 1121 to the first source pad 1111, the current flowing in the horizontal direction in the metal layer 30 has a larger current-carrying cross-sectional area.

[0594] Thus, the semiconductor device 1e in a case where a current flows from the first source pad 1111 to the second source pad 1121 or from the second source pad 1121 to the first source pad 1111 can have a smaller resistance value than in the past.

[0595] Thus, according to the semiconductor device 1e having the above structure, a semiconductor device having a feature that a current can efficiently flow in a current path of a mounting substrate to be mounted can be provided.

[0596] According to the semiconductor module 5ib having the above structure, the semiconductor device 1ehg and the semiconductor device 1ehh are arranged in an inclined positional relationship with respect to each side of the semiconductor device 1ehg and each side of the semiconductor device 1ehh.

[0597] Thus, in the semiconductor module 5ib, the influence of heat generation of the semiconductor device 1ehg on the semiconductor device 1ehh and the influence of heat generation of the semiconductor device 1ehh on the semiconductor device 1ehg can be reduced.

[0598] Thus, according to the semiconductor module 5ib having the above structure, a semiconductor module having a feature that a current can efficiently flow in a current path of a mounting substrate to be mounted can be provided.

[0599] Next, a preferable range of the angle θ4 is examined.

[0600] FIG. 36 and FIG. 37 is a graph showing a relationship of the angle θ4 and a ratio of a resistance component of the metal layer 30 in the on-resistance of the semiconductor device 1e, that is, a resistance of the semiconductor device 1e in a case where a current flows from the first source pad 1111 to the second source pad 1121 or from the second source pad 1121 to the first source pad 1111 (hereinafter also referred to as "metal layer resistance component ratio").

[0601] In FIG. 36 and FIG. 37 , the horizontal axis is the angle θ4 and the vertical axis is the metal layer resistance component ratio.

[0602] In FIG. 36 and FIG. 37In the diagram, the black circle represents the resistivity ratio of the metal layer when the machining dimension of the metal layer 30 is a specified value. FIG. 36 In the diagram, the white circle represents the resistivity ratio of the metal layer when the thickness of the metal layer 30 is 4% thinner than the specified value during processing. FIG. 37 In the diagram, the white circle indicates the metal layer resistivity ratio when the thickness of the metal layer 30 is 10% thinner than the specified value during processing.

[0603] Semiconductor device 1e, due to manufacturing deviations in its manufacturing process, has a case where the processing dimension of the thickness of the metal layer 30 deviates within a range of ±4%.

[0604] like FIG. 35B As shown, in semiconductor device 1e, even if the thickness of the metal layer 30 is 4% thinner than the specified value due to manufacturing deviation, as long as θ4 is 16 degrees or more, it is possible to maintain the metal layer resistance ratio as when the thickness of the metal layer 30 is the specified value when θ4 is 0 degrees.

[0605] Therefore, θ4 is preferably 16 degrees or higher.

[0606] In addition, such as FIG. 38 As shown, the semiconductor device 1e can maintain the metal layer resistance ratio when θ4 is 0 degrees by setting θ4 to 26 degrees or more, and the thickness of the metal layer 30 is reduced by 10%.

[0607] Therefore, by setting θ4 to 26 degrees or more, the semiconductor device 1e can achieve a low resistance effect equivalent to that when the thickness of the metal layer 30 is increased by 10%. Thus, θ4 is preferably 26 degrees or more.

[0608] The following describes the extension direction of the mounting substrate 50fd in the semiconductor module 5ib (in the longitudinal direction). FIG. 39 The offsets of semiconductor devices 1ehg and 1ehh (hereinafter also referred to as "offsets between semiconductor devices 1e") on the x-axis direction are examined.

[0609] The inventors of this invention have realized that in the semiconductor module 5ib, by increasing the offset between semiconductor devices 1e, the influence of heat generation from semiconductor device 1ehg on semiconductor device 1ehh, and the influence of heat generation from semiconductor device 1ehh on semiconductor device 1ehg, can be reduced. On the other hand, if the offset between semiconductor devices 1e is too large, the disadvantage of the mounting substrate 50fd becoming longer in the longitudinal direction occurs.

[0610] Therefore, the inventors of the present application have conducted experiments and researches repeatedly in order to calculate an effective value of the shift amount between the semiconductor devices 1e. As a result, the inventors of the present application have obtained the following recognition: the shift amount between the semiconductor devices 1e is preferably more than half of the width of the semiconductor devices 1e in the extension direction of the length direction of the mounting substrate 50fd.

[0611] FIG. 38 A diagram showing the relationship between the size of the two semiconductor devices 1e (semiconductor device 1ehg and semiconductor device 1ehh) of the semiconductor module 5ib, the shift amount between the semiconductor devices 1e, and the angle θ of the straight line connecting the centers of the two semiconductor devices 1e and the direction orthogonal to the extension direction of the length direction of the mounting substrate 50fd.

[0612] FIG. 39 is a diagram showing an example of the relationship between the size of the two semiconductor devices 1e and the shift amount between the semiconductor devices 1e and the angle θ, which is considered to be preferable by the inventors of the present application.

[0613] In FIG. 39 and ​ , the length Y is the width of the semiconductor device 1e in the direction orthogonal to the extension direction of the length direction of the mounting substrate 50fd, the length X is the width of the semiconductor device 1e in the extension direction of the length direction of the mounting substrate 50fd, the length T is the distance between the two semiconductor devices 1e in the direction orthogonal to the extension direction of the length direction of the mounting substrate 50fd, and the angle θ is the angle of the straight line connecting the centers of the two semiconductor devices 1e and the direction orthogonal to the extension direction of the length direction of the mounting substrate 50fd.

[0614] As shown in ​ , the angle θ is 25.8 degrees to 26.0 degrees, and the shift amount is preferably more than 26 degrees.

[0615] The effect of Embodiment 8 is to reduce the resistance component when the current flowing in the metal layer 30 of the semiconductor device 1e flows in the horizontal direction. However, if the internal boundary line 400 originally includes a portion in which the current does not flow in the horizontal component, the effect is weakened. That is, if the so-called active regions in which the channels of the first transistor and the second transistor are respectively formed and contribute to conduction are opposed to each other to constitute the internal boundary line 400, the effect cannot be expected regardless of how long the internal boundary line 400 is. Thus, in order to appropriately obtain the effect of Embodiment 8, it is preferable that the internal boundary line 400 be constituted only by the opposed length of the active regions.

[0616] Further, the inclination angle θ of the internal boundary line 400 described above has an upper limit. If an aspect ratio α (= Ly / Lx) is calculated from the length Lx of the long side and the length Ly of the short side of the semiconductor device le, the upper limit of the angle θ in the case where both ends of the internal boundary line 400 are on the short side of the semiconductor device le is atan(α) degrees, and the upper limit of the angle θ in the case where both ends of the internal boundary line 400 are on the long side of the semiconductor device le is atan(l / α) degrees.

[0617] (Supplement)

[0618] The above describes the semiconductor device and the semiconductor module of the technical solution of the present disclosure based on Embodiments 1 to 8, but the present disclosure is not limited to these embodiments. As long as the spirit of the present disclosure is not deviated, various modified forms thought by those skilled in the art or forms constructed by combining constituent elements of different embodiments can also be included in the scope of one or more technical solutions of the present disclosure.

[0619] Industrial applicability

[0620] The present disclosure can be widely used in semiconductor devices and semiconductor modules using the same, and the like.

[0621] Explanation of reference numerals

[0622] 1, 1a, 1ab, 1ad, 1aea, 1aeb, 1aec, 1aed, 1afa, 1afb, 1afc, 1afd, 1aga, 1agb, 1c, 1cea, 1ceb, 1cfa, 1cfb, 1d, 1dea, 1deb, 1dfa, 1dfb, 1e, 1ea, 1eb, 1ec, 1ed, 1efa, 1efb, 1eha, 1ehb, 1ehc, 1ehd, 1ehe, 1ehf, 1ehg, 1ehh, 1fa, 1fb, 1fc, 1fd, 1ga, 1gb semiconductor device

[0623] 5, 5a, 5b, 5c, 5d, 5ea, 5eb, 5ec, 5ed, 5ee, 5fa, 5fb, 5fc, 5fd, 5fe, 5ff, 5ga, 5gb, 5ha, 5hb, 5ia, 5ib semiconductor module

[0624] 10 transistor (1st vertical MOS transistor)

[0625] 11 1st source electrode

[0626] 12, 13, 13a, 13c, 13d, 17, 27, 22, 23, 23a, 23c, 23d, 68, 69, 78, 79 portion

[0627] 14 first source region

[0628] 15 first gate conductor

[0629] 16 first gate insulating film

[0630] 18, 18e first body region

[0631] 20 transistor (second vertical MOS transistor)

[0632] 21 second source electrode

[0633] 24 second source region

[0634] 25 second gate conductor

[0635] 26 second gate insulating film

[0636] 28, 28e second body region

[0637] 30 metal layer

[0638] 32 semiconductor substrate

[0639] 33 low-concentration impurity layer

[0640] 34 oxide film

[0641] 35 protective layer

[0642] 36 insulating film

[0643] 40 semiconductor layer

[0644] 50, 50a, 50b, 50c, 50d, 50ea, 50eb, 50ec, 50ed, 50ee, 50fa, 50fb, 50fc, 50fd, 50fe, 50ff, 50ga mounting substrate

[0645] 51, 51a, 51b, 51c, 51d, 51ea, 51eb, 51ec, 51ed, 51ee, 51fa, 51fb, 51fc, 51fd, 51fe, 51ff, 51ga, 51gb, 51gc, 51gd first metal wiring

[0646] 52, 52a, 52b, 52c, 52d, 52ea, 52eb, 52ec, 52ed, 52ee, 52fa, 52fb, 52fc, 52fd, 52fe, 52ff, 52ga, 52gb, 52gc, 52gd second metal wiring

[0647] 53ea, 53eb, 53ec, 53ed, 53ee third metal wiring

[0648] 54, 54a, 54b, 54c, 54d, 54ea, 54eb, 54ec, 54ed, 54ee, 54ef, 54eg, 54eh, 54ei, 54ej, 54fa, 54fb, 54fc, 54fd, 54fe, 54ff, 54ga, 54gb, 54gc, 54gd gap

[0649] 55, 55b, 55c, 55ea, 55ec, 55ed, 55fa, 55fb, 55fd, 55fe, 55ga, 55gb, 56, 56b, 56c, 56ea, 56ec, 56ed, 56fa, 56fb, 56fd, 56fe, 56ga, 56gb, 57ea, 57ec, 57ed, 57fa, 57fb, 57fd, 57fe, 58ea, 58ec, 58ed, 58fb, 58fd, 58fe metal wiring

[0650] 61, 61b, 61c, 61ea, 61ec, 61ed, 61fa, 61fb, 61fd, 61fe, 61ga first via

[0651] 62, 62b, 62c, 62ea, 62ec, 62ed, 62fa, 62fb, 62fd, 62fe, 62ga second via

[0652] 63ea, 63ec, 63ed, 63fb, 63fd, 63fe third via

[0653] 64ea, 64ec, 64ed, 64fb, 64fd, 64fe fourth via

[0654] 71 first control region

[0655] 72 second control region

[0656] 91 first imaginary straight line

[0657] 92, 92d second imaginary straight line

[0658] 93 opposing line segment

[0659] 94 line segment

[0660] 95 third imaginary straight line

[0661] 111, 111a, 111b, 111c, 111d, 111e, 111f, 111g, 111h, 111i, 111j, 111k, 1111, 1111a, 1111b, 1111c, 1111d, 1111e, 1111f, 1111g, 1111h, 1111i, 2111, 2111a, 2111b, 2111c, 2111d, 2111e, 2111f, 2111g, 2111h, 2111i, 2111j, 2111k, 2111l, 2111m, 2111n, 2111o, 2111p, 2111q, 3111, 3111a, 3111b, 3111c, 3111d, 3111e, 3111f, 3111g, 3111h first source pad

[0662] 119 first gate pad

[0663] 121, 121a, 121b, 121c, 121d, 121e, 121f, 121g, 121h, 121i, 121j, 121k, 1211, 1211a, 1211b, 1211c, 1211d, 1211e, 1211f, 1211g, 1211h, 1211i, 2211, 2211a, 2211b, 2211c, 2211d, 2211e, 2211f, 2211g, 2211h, 2211i, 2211j, 2211k, 2211l, 2211m, 2211n, 2211o, 2211p, 2211q, 3211, 3211a, 3211b, 3211c, 3211d, 3211e, 3211f, 3211g, 3211h second source pad

[0664] 129 second gate pad

[0665] 201 first side

[0666] 202 second side

[0667] 203 third side

[0668] 204 fourth side

[0669] 400, 400e internal boundary line

[0670] 401 first end

[0671] 402 second end

[0672] 501 1st vertex

[0673] 502 2nd vertex

[0674] 503 3rd vertex

[0675] 504 4th vertex

[0676] 600, 600a, 600c, 600d upper surface boundary line

[0677] 601, 601d 1st intersection point

[0678] 602, 602d 2nd intersection point

[0679] 611, 612, 613 1st through hole

[0680] 621, 622, 623 2nd through hole

[0681] A1, A1e 1st semiconductor layer inner region

[0682] A2, A2e 2nd semiconductor layer inner region

[0683] S1, S1a, S1c, S1d 1st semiconductor layer upper surface region

[0684] S2, S2a, S2c, S2d 2nd semiconductor layer upper surface region

Claims

1. A semiconductor device, which is a chip size package type semiconductor device capable of face-down mounting, characterized by comprising: a semiconductor layer; a metal layer formed in contact with a back surface of the semiconductor layer; a first vertical MOS transistor formed in a first semiconductor layer inner region inside the semiconductor layer; a second vertical MOS transistor formed in a second semiconductor layer inner region inside the semiconductor layer adjacent to the first semiconductor layer inner region in a plan view of the semiconductor layer; one or more first source pads connected to source electrodes of the first vertical MOS transistor and one first gate pad connected to gate electrodes of the first vertical MOS transistor formed in a first semiconductor layer upper surface region on an upper surface of the semiconductor layer; and one or more second source pads connected to source electrodes of the second vertical MOS transistor and one second gate pad connected to gate electrodes of the second vertical MOS transistor formed in a second semiconductor layer upper surface region on the upper surface of the semiconductor layer adjacent to the first semiconductor layer upper surface region in the plan view of the semiconductor layer, wherein the first semiconductor layer inner region and the second semiconductor layer inner region are one and the other of two equal parts in area of the semiconductor layer in the plan view of the semiconductor layer, wherein the first semiconductor layer upper surface region and the second semiconductor layer upper surface region are one and the other of two equal parts in area of the semiconductor layer in the plan view of the semiconductor layer, wherein the semiconductor layer has a semiconductor substrate, wherein the semiconductor substrate functions as a common drain region of the first vertical MOS transistor and the second vertical MOS transistor, wherein the semiconductor layer is rectangular in the plan view of the semiconductor layer, wherein in the plan view of the semiconductor layer, a first imaginary straight line connecting a center of the first gate pad with a center of the second gate pad passes through a center of the semiconductor layer at an angle of 45 degrees to each side of the semiconductor layer, wherein a length of an upper surface boundary line between the first semiconductor layer upper surface region and the second semiconductor layer upper surface region is longer than a length of a long side of the semiconductor layer, and wherein the upper surface boundary line monotonously changes in a long side direction in which the long side extends and in a short side direction in which a short side of the semiconductor layer extends.

2. The semiconductor device according to claim 1, wherein the semiconductor layer is square in the plan view of the semiconductor layer.

3. The semiconductor device according to claim 2, wherein in the plan view of the semiconductor layer, the first gate pad is disposed such that none of the one or more first source pads is sandwiched between the first gate pad and first and second sides of the four sides of the semiconductor layer closest thereto. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ In a plan view of the semiconductor layer, the second gate pad is arranged such that none of the one or more second source pads is sandwiched between the second gate pad and the closest of the third and fourth edges of the semiconductor layer.

4. The semiconductor device according to claim 3, wherein In a case where an intersection of the upper surface boundary line and the first edge or the second edge is set as a first intersection, and an intersection of the upper surface boundary line and the third edge or the fourth edge is set as a second intersection, a second imaginary straight line connecting the first intersection and the second intersection forms an angle with the first imaginary straight line in a plan view of the semiconductor layer, the angle being greater than 45 degrees and being 90 degrees or less.

5. The semiconductor device according to claim 4, wherein The angle between the second imaginary straight line and the first imaginary straight line in the plan view of the semiconductor layer is 60 degrees or more and 90 degrees or less.

6. The semiconductor device according to claim 3, wherein In a case where an intersection of the upper surface boundary line and the first edge or the second edge is set as a first intersection, and an intersection of the upper surface boundary line and the third edge or the fourth edge is set as a second intersection, a second imaginary straight line connecting the first intersection and the second intersection forms an angle with the first imaginary straight line in a plan view of the semiconductor layer, the angle being 0 degrees or more and less than 45 degrees.

7. The semiconductor device according to claim 6, wherein The angle between the second imaginary straight line and the first imaginary straight line in the plan view of the semiconductor layer is 0 degrees or more and less than 22 degrees.

8. The semiconductor device according to claim 2, wherein In a plan view of the semiconductor layer, In the four edges of the semiconductor layer, an edge closest to the first gate pad and having an intersection with the upper surface boundary line is set as a first edge, an edge closest to the first gate pad and not having an intersection with the upper surface boundary line is set as a second edge, an edge closest to the second gate pad and having an intersection with the upper surface boundary line is set as a third edge, an edge closest to the second gate pad and not having an intersection with the upper surface boundary line is set as a fourth edge, a vertex formed by the first edge and the fourth edge is set as a first vertex, a vertex formed by the second edge and the third edge is set as a second vertex, an intersection of the upper surface boundary line and the first edge is set as a first intersection, and an intersection of the upper surface boundary line and the third edge is set as a second intersection, A distance between the first vertex and the first intersection is 1 / N or more of a length of an edge of the semiconductor layer and is longer than a maximum diameter of the first gate pad, and a distance between the second vertex and the second intersection is 1 / N or more of the length of the edge of the semiconductor layer and is longer than a maximum diameter of the second gate pad, N being an integer of 3 or more; The upper surface boundary line is formed by alternately connecting N-1 line segments parallel to the second edge and N-2 line segments parallel to the first edge.

9. The semiconductor device according to claim 8, wherein N is any one of 3, 4, or 5.

10. The semiconductor device according to claim 8 or 9, wherein the one or more first source pads are a plurality of pads; in a plan view of the semiconductor layer, the one or more first source pads are each a rectangle or an oblong having a length direction in a direction parallel to the first side, and are formed in a strip shape parallel to the first side; the one or more second source pads are a plurality of pads; in a plan view of the semiconductor layer, the one or more second source pads are each a rectangle or an oblong having a length direction in a direction parallel to the first side, and are formed in a strip shape parallel to the first side.

11. The semiconductor device according to claim 3, wherein the one or more first source pads are one pad, and are disposed on substantially the entire surface of the first semiconductor layer surface region except for the region of the first gate pad; the one or more second source pads are one pad, and are disposed on substantially the entire surface of the second semiconductor layer surface region except for the region of the second gate pad.

12. The semiconductor device according to claim 3, wherein the one or more first source pads are a plurality of pads; the one or more first source pads are each a shape having edges opposite to other first source pads, which are edges orthogonal or parallel to the upper surface boundary line; the one or more second source pads are a plurality of pads; the one or more second source pads are each a shape having edges opposite to other second source pads, which are edges orthogonal or parallel to the upper surface boundary line.

13. A semiconductor device, which is a chip size package type semiconductor device capable of face-down mounting, characterized by comprising: a semiconductor layer; a metal layer formed in contact with a back surface of the semiconductor layer; a first vertical MOS transistor formed in a first semiconductor layer inner region inside the semiconductor layer; a second vertical MOS transistor formed in a second semiconductor layer inner region inside the semiconductor layer adjacent to the first semiconductor layer inner region in a plan view of the semiconductor layer; a first gate pad and one or more first source pads formed on a first semiconductor layer surface region of an upper surface of the semiconductor layer, the first source pads being connected to source electrodes of the first vertical MOS transistor, and the first gate pad being connected to a gate electrode of the first vertical MOS transistor; and a second gate pad and one or more second source pads formed on a second semiconductor layer surface region of the upper surface adjacent to the first semiconductor layer surface region in a plan view of the semiconductor layer, the second source pads being connected to source electrodes of the second vertical MOS transistor, and the second gate pad being connected to a gate electrode of the second vertical MOS transistor; the first semiconductor layer inner region and the second semiconductor layer inner region are one of two equal parts of the semiconductor layer in area in a plan view of the semiconductor layer. ​ The first semiconductor layer upper surface region and the second semiconductor layer upper surface region are one and the other that bisects the semiconductor layer in area in a plan view of the semiconductor layer; The semiconductor layer has a semiconductor substrate; The semiconductor substrate functions as a common drain region of the first vertical MOS transistor and the second vertical MOS transistor; The semiconductor layer is rectangular in a plan view of the semiconductor layer; In a plan view of the semiconductor layer, a boundary line between the first semiconductor layer inner region and the second semiconductor layer inner region, that is, an internal boundary line, monotonously changes in a long side direction in which a long side of the semiconductor layer extends and a short side direction in which a short side of the semiconductor layer extends; In a plan view of the semiconductor layer, an angle formed by an imaginary straight line connecting a first end of one of the internal boundary lines and a second end of the other of the internal boundary lines and a side of the semiconductor layer that does not have the first end or the second end is 16 degrees or more; In a plan view of the semiconductor layer, the internal boundary line is composed only of portions in which the active region of the first vertical MOS transistor and the active region of the second vertical MOS transistor face each other.

14. A semiconductor device, which is a chip size package type semiconductor device capable of face-down mounting, characterized by comprising: a semiconductor layer; a metal layer formed in contact with a back surface of the semiconductor layer; a first vertical MOS transistor formed in a first semiconductor layer inner region inside the semiconductor layer; a second vertical MOS transistor formed in a second semiconductor layer inner region inside the semiconductor layer that is adjacent to the first semiconductor layer inner region in a plan view of the semiconductor layer; a first gate pad and one or more first source pads formed in a first semiconductor layer upper surface region of an upper surface of the semiconductor layer, the first source pads being connected to source electrodes of the first vertical MOS transistor, and the first gate pad being connected to a gate electrode of the first vertical MOS transistor; and a second gate pad and one or more second source pads formed in a second semiconductor layer upper surface region of the upper surface that is adjacent to the first semiconductor layer upper surface region in the plan view of the semiconductor layer, the second source pads being connected to source electrodes of the second vertical MOS transistor, and the second gate pad being connected to a gate electrode of the second vertical MOS transistor; the first semiconductor layer inner region and the second semiconductor layer inner region are one and the other that bisects the semiconductor layer in area in a plan view of the semiconductor layer; the first semiconductor layer upper surface region and the second semiconductor layer upper surface region are one and the other that bisects the semiconductor layer in area in a plan view of the semiconductor layer; the semiconductor layer has a semiconductor substrate; the semiconductor substrate functions as a common drain region of the first vertical MOS transistor and the second vertical MOS transistor; the semiconductor layer is rectangular in a plan view of the semiconductor layer; ​ In a plan view of the semiconductor layer, the internal boundary line between the first semiconductor layer inner region and the second semiconductor layer inner region monotonously changes in a long side direction in which a long side of the semiconductor layer extends and a short side direction in which a short side of the semiconductor layer extends; In a plan view of the semiconductor layer, an angle formed by an imaginary straight line connecting a first end of one side of the internal boundary line and a second end of the other side of the internal boundary line and an edge of the semiconductor layer that does not have the first end or the second end is 16 degrees or more; In a plan view of the semiconductor layer, the internal boundary line is composed of an imaginary straight line that passes through a center position of an interval between a portion of a source electrode of the first vertical MOS transistor formed in the first semiconductor layer inner region and a portion of a source electrode of the second vertical MOS transistor formed in the second semiconductor layer inner region.

15. A semiconductor device, which is a chip size package type semiconductor device capable of face-down mounting, characterized by comprising: a semiconductor layer; a metal layer formed in contact with a back surface of the semiconductor layer; a first vertical MOS transistor formed in a first semiconductor layer inner region inside the semiconductor layer; a second vertical MOS transistor formed in a second semiconductor layer inner region inside the semiconductor layer adjacent to the first semiconductor layer inner region in a plan view of the semiconductor layer; a first gate pad and one or more first source pads formed in a first semiconductor layer upper surface region of an upper surface of the semiconductor layer, the first source pads being connected to source electrodes of the first vertical MOS transistor, the first gate pad being connected to a gate electrode of the first vertical MOS transistor; and a second gate pad and one or more second source pads formed in a second semiconductor layer upper surface region of the upper surface adjacent to the first semiconductor layer upper surface region in the plan view of the semiconductor layer, the second source pads being connected to source electrodes of the second vertical MOS transistor, the second gate pad being connected to a gate electrode of the second vertical MOS transistor; the first semiconductor layer inner region and the second semiconductor layer inner region are one and the other that bisect the semiconductor layer in area in the plan view of the semiconductor layer; the first semiconductor layer upper surface region and the second semiconductor layer upper surface region are one and the other that bisect the semiconductor layer in area in the plan view of the semiconductor layer; the semiconductor layer has a semiconductor substrate; the semiconductor substrate functions as a common drain region of the first vertical MOS transistor and the second vertical MOS transistor; the semiconductor layer is rectangular in the plan view of the semiconductor layer; in a plan view of the semiconductor layer, the internal boundary line between the first semiconductor layer inner region and the second semiconductor layer inner region monotonously changes in a long side direction in which a long side of the semiconductor layer extends and a short side direction in which a short side of the semiconductor layer extends; ​ In a plan view of the semiconductor layer, an angle formed by an imaginary straight line connecting a first end of one side of the internal boundary line and a second end of the other side of the internal boundary line and a side of the semiconductor layer which does not have the first end or the second end is 16 degrees or more; In a plan view of the semiconductor layer, a portion of the gate electrode of the first vertical MOS transistor formed in the first semiconductor layer inner region is not disposed between the internal boundary line and a portion of the source electrode of the first vertical MOS transistor formed in the first semiconductor layer inner region, and a portion of the gate electrode of the second vertical MOS transistor formed in the second semiconductor layer inner region is not disposed between the internal boundary line and a portion of the source electrode of the second vertical MOS transistor formed in the second semiconductor layer inner region.

16. The semiconductor device according to any one of claims 13 to 15, wherein In a plan view of the semiconductor layer, the first end of one side of the internal boundary line is located on a first long side of the semiconductor layer; the second end of the other side of the internal boundary line is located on a second long side of the semiconductor layer.

17. The semiconductor device according to claim 16, wherein the angle is 26 degrees or more.

18. The semiconductor device according to any one of claims 13 to 15, wherein In a plan view of the semiconductor layer, the first end of one side of the internal boundary line is located on a first short side of the semiconductor layer; the second end of the other side of the internal boundary line is located on a second short side of the semiconductor layer.

19. The semiconductor device according to claim 18, wherein the angle is 26 degrees or more.

20. The semiconductor device according to any one of claims 13 to 15, wherein In a plan view of the semiconductor layer, the semiconductor layer is a square; a distance between the first end of one side of the internal boundary line and a first vertex of the semiconductor layer closest to the first end is 1 / N or more of a length of a side of the semiconductor layer, and a distance between the second end of the other side of the internal boundary line and a second vertex of the semiconductor layer closest to the second end is 1 / N or more of the length of the side of the semiconductor layer, N being an integer of 3 or more; the internal boundary line is formed by alternately connecting N-1 line segments orthogonal to a side of the semiconductor layer on which the first end is located and N-2 line segments parallel to the side of the semiconductor layer on which the first end is located.

21. The semiconductor device according to any one of claims 13 to 15, wherein In a plan view of the semiconductor layer, a boundary line between the first semiconductor layer upper surface region and the second semiconductor layer upper surface region, that is, an upper surface boundary line coincides with the internal boundary line.

22. A semiconductor module comprising: a first semiconductor device according to claim 1; and a second semiconductor device according to claim 1. mounting the first semiconductor device upside down on the mounting substrate; the mounting substrate has a first through-hole through which a first conductor electrically connected to the first gate pad of the first semiconductor device passes, and a second through-hole through which a second conductor electrically connected to the second gate pad of the first semiconductor device passes.

23. The semiconductor module according to claim 22, wherein in a plan view of the mounting substrate, the center of the first through-hole and the center of the second through-hole are on the first imaginary straight line of the first semiconductor device.

24. The semiconductor module according to claim 22, wherein the first semiconductor device is the semiconductor device according to claim 3; in a plan view of the mounting substrate, the center of the first through-hole is on the first imaginary straight line of the first semiconductor device, (2) outside the first semiconductor device in the extension direction of the first side beyond the second side, and between the center of the first gate pad and the first side in the extension direction of the second side, or (3) outside the first semiconductor device in the extension direction of the second side beyond the first side, and between the center of the first gate pad and the second side in the extension direction of the first side; the center of the second through-hole is on the first imaginary straight line of the first semiconductor device, (2) outside the first semiconductor device in the extension direction of the third side beyond the fourth side, and between the center of the second gate pad and the third side in the extension direction of the fourth side, or (3) outside the first semiconductor device in the extension direction of the fourth side beyond the third side, and between the center of the second gate pad and the fourth side in the extension direction of the third side.

25. The semiconductor module according to claim 24, wherein the first semiconductor device is the semiconductor device according to claim 4; in a plan view of the mounting substrate, the mounting substrate has a width at least at a portion where the first semiconductor device is mounted and extends in a length direction, and on the first surface of the mounting substrate, has a first metal wiring which is joined to all of the one or more first source pads of the first semiconductor device in the extension direction of the length direction, and a second metal wiring which is joined to all of the one or more second source pads of the first semiconductor device in the extension direction of the length direction; the first semiconductor device is mounted on the first surface in such an orientation that an angle formed by the second imaginary straight line and the extension direction of the length direction is 15 degrees or more and 75 degrees or less.

26. The semiconductor module according to claim 25, wherein a second semiconductor device which is the semiconductor device according to claim 4 is further provided; in a plan view of the mounting substrate, The first semiconductor device is mounted face down on the first surface with the position of the first gate pad of the first semiconductor device located on the first extension direction side in the extension direction of the length direction; The second semiconductor device is mounted face down on the first surface with the position of the first gate pad of the second semiconductor device located on the first extension direction side in the extension direction of the length direction, and with the second imaginary straight line of the first semiconductor device and the second imaginary straight line of the second semiconductor device being parallel, and the second imaginary straight line of the second semiconductor device being parallel to the first imaginary straight line of the first semiconductor device; The mounting substrate further has a third metal wiring on the first surface, the third metal wiring being arranged in the second extension direction with respect to the second metal wiring and being joined to all of the one or more second source pads of the second semiconductor device; The second metal wiring is further joined to all of the one or more first source pads of the second semiconductor device.

27. The semiconductor module according to claim 25, wherein the semiconductor module further comprises a second semiconductor device as the semiconductor device according to claim 4; in a plan view of the mounting substrate, the first semiconductor device is mounted face down on the first surface with the position of the first gate pad of the first semiconductor device located on the first extension direction side in the extension direction of the length direction; the second semiconductor device is mounted face down on the first surface with the position of the first gate pad of the second semiconductor device located on the first extension direction side in the extension direction of the length direction, and with the second imaginary straight line of the first semiconductor device and the second imaginary straight line of the second semiconductor device being parallel, and the second imaginary straight line of the second semiconductor device being orthogonal to the first imaginary straight line of the first semiconductor device; the first metal wiring is further joined to all of the one or more first source pads of the second semiconductor device; the second metal wiring is further joined to all of the one or more second source pads of the second semiconductor device; the second gate pad of the second semiconductor device is electrically connected to the second conductor.

28. The semiconductor module according to claim 25, wherein the semiconductor module further comprises a second semiconductor device as the semiconductor device according to claim 4; in a plan view of the mounting substrate, the first semiconductor device is mounted face down on the first surface with the position of the first gate pad of the first semiconductor device located on the first extension direction side in the extension direction of the length direction; The above-mentioned second semiconductor device is mounted face down on the above-mentioned first surface with the position of the above-mentioned first gate pad of the above-mentioned second semiconductor device on the side of the above-mentioned first extension direction so as to make the above-mentioned second imaginary straight line of the above-mentioned first semiconductor device and the above-mentioned second imaginary straight line of the above-mentioned second semiconductor device be on a straight line or parallel, and the position of the above-mentioned first gate pad of the above-mentioned second semiconductor device be on the side of the above-mentioned first extension direction; The above-mentioned first metal wiring is also joined to all of the above-mentioned one or more first source pads of the above-mentioned second semiconductor device; The above-mentioned second metal wiring is also joined to all of the above-mentioned one or more second source pads of the above-mentioned second semiconductor device.

29. The semiconductor module according to claim 25, wherein a second semiconductor device is further provided as the semiconductor device according to claim 4; in a plan view of the mounting substrate, the above-mentioned first semiconductor device is mounted face down on the above-mentioned first surface with the position of the above-mentioned first gate pad of the above-mentioned first semiconductor device on the side of the above-mentioned first extension direction so as to make the angle between each side of the above-mentioned first semiconductor device and the above-mentioned extension direction be 45 degrees; the above-mentioned second semiconductor device is mounted face down on the above-mentioned second surface of the mounting substrate opposite to the above-mentioned first surface with the position of the above-mentioned first gate pad of the above-mentioned second semiconductor device on the side of the above-mentioned first extension direction so as to make the above-mentioned first semiconductor layer upper surface region of the above-mentioned first semiconductor device and the above-mentioned first semiconductor layer upper surface region of the above-mentioned second semiconductor device overlap more than 50%, and the above-mentioned second semiconductor layer upper surface region of the above-mentioned first semiconductor device and the above-mentioned second semiconductor layer upper surface region of the above-mentioned second semiconductor device overlap more than 50% in a plan view of the semiconductor substrate; the above-mentioned first gate pad of the above-mentioned second semiconductor device is electrically connected to the above-mentioned first conductor; the above-mentioned second gate pad of the above-mentioned second semiconductor device is electrically connected to the above-mentioned second conductor.

30. The semiconductor module according to claim 24, wherein the above-mentioned first semiconductor device is the semiconductor device according to claim 6; in a plan view of the mounting substrate, the above-mentioned mounting substrate has a shape extending in the above-mentioned extension direction with a certain width at least at the portion where the above-mentioned first semiconductor device is mounted, and has the above-mentioned first metal wiring joined to all of the above-mentioned one or more first source pads of the above-mentioned first semiconductor device and the above-mentioned second metal wiring joined to all of the above-mentioned one or more second source pads of the above-mentioned first semiconductor device on the above-mentioned first surface of the mounting substrate; the above-mentioned first semiconductor device is mounted face down on the above-mentioned mounting substrate with the angle between each side of the above-mentioned first semiconductor device and the above-mentioned extension direction be 45 degrees.

31. The semiconductor module according to claim 30, wherein a second semiconductor device is further provided as the semiconductor device according to claim 6; in a plan view of the mounting substrate, The first semiconductor device is mounted face down on the first surface with the position of the first gate pad of the first semiconductor device located on the first extension side in the extension direction of the length direction; The second semiconductor device is mounted face down on the first surface in a position parallelly moved in the extension direction of the length direction with respect to the first semiconductor device with the second imaginary straight line of the first semiconductor device and the second imaginary straight line of the second semiconductor device parallel; The first metal wiring is further joined to all of the one or more first source pads of the second semiconductor device; The second metal wiring is further joined to all of the one or more second source pads of the second semiconductor device; The mounting substrate further has a third through-hole through which a third conductor electrically connected to the first gate pad of the second semiconductor device passes, and a fourth through-hole through which a fourth conductor electrically connected to the second gate pad of the second semiconductor device passes; The first through-hole, the second through-hole, the third through-hole, and the fourth through-hole are located between the first metal wiring and the second metal wiring in the extension direction of the length direction of the mounting substrate.

32. A semiconductor module comprising: a first semiconductor device according to claim 21; a second semiconductor device according to claim 21; and a mounting substrate on which the first semiconductor device and the second semiconductor device are mounted face down on a first surface, in a plan view of the mounting substrate, the mounting substrate has a width at least at a portion on which the first semiconductor device and the second semiconductor device are mounted and extends in a length direction; the second semiconductor device is mounted face down on the first surface in a position parallelly moved in the extension direction of the length direction with respect to the first semiconductor device with the same orientation as the first semiconductor device; the mounting substrate has a first metal wiring, a second metal wiring, and a third metal wiring arranged in order in the extension direction of the length direction on the first surface of the mounting substrate, the first metal wiring is joined to all of the one or more first source pads of the first semiconductor device, the second metal wiring is joined to all of the one or more second source pads of the first semiconductor device and all of the one or more first source pads of the second semiconductor device, and the third metal wiring is joined to all of the one or more second source pads of the second semiconductor device.

33. A semiconductor module comprising: a first semiconductor device according to claim 21; a second semiconductor device according to claim 21; and a mounting substrate on which the first semiconductor device and the second semiconductor device are mounted face down on a first surface, in a plan view of the mounting substrate, the mounting substrate has a width at least at a portion on which the first semiconductor device and the second semiconductor device are mounted and extends in a length direction; ​ The above-mentioned second semiconductor device is mounted on the above-mentioned first surface with the same orientation as the above-mentioned first semiconductor device after being moved substantially in parallel in a direction in which the above-mentioned imaginary straight line extends with respect to the above-mentioned first semiconductor device; The above-mentioned mounting substrate has a shape extending in a length direction with a certain width at least at portions where the above-mentioned first semiconductor device and the above-mentioned second semiconductor device are mounted, has a first metal wiring and a second metal wiring arranged in an extending direction of the above-mentioned length direction on a first surface of the above-mentioned mounting substrate, the above-mentioned first metal wiring is joined to all of the above-mentioned one or more first source pads of the above-mentioned first semiconductor device and all of the above-mentioned one or more first source pads of the above-mentioned second semiconductor device, and the above-mentioned second metal wiring is joined to all of the above-mentioned one or more second source pads of the above-mentioned first semiconductor device and all of the above-mentioned one or more second source pads of the above-mentioned second semiconductor device.

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