A multi-chip packaging structure, a switch

Abstract

Embodiments of the present application provide a multi-chip packaging structure and a switch, relating to a multi-chip packaging structure and a switch, which are used to solve the problem that switches with different switching capabilities require the preparation of switch chips with corresponding switching capacities, resulting in relatively high manufacturing costs. The multi-chip packaging structure includes a packaging substrate and a plurality of switch chips disposed on the packaging substrate. The switch chip includes at least two network interfaces and at least one chip-to-chip D2D interface. The switch chip is used to access the network through at least two network interfaces and transmit and receive data with the network. The switch chip is also used to connect to another switch chip through each of at least one D2D interface and transmit and receive data with each other. The switch chip is further used to forward the data received from at least two network interfaces or at least one D2D interface to at least one of at least two network interfaces and at least one D2D interface.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular, to a multi-chip package structure and a switch. Background Art

[0002] A switch is a network device used to forward electrical signals or optical signals. Multiple interfaces are provided on the switch, and data transmission can be achieved through any one of the multiple interfaces. The most common switch is an Ethernet switch that transmits data based on Ethernet. The interfaces of the switch can be directly connected to a host. The switch can connect multiple pairs of interfaces simultaneously, enabling collision-free data transmission between each pair of communicating hosts.

[0003] A switch chip is provided in the switch, and the switching capacity of the switch chip can determine the data switching ability of the switch. The larger the switching capacity of the switch chip, the higher the data switching ability of the switch, the more ports that can be set on the switch, and the larger the number of hosts it can connect. However, the switching capabilities required by different types of users for switches also vary. As a result, switch chips with corresponding switching capacities need to be manufactured according to the needs of different users, which is not conducive to reducing production costs. Summary of the Invention

[0004] Embodiments of this application provide a multi-chip package structure and a switch, which are used to solve the problem that switches with different switching capabilities require the preparation of switch chips with corresponding switching capacities, resulting in relatively high manufacturing costs.

[0005] To achieve the above object, this application adopts the following technical solutions:

[0006] In one aspect of the embodiments of the present application, a multi-chip packaging structure is provided. The multi-chip packaging structure includes a packaging substrate and at least multiple switch chips disposed on the packaging substrate. The switch chip includes at least two network interfaces and at least one chip-to-chip D2D interface. The switch chip is used to access the network through at least two network interfaces and send and receive data with the network. The switch chip is also used to connect to another switch chip through each D2D interface in at least one D2D interface and send and receive data with each other. The switch chip is further used to forward the data received from at least two network interfaces or at least one D2D interface to at least one of at least two network interfaces and at least one D2D interface. In this case, when there is one switch chip in the switch, the switching bandwidth of the switch chip is the actual switching bandwidth of the switch. At this time, the D2D interface of the switch chip can be in an idle state without being electrically connected to other chips. When there are multiple switch chips in the switch with the same switching bandwidth and they can be electrically connected end to end in sequence through their respective D2D interfaces, the actual switching bandwidth of the switch is the sum of the switching bandwidths of each switch chip inside it. In this way, in the solution provided by the embodiments of the present application, in order to obtain switches with different switching bandwidths, there is no need to separately manufacture corresponding switch chips for different switching bandwidths. Instead, only one type of switch chip needs to be produced, and according to the requirements of the switching bandwidth of the switch, the number of switch chips in the switch is set, and multiple switch chips with the same switching bandwidth are electrically connected through their respective D2D interfaces, then a series of switches with different switching bandwidths can be obtained, achieving the purpose of cost reduction. Moreover, in the same multi-chip packaging structure, the D2D interfaces of all switch chips are electrically connected end to end in sequence. In this way, the switching bandwidth of the multi-chip packaging structure can be the sum of the switching bandwidths of all switch chips in the multi-chip packaging structure, so that the switching bandwidth of the entire switch can be larger, for example, it can reach 50 Tbps, 100 Tbps or even larger.

[0007] Optionally, the switch chip further includes control logic, and the control logic is used to: obtain the destination information of the received data from the received data. Then, determine the sending port according to the destination information, and the sending port includes at least one D2D interface and at least two network interfaces in the current switch chip, and then send the received data through the sending port. Thus, the switch chip can implement the process of data forwarding and switching.

[0008] Optionally, multiple switch chips include a source switch chip and a destination switch chip. After the source switch chip determines the sending port according to the destination information, the control logic of the source switch chip is further configured to: determine at least one sending path between the source switch chip and the destination switch chip, queue and buffer the received data, and send a scheduling request to the destination switch chip. In addition, before the destination switch chip sends the received data through the sending port, the control logic of the destination switch chip is further configured to: generate a scheduling result according to the scheduling request and the bandwidth of the destination switch chip; the control logic of the source switch chip is further configured to: according to the scheduling result, dequeue the received data from the queue, and send the received data to the destination switch chip through at least one sending path. In this way, data exchange can be achieved between multiple electrically connected switch chips by sending scheduling requests, generating scheduling results, and sending data according to the scheduling results.

[0009] Optionally, the multi-chip package structure includes four switch chips. Each switch chip includes two D2D interfaces for respectively connecting with the D2D interfaces of the other two switch chips. The four switch chips are electrically connected end to end in sequence. In this way, two adjacent switch chips are electrically connected to each other, so the length of the metal lead used to electrically connect two adjacent switch chips does not need to be too long, thereby improving the signal transmission efficiency.

[0010] Optionally, the source switch chip is adjacent to the destination switch chip. The control logic of the source switch chip is specifically configured to: determine a sending path, and send the received data to the destination switch chip through the sending path; where the sending path includes: from the source switch chip to the destination switch chip. In this way, data forwarding between adjacent switch chips can be achieved through the above sending path.

[0011] Optionally, among the four switch chips, there is an intermediate switch chip between the source switch chip and the destination switch chip. The control logic of the source switch chip is specifically configured to: determine a sending path, and send the received data to the destination switch chip through the sending path; where the sending path includes: from the source switch chip, through the intermediate switch chip to the destination switch chip. In this way, data forwarding between two switch chips arranged at intervals can be achieved through the above first sending path.

[0012] Optionally, among the four switch chips, along the first direction, a first intermediate switch chip is spaced between the source switch chip and the destination switch chip, and along the second direction, a second intermediate switch chip is spaced between the source switch chip and the destination switch chip; wherein, the first direction and the second direction are opposite. The control logic of the source switch chip is specifically used for: determining a first transmission path, and sending a part of the received data to the destination switch chip through the first transmission path. Wherein, the first transmission path includes: from the source switch chip, through the first intermediate switch chip to the destination switch chip. Determining a second transmission path, and sending another part of the received data to the destination switch chip through the second transmission path. Wherein, the second transmission path includes: from the source switch chip, through the second intermediate switch chip to the destination switch chip. In this way, since the data transmission directions of the first transmission path and the second transmission path are opposite, when data is forwarded between non-adjacent switch chips in the switch, the traffic of a part of the data can be transmitted along the first transmission path, and the traffic of another part can be forwarded along the second transmission path, improving the data transmission efficiency.

[0013] Optionally, the switch chip further includes a switching buffer unit and a transmission link. Wherein, the switching buffer unit is used to execute the control logic of the above-mentioned sending scheduling request, generating a scheduling result, and sending data according to the scheduling result. The transmission link is electrically connected to the D2D interface and the switching buffer unit, and the transmission link is used for receiving and sending data between the D2D interface and the switching buffer unit, and between different D2D interfaces. The data exchanged between multiple switch chips can be transmitted through the transmission link.

[0014] Optionally, the transmission link includes a first link and a second link. The first link includes a first receiving-end media access control (MAC) interface, a first buffer, and a first transmitting-end MAC interface that are electrically connected in sequence. The first receiving-end MAC interface and the first transmitting-end MAC interface are respectively electrically connected to two direct-to-die (D2D) interfaces of the switch chip. The first receiving-end MAC interface and the first buffer are also electrically connected to the switching buffer unit. In this way, the first receiving-end MAC interfaces and the first transmitting ends of multiple switch chips in the switch are electrically connected in sequence, so that the first links of multiple switch chips can be electrically connected, enabling data of multiple switch chips to be transmitted among different switch chips through the first link. Moreover, the data cached in the first buffer can be queued in the first buffer in a first-in-first-out (FIFO) manner and sent to the first transmitting-end MAC interface of the switch chip, thus avoiding data conflicts from the first receiving-end MAC interface and the output buffer processing unit. In addition, the data transmission direction in the second link is opposite to that in the first link. The second link includes a second receiving-end MAC interface, a second buffer, and a second transmitting-end MAC interface that are electrically connected in sequence. The second receiving-end MAC interface and the second transmitting-end MAC interface are respectively electrically connected to two D2D interfaces of the switch chip. The second receiving-end MAC interface and the second buffer are also electrically connected to the switching buffer unit. The technical effects of the second link and the second buffer are the same and will not be elaborated here. In addition, since the data transmission direction in the second link is opposite to that in the first link, when data is forwarded between non-adjacent switch chips in the switch, part of the data traffic can be transmitted along the first link, and the other part of the traffic can be forwarded along the second link, improving the data transmission efficiency.

[0015] Optionally, four switch chips are arranged in a 2×2 matrix form. In the multi-chip packaging structure, the first links of the four switch chips are electrically connected end to end in sequence to form a ring. The second links of the four switch chips are electrically connected end to end in sequence to form a ring. In this way, one switch chip can be electrically connected to another switch chip on its left (or right) and above (or below) through the first link and the second link. Since the two adjacent switch chips are electrically connected to each other, the length of the metal leads used to electrically connect the two adjacent switch chips does not need to be too long, thereby improving the signal transmission efficiency.

[0016] Optionally, the switch chip further includes a forwarding processing unit, a third receiving-end MAC interface, and a third transmitting-end MAC interface. The forwarding processing unit is used to execute the control logic for the above data forwarding. For example, according to the source address of the data from the network interface, obtain its destination address, and write the data into the switching cache unit. When the switch chip performs layer-2 forwarding, the forwarding processing unit can read the source MAC address in the data packet header, then read the destination MAC address in the data packet header, and look up the interface corresponding to the destination MAC address in the MAC address table. Alternatively, when the switch chip performs layer-3 forwarding, the forwarding processing unit can read the source IP address in the data packet header, then read the destination IP address in the data packet header, and look up the interface corresponding to the destination MAC address in the IP address table. In addition, the forwarding processing unit is electrically connected to the network interface and the switching cache unit. The forwarding processing unit is used to read data from the switching cache unit and send it to the network interface. When the switch chip performs layer-3 forwarding, the forwarding processing unit needs to change the source MAC address and the destination MAC address in the data packet header to complete the layer-2 encapsulation. The third receiving-end MAC interface is electrically connected to the network interface and the forwarding processing unit, and is used to transmit the data from the network interface to the forwarding processing unit. The third transmitting-end MAC interface is electrically connected to the network interface and the forwarding processing unit, and is used to transmit the data from the forwarding processing unit to the network interface.

[0017] Optionally, in the multi-chip package structure, the switching bandwidth of any two switch chips is the same. In this way, only one type of switch chip needs to be produced, and according to the requirement of the switching bandwidth of the switch, the number of switch chips in the switch is set, and multiple switch chips with the same switching bandwidth are electrically connected through their respective D2D interfaces, so that a series of switches with different switching bandwidths can be obtained, achieving the purpose of cost reduction.

[0018] Optionally, the multi-chip package structure further includes a plurality of optical modules disposed on the package substrate and on the same side as the switch chip. In this way, by encapsulating the optical module and the switch chip in the same multi-chip package structure, the switch can have an optical interface with a larger switching bandwidth.

[0019] On the other hand, an embodiment of the present application provides a switch. The switch includes a circuit board and any one of the above multi-chip package structures disposed on the circuit board. The switch has the same technical effects as the switch chip provided in the foregoing embodiment, and will not be described herein again.

[0020] In another aspect of the embodiments of the present application, a switch is provided. The switch includes a circuit board and at least two multi-chip packaging structures as described above disposed on the circuit board. The D2D interfaces of all the switch chips on the circuit board are electrically connected end to end in sequence. The switch has the same technical effects as the switch chip provided in the foregoing embodiments, which will not be elaborated herein.

[0021] Optionally, on the same circuit board, the switching bandwidths of any two switch chips are the same. In this way, the switching bandwidth of the switch can be the sum of the switching bandwidths of all the switch chips in the switch, so that the switching bandwidth of the entire switch can be larger, for example, it can reach 50 Tbps, 100 Tbps or even larger. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic structural diagram of a switching network provided by an embodiment of the present application;

[0023] Figure 2 is Figure 1 a schematic structural diagram of the switch in

[0024] Figure 3a is Figure 2 a schematic structural diagram of the multi-chip packaging structure in

[0025] Figure 3b is Figure 2 another schematic structural diagram of the multi-chip packaging structure in

[0026] Figure 4 is Figure 2 another schematic structural diagram of the multi-chip packaging structure in

[0027] Figure 5 is Figure 1 another schematic structural diagram of the switch in

[0028] Figure 6 is Figure 2 another schematic structural diagram of the multi-chip packaging structure in

[0029] Figure 7 is Figure 2 another schematic structural diagram of the multi-chip packaging structure in

[0030] Figure 8 It is a schematic structural diagram of a switch chip provided by an embodiment of the present application;

[0031] Figure 9 It is another schematic structural diagram of a switch chip provided by an embodiment of the present application;

[0032] Figure 10a is a plurality of such as Figure 9A schematic diagram of the electrical connection of the switch chip shown;

[0033] Figure 10b For multiple as Figure 9 Another schematic diagram of the electrical connection of the switch chips shown;

[0034] Figure 11 A data forwarding flowchart of the switch provided by the embodiment of the present application.

[0035] Reference numerals:

[0036] 01 - Switching network; 10 - Switch; 11 - Electronic device; 101 - Ethernet interface; 20 - Multi-chip package structure; 201 - Package substrate; 12 - Circuit board; 202 - Switch chip; 30 - Network interface; 31 - D2D interface; 100 - Ring bus; 203 - Optical engine; 40 - SWB; 41 - Transmission link; 401 - IB; 402 - EB; 411 - First link; 412 - Second link; 51 - First buffer; 52 - Second buffer. Detailed implementation manners

[0037] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0038] Hereinafter, terms such as "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features.

[0039] In addition, in the present application, orientation terms such as "upper", "lower", "left", and "right" are defined with respect to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, and they are used for relative description and clarification, and they may change accordingly with the change of the orientation of the components placed in the accompanying drawings.

[0040] In the present application, unless otherwise clearly defined and limited, the term "connection" should be understood in a broad sense. For example, "connection" may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium. In addition, the term "electrical connection" may be a direct electrical connection or an indirect electrical connection through an intermediate medium.

[0041] The switching network 01 provided by the embodiment of the present application is as Figure 1As shown in the figure, it may include at least one switch 10 and a plurality of electronic devices 11 electrically connected to the switch. The above-mentioned electronic devices 11 may be servers, computers, mobile terminals, data storage devices, network components, network devices, routers, switches, etc. Each of the electronic devices 11 in the above-mentioned switching network 01 may be electrically connected to one or more Ethernet interfaces 101 of the switch 10 through Ethernet transmission lines. In this case, the above-mentioned switch 10 may provide packet forwarding between multiple physical Ethernet interfaces 101, so that each of the electronic devices 11 in the switching network 01 can be electrically connected to each other through the switch 10 and communicate with each other.

[0042] In the switch 10 provided in the embodiment of the present application, as Figure 2 shown, it may include a circuit board 12, such as a printed circuit board (PCB), and at least one chip package structure 20 disposed on the circuit board 12. The multi-chip package structure 20 may include a package substrate 201 and at least one switch chip (die or chiplet) 202 disposed on the package substrate 201.

[0043] In the embodiment of the present application, any one of the switch chips 202 in the multi-chip package structure 20, as Figure 3a shown, may include at least two network interfaces 30 and at least one die-to-die (D2D) interface 31. The above-mentioned network interfaces 30 and D2D interfaces 31 serve as physical layer interfaces of the open system interconnection reference model (OSI model).

[0044] Among them, the switch chip 202 is used to access the network (such as Ethernet) through the above-mentioned at least two network interfaces 30 and send and receive data with the network. For example, the above-mentioned network interfaces 30 may be electrically connected to the Figure 1 shown physical Ethernet interfaces 101. The network interfaces 30 may receive data sent by each of the electronic devices 11 in the Ethernet. Or, the network interfaces 30 may send data to each of the above-mentioned electronic devices 11.

[0045] Exemplarily, the above network interface 30 can be a serializer - deserializer (SerDes) interface. For example, the above network interface 30 can be a very short reach (VSR) interface in the SerDes interface, which is used to connect the chip to a pluggable optical module. For the convenience of description hereinafter, in the drawings, the network interface is taken as an example of the VSR interface.

[0046] In an embodiment of the present invention, a switch chip 202 may include at least one D2D interface 31 and at least two network interfaces 30. Each D2D interface 31 in the at least one D2D interface 31 of a switch chip 202 is connected to another switch chip, and the two network interfaces 30 are respectively connected to the two Ethernet interfaces 101 of the switch 10. The switch chip 202 is used to be connected to another switch chip 202 through each D2D interface 31 in the at least one D2D interface 31 to transceive data therebetween. In addition, the switch chip 202 is further used to forward the data received from at least two network interfaces 30 or at least one D2D interface 31 to at least one of the at least two network interfaces 30 and the at least one D2D interface 31.

[0047] For the convenience of description, hereinafter, an example in which a switch chip 202 includes one D2D interface 31 and two network interfaces 30 is taken. In this case, the data from different network interfaces 30 can exchange data with other switch chips 202 through the D2D interface 31, and transceive data with the ports of at least two receivers and the external network.

[0048] It can be seen therefrom that the D2D interface 31 can be used to electrically connect between two switch chips 202, that is, die to die. In an embodiment of the present application, the D2D interface 31 can be a SerDes interface. For example, D2D can be an extreme short reach (XSR) interface in the SerDes interface, which is used to implement the electrical connection between chips. The trace length of the XSR interfaces fabricated on the PCB 12 can be 0 - 50 mm. Or, the D2D interface 31 can also be a parallel interface, such as an advanced interface bus (AIB).

[0049] Based on this, the switch chip 202 provided in the embodiment of the present application may include a processor, and the forwarding processing unit in the processor may be used to execute control logic. The control logic is used to obtain the destination information of the received data from the data received from the network interface 30 or the D2D interface 31. For example, the destination information may be the destination address of the received data. Then, the above control logic may be used to determine the sending port according to the destination information. The sending port includes the at least one D2D interface 31 and the at least two network interfaces 30 in the current switch chip. Next, the above control logic is further used to send the received data through the sending port, thereby implementing the data forwarding process.

[0050] It should be noted that in the embodiment of the present application, when multiple switch chips 202 are encapsulated in the chip packaging structure 20, the chip packaging structure 20 may be a multi-chip module (MCM) structure in which multiple switch chips 202 are directly disposed on a packaging substrate (substrate). Or, the chip packaging structure 20 may be a 2.5D packaging structure in which multiple switch chips 202 are disposed on an interposer by using a chip on wafer on substrate (COWOS) technology. Or, in some other embodiments, the above chip packaging structure 20 may be a fan-out package (FOP) structure in which multiple switch chips 202 are disposed on a redistribution layer (RDL) by using a fan-out package technology. Or, the above chip packaging structure 20 may be an embedded multi-die interconnect bridge (EMIB) packaging structure in which a connector is disposed in the packaging substrate and multiple switch chips 202 disposed on the packaging substrate are electrically connected through the connector.

[0051] On this basis, when the switch 10 includes at least two switch chips, for example, as Figure 3b shown by the switch chip 202a and the switch chip 202b, the switching bandwidth between any two switch chips on the same PCB 12 may be the same, for example, both are 12.8 Tbps. The following examples illustrate the setting methods of multiple switch chips 202 in the switch 10 according to different requirements of the switching bandwidth of the switch 10.

[0052] It should be noted that the switching bandwidth of the switch 10 in the present application is used to measure the total data switching ability of the switch 10. For example, when the switching bandwidth of the switch 10 is 50 Tbps, the data transmission rate of the switch 10 is 50 megabits per second.

[0053] Example 1

[0054] In this example, the preset switching bandwidth of the switch 10 is 50 Tbps. The switch 10 may include a multi-chip package structure 20 as shown in Figure 4 . At this time, the multi-chip package structure 20 may include four switch chips located on the same package substrate 201, namely switch chip 202-A, switch chip 202-B, switch chip 202-C, and switch chip 202-D.

[0055] In this case, in order to make the actual switching bandwidth of the switch 10 reach the above preset switching bandwidth (for example, 50 Tbps), the switch chips 202-A, 202-B, 202-C, and 202-D in the multi-chip package structure 20 may all be chips with a switching bandwidth of 12.8 Tbps prepared by using a 7 nm (the minimum line width of transistors in the chip) chip manufacturing process.

[0056] Based on this, the D2D interfaces 31 of the switch chips 202-A, 202-B, 202-C, and 202-D in the multi-chip package structure 20 are electrically connected end to end (one by one) in sequence to form a ring bus 100. For example, the D2D interface 31 of the switch chip 202-A is electrically connected to the D2D interface 31 of the switch chip 202-B. The D2D interface 31 of the switch chip 202-B is electrically connected to the D2D interface 31 of the switch chip 202-C. The D2D interface 31 of the switch chip 202-C is electrically connected to the D2D interface 31 of the switch chip 202-D.

[0057] In some embodiments of the present application, when the source switch chip for sending data and the destination switch chip for receiving data are adjacent, for example, the switch chip 202-A as the source switch chip can directly send data to the switch chip 202-B as the destination switch chip. Alternatively, in some other embodiments of the present application, when there is an intermediate switch chip between the source switch chip and the destination switch chip, for example, when the switch chip 202-A as the source switch chip sends data to the switch chip 202-C as the destination switch chip, the data sent by the switch chip 202-A can be transmitted to the switch chip 202-C in the clockwise direction after passing through the switch chip 202-B as the first intermediate switch chip. Alternatively, the data sent by the switch chip 202-A can be transmitted to the switch chip 202-C in the counterclockwise direction after passing through the switch chip 202-D as the second intermediate switch chip. Or, a part of the data sent by the switch chip 202-A as the source switch chip can be transmitted to the switch chip 202-C in the clockwise direction after passing through the switch chip 202-B as the first intermediate switch chip. The other part of the above data can be transmitted to the switch chip 202-C in the counterclockwise direction after passing through the switch chip 202-D as the second intermediate switch chip.

[0058] The D2D interface 31 of any one of the above switch chips 202-A, switch chip 202-B, switch chip 202-C, and switch chip 202-D can be a 128L-112G-XSR interface. Among them, the 128L-112G-XSR interface represents a 128-lane XSR interface, and the data transmission rate of each XSR interface is 112 Gbps. In this way, the bandwidth of the transmission circuit formed between two adjacent electrically connected D2D interfaces 31 for unidirectional data transmission is 14.3 Tbps (128×112 = 14.3 Tbps). At this time, the above transmission link can be used to carry 12.8 Tbps of Ethernet traffic for each switch chip when unidirectionally transmitting data, such as receiving data or sending data. And the remaining traffic of 1.5 Tbps (14.3 Tbps - 12.8 Tbps = 1.5 Tbps) can be used for internal consumption (over header).

[0059] It should be noted that the data transmitted between the D2D interfaces 31 of multiple switch chips has an address on its packet header, and this address needs to occupy a certain number of bytes. In addition, in addition to transmitting data, the D2D interfaces 31 of the above-mentioned multiple switch chips also need to transmit scheduling instructions and scheduling results related to this data. These scheduling instructions and scheduling results also need to occupy a certain number of bytes. Therefore, the traffic for internal consumption mentioned above can be used to transmit addresses, scheduling instructions, and scheduling results related to data. For example, the remaining traffic transmitted by the D2D interface 31 of each switch chip can be the switching bandwidth of this switch chip, such as about 10% of 12.8 Tbps. The above-mentioned addresses, scheduling instructions, and scheduling results related to data will be described in detail in the following embodiments.

[0060] However, on the above-mentioned ring bus 100, any D2D interface 31 of a switch chip can both receive data and send data. Therefore, when adjacent two electrically connected D2D interfaces 31 simultaneously receive and send data, the two-way bandwidth of the formed transmission link is 2 times 14.3 Tbps. In addition, on the ring bus 100, any switch chip can act as a source switch chip and also as a destination switch chip at the same time. When 4 switch chips on the ring bus 100 simultaneously receive and send data, the bandwidth of the transmission link formed on the above-mentioned ring bus 100 can be 8 (2×4) times 14.3 Tbps. At this time, each D2D interface 31 in the multi-chip package structure 20 is in a state of receiving and sending data.

[0061] Considering that the bandwidth of the above-mentioned transmission link formed inside the switch 10 has an acceleration ratio, the total switching bandwidth actually reflected by the switch 10 externally is the sum of the switching bandwidths of each switch chip 202 inside it. For example, the switching bandwidth of 4 times 14.3 Tbps, that is, 51.2 Tbps (4×14.3 = 51.2 Tbps), enables the switch 10 to have a line speed non-blocking switching ability of 51.2 Tbps, and this switching bandwidth is greater than the preset switching bandwidth of the switch 10 (for example, 50 Tbps).

[0062] In addition, the shape of the vertical projection of the switch chip 202 in the embodiment of the present application on the package substrate 201 or the PCB can be a rectangle or a square, and the embodiment of the present application does not limit this. Taking the shape of the vertical projection of the switch chip 202 on the package substrate 201 or the PCB can be a rectangle as an example, for example, Figure 4As shown, in the multi-chip package structure 20, the short side L1 of any one of the switch chips 202-A, 202-B, 202-C, and 202-D can be 25.5 mm, and the long side L2 can be 27.5 mm. For convenience of description below, most of the embodiments are described by taking the shape of the vertical projection of the above switch chips on the package substrate 201 or the PCB as a rectangle as an example.

[0063] In addition, by way of example, the network interface 30 of any one of the above switch chips 202-A, 202-B, 202-C, and 202-D can be a 64L-112G-VSR interface, or a 128L-112G-VSR interface. Among them, the 64L-112G-VSR interface represents a 64-channel VSR interface, and the data transmission rate of each VSR interface is 112 Gbps. At this time, the unidirectional data transmission bandwidth of the network interface 30 is 7.168 Tbps (64×112 = 7.168 Tbps).

[0064] In addition, the 128L-112G-VSR interface represents a 128-channel VSR interface, and the data transmission rate of each VSR interface is 112 Gbps. At this time, the unidirectional data transmission bandwidth of the network interface 30 is 14.3 Tbps (128×112 = 14.3 Tbps). The unidirectional data transmission bandwidth of the network interface 30 can be set according to the size of the transmission traffic of the electronic device 11 electrically connected to the network interface 30, and the present application does not limit this.

[0065] Example Two

[0066] In this example, the preset switching bandwidth of the switch 10 is 50 Tbps. The switch 10 can include two multi-chip package structures, namely the multi-chip package structure 20a and the multi-chip package structure 20b as shown. Figure 5 Among them, each multi-chip package structure can include two switch chips. For example, the multi-chip package structure 20a includes the switch chip 202-A and the switch chip 202-D, and the multi-chip package structure 20b includes the switch chip 202-B and the switch chip 202-C.

[0067] In addition, the switching bandwidths of any two switch chips in each multi-chip package structure can be the same. Moreover, between different multi-chip package structures, the switching bandwidths of any two switch chips can be the same. In this way, the switching bandwidths of all the switch chips in switch 10 can be equal. In this case, the above-mentioned switch chip 202-A, switch chip 202-B, switch chip 202-C, and switch chip 202-D can all be chips with a switching bandwidth of 12.8 Tbps fabricated using a 7nm chip manufacturing process.

[0068] Moreover, on the circuit board 12 in switch 10, the D2D interfaces 31 of all the switch chips are electrically connected end to end in sequence to form a ring bus 100. For example, the D2D interface 31 of switch chip 202-A in multi-chip package structure 20a is electrically connected to the D2D interface 31 of switch chip 202-B. The D2D interface 31 of switch chip 202-B in multi-chip package structure 20a is electrically connected to the D2D interface 31 of switch chip 202-C in multi-chip package structure 20b. The D2D interface 31 of switch chip 202-C in multi-chip package structure 20b is electrically connected to the D2D interface 31 of switch chip 202-D in multi-chip package structure 20a.

[0069] As can be seen from the above, the preset switching bandwidths of switch 10 in both Example 1 and Example 2 are 50 Tbps. This switch 10 includes four switch chips (switch chip 202-A, switch chip 202-B, switch chip 202-C, and switch chip 202-D), and the switching bandwidth of each switch chip is 12.8 Tbps. The difference lies in that in Example 1, the four switch chips are all co-packaged in the same multi-chip package structure 20. In this way, the total power consumption of the above multi-chip package structure may exceed 1000 W, and the total power consumption is relatively large. In Example 2, the above four switch chips are co-packaged in multi-chip package structures 20a and 20b in pairs, so that each multi-chip package structure contains two switch chips, thereby reducing the power consumption of each multi-chip package structure by half, for example, reducing it to about 500 W.

[0070] In summary, when there is one switch chip 202 in switch 10, the switching bandwidth of this switch chip 202, such as 12.8 Tbps, is the actual switching bandwidth of switch 10. At this time, the D2D interface 31 of this switch chip 202 can be in a vacant state and not be electrically connected to other chips. When there are multiple switch chips 202 with the same switching bandwidth in switch 10 and they are electrically connected end to end in sequence through their respective D2D interfaces 31, the actual switching bandwidth of this switch 10 is the sum of the switching bandwidths of each switch chip 202 inside it.

[0071] For example, when two switch chips 202 (12.8 Tbps) are provided in the switch 10, the actual switching bandwidth of the switch 10 is 25.6 Tbps (2 × 12.8 Tbps). Or, when three switch chips 202 (12.8 Tbps) are provided in the switch 10, the actual switching bandwidth of the switch 10 is 38.4 Tbps (3 × 12.8 Tbps). Or, when four switch chips 202 (12.8 Tbps) are provided in the switch 10, the actual switching bandwidth of the switch 10 is 51.2 Tbps (4 × 12.8 Tbps).

[0072] The manner of providing the remaining number of switch chips 202 in the switch 10 is the same as described above and will not be elaborated here. Among them, when multiple switch chips 202 are provided in the switch 10, the above-mentioned multiple switch chips 202 can be co-packaged in the same multi-chip package structure in the manner of Example 1. Or, they can also be packaged in different multi-chip package structures in the manner of Example 2.

[0073] In this way, in the solution provided by the embodiment of the present application, in order to obtain switches 10 with different switching bandwidths, there is no need to separately manufacture corresponding switch chips for different switching bandwidths. Instead, only one type of switch chip 202 (for example, with a switching bandwidth of 12.8 Tbps) needs to be produced, and the number of switch chips 202 in the switch 10 is set according to the switching bandwidth requirement of the switch 10. Then, multiple switch chips 202 with the same switching bandwidth are electrically connected end to end in sequence in the above manner, and a series of switches 10 with different switching bandwidths can be obtained, achieving the purpose of cost reduction.

[0074] The above takes the preset switching bandwidth of the switch 10 being 50 Tbps as an example to illustrate the setting manner of the switch chips 202 in the switch 10. The following illustrates the setting manner of the switch 10 with other preset switching bandwidths.

[0075] Example 3

[0076] In this example, the preset switching bandwidth of the switch 10 is 100 Tbps. The switch 10 may include a multi-chip package structure 20. At this time, the multi-chip package structure 20 may include four switch chips located on the same package substrate 201, namely the switch chip 202-A, switch chip 202-B, switch chip 202-C, and switch chip 202-D as shown Figure 4 in the figure.

[0077] In this case, in order to enable the actual switching bandwidth of the switch 10 to reach the above-mentioned preset switching bandwidth (for example, 100 Tbps), the switch chips 202-A, 202-B, 202-C, and 202-D in the multi-chip package structure 20 can all be chips with a switching bandwidth of 25.6 Tbps prepared by using a 5 nm (the minimum line width of the transistors in the chip) chip manufacturing process. In this way, the total switching bandwidth of the 4 switch chips with a switching bandwidth of 25.6 Tbps is 4 × 25.6 Tbps (4 × 25.6 = 102.4 Tbps), which can be greater than the preset switching bandwidth (for example, 100 Tbps).

[0078] Similarly, the D2D interfaces 31 of the switch chips 202-A, 202-B, 202-C, and 202-D in the multi-chip package structure 20 are electrically connected end to end in sequence to form a ring bus 100.

[0079] In this example, the D2D interface 31 of any one of the switch chips 202-A, 202-B, 202-C, and 202-D can be a 256L-112G-XSR interface. Among them, the 256L-112G-XSR interface represents 256 XSR interfaces, and the data transmission rate of each XSR interface is 112 Gbps. In this way, the unidirectional bandwidth of the transmission circuit formed between two adjacent electrically connected D2D interfaces 31 is 28.6 Tbps (256 × 112 = 28.6 Tbps). At this time, the above-mentioned transmission link can be used to carry the 25.6 Tbps Ethernet traffic of each switch chip when receiving data or sending data. And the remaining traffic of 3 Tbps (28.6 Tbps - 25.6 Tbps = 3 Tbps) can be used for the above-mentioned internal consumption.

[0080] In addition, for example, the network interface 30 of any one of the switch chips 202-A, 202-B, 202-C, and 202-D can be a 128L-112G-VSR interface.

[0081] Similarly, the above four switch chips are all co-packaged in the same multi-chip package structure 20. In this way, the total power consumption of the multi-chip package structure 20 may exceed 2000W, and the total power consumption is relatively large. Therefore, in order to reduce the power consumption of a single multi-chip package structure, the above four switch chips can be co-packaged in two different multi-chip package structures in pairs. As described above, two switch chips can be packaged in each multi-chip package structure, so that the power consumption of each multi-chip package structure can be reduced by half, for example, reduced to about 1000W.

[0082] In the multi-chip package structure 20 in the above Example 1, Example 2, and Example 3, the description is made by taking only the switch chip 202 being co-packaged as an example. In some other embodiments of the present application, in addition to the switch chip 202 being provided in the multi-chip package structure 20, other components can also be co-packaged. The following describes the multi-chip package structure 20 with other components co-packaged and the structure of the switch 10 having the multi-chip package structure 20.

[0083] Example 4

[0084] In this example, in at least one multi-chip package structure 20 of the switch 10, not only the switch chip 202 as shown in Figure 6 is packaged, but also a plurality of optical engines (OE) 203 are packaged. In this case, the above plurality of OEs 203 and the switch chip 202 are disposed on the same side of the package substrate 201, and signal interconnection can be achieved through the package substrate 201.

[0085] Among them, each OE 203 can serve as at least one optical interface for connecting to an optical fiber. The OE 203 is also used to receive the optical signal in the optical fiber and convert the optical signal into an electrical signal. And, the electrical signal output by the switch chip 202 is received through the package substrate 201 and converted into an optical signal, which is transmitted into the above optical fiber, so that optical signal transceiver and processing can be performed.

[0086] For example, as Figure 7 shown, the preset switching bandwidth of the switch 10 is 100 Tbps. The switch 10 may include a multi-chip package structure 20. Similarly, the multi-chip package structure 20 may include four switch chips located on the same package substrate 201, which are respectively as shown in Figure 7The shown switch chips 202-A, switch chip 202-B, switch chip 202-C, and switch chip 202-D. The switching bandwidth of any one of the above switch chips can be 25.6 Tbps. The above switch chips 202-A, switch chip 202-B, switch chip 202-C, and switch chip 202-D are electrically connected end to end in sequence through their respective D2D interfaces 31 as described above, which will not be elaborated here.

[0087] In this example, the shape of the vertical projection of any one of the above switch chips on the encapsulation substrate 201 or the PCB can be a square. For example, in the multi-chip packaging structure 20, the side length of any one side of any one of the switch chips 202-A, switch chip 202-B, switch chip 202-C, and switch chip 202-D can be 26 mm.

[0088] In addition, in some embodiments of the present application, 32 OEs 203 can also be co-packaged in the above multi-chip packaging structure 20. When one OE 203 serves as 4 optical interfaces and the switching bandwidth of each optical interface is 800 Gbps, the switching bandwidth of one OE 203 is 3.2 Tbps (4×800 Gbps = 3.2 Tbps). In this case, the switch 10 can have 128 (32×4 = 128) optical interfaces with a switching bandwidth of 800 Gbps.

[0089] Alternatively, in some other embodiments of the present application, 32 OEs 203 can also be co-packaged in the above multi-chip packaging structure 20. When one OE 203 serves as 8 optical interfaces and the switching bandwidth of each optical interface is 400 Gbps, the switching bandwidth of one OE 203 is 3.2 Tbps (8×400 Gbps = 3.2 Tbps). In this case, the switch 10 can have 128 (32×8 = 256) optical interfaces with a switching bandwidth of 400 Gbps.

[0090] Or, in some other embodiments of the present application, 64 OEs 203 can also be co-packaged in the above multi-chip packaging structure 20. When one OE 203 serves as 4 optical interfaces and the switching bandwidth of each optical interface is 400 G, the switching bandwidth of one OE 203 is 1.6 Tbps (4×400 Gbps = 1.6 Tbps). In this case, the switch 10 can have 128 (64×4 = 256) optical interfaces with a switching bandwidth of 400 Gbps.

[0091] It should be noted that the above is only an example of the number of OEs 203 co-packaged in the multi-chip packaging structure 20 and their switching bandwidths, and other examples will not be elaborated one by one here.

[0092] As can be seen from the above, by providing multiple switch chips 202 in the multi-chip package structure 20 of the switch 10, and each switch chip 202 in the switch 10 can be electrically connected through the D2D interface 31, the switching bandwidth of the switch 10 can reach 50 Tbps, 100 Tbps or even larger. Currently, for switch chips fabricated using the 7nm (the minimum line width of transistors in the chip) chip fabrication process, the best achievable switching bandwidth is 25 Tbps. Therefore, the switch 10 provided in the embodiments of the present application can obtain a larger switching bandwidth, which is beneficial to improving the performance of the switch 10.

[0093] The structure of the switch chip 202 in any of the above embodiments is as Figure 8 shown. The switch chip 202 may include a transmission link 41 and a processor for executing control logic. The processor includes a switch buffer (SWB) 40 as Figure 8 shown.

[0094] Among them, the transmission link 41 is electrically connected to the D2D interface 31 and the SWB 40. The transmission link 41 is used for transmitting data between the D2D interface 31, the SWB 40, and different D2D interfaces 31. In this way, the data in the SWB 40 of the source switch chip can be transmitted through the transmission link 41 to the D2D interface 31 of the source switch chip 202, and sent to the D2D interface 31 of the destination switch chip through the D2D interface 31. In addition, when the D2D interface 31 of the destination switch chip receives the data output by the source switch chip 202, the data can also be transmitted through the transmission link 41 to the SWB 40 of the destination switch chip.

[0095] In addition, the SWB 40 is used to execute the following control logic. Exemplarily, after the source switch chip determines the sending port according to the destination information, the control logic executed by the SWB 40 of the source switch chip is further used to: determine at least one sending path between the source switch chip and the destination switch chip, queue and cache the received data, and send a scheduling request to the destination switch chip.

[0096] In addition, before the destination switch chip sends the received data through the sending port, the control logic executed by the SWB 40 of the destination switch chip is further used to: generate a scheduling result according to the scheduling request and the bandwidth of the destination switch chip. And the control logic executed by the SWB 40 of the source switch chip is further used to: according to the scheduling result, dequeue the received data, and send the received data to the destination switch chip through at least one sending path.

[0097] On this basis, the above SWB 40 is as Figure 9As shown, it may include an ingress buffer (IB) 401 and an egress buffer (EB) 402 that are electrically connected. Among them, the IB 401 is electrically connected to the network interface 30. The IB 401 is used to determine at least one transmission path between the source switch chip and the destination switch chip, queue and cache the data from the network interface 30 in the form of a virtual output queue (VOQ), and send a scheduling request to the EB 402 of the destination switch chip.

[0098] The EB 402 is electrically connected to the transmission link 41 and the network interface 30. The EB 402 is used to receive scheduling requests sent by multiple source switch chips, generate multiple scheduling results according to the bandwidth, and send the multiple scheduling results to the IB 401 of the multiple source switch chips respectively. When the IB 401 of the source switch chip receives the above scheduling results, the data packet can dequeue from the VOQ queue of the IB 401 according to the scheduling results, and send the received data through at least one transmission path to the EB 402 of the destination switch chip. On this basis, the EB 402 of the target switch chip is also used to cache the data that is about to be sent from the source switch chip to the network interface 30 of the destination switch chip.

[0099] In addition, as Figure 9 shown, the above transmission link 41 may include a first link 411 and a second link 412. Among them, the transmission direction of the data in the second link 412 (as Figure 9 shown by the arrow direction) is opposite to the transmission direction of the data in the first link 411 (as Figure 9 shown by the arrow direction). In addition, in the switch 10, the first links 411 of all the switch chips 202 are electrically connected end to end in sequence, and the second links 412 of all the switch chips 202 are electrically connected end to end in sequence.

[0100] For example, as Figure 10a shown, when the switch 10 has four switch chips, namely switch chip 202-A, switch chip 202-B, switch chip 202-C, and switch chip 202-D that are electrically connected end to end in sequence, when the switch chip 202-A is the source switch chip for sending data and the switch chip 202-C is the destination switch chip for receiving data, a part of the traffic of the data sent by the switch chip 202-A can be along the first link 411 of each switch chip ( Figure 10a the solid arrow in), and is transmitted to the switch chip 202-C through the switch chip 202-B along the arrow. In addition, another part of the traffic of the data sent by the switch chip 202-A can be in the second link 412 of each switch chip (Figure 10a In the dashed arrow in (), it is transmitted to the switch chip 202-C along the arrow through the switch chip 202-D, so as to improve the data.

[0101] In some embodiments of the present application, such as Figure 10b As shown, the above four switch chips in the same multi-chip package structure 20, such as switch chip 202-A, switch chip 202-B, switch chip 202-C, and switch chip 202-D, can be arranged in a 2×2 matrix form. The first link 411 of switch chip 202-A, switch chip 202-B, switch chip 202-C, and switch chip 202-D ( Figure 10b The solid arrow in) is electrically connected end to end in sequence to form a ring. The second link 412 of switch chip 202-A, switch chip 202-B, switch chip 202-C, and switch chip 202-D ( Figure 10b The dashed arrow in) is electrically connected end to end in sequence to form a ring.

[0102] In this way, a switch chip, such as switch chip 202-A, can be electrically connected to the switch chip 202-B on its left (or right), and the switch chip 202-D on its lower (or upper) side through the first link 411 and the second link 412. Since two adjacent switch chips that are electrically connected to each other, such as switch chip 202-A and switch chip 202-B (or switch chip 202-D), are adjacent, the length of the metal leads (not shown in the figure) used to electrically connect the two adjacent switch chips can be not too long, thereby improving the signal transmission efficiency.

[0103] For example, as Figure 9 As shown, the above first link 411 may include a first MAC interface (hereinafter referred to as MAC-Rx1) and a first transmitting-end MAC interface (hereinafter referred to as MAC-Tx1). Among them, MAC-Rx1 is electrically connected to MAC-Tx1 and EB402. In this case, the D2D interface 31 of each switch chip 202 may include D2D-Rx1 for receiving signals and D2D-Tx1 for transmitting signals. The above D2D-Rx1 and D2D-Tx1 are electrically connected to the first link 411 as Figure 9 shown.

[0104] Based on this, when the switch 10 includes at least two switch chips, two adjacent switch chips, such as Figure 10aAs shown in the figure, the MAC-Rx1 of the switch chip 202-B is electrically connected to the MAC-Tx1 of the switch chip 202-A through its own D2D interface (such as D2D-Rx1) and the D2D interface (such as D2D-Tx1) of another switch chip, such as the switch chip 202-A. The MAC-Rx1 of the above-mentioned switch chip 202-B is used to write the data from the D2D interface (such as D2D-Rx1) into the EB402 of the switch chip 202-B, or send it to the MAC-Tx1 of the switch chip 202-B.

[0105] In addition, as Figure 10a shown, the MAC-Tx1 of the switch chip 202-B is electrically connected to the EB402, and is electrically connected to the MAC-Rx1 of the switch chip 202-C through the D2D interface (such as D2D-Tx1) of the switch chip 202-B and the D2D interface (such as D2D-Rx1) of another switch chip, such as the switch chip 202-C. Since the MAC-Tx1 of the switch chip 202-B is also electrically connected to the MAC-Rx1 of the switch chip 202-B, the MAC-Tx1 of the switch chip 202-B is used to send the data from the MAC-Rx1 of the switch chip 202-B or the EB402 of the switch chip 202-B to the D2D interface (such as D2D-Tx1) of the switch chip 202-B.

[0106] In addition, from the above, as Figure 9 shown, in the same switch chip 202, the MAC-Tx1 receives the data from the MAC-Rx1 and the EB402. Therefore, in order to avoid conflicts between the data from the MAC-Rx1 and the EB402, the first link 411 further includes a first buffer (BF) 51. The first buffer 51 is electrically connected to the MAC-Rx1, MAC-Tx1, and EB402 of the switch chip 202. The first buffer 51 is used to cache the data sent from the MAC-Rx1 and the EB402 to the MAC-Tx1 in the same switch chip 202. In this way, the data cached in the first buffer 51 can be queued in the first buffer 51 in a first-in-first-out (FIFO) manner and sent to the MAC-Tx1.

[0107] Similarly, as Figure 9 shown, the second link 412 may include a second receiving-end MAC interface (hereinafter referred to as MAC-Rx2) and a second sending-end MAC interface (hereinafter referred to as MAC-Tx2). In the same switch chip 202, the MAC-Rx2 is electrically connected to the MAC-Tx2 and the EB402.

[0108] It should be noted that MAC-Rx1 and MAC-Tx1 in the first link 411, as well as MAC-Rx2 and MAC-Tx2 in the second link 412, can adopt the standard Ethernet protocol or a customized simplified standard.

[0109] In this case, the D2D interface 31 of each switch chip 202 can also include D2D-Rx2 for receiving signals and D2D-Tx2 for transmitting signals. The above D2D-Rx2 and D2D-Tx2 are Figure 9 electrically connected to the second link 412 as shown. Based on this, when the switch 10 includes at least two switch chips, two adjacent switch chips, for example, Figure 10a the MAC-Rx2 of the switch chip 202-B as shown is electrically connected to the MAC-Tx2 of this switch chip 202-C through its own D2D interface (such as D2D-Rx2) and the D2D interface (such as D2D-Tx2) of another switch chip, such as the switch chip 202-C. The MAC-Rx2 of the above switch chip 202-B is used to write the data from the D2D interface (such as D2D-Rx2) to the EB402 or send it to the MAC-Tx2 of the switch chip 202-B.

[0110] In addition, as Figure 10a shown, the MAC-Tx2 of the switch chip 202-B is electrically connected to the EB402 and is electrically connected to the MAC-Rx2 of the switch chip 202-A through the D2D interface (such as D2D-Tx2) of the switch chip 202-B and the D2D interface (such as D2D-Rx2) of another switch chip, such as the switch chip 202-A. Since the MAC-Tx2 of the switch chip 202-B is also electrically connected to the MAC-Rx2 of the switch chip 202-B, the MAC-Tx2 of this switch chip 202-B is used to send the data from the MAC-Rx2 of the switch chip 202-B or the EB402 of the switch chip 202-B to the D2D interface (such as D2D-Tx2) of this switch chip 202-B.

[0111] In addition, as can be seen from the above, as Figure 9As shown, in the same switch chip 202, MAC-Tx2 receives data from MAC-Rx2 and EB402. Therefore, to avoid data conflicts from MAC-Rx2 and EB402, the second link 412 further includes a second buffer 52. The second buffer 52 is electrically connected to MAC-Rx2, MAC-Tx2, and EB402 of the switch chip 202. The second buffer 52 is used to cache the data sent from MAC-Rx2 and EB402 to MAC-Tx2 in the same switch chip 202. In this way, the data cached in the second buffer 52 can be queued in the second buffer 52 in a FIFO manner and sent to MAC-Tx2.

[0112] On this basis, the network interface 30 of the switch chip 202 provided in the embodiment of the present application may include Figure 9 VSR-Rx for receiving signals and VSR-Tx for transmitting signals as shown. In addition, the above switch chip 202 further includes a third receiving-end MAC interface (hereinafter referred to as MAC-Rx3) and a third transmitting-end MAC interface (hereinafter referred to as MAC-Tx3). MAC-Rx3 and MAC-Tx3 may adopt the standard Ethernet protocol. In addition, the forwarding processing unit in the processor of the switch chip 202 may include Figure 9 the ingress pipeline (IPP) and the egress pipeline (EPP) as shown.

[0113] Among them, MAC-Rx3 is electrically connected to the network interface (for example, VSR-Rx) and IPP. The MAC-Rx3 is used as an interface at the data link layer to transmit the data from VSR-Rx to IPP. The IPP is also electrically connected to SWB40. The IPP is used to obtain the destination address according to the source address of the data from VSR-Rx and write the data into the local SWB40. Specifically, when VSR-Rx receives a data packet and transmits it to IPP through MAC-Rx3. When the switch chip 202 performs layer-2 forwarding, the IPP can read the source MAC address in the data packet header, then read the destination MAC address in the data packet header, and look up the interface corresponding to the destination MAC address in the MAC address table. Or, when the switch chip 202 performs layer-3 forwarding, the IPP can read the source IP address in the data packet header, then read the destination IP address in the data packet header, and look up the interface corresponding to the destination MAC address in the IP address table.

[0114] In addition, as Figure 9As shown, the EPP is electrically connected to the MAC-Tx3 and the SWB40. The EPP is used to read data from the SWB40 and send it to the MAC-Tx3. When the switch chip 202 performs three-layer forwarding, the EPP needs to change the source MAC address and the destination MAC address in the data packet header to complete the layer-2 encapsulation. In addition, the MAC-Tx3 is also electrically connected to a network interface (for example, the MR-Tx). The MAC-Tx3 serves as an interface at the data link layer to transmit the data from the EPP to the MR-Tx in the future.

[0115] Exemplarily, the data exchange capacities of the IB401 and the EB402 in the SWB40 of any one of the switch chips 202 in the switch 10 can both be 12.8 Tbps (abbreviated as 12.8T in the figure). In this case, four IPPs can be respectively electrically connected to the IB401, and four MAC-Rx3s are set, with one MAC-Rx3 electrically connected to one IPP, so that the data processing capacity of each interface can be 3.2 Tbps (abbreviated as 3.2T in the figure). Similarly, four EPPs are respectively electrically connected to the EB402, and four MAC-Tx3s are set, with one MAC-Tx3 electrically connected to one EPP, so that the data processing capacity of each interface can be 3.2 Tbps (abbreviated as 3.2T in the figure).

[0116] The following takes Figure 10a the structure of the switch 10 shown as an example to illustrate the data forwarding process of four sequentially connected switch chips 202-A, switch chip 202-B, switch chip 202-C, and switch chip 202-D in the switch 10. The data forwarding process may include S101 to S103 as shown in Figure 11 the figure.

[0117] In some embodiments of the present application, when data is forwarded within the same switch chip in the switch 10, for example, in the switch chip 202-A, the destination switch chip and one of the source switch chips are both the switch chip 202-A.

[0118] S101. The source switch chip caches the data.

[0119] Specifically, Figure 9 the switch chip 202-A shown in the figure, as one of the source switch chips, the data output from each of its IPPs can be transmitted to the IB401 of the switch chip 202-A. The IB401 can cache the data from multiple IPPs in the VOQ queue.

[0120] It should be noted that one VOQ queue in the IB401 corresponds to one priority of one MAC-Tx3 of one switch chip. For example, when the switch 10 includes, asFigure 4 When there are four switch chips as shown, and each switch chip has 32 MAC-Tx3s, and each MAC-Tx3 has 8 priorities, 1024 (4×32×8 = 1024) VOQ queues can be set in the IB401 of each switch chip.

[0121] S102. The destination switch chip performs scheduling, and the scheduling result is sent to the source switch chip.

[0122] Specifically, when the switch chip 202-A is used as the source switch chip, the IB401 of the switch chip 202-A sends a scheduling request to the EB402 of the switch chip 202-A. When the switch chip 202-A is used as the destination switch chip, the EB402 of the switch chip 202-A receives the scheduling request sent by the IB401 of the switch chip 202-A. In addition, the EB402 of the switch chip 202-A can also receive the IB401s of the remaining source switch chips, such as the switch chip 202-B, the switch chip 202-C, and the switch chip 202-D, sending scheduling requests to the EB402 of the switch chip 202-A through the above transmission link 41 (as Figure 9 shown). The EB402 of the switch chip 202-A generates multiple scheduling results according to the bandwidth (for example, 12.8T) to perform scheduling, and sends the scheduling results to the IB401s of the above respective source switch chips.

[0123] It should be noted that the EB402 of the destination switch chip generating multiple scheduling results according to the bandwidth (for example, 12.8T) and sending the scheduling results to the IB401s of the above respective source switch chips means that the scheduling requests received by the EB402 of the destination switch chip may be greater than the bandwidth (for example, 12.8T), and the sending capacity of this EB402 is only 12.8T. Therefore, the scheduling results sent by the EB402 each time will not be greater than 12.8T, and the part exceeding the bandwidth will be sent in batches in the EB402.

[0124] S103. The source switch chip forwards data to the destination switch chip.

[0125] Specifically, after the IB401 of the switch chip 202-A acting as the source switch chip receives the scheduling result sent by the EB402 of the switch chip 202-A acting as the destination switch chip, the IB401 of the switch chip 202-A can, according to the scheduling result, dequeue the data packet from the VOQ queue of this IB401 and send it to the EB402 of the switch chip 202-A. This EB402 can send the data packet to the corresponding MAC-Tx3 through the EPP, and finally send it to the electronic device 11 electrically connected to this MR-TX through the MR-TX to complete the data forwarding.

[0126] Based on this, in order to avoid data conflicts when the EB402 sends data to the same MAC-Tx3, the EB402 of the switch chip 202 can also, according to the scheduling result, cache the data to be sent to the same MAC-Tx3 in a FIFO manner.

[0127] The above description is given by taking the data forwarding within the same switch chip in the switch 10, such as the switch chip 202-A, as an example. In another embodiment of the present application, during the process of the switch 10 forwarding data, when the switch chip 202-A forwards the data to the adjacent switch chip 202-B of the switch chip 202-A, the switch chip 202-A can act as one of the source switch chips, and the switch chip 202-B acts as the destination switch chip.

[0128] In this case, the data forwarding process of the switch 10 is still as Figure 11 shown. Specifically, first, execute S101 to enable the data output by each IPP in the switch chip 202-A to be cached in multiple VOQ queues of the IB401 in the switch chip 202-A acting as the source switch chip. At this time, the IB401 in the switch chip 202-A acting as the source switch chip can determine a sending path, and this sending path can include: from the switch chip 202-A acting as the source switch chip to the switch chip 202-B acting as the destination switch chip.

[0129] Next, during the execution of S102, Figure 10a the IB401 of the switch chip 202-A shown as the source switch chip will pass through the first link 411 ( Figure 10aThe solid arrow in sends a scheduling request to the EB402 of the switch chip 202-B, which is the destination switch chip. The EB402 of the switch chip 202-B receives the scheduling request sent by the IB401 of the switch chip 202-A. In addition, the EB402 of the switch chip 202-B can also receive the scheduling requests sent by the IB401 of the remaining source switch chips, such as the switch chips 202-B, 202-C, and 202-D, to the EB402 of the switch chip 202-B through the above-mentioned first link 411 or second link 412. The EB402 of the switch chip 202-B, which is the destination switch chip, generates multiple scheduling results according to the bandwidth (e.g., 12.8T) and sends the scheduling results to the IB401 of each of the above-mentioned source switch chips.

[0130] Next, perform the above S103. After the IB401 of the switch chip 202-A, which is the source switch chip, receives the scheduling result sent by the EB402 of the switch chip 202-B, the IB401 of the switch chip 202-A can dequeue the data packet from the VOQ queue of this IB401 according to the scheduling result, and send the data through the above-mentioned sending path to the EB402 of the switch chip 202-B via the first link 411. Among them, the data dequeued by the IB401 of the switch chip 202-A can be sent to the first buffer 51 of the switch chip 202-A through the EB402 of the switch chip 202-A. At this time, when the data received by the MAC-Rx1 of the switch chip 202-A is also sent to the first buffer 51, the first buffer 51 can cache the data in a FIFO manner and output it to the MAC-Tx1 of the switch chip 202-A.

[0131] Then, the switch chip 202-B electrically connected to the MAC-Tx1 of the switch chip 202-A receives the data to the EB402 of the switch chip 202-B through the MAC-Rx1 of this switch chip 202-B. The EB402 can send the data packet to the corresponding MAC-Tx3 of the switch chip 202-B through the EPP, or perform a cache in the EB402 of the switch chip 202-B.

[0132] Alternatively, in another embodiment of the present application, during the process of the switch 10 forwarding data, when the switch chip 202-A forwards the data to the switch chip 202-C, the switch chip 202-A can be used as one of the source switch chips, and the switch chip 202-C as the destination switch chip. At this time, as Figure 10bAs shown, when transmitting data along the first reverse direction (e.g., clockwise), there is a switch chip 202-B, which serves as the first intermediate switch chip, between the switch chip 202-A and the switch chip 202-C. Alternatively, when transmitting data along the second direction (e.g., counterclockwise), there is a switch chip 202-D, which serves as the second intermediate switch chip, between the switch chip 202-A and the switch chip 202-C.

[0133] In this case, the data forwarding process of the switch 10 is still as Figure 11 shown. Specifically, first, S101 is executed, so that in the switch chip 202-A, the data output by each IPP can be cached in multiple VOQ queues of the IB401 in the switch chip 202-A, which serves as the source switch chip. At this time, the first transmission path that can be determined by the IB401 in the switch chip 202-A, which serves as the source switch chip, may include: from the switch chip 202-A, which serves as the source switch chip, through the switch chip 202-B, which serves as the first intermediate switch chip, to the switch chip 202-B, which serves as the destination switch chip.

[0134] Next, during the execution of S102, Figure 10a the IB401 of the switch chip 202-A, which is shown as the source switch chip, will send a scheduling request to the EB402 of the switch chip 202-C through the switch chip 202-B via the first link 411 ( Figure 10a the solid arrow in).

[0135] Then, the EB402 of the switch chip 202-C, which serves as the destination switch chip, receives the scheduling request sent by the IB401 of the switch chip 202-A. In addition, the EB402 of the switch chip 202-C can also receive the scheduling requests sent to the EB402 of the switch chip 202-C by the IB401 of the remaining source switch chips, such as the switch chip 202-B, the switch chip 202-C, and the switch chip 202-D, via the above-mentioned first link 411 or the second link 412. The EB402 of the switch chip 202-C generates multiple scheduling results according to the bandwidth and sends the scheduling results to the IB401 of each of the above-mentioned source switch chips.

[0136] Next, the above-mentioned S103 is executed. After the IB401 of the switch chip 202-A, which serves as the source switch chip, receives the scheduling result sent by the EB402 of the switch chip 202-C, the IB401 of the switch chip 202-A can dequeue the data packet from the VOQ queue of the IB401 according to the scheduling result. The data can be transmitted through the above-mentioned first transmission path via the first link 411 ( Figure 10a(the solid arrow in it) is sent to EB402 of switch chip 202-C through switch chip 202-B.

[0137] Alternatively, in some other embodiments of the present application, S101 is executed. IB401 in switch chip 202-A can determine a second transmission path. The second transmission path can be: when data is transmitted from switch chip 202-A through switch chip 202-D, which is used as the second intermediate switch chip, to switch chip 202-B, which is used as the destination switch chip, the data transmission process is the same as described above and will not be elaborated here.

[0138] Or, in some other embodiments of the present application, S101 is executed. IB401 in switch chip 202-A, which is used as the source switch chip, can simultaneously determine the first transmission path and the second transmission path. Next, during the execution of S102, Figure 10a IB401 of switch chip 202-A, which is shown as the source switch chip, will send a scheduling request to EB402 of this switch chip 202-C through the first link 411 ( Figure 10a the solid arrow in it). Alternatively, IB401 of switch chip 202-A can send a scheduling request to EB402 of this switch chip 202-C through the second link 412 ( Figure 10a the dashed arrow in it) through switch chip 202-D.

[0139] Then, EB402 of switch chip 202-C, which is used as the destination switch chip, receives the scheduling request sent by IB401 of switch chip 202-A. In addition, EB402 of switch chip 202-C can also receive scheduling requests sent by IB401 of the remaining source switch chips, such as switch chip 202-B, switch chip 202-C, and switch chip 202-D, to EB402 of switch chip 202-C through the above-mentioned first link 411 or second link 412. EB402 of switch chip 202-C generates multiple scheduling results according to the bandwidth and sends the scheduling results to IB401 of each of the above-mentioned source switch chips.

[0140] Next, the above-mentioned S103 is executed. After IB401 of switch chip 202-A, which is used as the source switch chip, receives the scheduling result sent by EB402 of switch chip 202-C, IB401 of switch chip 202-A can, according to the scheduling result, dequeue the data packet from the VOQ queue of this IB401. A part of the data is sent through the above-mentioned first transmission path by the first link 411 ( Figure 10aThe solid arrow in (), is sent to EB402 of switch chip 202-C through switch chip 202-B. In addition, another part of the data is sent through the second sending path described above by the second link 412( Figure 10a The solid arrow in (), is sent to EB402 of switch chip 202-C, which is the destination switch chip, through switch chip 202-D. Among them, the function of the second buffer 52 in the second link 412 is the same as that of the first buffer 51, and will not be elaborated here.

[0141] Next, EB402 of switch chip 202-C can send the data packet to MAC-Tx3 corresponding to switch chip 202-C through EPP, or perform a cache in EB402 of switch chip 202-C.

[0142] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A multi-chip packaging structure, characterized in that, It includes a packaging substrate and multiple switch chips disposed on the packaging substrate. The switch chips include at least two network interfaces and at least one chip-to-chip D2D interface. The switch chips are used to access a network through the at least two network interfaces and send and receive data with the network. The switch chips are also used to be connected to another switch chip through each D2D interface in the at least one D2D interface and send and receive data with each other. The switch chips are further used to forward the data received from the at least two network interfaces or the at least one D2D interface to at least one of the at least two network interfaces and the at least one D2D interface. The multi-chip packaging structure includes four of the switch chips; each of the switch chips includes two of the D2D interfaces for respectively connecting to the D2D interfaces of two other switch chips; the four switch chips are electrically connected end to end in sequence.

2. The multi-chip package structure according to claim 1, wherein, The switch chips further include control logic, and the control logic is used for: Obtaining the destination information of the received data from the received data. Determining a sending port according to the destination information, where the sending port includes the at least one D2D interface and the at least two network interfaces in the current switch chip. Sending the received data through the sending port.

3. The multi-chip package structure according to claim 2, wherein The multiple switch chips include a source switch chip and a destination switch chip. After the source switch chip determines the sending port according to the destination information, the control logic of the source switch chip is further used for: determining at least one sending path between the source switch chip and the destination switch chip, queuing and caching the received data, and sending a scheduling request to the destination switch chip. Before the destination switch chip sends the received data through the sending port, the control logic of the destination switch chip is further used for: generating a scheduling result according to the scheduling request and the bandwidth of the destination switch chip; the control logic of the source switch chip is further used for: according to the scheduling result, dequeuing the received data from the queue, and sending the received data to the destination switch chip through the at least one sending path.

4. The multi-chip package structure according to claim 3, wherein, The source switch chip is adjacent to the destination switch chip. The control logic of the source switch chip is specifically used for: determining one of the sending paths, and sending the received data to the destination switch chip through the sending path; where the sending path includes: from the source switch chip to the destination switch chip.

5. The multi-chip package structure according to claim 3, wherein Among the four switch chips, there is an intermediate switch chip between the source switch chip and the destination switch chip. The control logic of the source switch chip is specifically used for: determining one of the sending paths, and sending the received data to the destination switch chip through the sending path; where the sending path includes: from the source switch chip, passing through the intermediate switch chip to the destination switch chip.

6. The multi-chip package structure according to claim 3, wherein, Among the four switch chips, along a first direction, a first intermediate switch chip is spaced between the source switch chip and the destination switch chip, and along a second direction, a second intermediate switch chip is spaced between the source switch chip and the destination switch chip; wherein, the first direction and the second direction are opposite to each other; The control logic of the source switch chip is specifically configured to: determine a first transmission path, and send a part of the received data to the destination switch chip through the first transmission path; wherein, the first transmission path includes: from the source switch chip, passing through the first intermediate switch chip to the destination switch chip; determine a second transmission path, and send another part of the received data to the destination switch chip through the second transmission path; wherein, the second transmission path includes: from the source switch chip, passing through the second intermediate switch chip to the destination switch chip.

7. The multi-chip package structure according to any one of claims 2-6, characterized in that, The switch chip further includes: a switching buffer unit for executing the control logic; a transmission link; the transmission link is electrically connected to the D2D interface and the switching buffer unit, and the transmission link is used for data transceiver between the D2D interface and the switching buffer unit, and between different D2D interfaces.

8. The multi-chip package structure according to claim 7, wherein, The transmission link includes: a first link; the first link includes a first receiving end media access control (MAC) interface, a first buffer, and a first sending end MAC interface that are electrically connected in sequence; the first receiving end MAC interface and the first sending end MAC interface are respectively electrically connected to two D2D interfaces of the switch chip; the first receiving end MAC interface and the first buffer are also electrically connected to the switching buffer unit; a second link, the transmission direction of data in the second link is opposite to the transmission direction of data in the first link; the second link includes a second receiving end MAC interface, a second buffer, and a second sending end MAC interface that are electrically connected in sequence; the second receiving end MAC interface and the second sending end MAC interface are respectively electrically connected to two D2D interfaces of the switch chip; the second receiving end MAC interface and the second buffer are also electrically connected to the switching buffer unit.

9. The multi-chip package structure according to claim 8, wherein, The four switch chips are arranged in a 2×2 matrix form; in the multi-chip package structure, the first links of the four switch chips are electrically connected end to end in sequence to form a ring; the second links of the four switch chips are electrically connected end to end in sequence to form a ring.

10. The multi-chip package structure according to claim 2, wherein The switch chip further includes: a forwarding processing unit for executing the control logic; a third receiving end MAC interface, electrically connected to the network interface and the forwarding processing unit, for transmitting data from the network interface to the forwarding processing unit; a third sending end MAC interface, electrically connected to the network interface and the forwarding processing unit, for transmitting data from the forwarding processing unit to the network interface.

11. The multi-chip package structure according to claim 1, wherein, In the multi-chip package structure, the switching bandwidths of any two switch chips are the same.

12. The multi-chip packaging structure according to any one of claims 1-6, 10, and 11, characterized in that, The multi-chip package structure further includes a plurality of optical modules disposed on the package substrate and on the same side as the switch chip.

13. A switch, characterized in that, It includes a circuit board and the multi-chip package structure according to any one of claims 1-12 disposed on the circuit board.

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