Chip with debugging function and chip debugging method

Abstract

The present disclosure relates to a chip with debug function and a chip debug method. The chip includes a plurality of functional circuitry, a selection circuitry, a data reconstruction circuitry and a switch circuitry. Each functional circuitry includes a decoding circuitry which stores a set of debug signals and outputs a signal in the set of debug signals as a corresponding one in a plurality of first signals according to one of a plurality of address signals. The selection circuitry selects a plurality of second signals from the first signals according to the address signals. The data reconstruction circuitry selects a plurality of first data from the second signals according to a plurality of split signals and outputs the first data as debug data. Each first data is a partial data of one of the second signals. The switch circuitry determines whether to output the debug data or output signals of the functional circuitry via a plurality of output ports according to a plurality of switch signals.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to chips with debug functions, and in particular, to chips with debug signals selectively output from different circuit systems and methods for debugging chips. BACKGROUND

[0002] To ensure that a chip meets design requirements, some important signals in the chip can be output as a set of debug signals via output ports in the chip, and the set of debug signals can be read via at least one external instrument. In this way, whether the chip has errors can be determined according to the set of debug signals, so as to decide whether to adjust the design of the chip. With the development of technology, the number of circuits in the chip is increasing. If more debug signals of circuits are to be read, the number of output ports needs to be increased. However, in practical applications, the number of output ports is usually insufficient to output debug signals of a large number of circuits, resulting in an increase in the difficulty of chip testing. SUMMARY

[0003] In some embodiments, one of the purposes of the present disclosure is to provide, but not limited to, chips with debug signals selectively output from different circuit systems and methods for debugging chips.

[0004] In some embodiments, a chip with debug functions includes a plurality of functional circuit systems, a selection circuit system, a data reconstruction circuit system, and a switching circuit system. The plurality of functional circuit systems are used to generate a plurality of sets of debug signals, respectively. Each of the functional circuit systems includes a decoding circuit used to store a corresponding set of debug signals among the sets of debug signals and output a corresponding debug signal in the corresponding set of debug signals as a corresponding signal in a plurality of first signals according to a corresponding address signal in a plurality of address signals. The selection circuit system is used to select a plurality of second signals from the first signals according to the address signals. The data reconstruction circuit system is used to select a plurality of first data from the second signals according to a plurality of split signals and output the first data as first debug data. Each of the first data is partial data of a corresponding signal in the second signals. The switching circuit system is used to determine whether to output the first debug data or at least one output signal associated with the functional circuit systems via a plurality of output ports according to a plurality of switching signals.

[0005] In some embodiments, a chip debugging method includes the following operations: outputting a plurality of first signals from a plurality of groups of debugging signals according to a plurality of address signals, wherein the groups of debugging signals are respectively generated by a plurality of functional circuit systems of a chip; selecting a plurality of second signals from the first signals according to the address signals; selecting a plurality of first data from the second signals according to a plurality of split signals and outputting the first data as first debugging data, wherein each of the first data is a partial data of a corresponding signal among the second signals; and determining whether to output the first debugging data or at least one output signal associated with the functional circuit systems via a plurality of output ports of the chip according to a plurality of switch signals.

[0006] As to the features, implementations and effects of the present application, detailed descriptions are provided below with reference to the preferred embodiments and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 A schematic diagram of a chip according to some embodiments of the present application is shown;

[0008] Figure 2A A schematic diagram of the correspondence between the decoding circuits and the groups of debugging signals in Figure 1 according to some embodiments of the present application is shown;

[0009] Figure 2B A schematic diagram of the decoding circuit in Figure 1 according to some embodiments of the present application is shown;

[0010] Figure 2C A flowchart of the operations performed by the decoding circuit in Figure 2B according to some embodiments of the present application is shown;

[0011] Figure 3A A schematic diagram of the selection circuit system in Figure 1 according to some embodiments of the present application is shown;

[0012] Figure 3B A flowchart of the operations performed by the selection circuit in Figure 3A according to some embodiments of the present application is shown;

[0013] Figure 4A A schematic diagram of the data reconstruction circuit system in Figure 1 according to some embodiments of the present application is shown;

[0014] Figure 4B A flowchart of the operations performed by the data reconstruction circuit system in Figure 4A according to some embodiments of the present application is shown;

[0015] Figure 5 A schematic diagram of a chip according to some embodiments of the present application is shown;Figure 1 a flowchart of operations performed by shift circuitry in

[0016] Figure 6A a schematic diagram of a chip drawn in accordance with some embodiments of the present application;

[0017] Figure 6B a schematic diagram of a chip drawn in accordance with some embodiments of the present application Figure 6A a flowchart of operations performed by shift circuitry in

[0018] Figure 7 a flowchart of a chip debugging method drawn in accordance with some embodiments of the present application. DETAILED DESCRIPTION

[0019] All words used herein are to be interpreted according to their normal meaning. Definitions of the above words in common usage dictionaries, including any examples of usage of the words discussed herein, are to be construed as examples only and should not limit the scope and meaning of the present application. Similarly, the present application is not to be limited to the various embodiments shown in the specification.

[0020] With respect to the use of "coupled" or "connected" herein, two or more elements are coupled or connected together in such a manner that they are either in direct physical or electrical contact with each other, or that they are not in direct contact with each other, but are able to co-operate or interact with each other. As used herein, the term "circuitry" can refer to a single overall system formed from at least one circuit, and the term "circuit" can refer to a device that processes signals by way of at least one transistor and / or at least one passive element connected in a certain manner to process signals.

[0021] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In the present document, the use of the terms first, second, and third, etc. do not denote any quantity or order but are used merely to distinguish one element from another. Thus, a first element as discussed herein could also be termed a second element without departing from the spirit of the present application. For ease of understanding, like elements will be designated by the same reference number in the various drawings.

[0022] Figure 1 a schematic diagram of a chip 100 drawn in accordance with some embodiments of the present application. In some embodiments, the chip 100 can be an application specific integrated circuit having a debug function. With the debug function, the chip 100 can selectively output internal signals of different circuitries in the chip 100 for functional verification and / or circuit testing.

[0023] The chip 100 comprises a plurality of functional circuitry 110[1]~110[n], a selection circuitry 120, a data reconstruction circuitry 130, a switching circuitry 140, and an output circuitry 150. The plurality of functional circuitry 110[1]~110[n] can respectively generate a plurality of sets of debug signals (e.g., a plurality of sets of debug signals DB[1]~DB[n] in Figure 2A

[0024] According to different applications, the plurality of functional circuitry 111[1]~111[n] can respectively perform a plurality of preset functions (e.g., but not limited to, analog / digital signal processing, image processing, deep learning, communication, etc.). Each of the plurality of decoding circuitry 112[1]~112[n] can be used to store a set of debug signals generated by the corresponding one of the plurality of functional circuitry 111[1]~111[n] when performing the preset function, and output a corresponding debug signal in the set of debug signals as a corresponding one of the plurality of first signals S1[1]~S1[n] according to a corresponding address signal in the plurality of address signals ADR[1]~ADR[x]. In some embodiments, the aforementioned debug signals can be (but not limited to) internal signals of the functional circuitry 111[1]~111[n] when the functional circuitry 111[1]~111[n] is operating. In some embodiments, the aforementioned numerical value n and numerical value x are both positive integers, and n is greater than x.

[0025] For example, the decoding circuitry 112[1] can store a set of debug signals (e.g., the first set of debug signals DB[1] in Figure 2A ) generated by the functional circuitry 111[1] when performing the preset function, and output a corresponding debug signal in the set of debug signals as the first signal S1[1] according to a corresponding address signal in the plurality of address signals ADR[1]~ADR[x]. In the same way, it can be understood that the decoding circuitry 112[n] can store a set of debug signals (e.g., the nth set of debug signals DB[n] in Figure 2A ​the nth group of debug signals DB[n]) and outputs a corresponding debug signal in the group of debug signals as a first signal S1[n] according to a corresponding address signal in the plurality of address signals ADR[1]~ADR[x].

[0026] The selection circuitry 120 is configured to select a plurality of second signals S2[1]~S2[x] from the plurality of first signals S1[1]~S1[n] according to the plurality of address signals ADR[1]~ADR[x]. By the selection circuitry 120, unwanted signals in the plurality of first signals S1[1]~S1[n] can be filtered out and the remaining signals in the plurality of first signals S1[1]~S1[n] can be outputted as the plurality of second signals S2[1]~S2[x].

[0027] The data reconstruction circuitry 130 is configured to select a plurality of first data D1~Dx from the plurality of second signals S2[1]~S2[x] according to the plurality of split signals SS[1]~SS[x] and output the first data D1~Dx as first debug data DO1. The operation of the data reconstruction circuitry 130 will be described later with reference to Figure 4A and Figure 4B be described in detail.

[0028] The switching circuitry 140 is coupled between the data reconstruction circuitry 130 and the output circuitry 150. The output circuitry 150 is configured to transmit at least one output signal VO (which comprises a plurality of bits B[1]~B[y]) associated with the plurality of functional circuitries 110[1]~110[n]. In some embodiments, the value y can be the product of the value x and the value p, which will be described later. The at least one output signal VO can be a signal generated by at least one of the plurality of functional circuitries 110[1]~110[n] performing the aforementioned predetermined function. The switching circuitry 140 is configured to determine whether to output a corresponding data in the first debug data DO1 or a corresponding bit in the plurality of bits B[1]~B[y] via a plurality of output ports P[1]~P[y] (for example, but not limited to, a plurality of input / output pads) of the chip 100 according to a plurality of switching signals S[1]~S[y]. By the above arrangement, the debug signals in the chip 100 can share the plurality of output ports P[1]~P[y] with general signals (for example, the at least one output signal VO). In this way, the chip 100 can output the debug signals without using extra output ports to verify whether the chip 100 operates correctly. The detailed operation of the switching circuitry 140 will be described later with reference to Figure 5 description.

[0029] Figure 2A to draw Figure 1A schematic diagram showing the correspondence between multiple decoding circuits 112[1]~112[n] and multiple sets of debugging signals DB[1]~DB[n]. For example... Figure 2A As shown, multiple decoding circuits 112[1] to 112[n] store multiple sets of debugging signals DB[1] to DB[n], which correspond to multiple address ranges that increase sequentially. For example, decoding circuit 112[1] stores the first set of debugging signals DB[1], and its corresponding address range is from address 1 to address A1. Decoding circuit 112[2] stores the second set of debugging signals DB[2], and its corresponding address range is from address A1+1 to address A1+A2. And so on. It can be understood that decoding circuit 112[n] stores the nth set of debugging signals DB[n], and its corresponding address range is from address A1+A2+…+1 to A1+A2+…+An.

[0030] Each of the multiple sets of debug signals DB[1] to DB[n] contains multiple debug signals and preset flag values, and all debug signals have the same number of bits (e.g., such as...). Figure 4A As shown, it can be x*p units. For example, the first group of debugging signals DB[1] contains multiple debugging signals d1[1] to d1[A1-1] and a preset flag value F1, which correspond to multiple addresses 1 to A1 in sequence. The second group of debugging signals DB[2] contains multiple debugging signals d2[1] to d2[A2-1] and a preset flag value F2, which correspond to multiple addresses A1+1 to A1+A2 in sequence. And so on, it should be understood that the nth group of debugging signals DB[n] contains multiple debugging signals dn[1] to dn[An-1] and a preset flag value Fn, which correspond to multiple addresses A1+A2+...+1 to A1+A2+...+An in sequence. The aforementioned preset flag values ​​F1 to Fn are all preset values, which can be used to verify whether the debugging functions (such as the operation of decoding circuit 112[1] to 112[n], selection circuit system 120, data reconstruction circuit system 130 and switching circuit system 140) are correct.

[0031] Figure 2B Drawing based on some embodiments of this case Figure 1 A schematic diagram of the decoding circuit 112[1] in the middle. Figure 1 Each of the multiple decoding circuits 112[1] to 112[n] has the same circuit structure. Taking decoding circuit 112[1] as an example, decoding circuit 112[1] includes a lookup table circuit 210 and a comparison circuit 220. The lookup table circuit 210 can be used to store... Figure 2AThe first set of debugging signals DB[1] is recorded, and the correspondence between the first set of debugging signals DB[1] and multiple addresses 1 to A1 is recorded. For example, the lookup table circuit 210 can be a memory circuit or a register circuit, which can be used to store a lookup table that reflects the correspondence between multiple debugging signals d1[1] to d1[A1-1] and the preset flag value F1 and multiple addresses 1 to A1. The comparison circuit 220 can be used to sequentially confirm whether multiple address signals ADR[1] to ADR[x] match the corresponding address range (e.g., address 1 to address A1) in multiple address ranges, so as to select the corresponding address signal ADR among multiple address signals ADR[1] to ADR[x]. In this way, the lookup table circuit 210 can output the corresponding debugging signal in the first set of debugging signals DB[1] as the first signal S1[1] according to this corresponding address signal ADR. In some embodiments, the comparison circuit 220 can be executed by (but is not limited to) Figure 2C At least one digital logic circuit implements a portion of the operation (e.g., operation S210 and operation S230).

[0032] Figure 2C Drawing based on some embodiments of this case Figure 2B The flowchart shows the multiple operations performed by the decoding circuit 112[1]. In operation S210, multiple address signals (e.g., multiple address signals ADR[1] to ADR[x]) are sequentially compared with a corresponding address range (e.g., for the decoding circuit 112[1], the corresponding address range is address 1 to address A1) to select the corresponding address signal that matches the corresponding address range (e.g., ...). Figure 2B (The corresponding address signal ADR in the code). If the corresponding address signal is selected, execute operation S220. Or, if the corresponding address signal is not selected, execute operation S230.

[0033] For example, such as Figure 2C As shown, the comparison circuit 220 can compare the address signal ADR[1] with the corresponding address range (i.e., address 1 to address A1). If the address signal ADR[1] matches the corresponding address range (i.e., the address signal ADR[1] is greater than or equal to address 1 and less than or equal to address A1), the comparison circuit 220 can determine that the address signal ADR[1] matches the corresponding address range and output the address signal ADR[1] as the corresponding address signal ADR. Alternatively, if the address signal ADR[1] does not match the corresponding address range, the comparison circuit 220 can determine that the address signal ADR[1] does not match the corresponding address range and start comparing the address signal ADR[2] with the corresponding address range. By analogy, the comparison circuit 220 can find the signal that matches the corresponding address range among multiple address signals ADR[1] to ADR[x] and output the signal as the corresponding address signal ADR.

[0034] In operation S220, a corresponding group of debug signals (e.g., the 1st group of debug signals DB[1]) is outputted according to the corresponding address signal. A corresponding debug signal in the corresponding group of debug signals is a corresponding signal (e.g., the 1st signal S1[1]) in the plurality of 1st signals. Figure 2A

[0035] For example, if the value of the address signal ADR[1] is the same as the address 1, the comparison circuit 220 can confirm that the address signal ADR[1] is within the corresponding address range, and output the address signal ADR[1] as the corresponding address signal ADR. The lookup table circuit 210 can output the debug signal d1[1] corresponding to the address 1 as the 1st signal S1[1] according to the corresponding address signal ADR. Similarly, if the value of the address signal ADR[1] is the same as the address A1, the comparison circuit 220 can confirm that the address signal ADR[1] is within the corresponding address range, and output the address signal ADR[1] as the corresponding address signal ADR. The lookup table circuit 210 can thus output the preset flag value F1 corresponding to the address A1 as the 1st signal S1[1] according to the corresponding address signal ADR.

[0036] In operation S230, the corresponding signal in the plurality of 1st signals is set to a preset value. For example, if none of the plurality of address signals ADR[1] to ADR[x] is within the corresponding address range, the comparison circuit 220 can set the 1st signal S1[1] to a preset value (e.g., but not limited to, 0) to reflect that none of the plurality of address signals ADR[1] to ADR[x] is within the address range of the decoding circuit 112[1].

[0037] ​By the above operations, the decoding circuit 112[1] can output a specific debug signal as the first signal S1[1] according to the address signals ADR[1]-ADR[x]. In this way, the user can freely select the debug signal to be observed by setting the address signals ADR[1]-ADR[x]. For example, in the initial stage, the user can set the value of the address signal ADR[1] as the address A1, so that the decoding circuit 112[1] outputs the preset flag value F1 as the corresponding first signal S1[1]. In this way, the user can use an external instrument (for example, but not limited to, an oscilloscope, a logic analyzer, etc.) to verify whether the decoding circuit 112[1] correctly outputs the first signal S1[1]. If the first signal S1[1] is the preset flag value F1, it means that the decoding circuit 112[1] can correctly output the preset flag value F1 as the first signal S1[1]. If the first signal S1[1] is not the preset flag value F1, it means that the decoding circuit 112[1] cannot correctly output the preset flag value F1 as the first signal S1[1]. Under this condition, it means that the decoding circuit 112[1] (or at least one of the selection circuit system 120, the data reconstruction circuit system 130, and the switching circuit system 140) may

[0038] Figure 3A FIG. 1 shows a schematic diagram of a debug circuit according to some embodiments of the present application. Figure 1 In some embodiments, the selection circuit system 120 includes a plurality of selection circuits 310[1]-310[x]. Each of the plurality of selection circuits 310[1]-310[x] receives a corresponding one of the address signals ADR[1]-ADR[x] and the first signals S1[1]-S1[n], and is configured to compare the corresponding one of the address signals ADR[1]-ADR[x] with the address ranges to select a corresponding one of the second signals S2[1]-S2[x] from the first signals S1[1]-S1[n].

[0039] For example, selection circuit 310[1] can receive address signal ADR[1] and multiple first signals S1[1] to S1[n], and sequentially compare address signal ADR[1] with multiple address ranges to select second signal S2[1] from multiple first signals S1[1] to S1[n]. Selection circuit 310[2] can receive address signal ADR[2] and multiple first signals S1[1] to S1[n], and sequentially compare address signal ADR[2] with multiple address ranges to select second signal S2[2] from multiple first signals S1[1] to S1[n]. By analogy, the correspondence between multiple selection circuits 310[1] to 310[x], multiple address signals ADR[1] to ADR[x], and multiple second signals S2[1] to S2[x] should be understood. In some embodiments, each of the multiple selection circuits 310[1] to 310[x] has the same circuit structure. For example, each of the multiple selection circuits 310[1] to 310[x] can be executed by (but is not limited to) Figure 3B The operation is implemented by at least one digital logic circuit.

[0040] Figure 3B Drawing based on some embodiments of this case Figure 3A The flowchart shows the multiple operations performed by the selection circuit 310[1]. In operation S310, the received address signal (for example, for the selection circuit 310[1], the received address signal is address signal ADR[1]) is sequentially compared with multiple address ranges (for example, address 1 to address A1, address A1+1 to address A1+A2, ..., address A1+A2+...+1 to address A1+A2+...+An) to select the corresponding address range that matches the address signal from these address ranges. If the corresponding address range is found, operation S320 is performed. Or, if the corresponding address range is not found, operation S330 is performed.

[0041] For example, such as Figure 3B As shown, the selection circuit 310[1] can compare the address signal ADR[1] with the first address range (i.e., address 1 to address A1). If the address signal ADR[1] matches (is located in) the corresponding address range (i.e., the address signal ADR[1] is greater than or equal to address 1 and less than or equal to address A1), the selection circuit 310[1] can determine that the address signal ADR[1] matches the first address range. Alternatively, if the address signal ADR[1] does not match the first address range, the selection circuit 310[1] can continue to compare the address signal ADR[1] with the second address range (i.e., address A1+1 to address A1+A2). And so on, the selection circuit 310[1] can find the corresponding address range that matches the address signal ADR[1] among multiple address ranges.

[0042] In operation S320, a signal stored in the corresponding address range is selected from the plurality of first signals, and the signal is outputted as the corresponding one of the plurality of second signals (e.g., second signal S2[1] for selection circuit 310[1]). For example, in operation S310, selection circuit 310[1] confirms that the corresponding address range matched by address signal ADR[1] is the first address range (i.e., address 1 to address Al). Since first signal S1[1] is stored in the first address range (see FIG. 3), selection circuit 310[1] outputs first signal S1[1] as second signal S2[1]. Alternatively, if selection circuit 310[1] confirms that the corresponding address range matched by address signal ADR[1] is the second address range (i.e., address Al+1 to address Al+A2), since first signal S1[2] is stored in the second address range (see FIG. 3), selection circuit 310[1] outputs first signal S1[2] as second signal S2[1]. Figure 2A Figure 2A

[0043] In operation S330, the corresponding one of the plurality of second signals (e.g., second signal S2[1] for selection circuit 310[1]) is set to a predetermined value. For example, if address signal ADR[1] does not match any of the address ranges, it means that the value of address signal ADR[1] can be incorrect. In this case, selection circuit 310[1] can set second signal S2[1] to a predetermined value (e.g., but not limited to, 0) to reflect that address signal ADR[1] does not match any of the address ranges.

[0044] For ease of understanding, the above operations are described by way of example using selection circuit 310[1]. It should be understood that the remaining selection circuits 310[2]-310[x] can perform the same operations according to the remaining address signals ADR[2]-ADR[x]. For example, selection circuit 310[2] can sequentially confirm the corresponding address range that matches address signal ADR[2] from the plurality of address ranges, and select a signal stored in the corresponding address range from the plurality of first signals S1[1]-S1[n], and output the signal as second signal S2[2]. Alternatively, if address signal ADR[2] does not match any of the address ranges, selection circuit 310[2] can set second signal S2[2] to a predetermined value.

[0045] By the above operations, a user can select a specific object to be observed from the plurality of functional circuit systems 110[1]-110[n] by setting the plurality of address signals ADR[1]-ADR[x]. In other words, by the plurality of address signals ADR[1]-ADR[x] and the plurality of selection circuits 310[1]-310[x], a user can exclude unnecessary signals from the plurality of first signals S1[1]-S1[n]. ​​

[0046] Figure 4A FIG. 1 shows a diagram of a system according to some embodiments of the present disclosure. Figure 1 FIG. 2 shows a diagram of a data reconstruction circuit according to some embodiments of the present disclosure. In some embodiments, the data reconstruction circuit 130 comprises a plurality of data selection circuits 410[1]~410[x]. Each of the plurality of data selection circuits 410[1]~410[x] is configured to split a corresponding one of the plurality of second signals S2[1]~S2[x] into a plurality of second data, and select a corresponding data from the second data according to a corresponding one of the plurality of split signals SS[1]~SS[x] as a corresponding one of the plurality of first data D1~Dx.

[0047] In some embodiments, each of the plurality of data selection circuits 410[1]~410[x] has the same circuit structure. For example, the data selection circuit 410[1] comprises a splitting circuit 411[1] and a reconstruction circuit 412[1]. The splitting circuit 411[1] receives the second signal S2[1], and splits the second signal S2[1] into a plurality of second data D2[1]~D2[x]. As previously described, all of the debug signals in the plurality of groups of debug signals DB[1]~DB[n] have the same number of bits. As such, each of the plurality of first signals S1[1]~S1[n] and the plurality of second signals S2[1]~S2[x] also has the same number of bits. Assuming that each of the debug signals has x*p bits (where x and p are positive integers), the splitting circuit 411[1] can split the second signal S2[1] into x second data D2[1]~D2[x], where each of the second data D2[1]~D2[x] is p bits. For example, if the second signal S2[1] has the data [x*p-1, …, (x-1)*p, …, 2p-1, …, p, p-1, …, 0], the second data D2[1] can be [p-1, …, 0], the second data D2[2] can be [2p-1, …, p], and the second data D2[x] can be [x*p-1, …, (x-1)*p]. The reconstruction circuit 412[1] is configured to select a corresponding data from the second data D2[1]~D2[x] according to the split signal SS[1] as the first data D1.

[0048] Similarly, it should be understood that there is a correspondence between the remaining multiple data selection circuits 410[2]~410[x], multiple second signals S2[2]~S2[x], and multiple first data D2~Dx. For example, in data selection circuit 410[2], the splitting circuit receives the second signal S2[2] and splits the second signal S2[2] into multiple second data, and the reconstruction circuit selects the corresponding data as the first data D2 from these second data according to the splitting signal SS[2]. In data selection circuit 410[x], the splitting circuit receives the second signal S2[x] and splits the second signal S2[x] into multiple second data, and the reconstruction circuit selects the corresponding data as the first data Dx from these second data according to the splitting signal SS[x]. Accordingly, it should be understood that each of the multiple first data D1~Dx is a part of the corresponding signal in the multiple second signals. Taking the first data D1 as an example, the first data D1 is a portion of the data of the second signal S2[1] (i.e., the corresponding data among the multiple second data D2[1] to D2[x]). Through the above operation, the multiple data selection circuits 410[1] to 410[x] can output the multiple first data D1 to Dx as the first debugging data DO1. For example, as Figure 1 As shown, the first debug data DO1 can be represented as [Dx, …, D2, D1].

[0049] As previously described, in some embodiments, each of the plurality of data selection circuits 410[1] to 410[x] may have the same circuit structure. For example, each of the plurality of data selection circuits 410[1] to 410[x] may be executed by (but not limited to) Figure 4B The operation is implemented by at least one digital logic circuit. In some embodiments, the aforementioned split circuit 411[1] and reconfiguration circuit 412[1] may (but are not limited to) be combined into the same digital circuit or share some circuits.

[0050] Figure 4B Drawing based on some embodiments of this case Figure 4A The flowchart shows the multiple operations performed by the data reconstruction circuit system 130. In operation S410, multiple second signals are split into multiple second data (e.g., multiple second data D2[1] to D2[x]). As mentioned above, the splitting circuit 411[1] can split the second signal S2[1] into multiple second data D2[1] to D2[x]. Similarly, the remaining multiple data selection circuits 410[2] to 410[x] can split the remaining second signals S2[2] to S2[n] into multiple second data respectively.

[0051] In operation S420, the corresponding data among the second data is selected as the corresponding data among the first data based on the corresponding data among the multiple split signals. Taking the data selection circuit 410[1] as an example, as followsFigure 4B As shown, if the value of the split signal SS[1] is 1, the data selection circuit 410[1] can select the second data D2[1] as the first data D1 from multiple second data D2[1] to D2[x] according to the split signal SS[1]. If the value of the split signal SS[1] is 2, the split circuit 411[1] can select the second data D2[2] as the first data D1 from multiple second data D2[1] to D2[x] according to the split signal SS[1]. Similarly, if the value of the split signal SS[1] is x, the data selection circuit 410[1] can select the second data D2[x] as the first data D1 from multiple second data D2[1] to D2[x] according to the split signal SS[1]. Alternatively, if the value of the split signal SS[1] is not equal to any value from 1 to x, the split circuit 411[1] can set the first data D1 to a preset value (for example, but not limited to, 0). Similarly, the data selection circuit 410[2] can select the data as the first data D2 from multiple second data D2[1] to D2[x] according to the split signal SS[2], and the data selection circuit 410[x] can select the data as the first data Dx from multiple second data D2[1] to D2[x] according to the split signal SS[x].

[0052] In operation of S430, these first data are output as first debug data. For example, such as Figure 4A As shown, multiple data selection circuits 410[1]~410[x] can output multiple selected first data D1~Dx as first debugging data DO1.

[0053] Using the above functions, the required data can be selected from each of the multiple second signals S2[1] to S2[x] by setting the values ​​of multiple split signals SS[1] to SS[x], and the selected data can be recombined into the first debugging data DO1. In this way, the user can simultaneously read the debugging signals of x circuit systems in the multiple functional circuit systems 110[1] to 110[n] in the chip 100 through an external instrument.

[0054] Figure 5 Drawing based on some embodiments of this case Figure 1 A flowchart illustrating multiple operations performed by the switching circuit system 140. In some embodiments, the switching circuit system 140 may be performed by (but is not limited to) Figure 5 The operation is implemented by at least one digital logic circuit and / or at least one switching circuit.

[0055] In operation S510-1, it is confirmed whether the switching signal S[1] is a preset logic value (e.g., but not limited to, logic value 1). If the switching signal S[1] is the preset logic value, operation S510-2 is performed. If the switching signal S[1] is not the preset logic value, operation S510-3 is performed. In operation S510-2, the first data D1 in the first debug data DO1 is output via the output port P[1]. In operation S510-3, the bit B[1] in the at least one output signal VO is output via the output port P[1].

[0056] Similarly, in operation S520-1, it is confirmed whether the switching signal S[2] is a preset logic value. If the switching signal S[2] is the preset logic value, operation S520-2 is performed. If the switching signal S[2] is not the preset logic value, operation S520-3 is performed. In operation S520-2, the first data D2 in the first debug data DO1 is output via the output port P[2]. In operation S520-3, the bit B[2] in the at least one output signal VO is output via the output port P[2].

[0057] By analogy, in operation S5y0-1, it is confirmed whether the switching signal S[y] is a preset logic value. If the switching signal S[y] is the preset logic value, operation S5y0-2 is performed. If the switching signal S[y] is not the preset logic value, operation S5y0-3 is performed. In operation S5y0-2, the first data Dy in the first debug data DO1 is output via the output port P[y]. In operation S5y0-3, the bit B[y] in the at least one output signal VO is output via the output port P[y].

[0058] In other words, each output port P[1]~P[y] of the chip 100 can be controlled by a corresponding one of the plurality of switching signals S[1]~S[y]. When the corresponding one of the plurality of switching signals S[1]~S[y] has the preset logic value, the switching circuitry 140 can output a corresponding data in the first debug signal DO1 via a corresponding output port of the plurality of output ports P[1]~P[y]. Alternatively, when the corresponding one of the plurality of switching signals S[1]~S[y] does not have the preset logic value, the switching circuitry 140 can output a corresponding bit in the at least one output signal VO via the corresponding output port. By the above arrangement, the chip 100 can output the debug signal without adding extra output ports to verify whether the chip 100 operates correctly.

[0059] Figure 6A A schematic diagram of a chip 600 according to some embodiments of the present application. Compared with the chip 100, the chip 600 has a plurality of output ports P[1]~P[y] and a plurality of switching signals S[1]~S[y]. The chip 600 can output the first debug data DO1 via the plurality of output ports P[1]~P[y] and the plurality of switching signals S[1]~S[y]. The chip 600 can output the at least one output signal VO via the plurality of output ports P[1]~P[y] and the plurality of switching signals S[1]~S[y]. Figure 1In this example, chip 600 further includes a shift circuit system 610. The shift circuit system 610 is coupled to the data reconstruction circuit system 130 and the switching circuit system 140, and is used to selectively shift the first debug data DO1 according to the shift signal SF to generate the second debug data DO2. In some embodiments, the shift signal SF is used to indicate the number of bits to be shifted in the first debug DO1. If one of the multiple output ports P[1] to P[y] fails, or the number of multiple output ports P[1] to P[y] is insufficient, the shift signal SF can be set to shift the multiple first data D1 to Dx in the first debug data DO1, so that the multiple data of the multiple first data D1 to Dx that are to be observed or that are more important can be output through a limited number of output ports as multiple data of the second debug data DO2. In this way, it can be ensured that the debug signal to be observed can be read correctly to determine whether chip 600 has an error. In some embodiments, the shift circuit system 610 can be executed by (but is not limited to) Figure 6B The operation is implemented by at least one digital logic circuit and / or shift register circuit.

[0060] Figure 6B Drawing based on some embodiments of this case Figure 6A The flowchart illustrates the multiple operations performed by the shift circuit system 610. In operation S610, the value matched by the shift signal is confirmed. If a value matching the shift signal is found, operation S620 is executed. Alternatively, if a value matching the shift signal is not found, operation S640 is executed. In operation S620, the first debug data is shifted according to the value matched by the shift signal. In operation S630, the processed first debug data is output as second debug data. In operation S640, the first debug data is directly output as second debug data.

[0061] For example, the shift circuit system 610 can sequentially determine whether the shift signal SF is equal to one of a plurality of values ​​from 0 to x, in order to find the value matched by the shift signal SF. For example, if the shift signal SF is equal to 0, the shift circuit system 610 can determine that the value matched by the shift signal SF is 0. If the shift signal SF is equal to 1, the shift circuit system 610 can determine that the value matched by the shift signal SF is 1. And so on, if the shift signal SF is equal to x, the shift circuit system 610 can determine that the value matched by the shift signal SF is x.

[0062] Next, the shift circuit system 610 can right shift the plurality of first data D1-Dx in the first debug data DOl according to the value matched by the shift signal SF. For example, if the value matched by the shift signal SF is 0, the shift circuit system 610 does not right shift the first debug data DOl. In this condition, the first debug data DOl can be represented as [Dx, Dx-1,..., D2, Dl] (as shown in Figure 6A or, if the value matched by the shift signal SF is 1, the shift circuit system 610 right shifts the first debug data DOl by 1 bit. In this condition, the right shifted first debug data DOl can be represented as [Dl, Dx, Dx-1,..., D2], and the shift circuit system 610 can output the shifted first debug data DOl as the second debug data DO2. By analogy, if the value matched by the shift signal SF is x, the shift circuit system 610 right shifts the first debug data DOl by x bits. In this condition, the right shifted first debug data DOl can be represented as [Dx-1,..., D2, Dl, Dx], and the shift circuit system 610 can output the shifted first debug data DOl as the second debug data DO2.

[0063] Alternatively, if the shift circuit system 610 confirms that the shift signal SF is not equal to one of the plurality of values 1-x, it means that the shift signal SF can be incorrect. In this condition, the shift circuit system 610 does not right shift the first debug data DOl, so the first debug data DOl can still be represented as [Dx, Dx-1,..., D2, Dl]. The shift circuit system 610 can directly output the first debug data DOl as the second debug data DO2. The above examples are illustrated by right shifting, but the present application is not limited thereto. In different embodiments, the shift circuit system 610 can also be configured to left shift the first debug data DOl.

[0064] In the foregoing embodiments, the plurality of address signals ADR[1]-ADR[x], the plurality of split signals SS[1]-SS[x], the plurality of switch signals S[1]-S[y] and / or the shift signal SF can be stored in at least one register circuit (not shown) in the chip 100 (or the chip 600). The user can set the values of the plurality of address signals ADR[1]-ADR[x], the plurality of split signals SS[1]-SS[x], the plurality of switch signals S[1]-S[y] and / or the shift signal SF by using an external instrument and / or a programmable logic array (FPGA) and the like, so as to read out the debug signals to be observed from the chip 100 (or the chip 600).

[0065] Figure 7A flowchart of a chip debugging method 700 according to some embodiments is shown. In operation S710, a plurality of first signals of a plurality of sets of debugging signals are output according to a plurality of address signals, wherein the debugging signals are respectively generated by a plurality of functional circuit systems of a chip. In operation S720, a plurality of second signals are selected from the first signals according to the address signals. In operation S730, a plurality of first data are selected from the second signals according to a plurality of split signals and output as first debugging data, wherein each of the first data is a partial data of a corresponding signal of the second signals. In operation S740, it is determined whether to output the first debugging data or at least one output signal associated with the functional circuit systems via a plurality of output ports of the chip according to a plurality of switch signals.

[0066] The above operations can be understood with reference to the descriptions of the above embodiments, and thus will not be repeated here. Through the above operations, a user can selectively obtain debugging signals in different circuit systems of a chip and analyze the debugging signals through an oscilloscope or a logic analyzer to confirm the source of errors in the chip. In this way, a large number of debugging signals can be read out without using additional output ports, thereby improving the efficiency of chip verification.

[0067] In Figure 2C , Figure 3B , Figure 4B , Figure 5 , Figure 6B and / or Figure 7 The operations in the above figures are just examples, and are not limited to the order in which they are executed. Without departing from the operation mode and scope of the embodiments, the above operations can be appropriately added, replaced, omitted, or executed in different order. Alternatively, one or more of the above operations can be executed simultaneously or partially simultaneously.

[0068] In summary, the chip with debugging function and the chip debugging method in some embodiments can selectively switch the debugging signals output through a limited number of output ports, thereby improving the efficiency of chip verification.

[0069] Although the embodiments of the present application are described above, the embodiments are not intended to limit the present application. Those skilled in the art can make changes to the technical features of the present application according to the explicit or implicit content of the present application, and such changes can all fall within the scope of the patent protection sought by the present application. In other words, the scope of patent protection of the present application shall be subject to the patentable scope defined by the application patent range.

[0070] Symbol explanation

[0071] 100: chip

[0072] 110[1]~110[n]: functional circuitry

[0073] 111[1]~111[n]: functional circuit

[0074] 112[1]~112[n]: decoding circuit

[0075] 120: selection circuitry

[0076] 130: data reconstruction circuitry

[0077] 140: switching circuitry

[0078] 150: output circuitry

[0079] 210: table lookup circuit

[0080] 220: comparison circuit

[0081] 310[1]~310[x]: selection circuit

[0082] 410[1]~410[x]: data selection circuit

[0083] 411[1]: splitting circuit

[0084] 412[1]: reconstruction circuit

[0085] 600: chip

[0086] 610: shift circuitry

[0087] 700: chip debugging method

[0088] 1~A1, A1+1~A2+ A1, A1+A2+…+1~A1+A2+…+An: address

[0089] ADR: corresponding address signal

[0090] ADR[1]~ADR[x]: address signal

[0091] B[1]~B[y]: bit

[0092] D1~Dx, Dy: first data

[0093] DB[1]~DB[n]: set of debugging signals

[0094] DO1: first debugging data

[0095] DO2: second debugging data

[0096] F1~Fn: preset flag value

[0097] P[1]~P[y]: output port

[0098] S[1]~S[y]: switching signal

[0099] S1[1]~S1[n]: first signal

[0100] S2[1]~S2[x]: second signal

[0101] S210, S220, S230, S310, S320, S330, S410, S420, S430: operation

[0102] S510-1, S510-2, S510-3, S520-1, S520-2, S520-3, S5y0-1, S5y0-2, S5y0-3: operation

[0103] S610, S620, S630, S640, S710, S720, S730, S740: operation

[0104] SF: shift signal

[0105] SS[1]~SS[x]: split signal

[0106] VO: at least one output signal

[0107] d1[1]~d1[A1-1], d2[1]~d2[A2-1], dn[1]~dn[An-1]: debug signal

Claims

1. A chip with debug function, comprising: a plurality of functional circuitry for generating a plurality of sets of debug signals, respectively, wherein each of the plurality of functional circuitry comprises a decoding circuit for storing a corresponding set of debug signals of the plurality of sets of debug signals and outputting a corresponding debug signal of the corresponding set of debug signals as a corresponding signal of a plurality of first signals according to a corresponding address signal of a plurality of address signals; a selection circuitry for selecting a plurality of second signals from the plurality of first signals according to the plurality of address signals; a data reconstruction circuitry for selecting a plurality of first data from the plurality of second signals according to a plurality of split signals and outputting the plurality of first data as first debug data, wherein each of the plurality of first data is a partial data of a corresponding signal of the plurality of second signals; and a switching circuitry for determining whether to output the first debug data or at least one output signal associated with the plurality of functional circuitry via a plurality of output ports according to a plurality of switching signals, wherein the at least one output signal is a signal generated by at least one of the plurality of functional circuitry performing a predetermined function.

2. The chip with debug function of claim 1, wherein all of the debug signals of the plurality of sets of debug signals have a same bit number.

3. The chip with debug function of claim 1, wherein the plurality of sets of debug signals correspond to a plurality of address ranges that are sequentially increasing, respectively, and the decoding circuit is further for sequentially confirming whether the plurality of address signals match a corresponding address range of the plurality of address ranges to select the corresponding address signal.

4. The chip with debug function of claim 1, wherein the decoding circuit is further for storing a predetermined flag value, and when the corresponding address signal is a predetermined address, the decoding circuit is for outputting the predetermined flag value as the corresponding signal of the plurality of first signals to verify whether the decoding circuit correctly outputs the corresponding signal of the plurality of first signals.

5. The chip with debug function of claim 1, wherein the plurality of sets of debug signals correspond to a plurality of address ranges that are sequentially increasing, respectively, the selection circuitry comprises a plurality of selection circuits, and each of the plurality of selection circuits is for comparing a corresponding one of the plurality of address signals with the plurality of address ranges to select a corresponding one of the plurality of second signals from the plurality of first signals.

6. The chip with debug function of claim 1, wherein the data reconstruction circuitry comprises a plurality of data selection circuits, and each of the plurality of data selection circuits is for splitting a corresponding one of the plurality of second signals into a plurality of second data and selecting a corresponding data from the plurality of second data according to a corresponding one of the plurality of split signals as a corresponding one of the plurality of first data.

7. The chip with debug function of claim 1, wherein the switching circuitry is for determining whether to output a corresponding data of the first debug data or a corresponding bit of the at least one output signal via a corresponding one of the plurality of output ports according to a corresponding one of the plurality of switching signals.

8. The chip with debug function of claim 1, further comprising: ​ shift circuitry for selectively shifting the first debug data according to a shift signal to generate second debug data, wherein the switch circuitry is further configured to determine whether to output corresponding data in the second debug data or corresponding bits in the at least one output signal via the output ports according to the switch signals.

9. The chip with debug function of claim 8, wherein the shift signal is used to indicate a number of bits to be shifted in the first debug data.

10. A chip debug method, comprising: outputting a plurality of first signals in a plurality of debug signals according to a plurality of address signals, wherein the plurality of debug signals are respectively generated by a plurality of functional circuitries of a chip; selecting a plurality of second signals from the plurality of first signals according to the plurality of address signals; selecting a plurality of first data from the plurality of second signals according to a plurality of split signals, and outputting the plurality of first data as first debug data, wherein each of the plurality of first data is a partial data of a corresponding signal in the plurality of second signals; and determining whether to output the first debug data or at least one output signal associated with the plurality of functional circuitries via a plurality of output ports of the chip according to a plurality of switch signals, wherein the at least one output signal is a signal generated by at least one of the plurality of functional circuitries when performing a predetermined function. ​

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