A processing method and system supporting PCIe bus ordering rules, a terminal and a medium

Abstract

The application relates to the field of integrated circuit design and discloses a processing method and system supporting PCIe bus ordering rules, a terminal and a medium, wherein the sequence number of a received transaction layer packet remains unchanged under certain conditions, the sequence number of a next transaction layer packet received when the cache for storing the transaction layer packet is empty is rolled back to the minimum value, and the like, so that multiple transaction layer packets can use the same sequence number; the sequence number is timely rolled back to the initial minimum value when the sequence number does not reach the maximum value; and the transaction layer packet reading method of the application is used, so that the number of bits constituting the sequence number remains unchanged; the time for the sequence number to increase to the maximum value is greatly delayed under the premise that the transaction layer packet reading scheduling in the cache is guaranteed to follow the PCIe ordering rules; and the cache writing of the transaction layer packet and the sequence number generation are suspended until the cache is empty, so that the damage of the PCIe ordering rules to the transaction layer packet reading scheduling in the cache caused by the sequence number roll back after the sequence number is set to the maximum value is solved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, specifically to a processing method, system, terminal, and medium that supports PCIe bus sequencing rules. Background Technology

[0002] The PCIe bus, as a third-generation high-performance I / O bus, is widely used in computer systems. A PCIe bus device consists of transaction layer packets, a data link layer, and a physical layer. Transaction layer packets are data packets generated and transmitted by the transaction layer—the highest layer in the PCIe bus hierarchy. Transaction layer packets include memory transaction requests, I / O transaction requests, configuration transaction requests, message requests, and completion packets (CPL TLP). Memory write requests and message requests are forwarded transaction layer packets (Posted TLP, PTLP), while I / O transaction requests, configuration transaction requests, and memory read requests are non-posted transaction layer packets (Non-Posted TLP, NP TLP).

[0003] To avoid problems such as deadlock, the PCIe bus has established a set of sorting rules for three types of transaction layer packets: P transaction layer packets, NP transaction layer packets, and completion packets. The transmission of each type of transaction layer packet must meet these sorting rules.

[0004] Existing technologies use the method of storing each received transaction layer packet in the circuit with a timestamp or a sequence number to achieve first-in-first-out transmission scheduling that conforms to the PCIe sorting rules. However, no literature mentions how to avoid and deal with the important problem of the recorded transaction layer packet receiving order being disordered due to the rollback after the maximum value of the timestamp or sequence number. Summary of the Invention

[0005] In order to overcome the defects of the prior art, the present invention aims to provide a processing method, system, terminal and medium that supports PCIe bus sorting rules, so as to solve the technical problem that the order of receiving transaction layer packets is disordered due to the rollback after the maximum value of the timestamp or sequence number in the prior art.

[0006] This invention is achieved through the following technical solution:

[0007] A processing method that supports PCIe bus sorting rules includes the following steps:

[0008] Step 1: Number the PCIe bus transaction layer packets with serial numbers. By keeping the serial number of a received transaction layer packet unchanged and the buffer storing the transaction layer packets is empty, the serial number of the next received transaction layer packet is rolled back to the minimum value, so that multiple transaction layer packets can use the same serial number. The serial number is rolled back to the initial minimum value before reaching the maximum value, thus completing the generation of the serial number.

[0009] Step 2: Pause the writing of the PCIe bus transaction layer packet with the generated serial number to the cache and generate the serial number until the cache is empty, and then read the PCIe bus transaction layer packet.

[0010] Preferably, in step 1, the specific process of serializing the PCIe bus transaction layer packets is as follows:

[0011] Step 11: Set the sequence number of the first received transaction layer packet to the minimum value 0, and generate the sequence number of the next transaction layer packet by incrementing the sequence number of the previous transaction layer packet by 1.

[0012] Step 12: Determine if the transaction layer packet cache is empty;

[0013] Step 13: When the transaction layer packet buffer is empty, the sequence number of the received transaction layer packet is set to the minimum value of 0, regardless of the sequence number of the previous transaction layer packet, thus completing the generation of the current sequence number.

[0014] Step 14: When the transaction layer packet cache is not empty, determine whether the received transaction layer packet meets the set conditions.

[0015] Step 15: When the set conditions are met, the sequence number of the received transaction layer packet is set to be the same as the sequence number of the previous transaction layer packet, thus completing the generation of the current sequence number.

[0016] Step 16: When the set conditions are not met, determine whether the sequence number of the previous transaction layer packet is equal to the maximum value that can be represented by the multiple bits that make up the sequence number;

[0017] Step 17: When the sequence number of the current transaction layer packet is equal to the maximum value that can be represented by the multiple bits that make up the sequence number and the cache of the transaction layer packet is not empty, pause the cache writing and sequence number generation of the transaction layer packet until the cache of the transaction layer packet is empty, and return to execute step 13.

[0018] Step 18: When the sequence number of the previous transaction layer packet is not equal to the maximum value that can be represented by the multiple bits that make up the sequence number, the sequence number of the previous transaction layer packet is incremented by 1 and used as the sequence number of the received transaction layer packet, thus completing the generation of the current sequence number.

[0019] Furthermore, in step 14, the setting conditions are set according to the transaction layer packet type, wherein the transaction layer packet type includes forwarding transaction layer packets, non-forwarding transaction layer packets, or completion packets;

[0020] The conditions set include the following:

[0021] a. The next transaction layer packet and the previous transaction layer packet have the same type, where the same type means that they are both forwarding transaction layer packets, both non-forwarding transaction layer packets, or both completion packets;

[0022] b. If the preceding transaction layer packet is a forwarding transaction layer packet, the next transaction layer packet will be a non-forwarding transaction layer packet or a completion packet.

[0023] c. The preceding transaction layer packet is a completion packet, and the following transaction layer packet is a non-forwarding transaction layer packet.

[0024] Furthermore, in step 17, when the transaction layer packet cache is not empty, execution can still be performed based on the transaction layer packet cache status, and the execution status is as follows:

[0025] If the sequence number of the previous transaction layer packet is equal to the maximum value that can be represented by the multiple bits that make up the sequence number and there are only non-forwarded transaction layer packets in the buffer, continue to receive the next transaction layer packet and set its sequence number to 0;

[0026] If the sequence number of the previous transaction layer packet is equal to the maximum value that can be represented by the multiple bits that make up the sequence number, and there is a completion packet or a forwarded transaction layer packet in the buffer, and the next transaction layer packet is a forwarded transaction layer packet, then continue to receive the next transaction layer packet and set its sequence number to the maximum sequence number value in the forwarded transaction layer packet and the completion packet in the buffer;

[0027] When the cache storing transaction layer packets contains only one type of transaction layer packet, you can choose to reset the sequence number of all transaction layer packets of that type in the cache to 0, and set the sequence number of the next transaction layer packet to 1.

[0028] Furthermore, after step 13, it can be determined whether there are only transaction layer packets of the same type in the cache of the stored transaction layer packets. If there are not only transaction layer packets of the same type in the cache of the stored transaction layer packets, step 14 is executed. Otherwise, the sequence number of all transaction layer packets of that type in the cache is reset to 0 and the sequence number of the next transaction layer packet is set to 1, thus completing the generation of the current sequence number.

[0029] Preferably, in step 2, the steps for reading the completed PCIe bus transaction layer packet are as follows:

[0030] Step 21: Monitor and compare the transaction layer packet sequence numbers at the head of each queue in the packet header FIFO of the transaction layer packet type, where the transaction layer packet type includes forwarding transaction layer packets, non-forwarding transaction layer packets, or completion packets;

[0031] Step 22: Select a transaction layer packet to read based on the size relationship of the sequence number and the type of different transaction layer packets.

[0032] Furthermore, during the reading process, if there is only one type of transaction layer packet in the cache, then that transaction layer packet is read;

[0033] When there are only two types of transaction layer packets in the cache, if the sequence numbers of the two transaction layer packets are different, the transaction layer packet with a smaller sequence number is read; if the sequence numbers of the two transaction layer packets are the same and there is a forwarding transaction layer packet, the forwarding transaction layer packet is read; otherwise, the completion transaction layer packet is read;

[0034] When there are three types of transaction layer packets in the cache, reading is performed according to the following conditions:

[0035] A. When the sequence number of one type of transaction layer packet is smaller than the sequence numbers of the other two types of transaction layer packets, read the transaction layer packet of the type with the minimum sequence number;

[0036] B. When the sequence numbers of the three types of transaction layer packets are the same, abbreviated as P=CPL=NP, read the forwarding transaction layer packet;

[0037] C. Among the three types of transaction layer packets, when the sequence number of the forwarding transaction layer packet is smaller than the sequence number of the non-forwarding transaction layer packet, and the sequence number of the completion packet is the same as that of the forwarding transaction layer packet, abbreviated as P=CPL<NP, read the forwarding transaction layer packet;

[0038] D. Among the three types of transaction layer packets, when the sequence number of the forwarding transaction layer packet is smaller than the sequence number of the completion packet, and the sequence number of the forwarding transaction layer packet is the same as that of the non-forwarding transaction layer packet, abbreviated as P=NP<CPL, read the forwarding transaction layer packet;

[0039] E. Among the three types of transaction layer packets, when the sequence number of the forwarding transaction layer packet is greater than that of the completion packet, and the sequence number of the completion packet is the same as that of the non-forwarding transaction layer packet, abbreviated as P>CPL=NP, read the completion packet.

[0040] A processing system supporting PCIe bus ordering rules, comprising

[0041] a data numbering module, configured to number sequence numbers for PCIe bus transaction layer packets, wherein the sequence number of a received transaction layer packet remains unchanged; when the cache storing transaction layer packets is empty, the sequence number of the next received transaction layer packet is wrapped around to the minimum value, so that multiple transaction layer packets can use the same sequence number, and the sequence number is wrapped around to the initial minimum value before reaching the maximum value, completing the generation of sequence numbers;

[0042] a data reading module, configured to perform cache writing of suspended transaction layer packets for the PCIe bus transaction layer packets with generated sequence numbers, reset the sequence number generation to cache empty, and complete reading of PCIe bus transaction layer packets.

[0043] A mobile terminal includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of a processing method supporting PCIe bus sorting rules as described above.

[0044] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of a processing method supporting PCIe bus sorting rules as described above.

[0045] Compared with the prior art, the present invention has the following beneficial technical effects:

[0046] This invention provides a processing method supporting PCIe bus sequencing rules. Based on the strict first-in-first-out (FIFO) characteristic of three types of transaction layer packets—forwarded transaction layer packets, non-forwarded transaction layer packets, and completion packets—it provides a PCIe bus transaction layer packet serial numbering method and a transaction layer packet reading method. It uniformly assigns serial numbers to different types of transaction layer packets based on the receiving order. Through methods such as maintaining the serial number of a received transaction layer packet unchanged under certain conditions and ensuring that the serial number of the next received transaction layer packet is minimized when the buffer storing transaction layer packets is empty, multiple transaction layer packets can use the same sequence. The sequence number promptly reverts to its initial minimum value before reaching its maximum value. Combined with the invented transaction layer packet reading method, this significantly delays the time it takes for the sequence number to increment to its maximum value while maintaining the PCIe sorting rules for transaction layer packet read scheduling in the cache, all while ensuring the sequence number remains constant. This reduces the transaction layer packet's demand for sequence number resources and effectively lowers the hardware overhead of the transaction layer packet sequence number. Furthermore, by pausing transaction layer packet cache writing and sequence number generation until the cache is empty, the disruption of the PCIe sorting rules during transaction layer packet read scheduling in the cache after the sequence number is set to its maximum value is resolved. Attached Figure Description

[0047] Figure 1 This is a flowchart of the processing method supporting PCIe bus sorting rules in this invention;

[0048] Figure 2 This is a flowchart of the PCIe bus transaction layer packet sequence number numbering method according to Embodiment 1 of the present invention;

[0049] Figure 3 This is a flowchart of the PCIe bus transaction layer packet sequence numbering method according to Embodiment 2 of the present invention;

[0050] Figure 4 This is a flowchart of a PCIe bus transaction layer packet reading method according to an embodiment of the present invention;

[0051] Figure 5 This is a schematic diagram illustrating the storage of sequence numbers in the cache queue for the transaction layer in an embodiment of the present invention. Detailed Implementation

[0052] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0053] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0054] The present invention will now be described in further detail with reference to the accompanying drawings:

[0055] The purpose of this invention is to provide a processing method, system, terminal, and medium that supports PCIe bus sorting rules, so as to solve the technical problem in the prior art that the order of receiving transaction layer packets is disordered due to the rollback after the maximum value of the timestamp or sequence number.

[0056] Specifically, according to Figure 1 As shown, this processing method that supports PCIe bus sorting rules includes the following steps:

[0057] Step 1: Number the PCIe bus transaction layer packets with serial numbers. By keeping the serial number of a received transaction layer packet unchanged and the buffer storing the transaction layer packets is empty, the serial number of the next received transaction layer packet is rolled back to the minimum value, so that multiple transaction layer packets can use the same serial number. The serial number is rolled back to the initial minimum value before reaching the maximum value, thus completing the generation of the serial number.

[0058] Step 2: Pause the writing of the PCIe bus transaction layer packet with the generated serial number to the cache and generate the serial number until the cache is empty, and then read the PCIe bus transaction layer packet.

[0059] Specifically, in step 1, the process of serializing PCIe bus transaction layer packets is as follows:

[0060] Step 11: Set the sequence number of the first received transaction layer packet to the minimum value 0, and generate the sequence number of the next transaction layer packet by incrementing the sequence number of the previous transaction layer packet by 1.

[0061] Step 12: Determine if the transaction layer packet cache is empty;

[0062] Step 13: When the transaction layer packet buffer is empty, the sequence number of the received transaction layer packet is set to the minimum value of 0, regardless of the sequence number of the previous transaction layer packet, thus completing the generation of the current sequence number.

[0063] Step 14: When the transaction layer packet cache is not empty, determine whether the received transaction layer packet meets the set conditions.

[0064] Step 15: When the set conditions are met, the sequence number of the received transaction layer packet is set to be the same as the sequence number of the previous transaction layer packet, thus completing the generation of the current sequence number.

[0065] Step 16: When the set conditions are not met, determine whether the sequence number of the previous transaction layer packet is equal to the maximum value that can be represented by the multiple bits that make up the sequence number;

[0066] Step 17: When the sequence number of the current transaction layer packet is equal to the maximum value that can be represented by the multiple bits that make up the sequence number and the cache of the transaction layer packet is not empty, pause the cache writing and sequence number generation of the transaction layer packet until the cache of the transaction layer packet is empty, and return to execute step 13.

[0067] Step 18: When the sequence number of the previous transaction layer packet is not equal to the maximum value that can be represented by the multiple bits that make up the sequence number, the sequence number of the previous transaction layer packet is incremented by 1 and used as the sequence number of the received transaction layer packet, thus completing the generation of the current sequence number.

[0068] In step 14, the setting conditions are set according to the transaction layer packet type, which includes forwarded transaction layer packets, non-forwarded transaction layer packets, or completion packets.

[0069] The conditions set include the following:

[0070] a. The next transaction layer packet and the previous transaction layer packet have the same type, where the same type means that they are both forwarding transaction layer packets, both non-forwarding transaction layer packets, or both completion packets;

[0071] b. If the preceding transaction layer packet is a forwarding transaction layer packet, the next transaction layer packet will be a non-forwarding transaction layer packet or a completion packet.

[0072] c. The preceding transaction layer packet is a completion packet, and the following transaction layer packet is a non-forwarding transaction layer packet.

[0073] In step 17, when the transaction layer packet cache is not empty, the execution can also be performed based on the transaction layer packet cache status, and the execution status is as follows:

[0074] If the sequence number of the previous transaction layer packet is equal to the maximum value that can be represented by the multiple bits that make up the sequence number and there are only non-forwarded transaction layer packets in the buffer, continue to receive the next transaction layer packet and set its sequence number to 0;

[0075] If the sequence number of the previous transaction layer packet is equal to the maximum value that can be represented by the multiple bits that make up the sequence number, and there is a completion packet or a forwarded transaction layer packet in the buffer, and the next transaction layer packet is a forwarded transaction layer packet, then continue to receive the next transaction layer packet and set its sequence number to the maximum sequence number value in the forwarded transaction layer packet and the completion packet in the buffer;

[0076] When the cache storing transaction layer packets contains only one type of transaction layer packet, you can choose to reset the sequence number of all transaction layer packets of that type in the cache to 0, and set the sequence number of the next transaction layer packet to 1.

[0077] In step 13, it can be determined whether the cache storing transaction layer packets contains only transaction layer packets of the same type. If the cache storing transaction layer packets contains more than one type of transaction layer packets, step 14 is executed. Otherwise, the sequence number of all transaction layer packets of that type in the cache is reset to 0 and the sequence number of the next transaction layer packet is set to 1, thus completing the generation of the current sequence number.

[0078] Specifically, in step 2, the steps for reading the completed PCIe bus transaction layer packet are as follows:

[0079] Step 21: Monitor and compare the transaction layer packet sequence numbers at the head of each queue in the packet header FIFO of the transaction layer packet type, where the transaction layer packet type includes forwarding transaction layer packets, non-forwarding transaction layer packets, or completion packets;

[0080] Step 22: Select a transaction layer packet to read based on the size relationship of the sequence number and the type of different transaction layer packets.

[0081] During the reading process, if there is only one type of transaction layer packet in the cache, then that transaction layer packet is read.

[0082] When there are only two types of transaction layer packets in the cache, if the sequence numbers of the two transaction layer packets are different, the transaction layer packet with the smaller sequence number is read; if the sequence numbers of the two transaction layer packets are the same and there is a forwarded transaction layer packet, the forwarded transaction layer packet is read; otherwise, the complete transaction layer packet is read.

[0083] When there are three types of transaction layer packets in the cache, reading is performed according to the following cases.

[0084] A. When the sequence number of one type of transaction layer packet is smaller than the sequence numbers of the other two types of transaction layer packets, read the transaction layer packet of the type with the minimum sequence number;

[0085] B. When the sequence numbers of the three types of transaction layer packets are the same, abbreviated as P=CPL=NP, read the posted transaction layer packet;

[0086] C. When among the three types of transaction layer packets, the sequence number of the posted transaction layer packet is smaller than the sequence number of the non-posted transaction layer packet, and the sequence number of the completion packet is the same as that of the posted transaction layer packet, abbreviated as P=CPL<NP, read the posted transaction layer packet;

[0087] D. When among the three types of transaction layer packets, the sequence number of the posted transaction layer packet is smaller than the sequence number of the completion packet, and the sequence number of the posted transaction layer packet is the same as that of the non-posted transaction layer packet, abbreviated as P=NP<CPL, read the posted transaction layer packet;

[0088] E. When among the three types of transaction layer packets, the sequence number of the posted transaction layer packet is greater than that of the completion packet, and the sequence number of the completion packet is the same as that of the non-posted transaction layer packet, abbreviated as P>CPL=NP, read the completion packet.

[0089] Example 1

[0090] In the transaction layer packet sending cache of the PCIe bus interface of a certain circuit, three caches are provided, namely posted transaction layer packet FIFO, non-posted transaction layer packet FIFO and completion packet FIFO. In the same FIFO, the transaction layer packet written first is read out for transmission first. Figure 2 It is a flow chart of the implementation of the PCIe bus transaction layer packet sequence number numbering method of Embodiment 1 in this circuit;

[0091] In this embodiment, an 8-bit sequence number is set for each transaction layer packet received by the PCIe bus interface from other logic in the circuit, and the reset initial value of the sequence number is 0. After the PCIe interface receives a transaction layer packet from other logic in the circuit, the sequence number of the transaction packet is generated according to the following steps:

[0092] Step 1: Determine whether the cache of the transaction layer packet is empty; when the cache storing the transaction layer packet is empty, go to step 2, otherwise go to step 3;

[0093] Step 2: The cache storing the transaction layer packet is empty, which is irrelevant to the sequence number of the previous transaction layer packet. The sequence number of the received transaction layer packet is set to the minimum value 0, and the generation of the current sequence number is completed;

[0094] Step 3: The cache storing the transaction layer packet is not empty, determine whether the received transaction layer packet meets one of the following three conditions:

[0095] (1) The type of the received transaction layer packet is the same as that of the previous transaction layer packet; the same type means that they are both forwarding transaction layer packets, both non-forwarding transaction layer packets, or both completion packets;

[0096] (2) The previous transaction layer packet is a forwarding transaction layer packet, and the received transaction layer packet is a non-forwarding transaction layer packet or a completion packet;

[0097] (3) The previous transaction layer packet is a completion packet, and the received transaction layer packet is a non-forwarding transaction layer packet;

[0098] If the received transaction layer packet meets one of the three conditions in step 3 above, proceed to step 4; otherwise, proceed to step 5.

[0099] Step 4: The received transaction layer packet meets one of the three conditions in Step 3 above, and the sequence number of the received transaction layer packet is set to be the same as the sequence number of the previous transaction layer packet.

[0100] Step 5: If the received transaction layer packet does not meet one of the three conditions in Step 3 above, this step determines whether the sequence number of the previous transaction layer packet is the maximum value of 255; if the sequence number is equal to the maximum value of 255, proceed to Step 6; otherwise, proceed to Step 7.

[0101] Step 6: The sequence number of the previous transaction layer packet is equal to the maximum value of 255. Since the transaction layer packet cache is not empty at this time, pause the cache writing and sequence number generation of the transaction layer packet, and wait for the cache to be empty before proceeding to step 2.

[0102] Step 7: If the sequence number of the previous transaction layer packet is less than the maximum value of 255, add 1 to the sequence number of the previous transaction layer packet and use it as the sequence number of the received transaction layer packet to complete the generation of the current sequence number.

[0103] Example 2

[0104] To simplify the complexity of sequence number generation, when the cache storing transaction layer packets contains only transaction layer packets of the same type, Implementation 1 does not implement a method to reset the sequence number of all transaction layer packets of that type in the cache to 0 and set the sequence number of the next transaction layer packet to 1.

[0105] like Figure 3 As shown in the flowchart, Embodiment 2 adds the following two steps between steps 1 and 3 of Embodiment 1 to implement a method that resets the sequence number of all transaction layer packets of the same type in the cache to 0 and sets the sequence number of the next transaction layer packet to 1 when the cache storing transaction layer packets contains only transaction layer packets of the same type:

[0106] Step 8: Determine whether the cache storing transaction layer packets contains only transaction layer packets of the same type; if the cache storing transaction layer packets does not contain only transaction layer packets of the same type, proceed to step 3; otherwise, proceed to step 9.

[0107] Step 9: Reset the sequence number of all transaction layer packets of this type in the cache to 0 and set the sequence number of the next transaction layer packet to 1 to complete the generation of the sequence number;

[0108] Similarly, by adding several steps after step 5 in Embodiment 1, it is possible to achieve the following: when the sequence number of the current transaction layer packet is equal to the maximum value of 255 and the buffer contains only non-forwarded transaction layer packets, continue to receive the next transaction layer packet and set its sequence number to 0; or when the sequence number of the current transaction layer packet is equal to the maximum value of 255 and the buffer contains a completion packet or a forwarded transaction layer packet and the next transaction layer packet is a forwarded transaction layer packet, continue to receive the next transaction layer packet and set its sequence number to the maximum sequence number value among the forwarded transaction layer packets and completion packets in the buffer; these details will not be elaborated here.

[0109] Example 3

[0110] according to Figure 4 The diagram shows a flowchart of an embodiment of the transaction layer packet reading method corresponding to the PCIe bus transaction layer packet serial number numbering method in Embodiment 3. To monitor and compare the transaction layer packet serial numbers at the head of each of the three types of packet header FIFOs, a transaction layer packet is selected for reading based on the size relationship of the serial numbers and the different types of transaction layer packets, as detailed below:

[0111] Step 1: If the cache contains only one type of transaction layer packet, read that transaction layer packet; otherwise, proceed to Step 2.

[0112] Step 2: When there are only two types of transaction layer packets in the cache, if the sequence numbers of the two transaction layer packets are different, read the transaction layer packet with the smaller sequence number; if the sequence numbers of the two transaction layer packets are the same and there is a forwarded transaction layer packet, read the forwarded transaction layer packet; otherwise, read the completed transaction layer packet. When there are three types of transaction layer packets in the cache, proceed to step 3.

[0113] Step 3: If the sequence number of a transaction layer packet of one type is less than the sequence numbers of the other two types of transaction layer packets, read the transaction layer packet of the type with the smallest sequence number; otherwise, proceed to step 4.

[0114] Step 4: If the sequence numbers of the three types of transaction layer packets are the same, read and forward the transaction layer packet; otherwise, proceed to step 5.

[0115] Step 5: If the sequence number of the forwarded transaction layer packet in the three types of transaction layer packets is less than the sequence number of the non-forwarded transaction layer packet and the sequence number of the completed packet is the same as the sequence number of the forwarded transaction layer packet, or if the sequence number of the forwarded transaction layer packet in the three types of transaction layer packets is less than the sequence number of the completed packet and the sequence number of the forwarded transaction layer packet is the same as the sequence number of the non-forwarded transaction layer packet, read the forwarded transaction layer packet; otherwise, proceed to step 6.

[0116] Step 6: In the three types of transaction layer packets, if the sequence number of the forwarded transaction layer packet is greater than that of the completion packet and the sequence number of the completion packet is the same as that of the non-forwarded transaction layer packet, read the completion packet.

[0117] Example 4:

[0118] Figure 5 This is a sequence numbering method for PCIe bus transaction layer packets in Embodiment 4, used to assign and store sequence numbers for 10 consecutively received transaction layer packets in three different transaction layer packet queues; the numbers in [] are the sequence numbers, and the numbers outside [] are the order in which the transaction layer packets were received; it can be seen that only two sequence numbers, 0 and 1, are used for the 10 transaction layer packets; assuming completion Figure 4 After the 10 types of transaction layer packets shown are stored, the receiver can receive the stored transaction layer packets. The order of the transaction layer packets read using the transaction layer packet reading method of the present invention is 2, 6, 1, 0, 3, 4, 5, 7, 10, 8, 9. It can be seen that although the 2nd, 6th, 1st, and 10th transaction layer packets surpass the transaction layer packets received earlier, such as the 0th and 3rd, they still comply with the PCIe ordering rules that forwarded transaction layer packets can surpass non-forwarded transaction layer packets and completion packets, and completion packets can surpass non-forwarded transaction layer packets.

[0119] The present invention also provides a processing system that supports PCIe bus sorting rules, including a data numbering module and a data reading module;

[0120] The data numbering module is used to assign serial numbers to PCIe bus transaction layer packets. By keeping the serial number of a received transaction layer packet unchanged and storing the transaction layer packet buffer as empty, the serial number of the next received transaction layer packet is rolled back to the minimum value, so that multiple transaction layer packets can use the same serial number. The serial number is rolled back to the initial minimum value before reaching the maximum value, thus completing the generation of the serial number.

[0121] The data reading module is used to pause the writing of the PCIe bus transaction layer packet with the generated serial number to the cache and generate the serial number until the cache is empty, and to read the PCIe bus transaction layer packet.

[0122] The present invention also provides a mobile terminal, including a memory, a processor, and a computer program stored in the memory and executable on the processor, such as a processor that supports PCIe bus sorting rules.

[0123] When the processor executes the computer program, it implements the steps of the above-described processing method that supports PCIe bus sorting rules, for example:

[0124] The PCIe bus transaction layer packets are serialized. By keeping the serial number of a received transaction layer packet unchanged and the buffer storing the transaction layer packets is empty, the serial number of the next received transaction layer packet is rolled back to the minimum value, so that multiple transaction layer packets can use the same serial number. The serial number is rolled back to the initial minimum value before reaching the maximum value, thus completing the generation of the serial number.

[0125] The process involves pausing the writing of the PCIe bus transaction layer packet with the generated serial number to the cache and generating the serial number until the cache is empty, then reading the PCIe bus transaction layer packet.

[0126] Alternatively, when the processor executes the computer program, it implements the functions of each module in the above system, for example:

[0127] The data numbering module is used to assign serial numbers to PCIe bus transaction layer packets. By keeping the serial number of a received transaction layer packet unchanged and storing the transaction layer packet buffer as empty, the serial number of the next received transaction layer packet is rolled back to the minimum value, so that multiple transaction layer packets can use the same serial number. The serial number is rolled back to the initial minimum value before reaching the maximum value, thus completing the generation of the serial number.

[0128] The data reading module is used to pause the writing of the PCIe bus transaction layer packet with the generated serial number to the cache and generate the serial number until the cache is empty, and to read the PCIe bus transaction layer packet.

[0129] For example, the computer program can be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules / units can be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of the computer program in the mobile terminal. For example, the computer program can be divided into a data numbering module and a data reading module, with the specific functions of each module as follows:

[0130] The data numbering module is used to assign serial numbers to PCIe bus transaction layer packets. By keeping the serial number of a received transaction layer packet unchanged and storing the transaction layer packet buffer as empty, the serial number of the next received transaction layer packet is rolled back to the minimum value, so that multiple transaction layer packets can use the same serial number. The serial number is rolled back to the initial minimum value before reaching the maximum value, thus completing the generation of the serial number.

[0131] The data reading module is used to pause the writing of the PCIe bus transaction layer packet with the generated serial number to the cache and generate the serial number until the cache is empty, and to read the PCIe bus transaction layer packet.

[0132] The mobile terminal can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. The mobile terminal may include, but is not limited to, a processor and a memory.

[0133] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. This processor is the control center of the mobile terminal, connecting all parts of the mobile terminal via various interfaces and lines.

[0134] The memory can be used to store the computer program and / or module. The processor implements various functions of the mobile terminal by running or executing the computer program and / or module stored in the memory and calling the data stored in the memory.

[0135] The present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the processing method supporting PCIe bus sorting rules.

[0136] If the modules / units integrated in the mobile terminal are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.

[0137] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A processing method supporting PCIe bus sorting rules, characterized in that, Includes the following steps: Step 1: Number the PCIe bus transaction layer packets with serial numbers. By keeping the serial number of a received transaction layer packet unchanged and the buffer storing the transaction layer packets is empty, the serial number of the next received transaction layer packet is rolled back to the minimum value, so that multiple transaction layer packets can use the same serial number. The serial number is rolled back to the initial minimum value before reaching the maximum value, thus completing the generation of the serial number. Step 2: Pause the writing of the PCIe bus transaction layer packet to the cache and generate the serial number until the cache is empty, and then read the PCIe bus transaction layer packet. In step 1, the specific process of serializing the PCIe bus transaction layer packets is as follows: Step 11: Set the sequence number of the first received transaction layer packet to the minimum value 0, and generate the sequence number of the next transaction layer packet by incrementing the sequence number of the previous transaction layer packet by 1. Step 12: Determine if the transaction layer packet cache is empty; Step 13: When the transaction layer packet buffer is empty, the sequence number of the received transaction layer packet is set to the minimum value of 0, regardless of the sequence number of the previous transaction layer packet, thus completing the generation of the current sequence number. Step 14: When the transaction layer packet cache is not empty, determine whether the received transaction layer packet meets the set conditions. Step 15: When the set conditions are met, the sequence number of the received transaction layer packet is set to be the same as the sequence number of the previous transaction layer packet, thus completing the generation of the current sequence number. Step 16: When the set conditions are not met, determine whether the sequence number of the previous transaction layer packet is equal to the maximum value that can be represented by the multiple bits that make up the sequence number; Step 17: When the sequence number of the current transaction layer packet is equal to the maximum value that can be represented by the multiple bits that make up the sequence number and the cache of the transaction layer packet is not empty, pause the cache writing and sequence number generation of the transaction layer packet until the cache of the transaction layer packet is empty, and return to execute step 13. Step 18: When the sequence number of the previous transaction layer packet is not equal to the maximum value that can be represented by the multiple bits that make up the sequence number, the sequence number of the previous transaction layer packet is incremented by 1 and used as the sequence number of the received transaction layer packet, thus completing the generation of the current sequence number. In step 14, the setting conditions are set according to the transaction layer packet type, which includes forwarded transaction layer packets, non-forwarded transaction layer packets, or completion packets. The conditions set include the following: a. The next transaction layer packet and the previous transaction layer packet have the same type, where the same type means that they are both forwarding transaction layer packets, both non-forwarding transaction layer packets, or both completion packets; b. If the preceding transaction layer packet is a forwarding transaction layer packet, the next transaction layer packet will be a non-forwarding transaction layer packet or a completion packet. c. The preceding transaction layer packet is a completion packet, and the following transaction layer packet is a non-forwarding transaction layer packet.

2. The processing method supporting PCIe bus sorting rules according to claim 1, characterized in that, In step 17, when the transaction layer packet cache is not empty, the execution can still be performed based on the transaction layer packet cache status, and the execution status is as follows: If the sequence number of the previous transaction layer packet is equal to the maximum value that can be represented by the multiple bits that make up the sequence number and there are only non-forwarded transaction layer packets in the buffer, continue to receive the next transaction layer packet and set its sequence number to 0; When a sequence number of a current transaction layer packet is equal to the maximum value representable by a plurality of bits forming the sequence number, there are a completion packet or a forwarding transaction layer packet in a cache, and a next transaction layer packet is a forwarding transaction layer packet, continuing to receive the next transaction layer packet and setting a sequence number thereof as the maximum sequence number value among forwarding transaction layer packets and completion packets in the cache; When there is only one type of transaction layer packets in the cache storing transaction layer packets, the sequence numbers of all transaction layer packets of said type in the cache may be selected to be reset to 0, and the sequence number of the next transaction layer packet is set to 1.

3. The processing method supporting PCIe bus sorting rules according to claim 1, characterized in that, After step 13, it may further be determined whether there is only a same type of transaction layer packets in the cache storing transaction layer packets; when there is not only the same type of transaction layer packets in the cache storing transaction layer packets, step 14 is performed; otherwise, the sequence numbers of all transaction layer packets of said type in the cache are reset to 0, the sequence number of the next transaction layer packet is set to 1, and the generation of the current sequence number is completed.

4. The processing method supporting PCIe bus sorting rules according to claim 1, characterized in that, In step 2, the reading steps for the numbered PCIe bus transaction layer packets are as follows: step 21, monitoring and comparing the sequence numbers of transaction layer packets at respective queue heads in a header FIFO of transaction layer packet types, wherein the transaction layer packet types include a forwarding transaction layer packet, a non-forwarding transaction layer packet and a completion packet; step 22, selecting a transaction layer packet for reading according to the magnitude relationship of sequence numbers and types of different transaction layer packets.

5. The processing method supporting PCIe bus sorting rules according to claim 4, characterized in that, During the reading process, when there is only one type of transaction layer packets in the cache, the transaction layer packet is read; when there are only two types of transaction layer packets in the cache, if the sequence numbers of the two transaction layer packets are different, the transaction layer packet with a smaller sequence number is read; if the sequence numbers of the two transaction layer packets are the same and there is a forwarding transaction layer packet, the forwarding transaction layer packet is read, otherwise a completion transaction layer packet is read; when there are three types of transaction layer packets in the cache, reading is performed according to the following conditions: A. when the sequence number of one type of transaction layer packet is smaller than the sequence numbers of the other two types of transaction layer packets, reading the transaction layer packet of the type with the minimum sequence number; B. when the sequence numbers of the three types of transaction layer packets are the same, which is abbreviated as P=CPL=NP, reading the forwarding transaction layer packet; C. when among the three types of transaction layer packets, the sequence number of the forwarding transaction layer packet is smaller than the sequence number of the non-forwarding transaction layer packet, and the sequence number of the completion packet is the same as the sequence number of the forwarding transaction layer packet, which is abbreviated as P=CPL<NP, reading the forwarding transaction layer packet; D. when among the three types of transaction layer packets, the sequence number of the forwarding transaction layer packet is smaller than the sequence number of the completion packet, and the sequence number of the forwarding transaction layer packet is the same as the sequence number of the non-forwarding transaction layer packet, which is abbreviated as P=NP<CPL, reading the forwarding transaction layer packet; E. when among the three types of transaction layer packets, the sequence number of the forwarding transaction layer packet is greater than that of the completion packet, and the sequence number of the completion packet is the same as the sequence number of the non-forwarding transaction layer packet, which is abbreviated as P>CPL=NP, reading the completion packet.

6. A processing system supporting PCIe bus sorting rules, characterized in that, An apparatus for implementing the processing method supporting PCIe bus ordering rules according to any one of claims 1 to 5, comprising The data numbering module is used to assign serial numbers to PCIe bus transaction layer packets. By keeping the serial number of a received transaction layer packet unchanged and storing the transaction layer packet buffer as empty, the serial number of the next received transaction layer packet is rolled back to the minimum value, so that multiple transaction layer packets can use the same serial number. The serial number is rolled back to the initial minimum value before reaching the maximum value, thus completing the generation of the serial number. The data reading module is used to pause the writing of the PCIe bus transaction layer packet with the generated serial number to the cache and generate the serial number until the cache is empty, and to read the PCIe bus transaction layer packet.

7. A mobile terminal, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the processing method supporting PCIe bus sorting rules as described in any one of claims 1 to 5.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the processing method supporting PCIe bus sorting rules as described in any one of claims 1-5.

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