Three-dimensional chip and electronic device
By decomposing the physical layer of a logic chip into a physical connection layer and a physical logic layer, the problems of difficult timing checks of signals at the interface between the logic chip and the memory chip and excessive PHY area are solved, thereby improving the routing efficiency and implementability of the 3D chip.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XI AN UNIIC SEMICON CO LTD
- Filing Date
- 2023-01-29
- Publication Date
- 2026-06-05
AI Technical Summary
In existing technologies, timing checks of interface signals between logic chips and memory chips are difficult, and the large area of the PHY consumes wiring resources, increasing the difficulty of implementing 3D chips.
The physical layer of the logic chip is decomposed into a physical connection layer and a physical logic layer. The memory chip is connected through physical connection lines in the physical connection layer, and the physical connection lines are formed into multiple second connection ports on the second bonding surface, which are clustered in a small area to reduce the wiring resources occupied by the physical layer.
It improves the signal throughput of logic chips, reduces physical layer latency, power consumption and area overhead, simplifies interface routing and timing checks, and enhances chip implementability.
Smart Images
Figure CN116258105B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated chips, and in particular to a three-dimensional chip and electronic device. Background Technology
[0002] With the continuous development of semiconductor packaging technology, 3D integrated chips have gradually emerged, significantly increasing the difficulty of static timing analysis between 3D integrated chips. As the core of the entire chip, static timing analysis plays a decisive role in the chip's functionality, performance, and stability. Therefore, static timing analysis solutions have attracted great attention from designers. How to perform static timing analysis between logic chips and memory chips, meet the special timing requirements between signals, and improve chip stability has become the theme of current static timing analysis solutions.
[0003] In existing technologies, the timing of interface signals between logic chips and memory chips is usually achieved by adding a PHY (Physical Interface Layer) in between to meet the specific timing requirements between signals. When there are many logic or memory chip interfaces, the PHY area becomes very large, occupying a significant amount of the chip's wiring resources, which can prevent the chip from being routed. Summary of the Invention
[0004] This application provides at least one three-dimensional chip and electronic device.
[0005] The first aspect of this application provides a three-dimensional chip, which includes a logic chip and a memory chip. The memory chip includes a first bonding surface, and the first bonding surface includes a plurality of first connection ports.
[0006] The logic chip includes a second bonding surface, and
[0007] The logic chip includes a physical interconnect layer. The first end of the physical interconnect line in the physical interconnect layer is led out from the second bonding surface, and multiple second interconnect ports are formed on the second bonding surface. The second interconnect ports are connected one-to-one with the first interconnect ports, so that the logic chip and the memory chip are stacked in three dimensions.
[0008] The physical logic layer includes multiple input terminals and multiple output terminals that correspond one-to-one. The input terminals are connected to the functional circuits of the logic chip, and the output terminals are connected one-to-one to the second end of the physical connection line.
[0009] The density of the second connection port is less than the density of the second end of the physical connection line.
[0010] Optionally, the memory chip includes multiple memory arrays;
[0011] The physical connection layer includes multiple physical connection units, each of which is connected to a storage array.
[0012] In different physical connection units, the data transmission distance difference between the input terminal of the physical logic layer and the corresponding second connection port is within a preset range.
[0013] Optionally, the physical logic layer includes multiple logic branches, each logic branch being connected between each input and each output.
[0014] Optionally, each logic branch includes at least one register and at least one level conversion unit; the data terminal of the register is connected to the input terminal, the first terminal of the register is connected to the clock control terminal, the second terminal of the register is connected to the first terminal of the level conversion unit, and the second terminal of the level conversion unit is connected to the output terminal; or
[0015] Each logic branch includes at least one register. The data terminal of the register is connected to the input terminal, the first terminal of the register is connected to the clock control terminal, and the second terminal of the register is connected to the output terminal; or
[0016] Each logic branch includes at least one level conversion unit, with the first end of the level conversion unit connected to the input terminal and the second end of the level conversion unit connected to the output terminal.
[0017] Optionally, multiple physical connection units in the physical connection layer are located on the same metal layer, and the orthographic projection of the multiple physical connection units on the memory chip is located on one side of the orthographic projection of the physical logic layer on the memory chip.
[0018] Optionally, multiple physical connection units in the physical connection layer are located on the same metal layer, and the orthographic projections of the multiple physical connection units on the memory chip are located on both sides of the orthographic projection of the physical logic layer on the memory chip.
[0019] Optionally, the orthographic projection of the functional circuitry of the logic chip onto the memory chip is located on the side of the physical connection unit away from the physical logic layer.
[0020] Optionally, the orthographic projection of the functional circuit of the logic chip onto the memory chip is arranged adjacent to the orthographic projection of the physical connection unit onto the memory chip and the orthographic projection of the physical logic layer onto the memory chip.
[0021] Optionally, the physical connection layer is disposed on the top metal layer of the logic chip.
[0022] A second aspect of this application provides an electronic device comprising a three-dimensional chip as described above.
[0023] The beneficial effects of this application are as follows: Unlike the prior art, the logic chip and memory chip of this application are stacked and connected. This application decomposes the physical layer of the logic chip into a physical connection layer and a physical logic layer, connects the memory chip through physical connection lines in the physical connection layer, and integrates multiple second connection ports formed by the physical connection lines on the second bonding surface within a small preset range. The physical logic layer is set within this preset range, which reduces the logic wiring resources of the logic chip occupied by the physical layer, so that other wiring elements of the logic chip are set in the area vacated by the physical layer, thereby improving the signal routing rate of the logic chip and thus improving the chip's implementability.
[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 This is a schematic diagram of the structure of an embodiment of the three-dimensional chip of this application;
[0027] Figure 2 yes Figure 1 A schematic diagram of the planar structure of the first embodiment of the logic chip;
[0028] Figure 3 yes Figure 1 A schematic diagram of the planar structure of the second embodiment of the logic chip;
[0029] Figure 4 yes Figure 1 A schematic diagram of the planar structure of the third embodiment of the logic chip;
[0030] Figure 5 yes Figure 4 A schematic diagram of the structure of the first embodiment of the middle logic branch;
[0031] Figure 6 yes Figure 1 A schematic diagram of the planar structure of the fourth embodiment of the logic chip;
[0032] Figure 7 yes Figure 1 A schematic diagram of the planar structure of the fifth embodiment of the logic chip;
[0033] Figure 8 yes Figure 1 A schematic diagram of the planar structure of the sixth embodiment of the logic chip;
[0034] Figure 9 yes Figure 1 A schematic diagram of the planar structure of the seventh embodiment of the logic chip;
[0035] Figure 10 yes Figure 1 A schematic diagram of the planar structure of the eighth embodiment of the logic chip;
[0036] Figure 11 yes Figure 1 A schematic diagram of the planar structure of the ninth embodiment of the logic chip;
[0037] Figure 12 This is a schematic diagram of the structure of an embodiment of the electronic device of this application. Detailed Implementation
[0038] To enable those skilled in the art to better understand the technical solutions of this application, the three-dimensional chip and electronic device provided in this application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It is understood that the described embodiments are merely some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0039] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.
[0040] In existing technologies, logic chips and memory chips are bonded face-to-face to achieve three-dimensional stacking. There are numerous control and data signals between the logic and memory chips. To achieve vertical stacking, the positions of these signals are fixed. Therefore, during the design of the logic and memory chips, the corresponding signals need to be connected to fixed positions, using a PHY as an intermediate connection layer to meet the timing requirements of the signal interface. In logic chip design, the PHY contains numerous signals distributed over a large area. It must meet the signal placement requirements while minimizing the use of routing resources to improve the routing efficiency of the logic chip. However, the interface signals between the logic and memory chips are numerous and have specific timing requirements. The timing of the two chips cannot be automatically checked by backend tools, making timing convergence and checking of the interface between the logic and memory chips very difficult. A PHY is needed to ensure this, but due to the large number of signals, the PHY area becomes excessive, significantly occupying the logic routing resources and increasing the difficulty and risk of implementing the three-dimensional chip.
[0041] In view of this, this application proposes a three-dimensional chip. In the design of this three-dimensional chip, when implementing the PHY, because the signal distribution range is large, the signals at fixed positions are concentrated into a smaller range through the highest layer metal traces to realize part of the PHY's function. This part of the function is called PHY_IF (i.e., the physical connection layer). Other parts of the PHY, such as level shifting and flip-flop functions, are implemented by PHY_AA (physical logic layer). The implementation principle of PHY_AA is: the level shifter and flip-flops are concentrated within the range of PHY_IF, and the signals are connected to fixed positions through PHY_IF, thereby giving up as much wiring resources as possible for the logic chip. The following is a detailed description of this application with reference to the accompanying drawings.
[0042] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of one embodiment of the three-dimensional chip of this application. Figure 2 yes Figure 1A schematic diagram of the planar structure of the first embodiment of the logic chip. Specifically, the three-dimensional chip includes a logic chip 10 and a memory chip 20, which are stacked and connected in three dimensions. Specifically, the memory chip 20 includes a first bonding surface 201, which includes a plurality of first connection ports 202. The logic chip 10 includes a second bonding surface 101. Further, the logic chip 10 includes a physical connection layer 12 (PHY_IF) and a physical logic layer 13 (PHY_AA). The first end of the physical connection line in the physical connection layer 12 extends from the second bonding surface 101, and a plurality of second connection ports 102 are formed on the second bonding surface 101. The first connection ports 202 and the second connection ports 102 are connected one-to-one to enable the logic chip 10 and the memory chip 20 to be stacked and connected in three dimensions.
[0043] Furthermore, please combine Figure 3 , Figure 3 yes Figure 1 A schematic diagram of the planar structure of the second embodiment of the logic chip is shown. The physical connection layer 12 includes multiple physical connection lines 121. The first end of each physical connection line 121 extends from the second bonding surface 101, forming multiple second connection ports 102 on the second bonding surface 101. The second end of each physical connection line 121 connects to the physical logic layer 13. Specifically, the physical logic layer 13 includes multiple corresponding input terminals A and multiple output terminals B. Input terminals A connect to the functional circuitry of the logic chip 10, and output terminals B are connected to the second ends of the physical connection layer 12 in a one-to-one correspondence.
[0044] In this embodiment, the physical logic layer 13 is used to store the data signals received and / or output by the logic chip 10, and further receive data signals from the memory chip 20 through the physical connection line 121, and / or transmit data signals from the logic chip 10 to the memory chip 20 through the physical connection line 121. That is, in this embodiment, the physical connection layer 12 is set to realize the function of the PHY layer connecting the physical logic layer 13 and the memory chip 20. At the same time, since the density of the second connection port 102 is less than the density of the second end of the physical connection line 121, the physical connection layer 12 gathers the second end of the physical connection line 121 connecting the second connection port 102 at a fixed position, and sets the physical logic layer 13 at the fixed position, thereby concentrating the physical logic layer 13 within a preset range. The signal is received at the fixed position through the physical connection layer 12, so that the layout resources occupied by the physical logic layer 13 are less.
[0045] In one embodiment, the logic chip 10 includes multiple metal layers, and the physical connection layer 12 is disposed on the top metal layer of the multiple metal layers. That is, multiple physical connection lines 121 are laid on the top metal layer of the multiple metal layers, which does not need to occupy the wiring resources of other metal layers. This can greatly reduce the occupation of the wiring resources of the logic chip 10 by the physical connection layer 12, thereby reducing the impact on the component layout of the logic chip 10.
[0046] Specifically, the density of the second connection port 102 is less than the density of the second end of the physical connection line 121. Therefore, the second end of the physical connection line 121 connecting the second connection port 102 can be concentrated at a fixed location through the physical connection layer 12, and a physical logic layer 13 can be placed at this fixed location. This concentrates the physical logic layer 13 within a preset range, and the signal is received at the fixed location through the physical connection layer 12, reducing the wiring resources occupied by the physical logic layer 13, thereby freeing up wiring resources for the logic chip 10 as much as possible, and improving the chip's routing efficiency.
[0047] like Figure 3 As shown, the physical logic layer 13 occupies a much smaller area than the physical connection layer 12, and the physical connection layer 12 only occupies the wiring resources of the top metal layer in the multi-layer metal layer. At the same time, because it occupies a small area of metal layer, it can reduce the occupation of wiring resources of logic chip 10, release more wiring resources, and thus improve the routing efficiency of logic chip 10.
[0048] Optionally, the preset range accounts for 20%-30% of the total area of the top metal layer. The size of the preset range can be selected according to actual needs so that the components contained in the physical logic layer 13 can be completely controlled within the preset range, thereby realizing the centralized control of the components.
[0049] In one embodiment, please refer to Figure 4 , Figure 4 Yes, yes Figure 1 A schematic diagram of the planar structure of the third embodiment of the logic chip. (See attached diagram.) Figure 4 As shown, the physical logic layer 13 includes multiple logic branches 131, each logic branch 131 being connected between each input terminal A and each output terminal B. The physical logic layer 13 uses the logic branches 131 to perform functions such as level conversion of data signals and data registration.
[0050] In one embodiment, the vertical stacking of logic chip 10 and memory chip 20 significantly reduces the packaging and routing distances and distribution parameters. The interconnection between the vertically stacked logic chip 10 and memory chip 20 is close to the on-chip signal interconnection, which differs from the PHY used for common inter-chip interconnections. In this embodiment, the PHY_AA does not need to include functions such as drive amplification, debouncing, overvoltage protection, and ESD protection; even when the core voltages of logic chip 10 and memory chip 20 are the same, the level shifter can be omitted. This significantly reduces the latency, power consumption, and area overhead of the PHY_AA, forming the core advantage of the 3D stacked structure.
[0051] Specifically, in combination Figure 4 For further information Figure 5 , Figure 5 yes Figure 4 A schematic diagram of the structure of the first embodiment of the logic branch. In one embodiment, as shown... Figure 5 As shown, each logic branch 131 includes at least one register 1312 and at least one level conversion unit 1311.
[0052] Optionally, the register 1312 described in this embodiment can be a flip-flop. A flip-flop can store one bit of binary code. Connecting the clock ports of n flip-flops together can form a register 1312 that stores n bits of binary code.
[0053] The trigger may include a D trigger, which includes a data terminal D and a logic terminal Q. Optionally, in other embodiments, the trigger 1313 may also include an RS trigger, a JK trigger, and a T trigger, and may be one or more combinations thereof.
[0054] Combination Figure 5 For further information Figure 6 The data terminal D of register 1312 is connected to input terminal A. The first terminal of register 1312 is connected to the clock control terminal. The second terminal of register 1312 is connected to the first terminal of level conversion unit 1311. The second terminal of level conversion unit 1311 is connected to output terminal B. Optionally, the second terminal of register 1312 can be a logic terminal Q.
[0055] Alternatively, the logic terminal Q of register 1312 can be connected to input terminal A, the first terminal of register 1312 can be connected to the clock control terminal, the second terminal of register 1312 can be connected to the first terminal of level conversion unit 1311, and the second terminal of level conversion unit 1311 can be connected to output terminal B. Optionally, the second terminal of register 1312 can be a data terminal D.
[0056] Specifically, the corresponding register 1312 can be designed according to the data reading, writing or output.
[0057] Combination Figure 5 and Figure 6 For further information Figure 7 In another embodiment, when the core voltages of the logic chip 10 and the memory chip 20 are the same, the level conversion unit 1311 can be omitted to save power consumption, delay, and area, and simplify the power network design.
[0058] like Figure 7 As shown, each logic branch 131 includes at least one register 1312. The data terminal D of register 1312 is connected to the input terminal A, the first terminal of register 1312 is connected to the clock control terminal, and the second terminal of register 1312 is connected to the output terminal B. Optionally, the second terminal of register 1312 can be a logic terminal Q.
[0059] Alternatively, the logic terminal Q of register 1312 can be connected to input terminal A, the first terminal of register 1312 can be connected to the clock control terminal, and the second terminal of register 1312 can be connected to output terminal B. Optionally, the second terminal of register 1312 can be a data terminal D.
[0060] Combination Figure 5 and Figure 6 For further information Figure 8 In another embodiment, when the timing margin of vertical stacking is large, register 1312 can be omitted to save latency, power consumption, and area. That is, each logic branch 131 includes at least one level-shifting unit 1311, with its first terminal connected to input terminal A and its second terminal connected to output terminal B, as detailed below. Figure 8 As shown.
[0061] The layout of the physical interconnect layer 12 (PHY_IF) is fixed due to vertical stacking constraints, while the layout of the physical logic layer 13 (PHY_AA) can be flexibly configured to achieve optimal logic chip design under diverse vertical stacking strategies and PHY_IF granularities. Generally, the memory chip 20 includes multiple memory array banks, each requiring a corresponding PHY_IF. Therefore, in one embodiment, the physical interconnect layer 12 includes multiple physical interconnect units 120, each connected to a memory array bank.
[0062] Furthermore, combined Figures 1-6 Please see Figure 9 , Figure 9 Figure 1A schematic diagram of the planar structure of the seventh embodiment of the logic chip. This embodiment uses a memory chip 20 including two memory arrays BANK0 and BANK1 as an example for illustration. In one embodiment, multiple physical connection units 120 in the physical connection layer 12 are located in the same metal layer, and the orthographic projection of the multiple physical connection units 120 on the memory chip 20 is located on one side of the orthographic projection of the physical logic layer 13 on the memory chip 20, specifically as follows. Figure 9 As shown.
[0063] In this embodiment, physical connection line 121 in PHY_IF BANK0 is connected to the second connection port 102 corresponding to the memory array BANK0, and the density of physical connection line 121 at the end connected to PHY_AA BANK0 is greater than that at the end connected to the second connection port 102, thereby clustering PHY_AA BANK0 in a fixed, smaller location. Similarly, physical connection line 121 in PHY_IF BANK1 is connected to the second connection port 102 corresponding to the memory array BANK1, and the density of physical connection line 121 at the end connected to PHY_AA BANK1 is greater than that at the end connected to the second connection port 102, thereby clustering PHY_AA BANK1 in a fixed, smaller location. This reduces the area occupied by PHY_AA BANK0 and PHY_AA BANK1, providing more wiring area for the functional circuits of the logic chip 10, freeing up more wiring resources, and thus improving the routing efficiency of the logic chip 10.
[0064] Furthermore, combined Figures 1-6 as well as Figure 9 Please see Figure 10 Unlike the above embodiments, in this embodiment, the orthographic projections of the multiple physical connection units 120 on the memory chip 20 are located on both sides of the orthographic projection of the physical logic layer 13 on the memory chip 20.
[0065] Specifically, in this embodiment, the orthographic projection of the functional circuit of the logic chip 10 onto the memory chip 20 is located on the side of the physical connection unit 120 away from the physical logic layer 13.
[0066] In this embodiment, PHY_IF BANK0 and PHY_IF BANK1 can be located on the same metal layer or on different metal layers. It is understood that PHY_IF BANK0 and PHY_IF BANK1 can be located simultaneously on the top metal layer or on an inner metal layer; no specific limitation is made.
[0067] Understandably, the above Figure 9In the illustrated embodiment, the data transmission distance from input terminal A of the functional circuit connected to PHY_AA BANK0 to output terminal B of PHY_IF BANK0 is less than the data transmission distance from input terminal A of the functional circuit connected to PHY_AA BANK1 to output terminal B of PHY_IF BANK1. This will cause a delay in signal transmission. And the above... Figure 10 In the illustrated embodiment, in PHY_AA BANK0, the data transmission distance from input terminal A of the connecting functional circuit to output terminal B of PHY_IF BANK0 is greater than the data transmission distance from input terminal A of the connecting functional circuit to output terminal B of PHY_IF BANK1 in PHY_AA BANK1. To ensure that the signal transmission delay is within the acceptable range of the chip, the difference in data transmission distance between input terminal A of the physical logic layer 13 and the corresponding connected second connection port 102 in different physical connection units 120 is within a preset range. This can appropriately reduce the delay and ensure the signal transmission timing.
[0068] Furthermore, combined Figures 1-6 as well as Figure 9 Please see Figure 11 Unlike the above embodiments, in this embodiment, the orthographic projection of the functional circuit of the logic chip 10 on the memory chip 20 is arranged adjacent to the orthographic projection of the physical connection unit 120 on the memory chip 20 and the orthographic projection of the physical logic layer 13 on the memory chip 20.
[0069] Specifically, the physical connection unit 120, the logic chip 10, and another physical connection unit 120 are arranged adjacent to each other on the memory chip 20 along the first direction of the memory chip 20, and the physical connection unit 120 and the functional circuit are arranged adjacent to each other on the memory chip 20 along the second direction of the memory chip 20. The first direction and the second direction are perpendicular to each other.
[0070] In this embodiment, the data transmission distance from input terminal A of the functional circuit in PHY_AA BANK0 to output terminal B of PHY_IF BANK0 is equal to the data transmission distance from input terminal A of the functional circuit in PHY_AA BANK1 to output terminal B of PHY_IF BANK1. It can be seen that... Figure 11 The illustrated embodiment ensures consistent signal transmission delay.
[0071] It should be noted that, unlike the PHYs commonly used for inter-chip interconnects, splitting the vertically stacked interconnect PHYs allows for simpler PHY_AA circuitry, enabling semi-custom designs based on RTL-synthesis. This significantly reduces the development burden compared to the fully custom circuitry required for inter-chip interconnect PHYs.
[0072] The interface routing and timing checks of the three-dimensional chip integrating the logic chip 10 and the memory chip 20 in this application can be automated using EDA (Electronic Design Automation) tools, which is convenient and fast. Furthermore, the design method of the logic chip 10 in this application can be applied to different process technologies, making it widely applicable.
[0073] Furthermore, in another embodiment, the memory chip 20 also includes a register for storing data read from the memory array or data to be written to the memory array. The output of the register is connected to the first connection port 202 and connected to the second connection port 102 through the first connection port 202 to realize data transmission with the logic chip 10.
[0074] This application also provides an electronic device, please refer to... Figure 12 , Figure 12 This is a schematic diagram of the structure of an embodiment of the electronic device of this application. Figure 12 As shown, the electronic device 30 includes a three-dimensional chip 31, wherein the three-dimensional chip 31 is the three-dimensional chip described in any of the above embodiments, and will not be described again here.
[0075] The above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A three-dimensional chip, characterized in that, It includes a logic chip and a memory chip; the memory chip includes a first bonding surface, and the first bonding surface includes a plurality of first connection ports; The logic chip includes a second bonding surface, and The logic chip includes a physical connection layer, wherein the first end of the physical connection line in the physical connection layer is led out from the second bonding surface, and a plurality of second connection ports are formed on the second bonding surface; the second connection ports are connected one-to-one with the first connection ports, so that the logic chip and the memory chip are stacked in three dimensions. The physical logic layer includes multiple input terminals and multiple output terminals that correspond one-to-one. The input terminals are connected to the functional circuits of the logic chip, and the output terminals are connected one-to-one to the second end of the physical connection line. The density of the second connection port is less than the density of the second end of the physical connection line.
2. The three-dimensional chip according to claim 1, characterized in that, The memory chip includes multiple memory arrays; The physical connection layer includes multiple physical connection units, and each physical connection unit is connected to a storage array. In different physical connection units, the data transmission distance difference between the input terminal of the physical logic layer and the corresponding second connection port is within a preset range.
3. The three-dimensional chip according to claim 1 or 2, characterized in that, The physical logic layer includes multiple logic branches, each of which is connected between each input terminal and each output terminal.
4. The three-dimensional chip according to claim 3, characterized in that, Each of the aforementioned logic branches includes at least one register and at least one level shifting unit; the data terminal of the register is connected to the input terminal, the first terminal of the register is connected to the clock control terminal, the second terminal of the register is connected to the first terminal of the level shifting unit, and the second terminal of the level shifting unit is connected to the output terminal; or Each of the aforementioned logic branches includes at least one register, the data terminal of which is connected to the input terminal, the first terminal of which is connected to the clock control terminal, and the second terminal of which is connected to the output terminal; or Each of the logic branches includes at least one level conversion unit, with a first end of the level conversion unit connected to the input terminal and a second end of the level conversion unit connected to the output terminal.
5. The three-dimensional chip according to claim 2, characterized in that, The plurality of physical connection units in the physical connection layer are located on the same metal layer, and the orthographic projection of the plurality of physical connection units on the memory chip is located on one side of the orthographic projection of the physical logic layer on the memory chip.
6. The three-dimensional chip according to claim 2, characterized in that, The plurality of physical connection units in the physical connection layer are located on the same metal layer, and the orthographic projection of the plurality of physical connection units on the memory chip is located on both sides of the orthographic projection of the physical logic layer on the memory chip.
7. The three-dimensional chip according to claim 6, characterized in that, The orthographic projection of the functional circuitry of the logic chip onto the memory chip is located on the side of the physical connection unit away from the physical logic layer.
8. The three-dimensional chip according to claim 2, characterized in that, The orthographic projection of the functional circuit of the logic chip onto the memory chip, the orthographic projection of the physical connection unit onto the memory chip, and the orthographic projection of the physical logic layer onto the memory chip are arranged adjacent to each other.
9. The three-dimensional chip according to claim 1, characterized in that, The physical connection layer is disposed on the top metal layer of the logic chip.
10. An electronic device, characterized in that, The electronic device includes the three-dimensional chip according to any one of claims 1 to 9.