Memory device with high data bandwidth

Abstract

The present application provides a memory device with high data bandwidth. The memory device includes at least one memory chip and a logic chip. The at least one memory chip each includes a memory array, a plurality of bit lines and a plurality of data paths. The plurality of data paths respectively correspond to the plurality of bit lines. The number of the plurality of data paths is equal to or less than the number of the plurality of bit lines. A plurality of data transmission terminals of the logic chip are electrically connected to the plurality of data paths of the at least one memory chip in a one-to-one manner. The number of the plurality of data transmission terminals is equal to the total number of the plurality of data paths of the at least one memory chip.

Description

Technical Field

[0001] The present invention relates to a memory device, and more particularly to a memory device having high bandwidth access capability. Background Technology

[0002] In existing memory devices, logic chips access data from at least one memory chip. However, data access requires addressing, data input / output buffering, and other procedures. Therefore, to further improve the performance of memory devices, the aforementioned addressing and data input / output buffering will inevitably limit performance improvements. Summary of the Invention

[0003] The present invention provides a memory device with high bandwidth access capability.

[0004] The memory device of the present invention includes at least one memory chip and a logic chip. Each of the at least one memory chip includes a memory array, a plurality of bit lines, and a plurality of data paths. The plurality of bit lines are coupled to the memory array. The plurality of data paths correspond to the plurality of bit lines. The number of the plurality of data paths is equal to or less than the number of the plurality of bit lines. The logic chip includes a plurality of data transmission terminals. The plurality of data transmission terminals are electrically connected to the plurality of data paths of the at least one memory chip in a one-to-one manner. The number of the plurality of data transmission terminals is equal to the total number of the plurality of data paths of the at least one memory chip. The logic chip reads multiple data from the at least one memory chip through the plurality of data transmission terminals.

[0005] The memory device of the present invention includes at least one memory chip and a logic chip. Each of the at least one memory chip includes a substrate, a memory array, a plurality of bit lines, and a plurality of data paths. The memory array is disposed on the substrate. The plurality of bit lines are disposed on the substrate. The plurality of bit lines are coupled to the memory array. The plurality of data paths are disposed on the substrate. The plurality of data paths correspond to the plurality of bit lines. The number of the plurality of data paths is equal to or less than the number of bit lines. The logic chip includes a plurality of data transmission terminals. The number of the plurality of data transmission terminals is equal to the total number of the plurality of data paths of the at least one memory chip. At least a portion of each of the plurality of data paths passes through the substrate and is connected to the plurality of data transmission terminals in a one-to-one manner.

[0006] Based on the above, the plurality of data transmission terminals are electrically connected to the plurality of data paths of each of the at least one memory chip in a one-to-one manner. The number of the plurality of data transmission terminals is equal to the total number of the plurality of data paths of the at least one memory chip. Therefore, the logic chip can read data from all data paths at least once. In this way, the memory device can have extremely high access bandwidth. Attached Figure Description

[0007] To make the above-mentioned features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features can be arbitrarily increased or decreased.

[0008] Figure 1 This is a schematic diagram of a memory device illustrated in the first embodiment of the present invention;

[0009] Figure 2 This is a schematic diagram of a memory device illustrated in the second embodiment of the present invention;

[0010] Figure 3 This is a partial schematic diagram of a memory device illustrated in the third embodiment of the present invention;

[0011] Figure 4 This is a partial schematic diagram of the memory device along section A-A' as shown in the third embodiment;

[0012] Figure 5 This is another schematic diagram of the memory device along section A-A' shown in the third embodiment.

[0013] Symbol Explanation

[0014] 100, 200: Memory devices

[0015] 110_1~110_4: Memory controller

[0016] 210, 310: Operational circuits

[0017] 220: Memory controller

[0018] 230: Local Address Decoder

[0019] MC, MC1~MC4: Memory chips

[0020] LC: Logic chip

[0021] MA: Memory Array

[0022] A, A': Sectional direction

[0023] BL1~BLn: Bit lines

[0024] C, C1, C2: Capacitors

[0025] CL1, CL2: Connecting wires

[0026] CNP2: Connection Path

[0027] DP1~DPn: Data paths

[0028] ICL: Inner Connector Layer

[0029] LO1~LO4: Interlayer insulation layers

[0030] M1, M2: Metal connecting wires

[0031] M11~Mnm: Dynamic Random Access Memory Unit

[0032] P1~Pn, P11~P1n, P21~P2n, P31~P3n, P41~P4n: Data transmission terminals

[0033] PL1: First surface of the substrate

[0034] PL2: The second side of the substrate

[0035] RD1~RDn: Data

[0036] SA1~SAn: Sensing amplifiers

[0037] SAA: Sensing Amplifier Array

[0038] SB:Substrate

[0039] SP11, SP12, SP21, SP22: Signal transmission terminals

[0040] T: Transistor

[0041] V1~V4: Through holes

[0042] WL1~WLm: Word lines Detailed Implementation

[0043] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description, when appearing in different drawings, are considered to be the same or similar components. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples as described in the claims of the present invention.

[0044] In the following description, "the first feature is formed on" or "on" the second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of the invention. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate any relationship between the various embodiments and / or configurations discussed.

[0045] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a memory device according to an embodiment of the present invention. In this embodiment, the memory device 100 includes memory chips MC1 to MC4 and a logic chip LC. Each of the memory chips MC1 to MC4 includes a memory array MA, multiple bit lines, and multiple data paths. Taking memory chip MC1 as an example, memory chip MC1 includes a memory array MA, bit lines BL1 to BLn, and data paths DP1 to DPn. Bit lines BL1 to BLn are coupled to the memory array MA. More specifically, bit line BL1 is coupled to the first row of memory cells in the memory array MA. Bit line BL2 is coupled to the second row of memory cells in the memory array MA, and so on. In this embodiment, data paths DP1 to DPn correspond to bit lines BL1 to BLn respectively. Data path DP1 corresponds to bit line BL1. Data path DP2 corresponds to bit line BL2, and so on. That is, bit lines BL1 to BLn correspond to data paths DP1 to DPn in a one-to-one manner. The number of data paths DP1 to DPn is equal to the number of bit lines BL1 to BLn. Therefore, in the memory device 100, the total number of data paths is equal to the total number of bit lines of the memory chips MC1 to MC4. For example, memory chips MC1 to MC4 each include 16 bit lines (this invention is not limited thereto). The total number of bit lines is 64. Therefore, the total number of data paths is also 64. In some embodiments, at least one of the data paths DP1 to DPn corresponds to multiple bit lines. The number of data paths DP1 to DPn is less than the number of bit lines BL1 to BLn. Therefore, in the memory device 100, the total number of data paths is less than the total number of bit lines of the memory chips MC1 to MC4.

[0046] In this embodiment, the logic chip LC includes data transmission terminals P11-P1n, P21-P2n, P31-P3n, and P41-P4n. These data transmission terminals P11-P1n, P21-P2n, P31-P3n, and P41-P4n are electrically connected to the multiple data paths of the memory chips MC1-MC4 in a one-to-one manner. Taking memory chip MC1 as an example, data path DP1 is directly electrically connected to data transmission terminal P11. Data path DP2 is directly electrically connected to data transmission terminal P12, and so on. Therefore, the number of data transmission terminals P11-P1n, P21-P2n, P31-P3n, and P41-P4n is equal to the total number of data paths in memory chips MC1-MC4.

[0047] In this embodiment, the logic chip LC reads multiple data from memory chips MC1 to MC4 through data transmission terminals P11-P1n, P21-P2n, P31-P3n, and P41-P4n. For example, memory chips MC1 to MC4 each include 16 bit lines (this invention is not limited thereto). The total number of bit lines is 64. Therefore, n equals 16 (this invention is not limited thereto). The logic chip LC can read 64 bits of data at once. It is worth mentioning that, compared to existing memory devices, the memory device 100 of this embodiment does not have a buffer, such as a latch, data selection circuit, or FIFO buffer, between the logic chip LC and the memory chips MC1 to MC4. As a result, the memory device 100 can have extremely high read bandwidth and data transmission speed. In this embodiment, the logic chip LC can also provide 64 bits of data to the memory chips MC1 to MC4 at once. As a result, the memory device 100 also has extremely high write bandwidth.

[0048] Furthermore, there is no buffer between the logic chip LC and the memory chips MC1 to MC4 of the memory device 100. Therefore, the power consumption of the memory device 100 can be reduced.

[0049] For ease of explanation, this embodiment uses four memory chips MC1 to MC4 as an example. Depending on actual needs, the number of memory chips can be one or more, and is not limited to this embodiment. Furthermore, the number of bit lines of memory chips MC1 to MC4 can be the same, not exactly the same, or completely different, and is not limited to this embodiment.

[0050] In this embodiment, there can be multiple memory chips MC1 to MC4. The logic chip LC includes memory controllers 110_1 to 110_4. Memory controllers 110_1 to 110_4 are respectively coupled to the corresponding memory chips among memory chips MC1 to MC4. Memory controllers 110_1 to 110_4 control the corresponding memory chips in response to operation commands. Therefore, memory chips MC1 to MC4 each have multiple word lines (not shown) providing multiple operating voltages corresponding to operation commands. Operation commands can be commands associated with programming operations, read operations, and refresh operations. In this embodiment, memory controller 110_1 controls memory chip MC1 through signal transmission terminals SP11 and SP12. Memory controller 110_2 controls memory chip MC1 through signal transmission terminals SP21 and SP22, and so on.

[0051] It is worth mentioning that the memory controllers 110_1 to 110_4 are located in the logic chip LC, rather than in the memory chips MC1 to MC4. Therefore, the area of ​​the memory chips MC1 to MC4 can be reduced. In this way, the logic chip LC can accommodate more memory chips to further improve access bandwidth.

[0052] Please refer to Figure 2 , Figure 2 This is a partial schematic diagram of a memory device according to a second embodiment of the present invention. In this embodiment, the memory device 200 includes a memory chip MC and a logic chip LC. The memory chip MC includes a memory array MA, bit lines BL1-BLn, word lines WL1-WLm, data paths DP1-DPn, and a sense amplifier array SAA. The sense amplifier array SAA includes sense amplifiers SA1-SAn. The sense amplifiers SA1-SAn respectively amplify the data (or read data) RD1-RDn located on the corresponding bit lines in bit lines BL1-BLn, and provide the amplified data RD1-RDn to the corresponding data paths in data paths DP1-DPn. Taking this embodiment as an example, sense amplifier SA1 amplifies the data RD1 located on bit line BL1 and provides the amplified data RD1 to data path DP1. Sense amplifier SA2 amplifies the data RD2 located on bit line BL2 and provides the amplified data RD2 to data path DP2, and so on. In the memory chip MC, the number of sense amplifiers SA1-SAn is equal to the number of bit lines BL1-BLn.

[0053] The logic chip LC includes data transmission terminals P1-Pn, an arithmetic circuit 210, and a memory controller 220. The logic chip LC receives amplified data RD1-RDn through the data transmission terminals P1-Pn. The arithmetic circuit 210 performs operations on at least one of the data RD1-RDn. The memory controller 220 controls the memory chip MC in response to operation commands. The operation commands also include addressing information. The memory controller 220 controls the memory chip MC based on the addressing information of the operation commands.

[0054] In this embodiment, the logic chip LC includes a local address decoder 230. The local address decoder 230 provides multiple operating voltages corresponding to the operation command to word lines WL1 to WLm based on the addressing information of the operation command.

[0055] In this embodiment, the memory array MA is a Dynamic Random Access Memory (DRAM) array. The memory array MA includes DRAM cells M11 to Mn1. DRAM cells M11 to M1m form the first row of memory cells. DRAM cells M21 to M2m form the second row of memory cells, and so on. DRAM cells M11 to Mn1 form the first column of memory cells. DRAM cells M12 to Mn2 form the second column of memory cells, and so on.

[0056] Taking dynamic random access memory (DRAM) cell M11 as an example, DRAM cell M11 includes transistor T and capacitor C. The control terminal of transistor T is coupled to word line WL1. The first terminal of transistor T is coupled to bit line BL1. Capacitor C is coupled between the second terminal of transistor T and a reference low voltage.

[0057] Please also refer to Figure 3 as well as Figure 4 , Figure 3 This is a partial schematic diagram of a memory device according to a third embodiment of the present invention. Figure 4 This is a partial schematic diagram of a cross-section along A-A' of a memory device according to the third embodiment. In this embodiment, the A-A' section is a cross-sectional view taken along the extension plane of bit line BL2 and data path DP2. Based on the A-A' section, structurally, the memory chip MC also includes a substrate SB and interlayer insulating layers LO1 to LO3. The interlayer insulating layer LO1 at least covers the first surface PL1 of the substrate SB and the transistors of the dynamic random access memory cells. Word line ( Figure 4 Only word lines WL1 and WL2 are shown embedded in the substrate SB. The first interlayer insulating layer also covers the sense amplifier ( Figure 4 Only the sensing amplifier SA2 is shown. Interlayer insulation layer LO2 at least covers interlayer insulation layer LO1. Similarly, interlayer insulation layer LO3 at least covers interlayer insulation layer LO2.

[0058] In this embodiment, bit lines ( Figure 4 Bit line BL2 (shown only) is disposed in the interlayer insulating layer LO1. Bit line BL2 is connected to the input terminal of sense amplifier SA2 via connection path CNP2. The output terminal of sense amplifier SA2 is connected to the second surface PL2 of substrate SB via data path DP2. Memory chip MC contacts logic chip LC through the second surface PL2 of substrate SB.

[0059] To further explain, the connection path CNP2 includes vias V1 and V2 and a connecting wire CL1. Via V1, connecting wire CL1, and via V2 are connected in series between the bit line BL2 and the input terminal of the sense amplifier SA2. The first end of via V1 is coupled to the bit line BL2. The first end of connecting wire CL1 is coupled to the second end of via V1. Via V2 is coupled between the second end of connecting wire CL1 and the input terminal of the sense amplifier SA2. In this embodiment, the connecting wire CL1 is disposed on the interlayer insulating layer LO2. Furthermore, the connecting wire CL1 is covered by the interlayer insulating layer LO3.

[0060] At least a portion of multiple data paths pass through the substrate SB and are connected to corresponding data transmission terminals in a one-to-one manner. In this embodiment, data path DP2 includes vias V3 and V4 and a connecting wire CL2. Via V3, connecting wire CL2, and via V4 are connected in series between the output terminal of the sense amplifier SA2 and the second surface PL2 of the substrate SB. The first end of via V3 is coupled to the output terminal of the sense amplifier SA2. The first end of connecting wire CL2 is coupled to the second end of via V3. Via V4 is disposed between the second end of connecting wire CL2 and the second surface PL2 of the substrate SB. That is, via V4 passes through the substrate SB and connects to the data transmission terminal P2. Data path DP2 does not need to bypass the edge of the substrate SB. Therefore, the path length of data path DP2 is shortened. In this embodiment, connecting wire CL2 is disposed on the interlayer insulating layer LO2. Therefore, connecting wires CL1 and CL2 can be conductive patterns located on the interlayer insulating layer LO2. Furthermore, connecting wire CL2 is also covered by the interlayer insulating layer LO3.

[0061] In this embodiment, the capacitor of the dynamic random access memory unit ( Figure 4 Only capacitors C1 and C2 are shown embedded in the interlayer insulating layer LO2. For example, capacitors C1 and C2 are metal-insulator-metal (MIM) stacked structures. The first terminal of capacitor C1 is coupled to a first transistor. Capacitor C1 and the first transistor together form a first dynamic random access memory (DRAM) cell. The first terminal of capacitor C2 is coupled to a second transistor. Capacitor C2 and the second transistor together form a second DRAM cell. The second terminals of capacitors C1 and C2 are coupled to a reference low voltage via connecting wire CL3. Therefore, connecting wires CL1 to CL3 can be conductive patterns located on the interlayer insulating layer LO2.

[0062] In this embodiment, the logic chip LC includes an arithmetic circuit 310, an inner interconnect layer ICL, and a data transmission terminal ( Figure 4Only the data transmission terminal P2 is shown. The inner interconnect layer ICL is coupled to the arithmetic circuit 310 and the data transmission terminal P2. The inner interconnect layer ICL receives data through the data transmission terminal P2 and transmits the data to the arithmetic circuit 310. In this embodiment, the memory chip MC is stacked on the logic chip LC. The second surface PL2 of the substrate SB of the memory chip MC is in contact with the inner interconnect layer ICL, so that the via V4 of the data path DP2 is electrically connected to the data transmission terminal P2.

[0063] In this embodiment, structurally, the memory chip MC further includes an interlayer insulating layer LO4 and metal interconnects M1 and M2. The interlayer insulating layer LO4 at least covers the interlayer insulating layer LO3. The metal interconnects M1 and M2 respectively transmit operating voltages and provide the operating voltages to the corresponding word lines. For example, metal interconnect M1 is connected to word line WL1 through a via (not shown). Metal interconnect M2 is connected to word line WL2 through another via (not shown).

[0064] Metal connecting wires M1 and M2 are respectively disposed on one of the interlayer insulating layers LO3 and LO4. Taking this embodiment as an example, metal connecting wire M1 is disposed on interlayer insulating layer LO4, and metal connecting wire M2 is disposed on interlayer insulating layer LO3. However, the present invention is not limited to this example. In some embodiments, metal connecting wires M1 and M2 are respectively disposed on interlayer insulating layer LO3. In some embodiments, metal connecting wires M1 and M2 are respectively disposed on interlayer insulating layer LO4. In some embodiments, metal connecting wire M1 is disposed on interlayer insulating layer LO3, and metal connecting wire M2 is disposed on interlayer insulating layer LO4.

[0065] Generally, metal interconnects M1 and M2, and word lines WL1 and WL2 may transmit higher operating voltages, such as 2.6 to 3.0 volts. It should be noted that in this embodiment, metal interconnects M1 and M2 are respectively disposed on one of the interlayer insulating layers LO3 and LO4. Connection path CNP2 and data path DP2 are covered by insulating layer LO2. Data from bit line BL2 is provided to the second surface PL2 of substrate SB via connection path CNP2, sense amplifier SA2, and data path DP2. Logic chip LC contacts the second surface PL2 of substrate SB via data transmission terminal P2. The aforementioned paths provide shorter data transmission distances and prevent data interference from higher word line operating voltages. The transmission paths of operating voltage and data do not intersect on the same interlayer insulating layer. Therefore, memory chip MC does not need to increase the bit line voltage or significantly increase the data gain to suppress word line operating voltage interference. In this way, the power consumption of memory chip MC can be reduced.

[0066] In the substrate SB, a shallow trench isolation (STI) structure is formed between the sense amplifier SA2 and the word line closest to the sense amplifier SA2 (e.g., word line WL2). Therefore, the operation of the sense amplifier SA2 is less susceptible to interference from operating voltage. In terms of layout, the distance between the sense amplifier SA2 and the memory array MA can be shortened. The length of the connecting wire CL1 can also be shortened.

[0067] Please also refer to Figure 3 as well as Figure 5 , Figure 3 This is a partial schematic diagram of a memory device according to a third embodiment of the present invention. Figure 5 This is another partial schematic diagram of the memory device along section A-A' as illustrated in the third embodiment. Regarding connection path CNP2, connection path CNP2 includes vias V1 and V2 and a connecting wire CL1. Via V1, connecting wire CL1, and via V2 are connected in series between bit line BL2 and the input terminal of sense amplifier SA2. Regarding data path DP2, data path DP2 includes vias V3 and V4 and a connecting wire CL2. Via V3, connecting wire CL2, and via V3 are connected in series between the output terminal of sense amplifier SA2 and the second surface PL2 of substrate SB. Figure 4 The difference is that the connecting wire CL1 is disposed on the interlayer insulation layer LO1. Furthermore, the connecting wire CL1 is covered by the interlayer insulation layer LO2. The connecting wire CL2 is disposed on the interlayer insulation layer LO1. Furthermore, the connecting wire CL2 is covered by the interlayer insulation layer LO2. Therefore, Figure 5 The heights of the through holes V1 and V2 shown will be significantly smaller than those of the through holes V1 and V2 shown. Figure 4 The heights of the through holes V1 and V2 are shown. In this way, Figure 5 The path length of the connection path CNP2 shown will be shortened. Furthermore, Figure 5 The height of the through hole V3 shown will be significantly smaller than that of the hole V3 shown. Figure 4 The height of the through hole V3 shown. Figure 5 The height of the through hole V4 shown will be significantly smaller than Figure 4 The height of the through hole V4 is shown. In this way, Figure 5 The path length of the data path DP2 shown will be shortened.

[0068] In some embodiments, the connecting wire CL1 may be disposed on the interlayer insulation layer LO2. In some embodiments, the connecting wire CL2 may be disposed on the interlayer insulation layer LO2.

[0069] In summary, the memory device of the present invention includes at least one memory chip and a logic chip. Each of the at least one memory chip includes a memory array, multiple bit lines, and multiple data paths. The multiple data transmission terminals are electrically connected to the multiple data paths of each of the at least one memory chip in a one-to-one manner. The number of the multiple data transmission terminals is equal to the total number of the multiple data paths of the at least one memory chip. The logic chip can directly read data from all data paths and directly provide data to all data paths. In this way, the memory device can have at least extremely high read bandwidth. The power consumption of the memory device can be reduced. The transmission paths of word line operating voltages and bit line data do not intersect in the same interlayer insulation layer. Therefore, the memory chip does not need to increase the bit line voltage value or significantly increase the data gain to suppress interference from high word line operating voltages. In this way, the power consumption of the memory chip can be reduced. Furthermore, the memory controller is disposed in the logic chip, not in the memory chip. Therefore, the memory capacity can be increased or the chip area can be reduced. In this way, the logic chip can accommodate more memory chips, thereby further improving the access bandwidth.

[0070] Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A memory device, comprising: at least one memory chip, each comprising: a substrate; a memory array comprising a plurality of dynamic random access memory cells; a first interlayer insulating layer covering a first side of the substrate and a plurality of transistors of the dynamic random access memory cells; a plurality of bit lines coupled to the memory array, wherein the bit lines are disposed in the first interlayer insulating layer; a plurality of data paths corresponding to the bit lines, respectively, wherein a number of the data paths is equal to or less than a number of the bit lines; and a sense amplifier array comprising a plurality of sense amplifiers, wherein the bit lines are connected to input terminals of corresponding sense amplifiers in the sense amplifiers via connection paths, respectively, wherein the connection paths comprise: a first via having a first end coupled to a corresponding bit line in the bit lines; a first connection wire having a first end coupled to a second end of the first via; and a second via coupled between a second end of the first connection wire and the input terminal of the corresponding sense amplifier; and a logic chip comprising: a plurality of data transmission terminals electrically connected to the data paths of the at least one memory chip in a one-to-one manner, wherein a number of the data transmission terminals is equal to a total number of the data paths of the at least one memory chip, and wherein the logic chip reads a plurality of data from the at least one memory chip through the data transmission terminals. 2.The memory device of claim 1, wherein each of the sense amplifiers is configured to amplify data located in a corresponding bit line in the bit lines and provide the amplified data to a corresponding data path in the data paths. 3.The memory device of claim 2, wherein: each of the at least one memory chip further comprises a plurality of word lines, each of the dynamic random access memory cells comprises: a transistor having a control terminal coupled to a corresponding word line in the word lines and a first terminal coupled to a corresponding bit line in the bit lines; and a capacitor coupled between a second terminal of the transistor and a reference low voltage. 4.The memory device of claim 3, wherein the word lines are embedded in the substrate. 5.The memory device of claim 4, wherein the first interlayer insulating layer further covers the sense amplifiers. 6.The memory device of claim 1, wherein each of the data paths comprises: a third via having a first end coupled to an output terminal of the corresponding sense amplifier; a second connection wire having a first end coupled to a second end of the third via; and a fourth via disposed between a second end of the second connection wire and a second side of the substrate, wherein the second side contacts the logic chip. 7.The memory device of claim 1, wherein the first connection wire is disposed on the first interlayer insulating layer. 8.The memory device of claim 1, wherein each of the at least one memory chip further comprises: a second interlayer insulating layer covering at least the first interlayer insulating layer, wherein the first connection wire is disposed on the second interlayer insulating layer. ​ 9. The memory device of claim 1, wherein each of the at least one memory chip further comprises: a third interlayer insulating layer covering at least the second interlayer insulating layer; a fourth interlayer insulating layer covering at least the third interlayer insulating layer; and a plurality of metal connection lines respectively coupled to corresponding ones of the word lines and configured to provide a plurality of operating voltages to the word lines, wherein the metal connection lines are respectively disposed on one of the third interlayer insulating layer and the fourth interlayer insulating layer.

10. The memory device of claim 1, wherein the logic chip comprises: an operation circuit configured to perform an operation on at least one of the data.

11. The memory device of claim 10, wherein the logic chip further comprises: an internal connection layer coupled to the operation circuit and the data transmission terminals and configured to receive the data through the data transmission terminals and transmit the data to the operation circuit.

12. The memory device of claim 1, wherein each of the at least one memory chip further comprises a plurality of word lines, and wherein the logic chip comprises: at least one memory controller respectively coupled to corresponding ones of the at least one memory chip and respectively configured to control the corresponding memory chip in response to an operation command such that the corresponding memory chip respectively provides a plurality of operating voltages corresponding to the operation command to the word lines.

13. A memory device, comprising: at least one memory chip, each comprising: a substrate; a memory array disposed on the substrate; a plurality of bit lines disposed on the substrate and coupled to the memory array; and a sense amplifier array comprising a plurality of sense amplifiers; and a plurality of data paths disposed on the substrate and respectively corresponding to the bit lines, wherein a number of the data paths is equal to or less than a number of the bit lines; and a logic chip comprising: a plurality of data transmission terminals, wherein a number of the data transmission terminals is equal to a total number of the data paths of the at least one memory chip, wherein at least some of the data paths respectively pass through the substrate and are connected to the data transmission terminals in a one-to-one manner, wherein each of the data paths comprises: a first via having a first end coupled to an output terminal of a corresponding sense amplifier; a connection wire having a first end coupled to a second end of the first via; and a second via disposed between a second end of the connection wire and a second surface of the substrate, wherein the second surface contacts the logic chip.

14. The memory device of claim 13, wherein each of the sense amplifiers is configured to amplify data located in a corresponding one of the bit lines and provide the amplified data to a corresponding one of the data paths.

15. The memory device of claim 14, wherein: each of the at least one memory chip further comprises a plurality of word lines, the memory array comprises a plurality of dynamic random access memory cells, each of the dynamic random access memory cells comprises: a transistor having a control terminal coupled to a corresponding one of the word lines and a first terminal coupled to a corresponding one of the bit lines; and ​ a capacitor coupled between a second terminal of the transistor and a reference low voltage.

16. The memory device of claim 15, wherein each of the at least one memory chip further comprises: a first interlayer insulating layer covering the first side of the substrate and a plurality of transistors of the dynamic random access memory cells, wherein the word lines are embedded in the substrate.

17. The memory device of claim 16, wherein the first interlayer insulating layer further covers the sense amplifiers.

Images