A soft-switching high-gain DC-DC topology circuit and control method

Abstract

The application discloses a soft-switching high-gain DC-DC topology circuit and a control method. in , a front-stage circuit composed of a switching module, a back-stage circuit composed of a voltage doubling module, an output capacitor C o and a load R load ; wherein the switching module is divided into three structures, namely structures a, b and c; the voltage doubling unit is composed of a multiplication capacitor C i (i∈[1,2n]) and multiplication diodes Di (i∈[1,2n]); and the control loop is composed of a voltage dividing resistor R1 and R2, a current sampling resistor R S , an operational amplifier EA1, an operational amplifier EA2, an isolation optocoupler and a main control chip. The application can realize super-high-gain conversion, reduce voltage stress of a switching tube device and reduce turn-on loss of the switching tube.

Description

Technical Field

[0001] This invention belongs to the field of DC topology technology, specifically relating to a soft-switching high-gain DC-DC topology circuit and its control method. Background Technology

[0002] High-gain DC-DC switching topologies have been widely used in modern industrial fields such as renewable energy power generation, gas discharge, and insulation detection. Traditional non-isolated boost circuits mainly include Boost and Buck-Boost circuits. The boost ratio of these two topologies often cannot exceed 8 times, while applications such as portable gas discharge detection often require topologies to achieve voltage gains of hundreds of times. If these two types are used in gas discharge power supplies, they need to operate at extremely high duty cycles, which will lead to considerable parasitic losses in the circuit. At the same time, because the switching devices operate at extremely high duty cycles, their own conduction losses will increase, and the voltage stress they withstand will be higher. Summary of the Invention

[0003] In order to obtain higher voltage gain, improve the performance of the topology, and reduce the voltage stress of the switching transistor, this invention provides a soft-switching high-gain DC-DC topology circuit and control method.

[0004] The present invention provides a soft-switching high-gain DC-DC topology circuit, including an input capacitor C. in The pre-amplifier circuit consists of a switching module; the post-amplifier circuit consists of a voltage multiplier module; and the output capacitor C. o and load R load The switching module is divided into three structures: structures a, b, and c. Transformer T1 can be equivalent to an ideal transformer, and the magnetizing inductance L... m and leakage L k The voltage multiplier unit consists of a multiplier capacitor C. i It consists of (i∈[1,2n]) and multiplier diode Di(i∈[1,2n]).

[0005] The voltage multiplier module consists of a multiplier capacitor C. iThe circuit consists of voltage multiplier circuit C1, i∈[1,6] and voltage multiplier diode Di, i∈[1,6]. The specific electrical connection relationship is as follows: one end of voltage multiplier circuit C1 is connected to the same-name terminal of the secondary winding of transformer T1, and the other end is connected to the cathode of D1, the anode of D2 and one end of C3 as the first connection terminal; the anode of D1 and one end of C2 are connected to the non-same-name terminal of the secondary winding of transformer T1 to form power ground; the other end of C2 is connected to the cathode of D2 as the second connection terminal; the other end of C3 is connected to the cathode of D3, the anode of D4 and one end of C5 as the third connection terminal; the anode of D3 and one end of C4 are connected to the second connection terminal; the other end of C4 is connected to the cathode of D4 as the fourth connection terminal; the other end of C5 is connected to the cathode of D5 and the anode of D6 as the fifth connection terminal; the anode of D5 and one end of C6 are connected to the fourth connection terminal; the other end of C6 is connected to the cathode of D6 as the sixth connection terminal; the output capacitor C... o Connected in parallel between the sixth connection terminal and the non-identical terminal of the secondary winding of transformer T1; voltage divider resistors R1 and R2 are connected in series, with their upper ends connected to the sixth connection terminal and their lower ends connected to ground; their series connection port is connected to the inverting input terminal of operational amplifier EA1; output load R load With sampling resistor R s Series connection; where the output load R load The other end is connected to the sixth connection terminal, sampling resistor R. s The other end is connected to the non-same-name terminal of the secondary winding of transformer T1; the series port of the two is connected to the inverting input terminal of operational amplifier EA2.

[0006] The control circuit consists of voltage divider resistors R1 and R2, and current sampling resistor R. S The system consists of operational amplifiers EA1 and EA2, an isolation optocoupler, and a main control chip. The specific connection method is as follows: the output terminal of operational amplifier EA1 is connected to diode D... C1 The cathode of EA2 is connected to the output of diode D. C2 The cathodes are connected, and diode D C1 With D C2 The anode of the optocoupler is connected to the input terminal of the isolation optocoupler, and the output terminal of the optocoupler is connected to the inverting input terminal of the main control chip voltage comparator COMP. The output terminal of the optocoupler is compared with the sawtooth wave signal at its positive input terminal to generate a square wave signal to drive the switching transistors S1 and S2.

[0007] The specific control process of the control loop is as follows: voltage divider resistors R1 and R2 are used to divide the high DC output voltage, and the resulting voltage divider signal v rs1 The reference voltage V, which is fed into the inverting input terminal of operational amplifier EA1 and is also fed into the non-inverting input terminal of operational amplifier EA1, is... ref1 Error signal v is generated after PI compensation. e1The error signal is sent to the inverting input of the main control chip's voltage comparator COMP via an isolation optocoupler, and compared with the sawtooth wave signal at its non-inverting input to generate a reset signal v. re To control the switching transistor S1 to open and close, thereby achieving an output voltage of V. ref1 The constant voltage control is defined by / k1, where k1 is the sampling rate of the output voltage; the current sampling resistor R... S It is used to acquire the output current signal and send it to the inverting input terminal of operational amplifier EA2, and to the reference voltage V at the non-inverting input terminal of operational amplifier EA2. ref2 Error signal v is generated after PI compensation. e2 The error signal is sent to the inverting input of the main control chip's voltage comparator COMP via an isolation optocoupler, and compared with the sawtooth wave signal at its non-inverting input to generate a reset signal v. re To control the switching transistor S2 to open and close, thereby achieving an output voltage of V. ref2 The constant current control is / k2, where k2 is the sampling rate of the output current.

[0008] The main control chip is divided into two types of driving logic, namely driving logic d and e. For structures a and b, driving logic d is used, which adopts a complementary conduction mode, and the generated driving signals vg1 and vg2 drive the switching transistors S1 and S2. For structure c, driving logic e is used, which adopts a symmetrical conduction mode, and the generated driving signals vg1 and vg2 drive the switching transistors S1 and S2.

[0009] The structure of the switching module a consists of switching transistors S1 and S2, and capacitor C. c It consists of a transformer T1, and the specific connection method is as follows: the drain of switch S1 is connected to the non-same-name terminal of the primary winding of transformer T1, and its source is connected to the input filter capacitor C. in The negative terminal and the input DC voltage V in The negative terminal is connected to form power ground; its gate is driven by the OUTA pin of the main control chip; capacitor C c One end is connected to the non-identical terminal of transformer T1, and the other end is connected to the drain of switching transistor S2. The source of switching transistor S2 is connected to the power ground terminal, and its gate is driven by the OUTB pin of the main control chip.

[0010] The structure b of the switching module consists of switching transistors S1 and S2, and capacitor C. c It consists of a transformer T1, and the specific connection method is as follows: the drain of switch S1 is connected to the non-same-name terminal of the primary winding of transformer T1, and its source is connected to the input filter capacitor C. in The negative terminal and the input DC voltage V in The negative terminal is connected to form power ground; its gate is driven by the OUTA pin of the main control chip; capacitor C cOne end is connected to the same-name terminal of transformer T1, and the other end is connected to the drain of switching transistor S2. The source of switching transistor S2 is connected to the non-same-name terminal of transformer, and its gate is driven by the OUTB pin of the main control chip.

[0011] The structure of the switching module c consists of switching transistors S1 and S2, and capacitor C. r1 C r2 It consists of a transformer T1 and a switch S1. The specific connection method is as follows: the drain of the switch S1 is connected to the same terminal of the primary winding of the transformer T1 and the capacitor C. r1 One end of the capacitor is connected, its source is connected to the drain of switch S2, and its gate is driven by the OUTA pin of the main control chip; capacitor C r1 The other end is connected to the non-identical terminal of transformer T1; the source of switch S2 is connected to the resonant capacitor C. r2 One end is connected to form power ground; its gate is driven by the OUTB pin of the main control chip; capacitor C r2 The other end is connected to the non-identical end of transformer T1.

[0012] This topology not only achieves electrical isolation between the primary and secondary sides but also achieves ultra-high voltage gain and low switching stress with a relatively small transformer turns ratio and low duty cycle. Structures a and b further reduce the voltage stress on the active switches by recovering energy stored in the transformer leakage inductance, and both active switches achieve zero-voltage switching, effectively reducing switching losses. Structure c improves transformer utilization and effectively reduces the voltage stress on the switching transistors by time-sharing the upper and lower transistors within one cycle.

[0013] The voltage multiplier unit is used to perform a secondary boosting of the alternating voltage generated on the secondary side of transformer T1; the multiplier diode D... i Used to control the multiplication capacitor C during the on and off processes of the switching transistor S1. i Perform charging and discharging; multiplying capacitor C i It is used to perform secondary boosting and filtering of alternating voltage during its own charging and discharging process.

[0014] Output capacitor C o It is used to smooth the DC voltage output and absorb the pulse current generated by the voltage multiplier unit.

[0015] Voltage divider resistors R1 and R2 are used to divide the high DC output voltage, and the resulting voltage divider signal v rs1 The reference voltage V, which is fed into the inverting input terminal of operational amplifier EA1 and is also fed into the non-inverting input terminal of operational amplifier EA1, is... ref1 Error signal v is generated after PI compensation. e1 The error signal is sent to the inverting input of the main control chip's voltage comparator COMP via an isolation optocoupler, and compared with the sawtooth wave signal at its non-inverting input to generate a reset signal v.re To control the opening and closing of the main switch S1, thereby achieving an output voltage of V. ref1 / k1 constant voltage control, where k1 is the sampling rate of the output voltage.

[0016] Current sampling resistor R S It is used to acquire the output current signal and send it to the inverting input terminal of operational amplifier EA2, and to the reference voltage V at the non-inverting input terminal of operational amplifier EA2. ref2 Error signal v is generated after PI compensation. e2 The error signal is sent to the inverting input of the main control chip's voltage comparator COMP via an isolation optocoupler, and compared with the sawtooth wave signal at its non-inverting input to generate a reset signal v. re By switching transistor S2 on and off, the output voltage V is achieved. ref2 The constant current control is / k2, where k2 is the sampling rate of the output current.

[0017] The main control chip outputs PWM waves to control the on / off state of the main switches S1 and S2. For structures a and b, the main control chip uses logic circuit d with a complementary conduction mode, generating drive signals vg1 and vg2 to drive switches S1 and S2. For structure c, the main control chip uses logic circuit e with a symmetrical conduction mode, generating drive signals vg1 and vg2 to drive switches S1 and S2. This is coordinated with the turns ratio of the primary and secondary windings of transformer T1 to output a low duty cycle. Furthermore, this control chip also features undervoltage protection and cycle-by-cycle current limiting protection, and the frequency of the internal oscillator is set via an external resistor to ground connected to the RT pin.

[0018] The beneficial technical effects of this invention are as follows:

[0019] This invention achieves ultra-high gain conversion by integrating the front-end switching module and the back-end voltage multiplier module, enabling the switching transistor to achieve a boost ratio of more than 40 times while operating at a low duty cycle of 0.4.

[0020] This invention operates under low duty cycle conditions, which can reduce the voltage stress on the switching transistor device.

[0021] The transformer of this invention features a smaller peak and effective value of primary-side excitation current. While achieving energy storage under the conducting state of the switching transistor, it also facilitates energy transfer from the low-voltage side to the high-voltage side, increasing the utilization rate of the magnetic core. Furthermore, the use of the transformer and optocoupler enables complete isolation of this topology, improving system reliability.

[0022] This invention improves efficiency by recovering energy stored in the transformer's leakage inductance and absorbs voltage spikes in the switching transistor, further reducing voltage stress on the transistor. Figure 2 , 3Both switches shown have achieved ZVS, which reduces the turn-on loss of the switches. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the principle structure and control loop of the high-gain DC-DC topology of the present invention.

[0024] Figure 2 The structure of the switch module is shown in section a.

[0025] Figure 3 The structure of the switch module is shown in section b.

[0026] Figure 4 The structure c is for the switch module.

[0027] Figure 5 This is the main control chip that drives logic d.

[0028] Figure 6 This is the main control chip that drives logic e.

[0029] Figure 7 The main operating waveforms of the circuit are shown when the switching module is structure a.

[0030] Figure 8 The main operating waveforms of the circuit are shown when the switching module is structure b.

[0031] Figure 9 The main operating waveforms of the circuit are shown when the switch module is structure c.

[0032] Figure 10 This is a schematic diagram of the equivalent circuit of the circuit in the working mode when the switching module is structure a.

[0033] Figure 11 This is a schematic diagram of the equivalent circuit of the circuit in the working mode when the switching module is structure b.

[0034] Figure 12 This is a schematic diagram of the equivalent circuit of the circuit in the working mode when the switching module is structure c.

[0035] Figure 13 This is a graph showing the relationship between the voltage stress of the switching transistor and the transformer turns ratio N and the multiplication stage number n under the conditions of duty cycle D = 0.4 and voltage gain M = 40.

[0036] Figure 14 The diagram shows the input and output parameter waveforms of the circuit in the working state of an embodiment of the present invention.

[0037] Figure 15 This is a waveform diagram of the primary and secondary currents of the transformer in the working state of the circuit of this embodiment of the invention.

[0038] Figure 16The diagram shows the driving waveform and voltage stress waveform of the main switch S1 in the working state of the circuit in the embodiment of the present invention.

[0039] Figure 17 The diagram shows the driving waveform and voltage stress waveform of the switching transistor S2 in the working state of the circuit in the embodiment of the present invention. Detailed Implementation

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0041] The present invention provides a soft-switching high-gain DC-DC topology circuit, such as... Figure 1 As shown, this topology consists of an input filter capacitor C. in The pre-amplifier circuit consists of a switching module, the post-amplifier circuit consists of a voltage multiplier module, and the output capacitor C... o and load R load .

[0042] The switching module can be divided into, for example... Figure 2-4 The three structures shown;

[0043] The structure of the switch module is as follows: Figure 2 As shown, the circuit consists of switches S1 and S2, and capacitor C. c It consists of a transformer T1, and the specific connection method is as follows: the drain of switch S1 is connected to the non-same-name terminal of the primary winding of transformer T1, and its source is connected to the input filter capacitor C. in The negative terminal and the input DC voltage V in The negative terminal is connected to form power ground; its gate is driven by the OUTA pin of the main control chip; capacitor C c One end is connected to the non-identical terminal of transformer T1, and the other end is connected to the drain of switching transistor S2. The source of switching transistor S2 is connected to the power ground terminal, and its gate is driven by the OUTB pin of the main control chip.

[0044] The structure of the switch module is as follows (b) Figure 3 As shown, the circuit consists of switches S1 and S2, and capacitor C. c It consists of a transformer T1, and the specific connection method is as follows: the drain of switch S1 is connected to the non-same-name terminal of the primary winding of transformer T1, and its source is connected to the input filter capacitor C. in The negative terminal and the input DC voltage V in The negative terminal is connected to form power ground; its gate is driven by the OUTA pin of the main control chip; capacitor C c One end is connected to the same-name terminal of transformer T1, and the other end is connected to the drain of switching transistor S2. The source of switching transistor S2 is connected to the non-same-name terminal of transformer, and its gate is driven by the OUTB pin of the main control chip.

[0045] The structure of the switch module is as follows: Figure 4As shown, the circuit consists of switches S1 and S2, and capacitor C. r1 C r2 It consists of a transformer T1 and a switch S1. The specific connection method is as follows: the drain of the switch S1 is connected to the same terminal of the primary winding of the transformer T1 and the capacitor C. r1 One end of the capacitor is connected, its source is connected to the drain of switch S2, and its gate is driven by the OUTA pin of the main control chip; capacitor C r1 The other end is connected to the non-identical terminal of transformer T1; the source of switch S2 is connected to the resonant capacitor C. r2 One end is connected to form power ground; its gate is driven by the OUTB pin of the main control chip; capacitor C r2 The other end is connected to the non-identical end of transformer T1.

[0046] Transformer T1 can be equivalent to an ideal transformer, with magnetizing inductance L m and leakage L k The voltage multiplier unit consists of a multiplier capacitor C. i The control loop consists of voltage divider resistors R1 and R2, and current sampling resistor R. (i∈[1,2n]) and multiplier diode Di(i∈[1,2n]). S It consists of operational amplifier EA1, operational amplifier EA2, isolation optocoupler and main control chip.

[0047] The electrical connection in this embodiment is a multiplier capacitor C. i (i∈[1,6]) and multiplication diode D i (i∈[1,6]). For example... Figure 1 As shown, the specific electrical connections are as follows: One end of the voltage multiplier circuit C1 is connected to the same-name terminal of the secondary winding of transformer T1, and the other end is connected to the cathode of D1, the anode of D2, and one end of C3, serving as the first connection terminal; the anode of D1 and one end of C2 are connected to the non-same-name terminal of the secondary winding of transformer T1, forming a power ground; the other end of C2 is connected to the cathode of D2, serving as the second connection terminal; the other end of C3 is connected to the cathode of D3, the anode of D4, and one end of C5, serving as the third connection terminal; the anode of D3 and one end of C4 are connected to the second connection terminal; the other end of C4 is connected to the cathode of D4, serving as the fourth connection terminal; the other end of C5 is connected to the cathode of D5 and the anode of D6, serving as the fifth connection terminal; the anode of D5 and one end of C6 are connected to the fourth connection terminal; the other end of C6 is connected to the cathode of D6, serving as the sixth connection terminal; the output capacitor C... o Connected in parallel between the sixth connection terminal and the non-identical terminal of the secondary winding of transformer T1; voltage divider resistors R1 and R2 are connected in series, with their upper ends connected to the sixth connection terminal and their lower ends connected to ground; their series connection port is connected to the inverting input terminal of operational amplifier EA1; output load R load With sampling resistor R s Series connection; where the output load R load The other end is connected to the sixth connection terminal, sampling resistor R.s The other end is connected to the non-same-name terminal of the secondary winding of transformer T1; the series port of the two is connected to the inverting input terminal of operational amplifier EA2.

[0048] The control circuit consists of voltage divider resistors R1 and R2, and current sampling resistor R. S The system consists of operational amplifiers EA1 and EA2, an isolation optocoupler, and a main control chip. The specific connection method is as follows: the output terminal of operational amplifier EA1 is connected to diode D... C1 The cathode of EA2 is connected to the output of diode D. C2 The cathodes are connected, and diode D C1 With D C2 The anode of the optocoupler is connected to the input terminal of the isolation optocoupler, and the output terminal of the optocoupler is connected to the inverting input terminal of the main control chip voltage comparator COMP. The output terminal of the optocoupler is compared with the sawtooth wave signal at its positive input terminal to generate a square wave signal to drive the switching transistors S1 and S2.

[0049] The specific control process of the control loop is as follows: voltage divider resistors R1 and R2 are used to divide the high DC output voltage, and the resulting voltage divider signal v rs1 The reference voltage V, which is fed into the inverting input terminal of operational amplifier EA1 and is also fed into the non-inverting input terminal of operational amplifier EA1, is... ref1 Error signal v is generated after PI compensation. e1 The error signal is sent to the inverting input of the main control chip's voltage comparator COMP via an isolation optocoupler, and compared with the sawtooth wave signal at its non-inverting input to generate a reset signal v. re To control the switching transistor S1 to open and close, thereby achieving an output voltage of V. ref1 The constant voltage control is defined by / k1, where k1 is the sampling rate of the output voltage; the current sampling resistor R... S It is used to acquire the output current signal and send it to the inverting input terminal of operational amplifier EA2, and to the reference voltage V at the non-inverting input terminal of operational amplifier EA2. ref2 Error signal v is generated after PI compensation. e2 The error signal is sent to the inverting input of the main control chip's voltage comparator COMP via an isolation optocoupler, and compared with the sawtooth wave signal at its non-inverting input to generate a reset signal v. re To control the switching transistor S2 to open and close, thereby achieving an output voltage of V. ref2 The constant current control is / k2, where k2 is the sampling rate of the output current.

[0050] The main control chip is divided into two types of driving logic, namely driving logic d and e (as shown in the figure below). Figure 5 , Figure 6As shown, for structures a and b, driving logic d is used, and complementary conduction mode is adopted. The generated driving signals vg1 and vg2 drive the switching transistors S1 and S2. For structure c, driving logic e is used, and symmetrical conduction mode is adopted. The generated driving signals vg1 and vg2 drive the switching transistors S1 and S2.

[0051] The high-gain DC-DC topology circuit is analyzed below. To analyze the working principle of this invention, the following assumptions are made: (1) All components are ideal components (their efficiency coefficients and parasitic parameters are not considered); (2) The output capacitor C... o Large enough, without considering voltage and current ripple; (3) Switching frequency f s Much greater than the power frequency f L That is, f s >>f L This topology has two different operating conditions: t on >T r / 2 and t on <T r / 2,t on and T r These represent the on-time of the switching transistor and the resonant period of the secondary current, respectively. To achieve higher efficiency, this invention primarily addresses the operating condition t. on >T r / 2 is analyzed.

[0052] For ease of analysis, the analysis process for the input stage only considers the coupled single-stage voltage multiplier unit; the analysis process for multi-stage voltage multiplier units is similar. Figure 2 The topology described in one switching cycle T s Within this topology, the input stage has 11 operating modes. Figure 7 The main waveform diagram for the operation of this circuit is shown below. The corresponding modal circuit is as follows: Figure 10 As shown.

[0053] Mode 1 [t0~t1]: At time t0, switch S2 is off, and switch S1 remains off. Transformer primary current i Lp The output capacitor C of switch S1 s1 Discharge, affecting the output capacitor C of switch S2. s2 Charge.

[0054] Mode 2 [t1~t2]: At time t1, the voltage across switch S1 is zero. After time t1, S1 is turned on and S2 is turned off. Since V... ds1 The voltage has dropped to 0, therefore S1 achieves zero-voltage conduction. Excitation current i Lm It increases linearly.

[0055]

[0056] At this time, the transformer leakage inductance L k and multiplier capacitor C r Resonance occurs, and the resonant current i r for:

[0057]

[0058] In the formula, C r For the equivalent resonant capacitance of the voltage multiplication capacitor, when only the coupled voltage multiplication unit is considered, Cr = C1C2 / (C1+C2); L k This refers to the leakage inductance on the secondary side of the transformer. and These are the angular frequency and equivalent impedance of the resonant circuit, respectively.

[0059] According to Kirchhoff's laws, the current in the primary winding of a transformer can be expressed as:

[0060] i Lp (t)=Ni Ls (t)+i Lm (t) (3)

[0061] Mode 3 [t2~t3]: At time t2, the leakage inductance L k and multiplier capacitor C r Continued resonance, i Lm Continue to increase linearly, when i Lm Mode 3 ends when the value increases from negative to 0.

[0062] Mode 4 [t3~t4]: In this mode, i Lm The current increases linearly from zero. The secondary side of the transformer continues to resonate. When the resonant current i... r When the value is zero, the mode ends.

[0063] Mode 5 [t4~t5]: In this mode, the primary current i of the transformer... Lp The excitation inductor current increases linearly. Lm With the transformer primary current i Lp same.

[0064] Mode 6 [t5~t6]: At time t5, S2 is turned off, and the transformer primary current i Lp The output capacitor C of S1 S1 Charging, for the output capacitor C of S2 S2 Discharge.

[0065] Mode 7 [t6~t7]: After time t6, S2 is turned on and S1 is turned off, because V ds2 The voltage has dropped to 0, therefore S2 achieves zero-voltage conduction. m Start with capacitor C cIt charges and transfers some energy to the secondary side of the transformer. Excitation current i Lm It decreases linearly, and its expression is:

[0066]

[0067] When considering only the coupling of the first-stage voltage multiplier unit, the transformer leakage inductance L k With the multiplier capacitor C1 and capacitor C c Resonance, resonant current i r It can be represented as:

[0068]

[0069] In the formula, the resonant impedance Z r2 and resonant angular frequency ω r2 It can be represented as:

[0070]

[0071]

[0072] The primary current of the transformer can also be represented by (3), and the mode ends when it drops to 0.

[0073] Mode 8 [t7~t8]: At time t7, the primary current i LP Reduced to 0, transformer leakage inductance L k With the multiplication capacitor C1 and capacitor C c The resonance continues until the primary current becomes zero, at which point the mode ends.

[0074] Mode 9 [t8~t9]: In this mode, the transformer leakage inductance L k With the multiplication capacitor C1 and capacitor C c Continuing to resonate, the equivalent circuit of this mode is the same as that of mode 7. When the transformer secondary current i Ls When the resonance is 0, the mode ends.

[0075] Mode 10 [t9~t] 10 In this mode, the primary current i Lp Linear decrease, when i Lp When the value decreases to 0, this mode ends.

[0076] Mode 11[t 10 ~t 11 In this mode, the primary current i of the transformer... Lp As the voltage decreases further, when the switching transistor S2 is turned off, one switching cycle ends and the next switching cycle begins.

[0077] Figure 3 The circuit topology and the main waveforms of its control loop shown are as follows: Figure 8 As shown. In one switching cycle T s It has 11 operating modes, and the corresponding modal circuits are as follows: Figure 11 As shown.

[0078] Mode 1 [t0~t1]: At time t0, switch S2 is turned off, while switch S1 remains off. Transformer primary current i Lp The output capacitor C of S1 s1 Discharge, affecting the output capacitor C of S2 s2 Charging, due to C s1 and C s2 The capacitance C is very small, so mode 1 is very short. s1 Discharge process and capacitance C s2 The charging process is approximately linear. Therefore, the excitation current in this mode is constant.

[0079] Mode 2 [t1~t2]: At time t1, the voltage across switch S1 is zero. After time t1, S1 turns on and S2 turns off. Due to the voltage stress V borne by S1... ds1 The voltage has dropped to 0, therefore S1 achieves ZVS. After S1 is turned on, the input power supply V... in Magnetizing inductor L m Charging, excitation current i Lm It increases linearly.

[0080]

[0081] When only considering the coupled single-stage voltage multiplier unit, the transformer leakage inductance L k and multiplier capacitor C r Resonance occurs, and the resonant current i r for:

[0082]

[0083] Among them, C r For the equivalent resonant capacitance, Cr = C1C2 / (C1+C2); L k This refers to the leakage inductance on the secondary side of the transformer. and Here, ω represents the angular frequency and equivalent impedance of the resonant circuit, respectively; N is the transformer turns ratio; the time of mode 2 is...

[0084] The current on the primary side of the transformer can be expressed as:

[0085] i Lp (t)=Ni Ls (t)+i Lm (t) (10)

[0086] Mode 3 [t2~t3]: At time t2, the leakage inductance L k and equivalent multiplication capacitance C r Continued resonance, i Lm Continue to increase linearly, when i Lm Mode 3 ends when the value increases from negative to 0.

[0087] Mode 4 [t3~t4]: In this mode, i Lm It continues to increase linearly from zero. The secondary side of the transformer continues to resonate, and when the resonant current i... r When the value is zero, the mode ends.

[0088] Mode 5 [t4~t5]: In this mode, the primary current i of the transformer... Lp The excitation inductor current i continues to increase linearly. Lm With the transformer primary current i Lp same.

[0089] Mode 6 [t5~t6]: At time t5, S2 is turned off, and the transformer primary current i Lp The output capacitor C of S1 S1 Charging, for the output capacitor C of S2 S2 Discharge. Similar to mode 1, the process of mode 6 is also very short, and the excitation current of this mode is also constant.

[0090] Mode 7 [t6~t7]: After time t6, S2 is turned on and S1 is turned off. Due to the voltage stress V borne by S2... ds2 The value has been reduced to 0, therefore S2 achieves ZVS. m Start with capacitor C c It charges and transfers some energy to the secondary side of the transformer. Excitation current i Lm It decreases linearly, and its expression is:

[0091]

[0092] Where V Cc For capacitor C c The voltage across the terminals is the same as the excitation inductance L in mode 7. m The voltages at both ends are the same.

[0093] When considering only the coupling of the first-stage voltage multiplier unit, the transformer leakage inductance L k With the multiplication capacitor C1 and capacitor C c Resonance, resonant current i r It can be represented as:

[0094]

[0095] Where V Cc and V C1 These are capacitors Cc The voltage across the multiplication capacitor C1, and the resonant impedance Z r2 and resonant angular frequency ω r2 It can be represented as:

[0096]

[0097]

[0098] The primary current of the transformer can also be represented by (3), and the mode ends when it drops to 0.

[0099] Mode 8 [t7~t8]: At time t7, the primary current i LP Reduced to 0, transformer leakage inductance L k With the multiplication capacitor C1 and capacitor C c The resonance continues until the primary current becomes zero, at which point the mode ends.

[0100] Mode 9 [t8~t9]: In this mode, the transformer leakage inductance L k With the multiplication capacitor C1 and capacitor C c Continuing to resonate, the equivalent circuit of this mode is the same as that of mode 7. When the transformer secondary current i Ls When the resonance is 0, the mode ends.

[0101] Mode 10 [t9~t] 10 In this mode, the primary current i Lp Linear decrease, when i Lp When the value decreases to 0, this mode ends.

[0102] Mode 11[t 10 ~t 11 In this mode, the primary current i of the transformer... Lp As the voltage decreases further, when the switching transistor S2 is turned off, one switching cycle ends and another switching cycle begins.

[0103] Figure 5 The main waveform diagram of the circuit operation is as follows: Figure 9 As shown, in one switching cycle T s Internally, there are 8 operating modes, and the corresponding modal circuits are as follows: Figure 12 As shown.

[0104] Mode 1 [t0~t1]: In this mode, both switch S1 and switch S2 remain off. The power supply is connected to the input capacitor C. in Charging. At time t1, switch S1 is turned on, and this mode ends.

[0105] Mode 2 [t1~t2]: At time t1, switch S1 is turned on, and the transformer primary current i LpFor the resonant capacitor C r1 Discharge, on the resonant capacitor C r2 Charging. In this mode, the leakage inductance L on the primary side of the transformer... k With equivalent resonant capacitance C r Resonance, excitation current i Lm It continues to increase linearly. The excitation current can be expressed as:

[0106]

[0107] When only considering the coupled single-stage voltage multiplier unit, the transformer leakage inductance L k and equivalent resonant capacitance C r Resonance occurs, and the resonant current i r for:

[0108]

[0109] Among them, C r For the equivalent resonant capacitance, Cr = C1C2 / (C1+C2); V cr2 It is capacitor C r2 The voltage across C r1 and C r2 Large enough that the voltage across its terminals can be equivalent to half the input voltage; L k This refers to the leakage inductance on the secondary side of the transformer. and Here, ω represents the angular frequency and equivalent impedance of the resonant circuit, respectively; N is the turns ratio of the transformer; the current on the primary side of the transformer can be expressed as:

[0110] i Lp (t)=Ni Ls (t)+i Lm (t) (17)

[0111] Mode 3 [t2~t3]: At time t2, the excitation current crosses zero. In this mode, the transformer leakage inductance L... k With resonant capacitor C r Continue to resonate.

[0112] Mode 4 [t3~t4]: Resonance ends at time t3, and the primary current i Lp(t) That is, the excitation current i Lm(t) The current increases linearly until time t4, when switch S1 is turned off, and this mode ends.

[0113] Mode 5 [t4~t5]: At time t4, switch S1 is turned off. During this stage, the transformer secondary current i Ls(t) The load decreases linearly and is powered by C2 until time t5, when switch S2 turns on, ending this mode.

[0114] Mode 6 [t5~t6]: At time t5, switch S2 is turned on, and the transformer primary current i Lp For the resonant capacitor C r1 Charging, for the resonant capacitor C r2 Discharge. Transformer leakage inductance L k With equivalent resonant capacitance C r The resonance continues until time t6, when the excitation current crosses zero, ending this mode.

[0115] When considering only the coupling of the first-stage voltage multiplier unit, the transformer leakage inductance L k With equivalent resonant capacitance C r Resonance, resonant current i r It can be represented as:

[0116]

[0117] Where V Cr1 It is capacitor C r1 The voltage across C r1 and C r2 When large enough, the voltage across its terminals can be equivalent to half the input voltage; L k This refers to the leakage inductance on the secondary side of the transformer. and C represents the angular frequency and equivalent impedance of the resonant circuit, respectively; when only the first-stage voltage multiplier circuit is considered, C... r =C1.

[0118] Mode 7 [t6~t7]: In this mode, the transformer leakage inductance L k With equivalent resonant capacitance C r Resonance occurs at time t7, at which point the resonance ends and this mode ends.

[0119] Mode 8 [t7~t8]: At time t7, resonance ends, and the primary current i Lp(t) That is, the excitation current i Lm(t) The current decreases linearly until time t8, when switch S2 turns off, ending this mode, one switching cycle, and the beginning of another. This invention patent analyzes the following circuit topology:

[0120] When switch S1 is turned on, the input voltage supplies power to the magnetizing inductor L. m Charging, its expression is:

[0121]

[0122] When switch S2 is turned on, magnetizing inductor L m The voltage across the terminals and the capacitance C c The voltages at both ends are the same, according to L m The second-volt balance on the above can be obtained as follows:

[0123] V in DV Cc (1-D)=0 (20)

[0124] In the formula, D = t on1 / T s It is the duty cycle of S1, V Cc It is the voltage across capacitor Cc.

[0125] Therefore V Cc It can be represented as:

[0126]

[0127] Ignoring the voltage drop across the transformer leakage inductance, V Cc It can also be expressed as:

[0128]

[0129] The voltage across the multiplier capacitor C2 can be expressed as:

[0130]

[0131] In the formula, V o is the output voltage, and n is the number of stages in the CW multiplier circuit.

[0132] Combining (18), (19) and (22), the voltage gain of this topology can be expressed as:

[0133]

[0134] The switching transistor S1 experiences voltage stress in modes 7 to 11, and the voltage stress it experiences is the sum of the input voltage and the voltage across the capacitor.

[0135]

[0136] Combining (9) to (13) and (14), the voltage stress of S1 can be expressed as:

[0137]

[0138] Switch S2 experiences voltage stress in modes 2 to 5. The voltage stress experienced by S2 can be expressed as:

[0139]

[0140] Multiplier capacitor C i The voltage stress it bears can be expressed as:

[0141]

[0142] Analysis shows that the voltage stress borne by the diode is related to the voltage across the even-multiplied capacitor:

[0143]

[0144] From equation (24), it can be seen that there is a certain relationship between the transformer turns ratio N and the voltage multiplication unit stage n, that is, when the voltage gain M and the duty cycle D are constant, the two are inversely proportional. From equations (26) and (27), it can be seen that, under the premise of ignoring the influence of leakage inductance, the voltage stress of the switching transistor is related to the duty cycle D, and the larger D is, the greater the voltage stress. In order to reduce its voltage stress, it can be achieved by reducing the working duty cycle of the topology. It is worth noting that when the influence of leakage inductance is taken into account, the voltage stress of the switching transistor should also be increased by the leakage inductance peak voltage on the basis of equation (25), and the transformer turns ratio N will also affect the voltage stress of the switching transistor. From equation (29), it can be seen that when the output voltage is constant, that is, the input voltage and voltage gain are constant, the voltage stress of the multiplication diode is only related to the voltage multiplication unit stage. When the output voltage is high enough, in order to reduce its voltage stress, the number of voltage multiplication unit stages used should not be too small. Through the above analysis, it can be seen that, under the premise that M and D are constant, N and n not only restrict each other, but also jointly affect the voltage stress of the switching transistor, while n alone affects the voltage stress of the multiplication diode. Choosing the right combination of transformer turns ratio and voltage multiplication unit number will be extremely important.

[0145] Figure 13 The relationship between the switching transistor voltage stress and N and n is presented under low duty cycle (D=0.4) and voltage gain (M=40). It is easy to see that as N or n increases, V... stress-S Both will decrease, but as N or n increases, V will decrease. stress-S However, the smaller the decrease, that is, when N≥20 or n≥3, V stress-S The effect of reducing voltage gradually becomes insignificant. For voltage stress in multiplier diodes, a larger n is desirable, but this increases topology size and cost. To ensure V... stress-S and V stress-D Neither should be too high; considering all factors, it is advisable to select 5≤N≤15 and 2≤n≤4.

[0146] To reduce the voltage stress on the switching transistor, the duty cycle D is set to approximately 0.4. When this invention achieves a voltage boost from 24V to 1000V, the boost ratio N≈9 can be calculated according to equation (24).

[0147] To verify the correctness of the above theoretical analysis results of the present invention, for Figure 2 The topology was verified in a physical manner, and the circuit parameters used are shown in Table 1.

[0148] Table 1 Circuit Parameters

[0149]

[0150]

[0151] Input and output parameter waveforms are as follows Figure 14 As shown. By Figure 14 It can be seen that when the input voltage is 24V, the output voltage is 1005V, which is close to the theoretical design value of 1000V, and the actual voltage gain M is 41.9. The output current is constant at 35.1mA, which meets the design value.

[0152] The waveforms of the primary and secondary currents of the transformer are as follows: Figure 15 As shown. By Figure 15 It can be seen that the primary resonant peak current of the soft-switching high-gain DC-DC topology of the present invention is 4.8A and the excitation peak current is 5.6A.

[0153] The active main switch S1 drive waveform and voltage stress waveform are as follows: Figure 16 As shown. Figure 16 As shown, the switching period T of the main switch S1 s = 15.02μs, switching period f s = 66.6kHz. On-time t on = 6.3μs, with an input voltage of 24V, the switching period T s The theoretical value is 15.15 μs, and the switching frequency f is... s The theoretical value is 66kHz, which is basically the same as the actual value. Figure 16 It can be seen that the duty cycle D = t on / T s =41.9%, consistent with the theoretical design value. The transient peak voltage of S1 is 40V, and the steady-state maximum voltage stress is 40V. Substituting the actual duty cycle D into equation (26), we can obtain V s1-max =41.3V, which is consistent with reality. As can be seen from the enlarged part of the figure, the main switch has achieved zero-voltage turn-on, reducing turn-on losses.

[0154] The drive waveform and voltage stress waveform of switch S2 are as follows: Figure 17 As shown. Figure 17 As shown, the switching period T of switch S2 s = 15.02μs, switching period f s = 66.6kHz. On-time t on = 8.4μs, with an input voltage of 24V, the switching period T s The theoretical value is 15.15 μs, and the switching frequency f is... s The theoretical value is 66kHz, which is basically the same as the actual value. At the same time, the switching transistor also achieved zero-voltage turn-on, reducing turn-on losses.

Claims

1. A soft-switching high-gain DC-DC topology circuit, characterized in that, Including input capacitor C in The pre-amplifier circuit consists of a switching module; the post-amplifier circuit consists of a voltage multiplier module; and the output capacitor C. o and load R load ; The switch module is divided into three structures, namely structures a, b, and c. The voltage multiplier module consists of a multiplier capacitor C. i The circuit consists of voltage multiplier circuit C1, i∈[1, 6] and voltage multiplier diode Di, i∈[1, 6]. The specific electrical connection relationship is as follows: one end of voltage multiplier circuit C1 is connected to the same-name terminal of the secondary winding of transformer T1, and the other end is connected to the cathode of D1, the anode of D2 and one end of C3 as the first connection terminal; the anode of D1 and one end of C2 are connected to the non-same-name terminal of the secondary winding of transformer T1 to form power ground; the other end of C2 is connected to the cathode of D2 as the second connection terminal; the other end of C3 is connected to the cathode of D3, the anode of D4 and one end of C5 as the third connection terminal; the anode of D3 and one end of C4 are connected to the second connection terminal; the other end of C4 is connected to the cathode of D4 as the fourth connection terminal; the other end of C5 is connected to the cathode of D5 and the anode of D6 as the fifth connection terminal; the anode of D5 and one end of C6 are connected to the fourth connection terminal; the other end of C6 is connected to the cathode of D6 as the sixth connection terminal; the output capacitor C o Connected in parallel between the sixth connection terminal and the non-identical terminal of the secondary winding of transformer T1; voltage divider resistors R1 and R2 are connected in series, with their upper ends connected to the sixth connection terminal and their lower ends connected to ground; their series connection port is connected to the inverting input terminal of operational amplifier EA1; output load R load With sampling resistor R s Series connection; where the output load R load The other end is connected to the sixth connection terminal, sampling resistor R. s The other end is connected to the non-same-name terminal of the secondary winding of transformer T1; the series connection port of the two is connected to the inverting input terminal of operational amplifier EA2; The control circuit consists of voltage divider resistors R1 and R2, and current sampling resistor R. S The system consists of operational amplifiers EA1 and EA2, an isolation optocoupler, and a main control chip. The specific connection method is as follows: the output terminal of operational amplifier EA1 is connected to diode D... C1 The cathode of EA2 is connected to the output of diode D. C2 The cathodes are connected, and diode D C1 With D C2 The anode of the optocoupler is connected to the input terminal of the isolation optocoupler, and the output terminal of the optocoupler is connected to the inverting input terminal of the main control chip voltage comparator COMP. The output terminal of the optocoupler is compared with the sawtooth wave signal at its positive input terminal to generate a square wave signal to drive the switching transistors S1 and S2. The specific control process of the control loop is as follows: voltage divider resistors R1 and R2 are used to divide the high DC output voltage, and the resulting voltage divider signal v rs1 The reference voltage V, which is fed into the inverting input terminal of operational amplifier EA1 and is parallel to the non-inverting input terminal of operational amplifier EA1, is... ref1 Error signal v is generated after PI compensation. e1 The error signal is sent to the inverting input of the main control chip's voltage comparator COMP via an isolation optocoupler, and compared with the sawtooth wave signal at its non-inverting input to generate a reset signal v. re To control the switching transistor S1 to open and close, thereby achieving an output voltage of V. ref1 The constant voltage control is defined by / k1, where k1 is the sampling rate of the output voltage; the current sampling resistor R... S It is used to acquire the output current signal and send it to the inverting input of operational amplifier EA2, and to the reference voltage V at the non-inverting input of operational amplifier EA2. ref2 Error signal v is generated after PI compensation. e2 The error signal is sent to the inverting input of the main control chip's voltage comparator COMP via an isolation optocoupler, and compared with the sawtooth wave signal at its non-inverting input to generate a reset signal v. re To control the switching transistor S2 to open and close, thereby achieving an output voltage of V. ref2 The constant current control is / k2, where k2 is the sampling rate of the output current; The main control chip is divided into two types of driving logic, namely driving logic d and e. For structures a and b, driving logic d is used, which adopts a complementary conduction mode, and the generated driving signals vg1 and vg2 drive the switching transistors S1 and S2. For structure c, driving logic e is used, which adopts a symmetrical conduction mode, and the generated driving signals vg1 and vg2 drive the switching transistors S1 and S2.

2. The soft-switching high-gain DC-DC topology circuit according to claim 1, characterized in that, The structure a of the switching module consists of switching transistors S1 and S2, and capacitor C. c It consists of a transformer T1, and the specific connection method is as follows: the drain of switch S1 is connected to the non-same-name terminal of the primary winding of transformer T1, and its source is connected to the input filter capacitor C. in The negative terminal and the input DC voltage V in The negative terminal is connected to form power ground; its gate is driven by the OUTA pin of the main control chip; capacitor C c One end is connected to the non-identical terminal of transformer T1, and the other end is connected to the drain of switching transistor S2. The source of switching transistor S2 is connected to the power ground terminal, and its gate is driven by the OUTB pin of the main control chip.

3. The soft-switching high-gain DC-DC topology circuit according to claim 1, characterized in that, The structure b of the switching module consists of switching transistors S1 and S2, and capacitor C. c It consists of a transformer T1, and the specific connection method is as follows: the drain of switch S1 is connected to the non-same-name terminal of the primary winding of transformer T1, and its source is connected to the input filter capacitor C. in The negative terminal and the input DC voltage V in The negative terminal is connected to form power ground; its gate is driven by the OUTA pin of the main control chip; capacitor C c One end is connected to the same-name terminal of transformer T1, and the other end is connected to the drain of switching transistor S2. The source of switching transistor S2 is connected to the non-same-name terminal of transformer, and its gate is driven by the OUTB pin of the main control chip.

4. The soft-switching high-gain DC-DC topology circuit according to claim 1, characterized in that, The structure c of the switching module consists of switching transistors S1 and S2, and capacitor C. r1 C r2 It consists of a transformer T1, and the specific connection method is as follows: the drain of switch S1 is connected to capacitor C. r1 One end of the capacitor has its source connected to the drain of switch S2 and the same-name terminal of the primary winding of transformer T1, and its gate is driven by the OUTA pin of the main control chip; capacitor C r1 The other end is connected to the non-identical terminal of transformer T1; the source of switch S2 is connected to the resonant capacitor C. r2 One end is connected to form power ground; its gate is driven by the OUTB pin of the main control chip; capacitor C r2 The other end is connected to the non-identical end of transformer T1.

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