High-voltage difference bidirectional level conversion circuit

Abstract

This invention discloses a high-voltage differential bidirectional level conversion circuit. In this circuit, resistor R1 is connected to VCC_H; R1 is connected to the source (S) of FET1, the anode of D1, and SDA_H; the cathode of D1 is connected to the gate (G) of FET1, R2, and the drain (D) of FET3; the source (S) of FET3 is connected to R5 and GND_H; the gate (G) of FET3 is connected to R5 and R12; the drain (D) of FET1 is connected to R3; R2 is connected to capacitor C1, R4, the source (S) of FET2, and VCC_H; the anode of D1 is connected to R6; R7 is connected to... VCC_L is connected; R7 is connected to the source (S) of MOSFET FET4, the anode of D2, and SDA_L; the cathode of D2 is connected to the gate (G) of FET4, R8, and the drain (D) of FET6; the gate (G) of FET6 is connected to R11 and R6; the drain (D) of FET4 is connected to the anode of ZD2; R9 is connected to the cathode of ZD2; R9 is connected to C2, R10, and the gate (G) of FET5; C2 is connected to R10, the source (S) of FET5, and VCC_H; the drain (D) of FET5 is connected to R12. This invention features a simple circuit structure, small board area, and low power consumption.

Description

Technical Field

[0001] This invention relates to the field of signal input control electronic circuits, and more specifically, to a high voltage differential bidirectional level conversion circuit. Background Technology

[0002] Signal level conversion circuits are a crucial component in various electronic products, enabling the conversion of logic levels across different applications based on their specific characteristics. For instance, when a high-voltage section needs to control a low-voltage module, signal conversion from high-voltage to low-voltage is required; conversely, when a low-voltage module needs to send information to a high-voltage section, signal conversion from low-voltage to high-voltage is necessary. During application, power consumption, speed, stability, and cost become unavoidable design challenges.

[0003] Currently, high voltage differential conversion circuits typically use two level converters, performing the conversion twice; or they use dedicated isolation chips, requiring two sets of isolated power supplies. This results in complex circuit structures, large board space, high power consumption, and high cost. Because the power consumption of the high and low voltage ends differs due to the need for two isolated power supplies, this method is generally not recommended in applications with high power balance requirements (e.g., BMS). Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide a high voltage differential bidirectional level conversion circuit.

[0005] This invention discloses a high-voltage differential bidirectional level conversion circuit, comprising 12 resistors, 2 capacitors, 4 diodes, and 6 MOSFETs. One end of resistor R1 is connected to the high-voltage power supply terminal VCC_H; the other end of R1 is connected to the source (S) of N-channel MOSFET FET1, the anode of switching diode D1, and to the high-voltage signal input / output terminal SDA_H. The cathode of switching diode D1 is connected to the gate (G) of FET1, one end of resistor R2, and the drain (D) of N-channel MOSFET FET3. The source (S) of N-channel MOSFET FET3 is connected to one end of resistor R5 and to the high-voltage reference level GN. D_H connection; the gate (G) of N-channel MOSFET FET3 is connected to the other end of resistor R5 and one end of resistor R12; the drain (D) of N-channel MOSFET FET1 is connected to one end of resistor R3; the other end of resistor R2 is connected to one end of capacitor C1, one end of resistor R4, and the source (S) of P-channel MOSFET FET2, and is connected to the high-voltage power supply terminal VCC_H; the other end of resistor R3 is connected to the other end of capacitor C1, the other end of resistor R4, and the gate (G) of P-channel MOSFET FET2; the drain (D) of P-channel MOSFET FET2 is connected to the cathode of Zener diode ZD1; Zener diode ZD1... The anode is connected to one end of resistor R6; one end of resistor R7 is connected to the low-voltage power supply terminal VCC_L; the other end of resistor R7 is connected to the source (S) of MOSFET 4, the anode of switching diode D2, and to the low-voltage signal input / output terminal SDA_L; the cathode of switching diode D2 is connected to the gate (G) of N-channel MOSFET FET4, one end of resistor R8, and the drain (D) of N-channel MOSFET FET6; the other end of resistor R8 is connected to the low-voltage power supply terminal VCC_L; the source (S) of N-channel MOSFET FET6 is connected to one end of resistor R11 and to the low-voltage reference level GND_L; N-channel... The gate (G) of N-channel MOSFET FET6 is connected to the other end of resistor R11 and the other end of resistor R6; the drain (D) of N-channel MOSFET FET4 is connected to the anode of Zener diode ZD2; one end of resistor R9 is connected to the cathode of Zener diode ZD2; the other end of resistor R9 is connected to one end of capacitor C2, one end of resistor R10, and the gate (G) of P-channel MOSFET FET5; the other end of capacitor C2 is connected to the other end of resistor R10, the source (S) of N-channel MOSFET FET5, and is connected to the high-voltage power supply terminal VCC_H; the drain (D) of N-channel MOSFET FET5 is connected to the other end of resistor R12.

[0006] In the circuit, R1 acts as a pull-up resistor, providing a high level and current limiting to the high-voltage input / output port; D1 is the high-voltage output signal control circuit, and its unidirectional conductivity cleverly controls the output level of the high-voltage side, unaffected by the input level; FET1 is the switch for the high-voltage input signal. With the cooperation of D1 and R2, the high-voltage input level can control the opening or closing of FET1, and the opening or closing of FET1 is unaffected by the high-voltage output level; R2 is the pull-up resistor for FET1, providing the drive voltage; R3 and R4 form a voltage divider circuit to provide a suitable drive voltage for FET2. R4 also acts as a pull-up resistor for FET2, allowing FET1 to... T2's operating point is more stable; C1 is a bypass capacitor, serving to filter out noise and smooth delay; FET2 is a level-shifting MOSFET, which, with the cooperation of FET1, R2, R3, C1, and R4, converts the high-voltage input level into an inverted low-voltage differential level; ZD1 is a Zener diode, which converts the high-voltage differential level into a normal signal level; R6 and R11 form a voltage divider circuit to provide a suitable drive voltage for FET6, and R11 also acts as a pull-down resistor for FET6, making the operating point of FET6 more stable; FET6 is a level-shifting MOSFET, which, with the cooperation of ZD1, R6, and R11, converts the low-voltage differential level into an inverted normal signal level; R7 acts as... R1 is a pull-up resistor that provides a high level and current limiting to the low-voltage input / output ports. D2 is the low-voltage output signal control circuit; the unidirectional conductivity of D1 cleverly controls the output level of the low-voltage side, unaffected by the input level. FET4 is the low-voltage input signal switch; with the cooperation of D2 and R8, the low-voltage input level can control the opening or closing of FET4, and the opening or closing of FET4 is unaffected by the low-voltage output level. R8 is the pull-up resistor driving FET4, providing the driving voltage. ZD2 is a Zener diode, which converts the high voltage difference level of the low-voltage side into the normal signal level of the high-voltage side. R9 and R10 act as a voltage divider circuit to provide a high voltage level to FET5. R10 provides a suitable drive voltage and also acts as a pull-up resistor for FET5, making the operating point of FET5 more stable. C2 is a bypass capacitor, which filters out noise and smooths the delay. FET5 is a level-shifting MOSFET. With the cooperation of FET4, R8, ZD2, R9, R10, and C2, the low-voltage input level is converted into the inverted normal signal level of the high-voltage side. R5 and R12 act as a voltage divider circuit to provide a suitable drive voltage for FET3. R5 also acts as a pull-down resistor for FET3, making the operating point of FET3 more stable. FET3 is a level-shifting MOSFET. With the cooperation of R5 and R12, the normal signal level of the high-voltage side is converted into the inverted normal signal level.

[0007] Idle State (Power-On): With the voltage difference between the high-voltage and low-voltage sides set to 45V, the voltage regulation parameters of Zener diodes ZD1 and ZD2 are selected as 45V. The idle state signal level at the high-voltage side input / output port is high. The high level defaults to VCC_H, and is turned on by the parasitic diode of FET1. Then, through R3 and R4, it reaches the gate (G) of FET2. The source (S) of FET2 is also directly connected to VCC_H, so VGS of FET2 is 0V, and FET2 is in the off state. The low-voltage drive voltage provided by FET2 is 0V, so ZD1 cannot conduct. After passing through R6 and R11, VGS of FET6 is also 0V, and FET6 is in the off state. The off state of FET6 does not affect the high / low level of the low-voltage input / output port. Similarly, the idle state signal level of the low-voltage input / output port is high. This high level defaults to VCC_L, and then conducts through the parasitic diode of FET4 to the anode of ZD2. The cathode of ZD2 is connected to VCC_H through R9 and R10. ZD2 does not conduct unless the voltage across it reaches 45V. VCC_H is supplied to the gate (G) of FET5 through R10, and the source (S) of FET5 is also directly connected to VCC_H. Therefore, the VGS of FET5 is 0V, and FET5 is off. The high-voltage drive voltage provided by FET5 is 0V. After passing through R5 and R12, the VGS of FET3 is also 0V, and FET3 is off. The off state of FET3 does not affect the high / low level of the high-voltage input / output port. Thus, in the idle state, both the high and low voltage input / output port levels are high and do not affect each other.

[0008] High-voltage input state (level from high to low): When the high-voltage input level decreases from high to low, the source (S) of FET1 is GND_H, while the gate (G) of FET1 is VCC_H due to the pull-up of R2. Therefore, the VGS of FET1 is high at 3.3V, and FET1 is turned on. The level at one end of R3 is GND_H. Through the voltage divider of R3 and R4, the VGS of FET2 is slightly lower than 3.3V, and FET2 is turned on. The cathode of ZD1 is VCC_H, and the voltage difference across ZD1 exceeds 45V, so the entire circuit is closed. After the voltage divider driven by R6 and R11, the VGS of FET6 is high at 3.3V, and FET6 is turned on. The low-voltage output port is pulled low to GND_L by FET6 through D2, and the low-voltage output level changes from high to low. Due to the unidirectional conduction characteristic of D2, the voltage difference between the cathode and anode of D2 is very small at this time, around 0.3V, that is, the VGS of FET4 is 0.3V, and FET4 is not turned on. With ZD2's anode floating, FET5 has no driving voltage, and FET5's VGS is low (0V), meaning FET5 is in an off state. The high-voltage drive voltage provided by FET5 is 0V. After passing through R5 and R12, FET3's VGS also becomes 0V, meaning FET3 is in an off state. The off state of FET3 does not affect the high / low level of the high-voltage input / output ports. Therefore, when the high-voltage input level changes from high to low, the low-voltage output level also changes accordingly from high to low, and the change in the low-voltage output level does not affect the high-voltage input level.

[0009] High-voltage input state (level from low to high): When the high-voltage input level changes from low to high, the source (S) of FET1 is VCC_H, and the gate (G) of FET1 is also VCC_H due to the pull-up resistor R2. Therefore, the VGS of FET1 is low (0V), and FET1 is in the off state. The high level is turned on through the parasitic diode of FET1, and then through R3 and R4 to the gate (G) of FET2. The source (S) of FET2 is also directly connected to VCC_H, so the VGS of FET2 is 0V, and FET2 is in the off state. The low-voltage drive voltage provided by FET2 is 0V, ZD1 cannot conduct, and after passing through R6 and R11, the VGS of FET6 is also 0V, and FET6 is in the off state. Since the low-voltage output level is in the off state, FET6 is not pulled to GND_L, but is pulled up to VCC_L by the pull-up resistor R7, and the low-voltage output level changes from low to low-high. The source (S) and gate (G) of FET4 are both high (VCC_L), and the voltage across FET4 is low (0V), meaning FET4 is off. The high voltage level conducts through the parasitic diode of FET4 to the anode of ZD2. The cathode of ZD2 is connected to VCC_H via resistors R9 and R10. ZD2 does not conduct unless the voltage across it reaches 45V. VCC_H flows through R10 to the gate (G) of FET5, and the source (S) of FET5 is also directly connected to VCC_H, so FET5's voltage across FET5 is 0V, meaning FET5 is off. The high-voltage drive voltage provided by FET5 is 0V. After passing through resistors R5 and R12, the voltage across FET3 is also 0V, meaning FET3 is off. The off state of FET3 does not affect the high / low level of the high-voltage input / output ports. Therefore, as the high-voltage input level changes from low to high, the low-voltage output level also changes accordingly from low to high, and the change in the low-voltage output level does not affect the high-voltage input level.

[0010] Low-voltage input state (level from high to low): When the low-voltage input level changes from high to low, the source (S) of FET4 is GND_L, and the gate (G) of FET4 is VCC_L due to the pull-up of R8. Therefore, the VGS of FET4 is high at 3.3V, and FET4 is turned on. The anode of ZD2 is GND_L, and the cathode of ZD2 is connected to VCC_H through R10 and R9. The initial level of the cathode of ZD2 is VCC_H. The voltage across ZD2 exceeds 45V, so it is turned on. After the driving voltage is divided by R10 and R9, the VGS of FET5 is 3.3V, and FET5 is turned on. After the driving voltage of FET3 is divided by R12 and R5, the VGS of FET3 is 3.3V, and FET3 is turned on. The high-voltage output port is pulled low to GND_H by FET3 through D1, and the high-voltage output level changes from high to low. Due to the unidirectional conduction characteristic of D1, the voltage difference between the anode and cathode of D1 is very small, around 0.3V, meaning that the VGS of FET1 is 0.3V, and FET1 is not conducting. The drain of FET1 is pulled up to VCC_H through R4 and R3. FET2 has no driving voltage, and its VGS is low (0V), so FET2 is in the off state. The high-voltage driving voltage provided by FET2 is 0V. After passing through ZD1, R6, and R11, the VGS of FET6 also becomes 0V, so FET6 is in the off state. The off state of FET6 does not affect the high or low level of the low-voltage input / output port. Thus, when the low-voltage input level changes from high to low, the high-voltage output level also changes accordingly from high to low, and the change in the high-voltage output level does not affect the level of the low-voltage input port.

[0011] Low-voltage input state (level from low to high): When the low-voltage input level changes from low to high, the source (S) of FET4 is VCC_L, and the gate (G) of FET4 is VCC_L due to the pull-up of R2. Therefore, the VGS of FET4 is low (0V), and FET4 is in the off state. When the level is high, it conducts through the parasitic diode of FET4. The anode of ZD2 is VCC_H, and the cathode of ZD2 is connected to VCC_H through R10 and R9. ZD2 does not conduct unless the voltage across it reaches 45V. VCC_H is supplied to the gate (G) of FET5 through R10, and the source (S) of FET5 is also directly connected to VCC_H. Therefore, the VGS of FET5 is 0V, and FET5 is in the off state. The high-voltage drive voltage provided by FET5 is 0V. After passing through R5 and R12, the VGS of FET3 is also 0V, and FET3 is in the off state. Since FET3 is in the off state, the high-voltage output level is not pulled to GND_H, but is pulled up to VCC_H by pull-up resistor R1, causing the high-voltage output level to change from low to low-high. The source (S) and gate (G) of FET1 are both high (VCC_H), and FET1's voltage level (VGS) is low (0V), meaning FET1 is off. The high voltage level is turned on by the parasitic diode of FET1, then passes through R3 and R4 to the gate (G) of FET2. Since the source (S) of FET2 is also directly connected to VCC_H, FET2's voltage level (VGS) is 0V, meaning FET2 is off. The low-voltage drive voltage provided by FET2 is 0V, so ZD1 cannot conduct. After passing through R6 and R11, FET6's voltage level (VGS) is also 0V, meaning FET6 is off. The off state of FET6 does not affect the high or low state of the low-voltage input / output port. Thus, when the low-voltage input state level changes from low to high, the high-voltage output state level also changes from low to high accordingly, and the change in the high-voltage output port level does not affect the level of the low-voltage input port.

[0012] The present invention has the following beneficial effects:

[0013] The method of this invention eliminates the need for two level converters or dedicated isolation chips; it also eliminates the need for two sets of isolated power supplies, using a limited set of conventional electronic components to achieve effective high voltage difference level conversion. This circuit features a pure hardware structure, low power consumption, high speed, good compatibility, strong anti-interference capability, low cost, high portability, and a short development cycle.

[0014] This method achieves high voltage differential level conversion using simple combinations of resistors, capacitors, transistors, and field-effect transistors, eliminating the need for multiple isolation power supplies and dedicated isolation ICs. It utilizes conventional resistors, capacitors, and semiconductor devices. The circuit structure is simple, requires a small board area, has low power consumption, and can respond quickly and stably to digital level signals. As a purely hardware structure, it effectively shortens debugging time. The minimal component combination results in a very low failure rate, leading to reliable operation, long lifespan, fast response, strong anti-interference capability, low cost, and a short development cycle. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the high voltage differential bidirectional level conversion circuit of the present invention;

[0016] Figure 2 This is a circuit parameter diagram of an embodiment;

[0017] Figure 3 This is a diagram showing the transformation of the high-voltage input and low-voltage output signals.

[0018] Figure 4 It is a diagram showing the transformation of the input signal at the low-voltage end and the output signal at the high-voltage end. Detailed Implementation

[0019] The invention will now be further described with reference to the accompanying drawings.

[0020] like Figure 1As shown, the circuit of this invention includes 12 resistors, 2 capacitors, 4 diodes, and 6 MOSFETs; one end of resistor R1 is connected to the high-voltage power supply terminal VCC_H; the other end of R1 is connected to the source (S) of N-channel MOSFET FET1, the anode of switching diode D1, and the high-voltage signal input / output terminal SDA_H; the cathode of switching diode D1 is connected to the gate (G) of FET1, one end of resistor R2, and the drain (D) of N-channel MOSFET FET3; the source (S) of N-channel MOSFET FET3 is connected to one end of resistor R5 and to the high-voltage reference level GND_H; N-channel... The gate (G) of N-channel MOSFET FET3 is connected to the other end of resistor R5 and one end of resistor R12; the drain (D) of N-channel MOSFET FET1 is connected to one end of resistor R3; the other end of resistor R2 is connected to one end of capacitor C1, one end of resistor R4, and the source (S) of P-channel MOSFET FET2, and is connected to the high-voltage power supply terminal VCC_H; the other end of resistor R3 is connected to the other end of capacitor C1, the other end of resistor R4, and the gate (G) of P-channel MOSFET FET2; the drain (D) of P-channel MOSFET FET2 is connected to the cathode of Zener diode ZD1; the anode of Zener diode ZD1 is connected to resistor R... One end of resistor R6 is connected; one end of resistor R7 is connected to the low-voltage power supply terminal VCC_L; the other end of resistor R7 is connected to the source (S) of MOSFET 4, the anode of switching diode D2, and to the low-voltage signal input / output terminal SDA_L; the cathode of switching diode D2 is connected to the gate (G) of N-channel MOSFET 4, one end of resistor R8, and the drain (D) of N-channel MOSFET 6; the other end of resistor R8 is connected to the low-voltage power supply terminal VCC_L; the source (S) of N-channel MOSFET 6 is connected to one end of resistor R11 and to the low-voltage reference level GND_L; N-channel MOSFET 4... The gate (G) of S-channel MOSFET FET6 is connected to the other end of resistor R11 and the other end of resistor R6; the drain (D) of N-channel MOSFET FET4 is connected to the anode of Zener diode ZD2; one end of resistor R9 is connected to the cathode of Zener diode ZD2; the other end of resistor R9 is connected to one end of capacitor C2, one end of resistor R10, and the gate (G) of P-channel MOSFET FET5; the other end of capacitor C2 is connected to the other end of resistor R10, the source (S) of N-channel MOSFET FET5, and is connected to the high-voltage power supply terminal VCC_H; the drain (D) of N-channel MOSFET FET5 is connected to the other end of resistor R12.

[0021] In the circuit, R1 acts as a pull-up resistor, providing a high level and current limiting to the high-voltage input / output port; D1 is the high-voltage output signal control circuit, and its unidirectional conductivity cleverly controls the output level of the high-voltage side, unaffected by the input level; FET1 is the switch for the high-voltage input signal. With the cooperation of D1 and R2, the high-voltage input level can control the opening or closing of FET1, and the opening or closing of FET1 is unaffected by the high-voltage output level; R2 is the pull-up resistor for FET1, providing the drive voltage; R3 and R4 form a voltage divider circuit to provide a suitable drive voltage for FET2. R4 also acts as a pull-up resistor for FET2, allowing FET1 to... T2's operating point is more stable; C1 is a bypass capacitor, serving to filter out noise and smooth delay; FET2 is a level-shifting MOSFET, which, with the cooperation of FET1, R2, R3, C1, and R4, converts the high-voltage input level into an inverted low-voltage differential level; ZD1 is a Zener diode, which converts the high-voltage differential level into a normal signal level; R6 and R11 form a voltage divider circuit to provide a suitable drive voltage for FET6, and R11 also acts as a pull-down resistor for FET6, making the operating point of FET6 more stable; FET6 is a level-shifting MOSFET, which, with the cooperation of ZD1, R6, and R11, converts the low-voltage differential level into an inverted normal signal level; R7 acts as... R1 is a pull-up resistor that provides a high level and current limiting to the low-voltage input / output ports. D2 is the low-voltage output signal control circuit; the unidirectional conductivity of D1 cleverly controls the output level of the low-voltage side, unaffected by the input level. FET4 is the low-voltage input signal switch; with the cooperation of D2 and R8, the low-voltage input level can control the opening or closing of FET4, and the opening or closing of FET4 is unaffected by the low-voltage output level. R8 is the pull-up resistor driving FET4, providing the driving voltage. ZD2 is a Zener diode, which converts the high voltage difference level of the low-voltage side into the normal signal level of the high-voltage side. R9 and R10 act as a voltage divider circuit to provide a high voltage level to FET5. R10 provides a suitable drive voltage and also acts as a pull-up resistor for FET5, making the operating point of FET5 more stable. C2 is a bypass capacitor, which filters out noise and smooths the delay. FET5 is a level-shifting MOSFET. With the cooperation of FET4, R8, ZD2, R9, R10, and C2, the low-voltage input level is converted into the inverted normal signal level of the high-voltage side. R5 and R12 act as a voltage divider circuit to provide a suitable drive voltage for FET3. R5 also acts as a pull-down resistor for FET3, making the operating point of FET3 more stable. FET3 is a level-shifting MOSFET. With the cooperation of R5 and R12, the normal signal level of the high-voltage side is converted into the inverted normal signal level.

[0022] Idle state (power-on): with Figure 2Taking an example, if the voltage difference between the high-voltage and low-voltage sides is set to 45V, then the voltage regulation parameters of Zener diodes ZD1 and ZD2 are selected as 45V. In the idle state, the high-voltage side signal input / output port has a high signal level. This high level, by default, reaches VCC_H. The high level is turned on by the parasitic diode of FET1, and then passes through R3 and R4 to the gate (G) of FET2. The source (S) of FET2 is also directly connected to VCC_H, so FET2's VGS is 0V, and FET2 is in an off state. The low-voltage side drive voltage provided by FET2 is 0V, so ZD1 cannot conduct. After passing through R6 and R11, FET6's VGS also becomes 0V, and FET6 is in an off state. The off state of FET6 does not affect the high / low level of the low-voltage input / output port. Similarly, the idle state signal level of the low-voltage input / output port is high. This high level defaults to VCC_L, and then conducts through the parasitic diode of FET4 to the anode of ZD2. The cathode of ZD2 is connected to VCC_H through R9 and R10. ZD2 does not conduct unless the voltage across it reaches 45V. VCC_H is supplied to the gate (G) of FET5 through R10, and the source (S) of FET5 is also directly connected to VCC_H. Therefore, the VGS of FET5 is 0V, and FET5 is off. The high-voltage drive voltage provided by FET5 is 0V. After passing through R5 and R12, the VGS of FET3 is also 0V, and FET3 is off. The off state of FET3 does not affect the high / low level of the high-voltage input / output port. Thus, in the idle state, both the high and low voltage input / output port levels are high and do not affect each other.

[0023] High-voltage input status (level from high to low): [Information on high-voltage input status is missing from the original text] Figure 3For example: When the high-voltage input level decreases from high to low, the source (S) of FET1 is GND_H, while the gate (G) of FET1 is VCC_H due to the pull-up of R2. Therefore, the VGS of FET1 is high at 3.3V, and FET1 is turned on. The voltage at one end of R3 is GND_H. Through the voltage divider of R3 and R4, the VGS of FET2 is slightly lower than 3.3V, and FET2 is turned on. The cathode of ZD1 is VCC_H, and the voltage difference across ZD1 exceeds 45V, so the entire circuit is closed. After the voltage divider of R6 and R11, the VGS of FET6 is high at 3.3V, and FET6 is turned on. The low-voltage output is pulled low to GND_L by FET6 through D2, and the low-voltage output level changes from high to low. Due to the unidirectional conduction characteristic of D2, the voltage difference between the cathode and anode of D2 is very small at this time, around 0.3V, meaning the VGS of FET4 is 0.3V, and FET4 is not turned on. With ZD2's anode floating, FET5 has no driving voltage, and FET5's VGS is low (0V), meaning FET5 is in an off state. The high-voltage drive voltage provided by FET5 is 0V. After passing through R5 and R12, FET3's VGS also becomes 0V, meaning FET3 is in an off state. The off state of FET3 does not affect the high / low level of the high-voltage input / output ports. Therefore, when the high-voltage input level changes from high to low, the low-voltage output level also changes accordingly from high to low, and the change in the low-voltage output level does not affect the high-voltage input level.

[0024] High-voltage input status (level from low to high): [Information on high-voltage input status is missing from the original text] Figure 3For example, when the high-voltage input level changes from low to high, the source (S) of FET1 is VCC_H, and the gate (G) of FET1 is also VCC_H due to the pull-up resistor R2. Therefore, the VGS of FET1 is low (0V), and FET1 is in an off state. The high level is turned on through the parasitic diode of FET1, and then through R3 and R4 to the gate (G) of FET2. The source (S) of FET2 is also directly connected to VCC_H, so the VGS of FET2 is 0V, and FET2 is in an off state. The low-voltage drive voltage provided by FET2 is 0V, ZD1 cannot conduct, and after passing through R6 and R11, the VGS of FET6 is also 0V, and FET6 is in an off state. Since the low-voltage output level is in an off state, FET6 is not pulled to GND_L, but is pulled up to VCC_L by the pull-up resistor R7, and the low-voltage output level changes from low to low-high. The source (S) and gate (G) of FET4 are both high (VCC_L), and the voltage across FET4 is low (0V), meaning FET4 is off. The high voltage level conducts through the parasitic diode of FET4 to the anode of ZD2. The cathode of ZD2 is connected to VCC_H via resistors R9 and R10. ZD2 does not conduct unless the voltage across it reaches 45V. VCC_H flows through R10 to the gate (G) of FET5, and the source (S) of FET5 is also directly connected to VCC_H, so FET5's voltage across FET5 is 0V, meaning FET5 is off. The high-voltage drive voltage provided by FET5 is 0V. After passing through resistors R5 and R12, the voltage across FET3 is also 0V, meaning FET3 is off. The off state of FET3 does not affect the high / low level of the high-voltage input / output ports. Therefore, as the high-voltage input level changes from low to high, the low-voltage output level also changes accordingly from low to high, and the change in the low-voltage output level does not affect the high-voltage input level.

[0025] Low-voltage input state (level from high to low): Figure 4For example: When the low-voltage input level changes from high to low, the source (S) of FET4 is GND_L, and the gate (G) of FET4 is VCC_L due to the pull-up of R8. Therefore, the VGS of FET4 is high at 3.3V, and FET4 is turned on. The anode of ZD2 is GND_L, and the cathode of ZD2 is connected to VCC_H through R10 and R9. The initial level of the cathode of ZD2 is VCC_H. The voltage across ZD2 exceeds 45V, so it is turned on. After the driving voltage is divided by R10 and R9, the VGS of FET5 is 3.3V, and FET5 is turned on. After the driving voltage of FET3 is divided by R12 and R5, the VGS of FET3 is 3.3V, and FET3 is turned on. The high-voltage output is pulled low to GND_H by FET3 through D1, and the high-voltage output level changes from high to low. Due to the unidirectional conduction characteristic of D1, the voltage difference between the anode and cathode of D1 is very small, around 0.3V, meaning that the VGS of FET1 is 0.3V, and FET1 is not conducting. The drain of FET1 is pulled up to VCC_H through R4 and R3. FET2 has no driving voltage, and its VGS is low (0V), so FET2 is in the off state. The high-voltage driving voltage provided by FET2 is 0V. After passing through ZD1, R6, and R11, the VGS of FET6 also becomes 0V, so FET6 is in the off state. The off state of FET6 does not affect the high or low level of the low-voltage input / output port. Thus, when the low-voltage input level changes from high to low, the high-voltage output level also changes accordingly from high to low, and the change in the high-voltage output level does not affect the level of the low-voltage input port.

[0026] Low-voltage input state (level from low to high): Figure 4For example: When the low-voltage input level changes from low to high, the source (S) of FET4 is VCC_L, and the gate (G) of FET4 is also VCC_L due to the pull-up resistor R2. Therefore, the VGS of FET4 is low (0V), and FET4 is in the off state. When the high level changes, the parasitic diode of FET4 conducts, the anode of ZD2 is VCC_H, and the cathode of ZD2 is connected to VCC_H via R10 and R9. ZD2 does not conduct until the voltage across it reaches 45V. VCC_H is supplied to the gate (G) of FET5 via R10, and the source (S) of FET5 is also directly connected to VCC_H. Therefore, the VGS of FET5 is 0V, and FET5 is in the off state. The high-voltage drive voltage provided by FET5 is 0V. After passing through R5 and R12, the VGS of FET3 is also 0V, and FET3 is in the off state. Since FET3 is in the off state, the high-voltage output level is not pulled to GND_H, but is pulled up to VCC_H by pull-up resistor R1, causing the high-voltage output level to change from low to low-high. The source (S) and gate (G) of FET1 are both high (VCC_H), and FET1's voltage level (VGS) is low (0V), meaning FET1 is off. The high voltage level is turned on by the parasitic diode of FET1, then passes through R3 and R4 to the gate (G) of FET2. Since the source (S) of FET2 is also directly connected to VCC_H, FET2's voltage level (VGS) is 0V, meaning FET2 is off. The low-voltage drive voltage provided by FET2 is 0V, so ZD1 cannot conduct. After passing through R6 and R11, FET6's voltage level (VGS) is also 0V, meaning FET6 is off. The off state of FET6 does not affect the high or low state of the low-voltage input / output port. Thus, when the low-voltage input state level changes from low to high, the high-voltage output state level also changes from low to high accordingly, and the change in the high-voltage output port level does not affect the level of the low-voltage input port.

[0027] From the initial power-on state where both the high-voltage and low-voltage terminals are idle at a high level, to the point where a digital level signal is sent as input from either the high-voltage or low-voltage terminal, the corresponding low-voltage output or the corresponding high-voltage output can be quickly, accurately, and stably converted to the corresponding digital level signal.

[0028] This invention operates using a simple combination of resistors, capacitors, transistors, and MOSFETs, achieving high voltage differential level conversion without requiring multiple isolated power supplies or dedicated isolation ICs. Furthermore, by adjusting the voltage regulation parameters of the Zener diode, it can quickly and easily adapt to different high voltage differential parameter environments, exhibiting excellent compatibility. The clever use of the Zener diode allows the circuit to operate in a switching state between conduction and cutoff, resulting in ultra-low power consumption. Simultaneously, utilizing the unidirectional conduction characteristic of semiconductors in conjunction with the conduction threshold of the MOSFET enables bidirectional level conversion without interference. This circuit is a purely hardware structure, effectively shortening debugging time. The limited number of components results in extremely low failure rates, leading to a small board area, reliable operation, long lifespan, fast response, strong anti-interference capability, low cost, and short development cycle.

Claims

1. A high-voltage differential bidirectional level conversion circuit, characterized in that, One end of resistor R1 is connected to the high-voltage power supply terminal VCC_H; the other end of R1 is connected to the source (S) of N-channel MOSFET FET1, the anode of switching diode D1, and the high-voltage signal input / output terminal SDA_H; the cathode of switching diode D1 is connected to the gate (G) of FET1, one end of resistor R2, and the drain (D) of N-channel MOSFET FET3; the source (S) of N-channel MOSFET FET3 is connected to one end of resistor R5 and to the high-voltage reference level GND_H; the gate (G) of N-channel MOSFET FET3 is connected to the other end of resistor R5 and resistor R12... One end is connected; the drain (D) of the N-channel MOSFET FET1 is connected to one end of resistor R3; the other end of resistor R2 is connected to one end of capacitor C1, one end of resistor R4, and the source (S) of the P-channel MOSFET FET2, and is connected to the high-voltage power supply terminal VCC_H; the other end of resistor R3 is connected to the other end of capacitor C1, the other end of resistor R4, and the gate (G) of the P-channel MOSFET FET2; the drain (D) of the P-channel MOSFET FET2 is connected to the cathode of Zener diode ZD1; the anode of Zener diode ZD1 is connected to one end of resistor R6; one end of resistor R7 is connected to the low-voltage power supply terminal VCC_H. The power supply terminal VCC_L is connected; the other end of resistor R7 is connected to the source (S) of MOSFET 4, the anode of switching diode D2, and the low-voltage signal input / output terminal SDA_L; the cathode of switching diode D2 is connected to the gate (G) of N-channel MOSFET FET4, one end of resistor R8, and the drain (D) of N-channel MOSFET FET6; the other end of resistor R8 is connected to the low-voltage power supply terminal VCC_L; the source (S) of N-channel MOSFET FET6 is connected to one end of resistor R11 and to the low-voltage reference level GND_L; the gate (G) of N-channel MOSFET FET6... The other end of resistor R11 and the other end of resistor R6 are connected; the drain of N-channel MOSFET FET4 is connected to the anode of Zener diode ZD2; one end of resistor R9 is connected to the cathode of Zener diode ZD2; the other end of resistor R9 is connected to one end of capacitor C2, one end of resistor R10, and the gate of P-channel MOSFET FET5; the other end of capacitor C2 is connected to the other end of resistor R10, the source of N-channel MOSFET FET5, and connected to the high-voltage power supply terminal VCC_H; the drain of N-channel MOSFET FET5 is connected to the other end of resistor R12.

2. The high voltage differential bidirectional level conversion circuit according to claim 1, characterized in that, In the circuit, R1 acts as a pull-up resistor, providing a high level and current limiting to the high-voltage input / output port; D1 is the high-voltage output signal control circuit. D1's unidirectional conductivity cleverly controls the output level of the high-voltage side, unaffected by the input level; FET1 is the high-voltage input signal switch. With the cooperation of D1 and R2, the high-voltage input level can control the opening or closing of FET1, and the opening or closing of FET1 is unaffected by the high-voltage output level. R2 is the pull-up resistor for FET1, providing the drive voltage; R3 and R4 form a voltage divider circuit to provide a suitable drive voltage for FET2. R4 also acts as a pull-up resistor for FET2, making the operating point of FET2 more stable; C1 is a bypass capacitor, which filters out noise and smooths the delay; FET2 is a level-shifting MOSFET. With the cooperation of FET1, R2, R3, C1, and R4, the high-voltage input level is converted into an inverted low-voltage differential level. ZD1 is a Zener diode, which converts the high voltage difference level into a normal signal level; R6 and R11 form a voltage divider circuit to provide a suitable drive voltage for FET6. R11 also acts as a pull-down resistor for FET6, making the operating point of FET6 more stable; FET6 is a level-shifting MOSFET. With the cooperation of ZD1, R6, and R11, the high voltage difference level at the low voltage side is converted into an inverted normal signal level; R7 acts as a pull-up resistor, providing a high level to the low voltage side signal input / output port and limiting current. D2 is the low-voltage output signal control circuit. The unidirectional conductivity of D1 cleverly controls the output level of the low-voltage side without being affected by the input level of the low-voltage side. FET4 is the switch for the input signal of the low-voltage side. With the cooperation of D2 and R8, the input level of the low-voltage side can control the opening or closing of FET4, and the opening or closing of FET4 is not affected by the output level of the low-voltage side. R8 is the pull-up resistor for FET4, providing the drive voltage; ZD2 is a Zener diode, which converts the high voltage difference level at the low voltage end into the normal signal level at the high voltage end; R9 and R10 form a voltage divider circuit to provide a suitable drive voltage for FET5, and R10 also acts as a pull-up resistor for FET5, making the operating point of FET5 more stable; C2 is a bypass capacitor, which filters out noise and smooths the delay; FET5 is a level-shifting MOSFET, which, with the cooperation of FET4, R8, ZD2, R9, R10, and C2, converts the low voltage input level into the inverted normal signal level at the high voltage end; R5 and R12 form a voltage divider circuit to provide a suitable drive voltage for FET3, and R5 also acts as a pull-down resistor for FET3, making the operating point of FET3 more stable; FET3 is a level-shifting MOSFET, which, with the cooperation of R5 and R12, converts the normal signal level at the high voltage end into the inverted normal signal level.

3. The high-voltage differential bidirectional level conversion circuit according to claim 1, characterized in that, In the idle state, the voltage difference between the high-voltage and low-voltage terminals is set to 45V. Therefore, the voltage regulation parameters of Zener diodes ZD1 and ZD2 are selected as 45V. The high-voltage input / output port signal level is high in the idle state. This high level, by default, reaches VCC_H. It conducts through the parasitic diode of FET1, then through resistors R3 and R4 to the gate (G) of FET2. Since the source (S) of FET2 is also directly connected to VCC_H, FET2's VGS is 0V, and FET2 is in an off state. The low-voltage drive voltage provided by FET2 is 0V, so ZD1 cannot conduct. After passing through resistors R6 and R11, FET6's VGS also becomes 0V, and FET6 is in an off state. The off state of FET6 does not affect the high or low state of the low-voltage input / output port signal level. Similarly, the low-voltage input / output port... In the idle state, the signal level is high. The high level defaults to VCC_L, and the high level conducts through the parasitic diode of FET4 to the anode of ZD2. The cathode of ZD2 is connected to VCC_H through R9 and R10. ZD2 does not conduct unless the voltage across it reaches 45V. VCC_H is supplied to the gate of FET5 through R10, and the source of FET5 is also directly connected to VCC_H. Therefore, the VGS of FET5 is 0V, and FET5 is in the off state. The high-voltage drive voltage provided by FET5 is 0V. After passing through R5 and R12, the VGS of FET3 is also 0V, and FET3 is in the off state. The off state of FET3 does not affect the high or low level of the high-voltage input / output port signal. Thus, in the idle state, the high and low voltage input / output port signal levels are both high and do not affect each other.

4. The high-voltage differential bidirectional level conversion circuit according to claim 1, characterized in that, When the voltage level changes from high to low, the high-voltage input state is as follows: The source (S) of FET1 is GND_H, while the gate (G) of FET1 is VCC_H due to the pull-up of R2. Therefore, the VGS of FET1 is high (3.3V), and FET1 is turned on. The voltage at one end of R3 is GND_H. Through the voltage divider of R3 and R4, the VGS of FET2 is slightly lower than 3.3V, and FET2 is turned on. The cathode of ZD1 is VCC_H, and the voltage difference across ZD1 exceeds 45V, so the entire circuit is closed. Driven by the voltage divider of R6 and R11, the VGS of FET6 is high (3.3V), and FET6 is turned on, and the low-voltage input... The output voltage is pulled low to GND_L by FET6 after passing through D2, and the low-voltage output level changes from high to low. Due to the unidirectional conduction characteristic of D2, the voltage difference between the anode and cathode of D2 is very small at this time, around 0.3V, that is, the VGS of FET4 is 0.3V, and FET4 is not conducting. The anode of D2 is floating, FET5 has no driving voltage, and the VGS of FET5 is low at 0V, so FET5 is in the off state. The high-voltage driving voltage provided by FET5 is 0V, and after passing through R5 and R12, the VGS of FET3 is also 0V, so FET3 is in the off state. The off state of FET3 does not affect the high or low level of the high-voltage signal input / output port. Thus, when the high-voltage input level changes from high to low, the low-voltage output level also changes accordingly from high to low, and the change in the low-voltage output level does not affect the level of the high-voltage input level.

5. The high-voltage differential bidirectional level conversion circuit according to claim 1, characterized in that, When the voltage level changes from low to high, the high-voltage input state is as follows: The source (S) of FET1 is VCC_H, and the gate (G) of FET1 is also VCC_H due to the pull-up resistor R2. Therefore, VGS of FET1 is low (0V), and FET1 is off. The high voltage level is turned on through the parasitic diode of FET1, and then through resistors R3 and R4 to the gate (G) of FET2. The source (S) of FET2 is also directly connected to VCC_H, so VGS of FET2 is 0V, and FET2 is off. The low-voltage drive voltage provided by FET2 is 0V, ZD1 cannot conduct, and after passing through resistors R6 and R11, VGS of FET6 is also 0V, and FET6 is off. Because FET6 is off, the low-voltage output level is not pulled to GND_L, but is pulled up to VCC_L by the pull-up resistor R7. The voltage output level changes from low to low-high; the source (S) of FET4 is high (VCC_L), and the gate (G) is also high (VCC_L). The voltage gate (VGS) of FET4 is low (0V), and FET4 is in the off state. The high voltage level conducts through the parasitic diode of FET4 to the anode of ZD2. The cathode of ZD2 is connected to VCC_H through R9 and R10. ZD2 is not conducting unless the voltage across it reaches 45V. VCC_H is supplied to the gate (G) of FET5 through R10. The source (S) of FET5 is also directly connected to VCC_H, so the voltage gate (VGS) of FET5 is 0V, and FET5 is in the off state. The high voltage driving voltage provided by FET5 is 0V. After passing through R5 and R12, the voltage gate (VGS) of FET3 is also 0V, and FET3 is in the off state. The off state of FET3 does not affect the high or low level of the high voltage input / output port. Thus, when the high-voltage input level changes from low to high, the low-voltage output level also changes accordingly from low to high, and the change in the low-voltage output level does not affect the level of the high-voltage input level.

6. The high voltage differential bidirectional level conversion circuit according to claim 1, characterized in that, When the voltage level changes from high to low, the low-voltage input state is as follows: The source (S) of FET4 is GND_L, and the gate (G) of FET4 is VCC_L due to the pull-up of R8. Therefore, the VGS of FET4 is high (3.3V), and FET4 is turned on. The anode of ZD2 is GND_L, and the cathode of ZD2 is connected to VCC_H through R10 and R9. The initial voltage level of the cathode of ZD2 is VCC_H. The voltage across ZD2 exceeds 45V, so it is turned on. After the driving voltage is divided by R10 and R9, the VGS of FET5 is 3.3V, and FET5 is turned on. After the driving voltage of FET3 is divided by R12 and R5, the VGS of FET3 is 3.3V, and FET3 is turned on. The high-voltage output is pulled low to GND_H by FET3 through D1, and the high-voltage output level changes from... The signal transitions from high to low. Due to the unidirectional conduction characteristic of D1, the voltage difference between the anode and cathode of D1 is very small, around 0.3V, meaning that the VGS of FET1 is 0.3V, and FET1 is not conducting. The drain of FET1 is pulled up to VCC_H through R4 and R3. FET2 has no driving voltage, and its VGS is low (0V), so FET2 is in the off state. The high-voltage driving voltage provided by FET2 is 0V. After passing through ZD1, R6, and R11, the VGS of FET6 is also 0V, so FET6 is in the off state. The off state of FET6 does not affect the high or low level of the low-voltage input / output port. Thus, when the low-voltage input level changes from high to low, the high-voltage output level also changes accordingly from high to low, and the change in the high-voltage output level does not affect the level of the low-voltage input port.

7. The high-voltage differential bidirectional level conversion circuit according to claim 1, characterized in that, When the voltage level changes from low to high, the input state at the low-voltage side is as follows: When the input voltage level changes from low to high, the source (S) of FET4 is VCC_L, and the gate (G) of FET4 is VCC_L due to the pull-up of R2. Therefore, the VGS of FET4 is low (0V), and FET4 is in the off state. The high-voltage side conducts through the parasitic diode of FET4. The anode of ZD2 is VCC_H, and the cathode of ZD2 is connected to VCC_H through R10 and R9. ZD2 does not conduct unless the voltage across it reaches 45V. VCC_H is supplied to the gate (G) of FET5 through R10, and the source (S) of FET5 is also directly connected to VCC_H. Therefore, the VGS of FET5 is 0V, and FET5 is in the off state. The high-voltage drive voltage provided by FET5 is 0V. After passing through R5 and R12, the VGS of FET3 is also 0V, and FET3 is in the off state. Because FET3 is in the off state, the high-voltage output level is not pulled to GND_H, but is pulled up by the voltage level. Resistor R1 pulls the voltage output level up to VCC_H, changing it from low to low-high. The source (S) and gate (G) of FET1 are both high (VCC_H), and FET1's voltage level (VGS) is low (0V), meaning FET1 is off. The high voltage level is then passed through the parasitic diode of FET1, and then through R3 and R4 to the gate (G) of FET2. Since the source (S) of FET2 is also directly connected to VCC_H, FET2's voltage level (VGS) is 0V, meaning FET2 is off. The low-voltage drive voltage provided by FET2 is 0V, so ZD1 cannot conduct. After passing through R6 and R11, FET6's voltage level (VGS) also becomes 0V, meaning FET6 is off. The off state of FET6 does not affect the high or low state of the low-voltage input / output ports. Therefore, as the low-voltage input level changes from low to high, the high-voltage output level also changes accordingly, and the change in the high-voltage output level does not affect the low-voltage input level.

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