Communication control methods and electronic devices for automotive Ethernet buses
By using a bus-type Ethernet bus and differential signal technology, the problems of low vehicle communication speed and numerous wiring harnesses were solved, achieving efficient and reliable vehicle communication.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-09
- Publication Date
- 2026-03-10
AI Technical Summary
Existing vehicle communication systems using CAN/LIN buses have low communication speeds, making it difficult to transmit image and video signals, and they require numerous wiring harnesses with complex layouts.
It adopts a bus-type Ethernet bus, uses 4-core signals to form 3 differential signals, and performs ID arbitration through timing control of differential signal lines to determine the transmission and reception timing, thereby realizing the transmission and reception of multiple differential signals and balancing the data transmission and reception of each node.
It improves vehicle communication speed, reduces the number of wiring harnesses, solves layout problems, and ensures communication reliability and efficiency.
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Figure CN116260671B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of vehicles, in particular to a communication control method of an Ethernet bus for a vehicle and an electronic device. BACKGROUND
[0002] At present, the vehicle-mounted network system mainly uses CAN (Controller Area Network) / LIN (Local Interconnect Network) bus, and the connection mode is to connect multiple nodes on one bus, for example, the functions of power train, body control, ADAS (Advanced Driving Assistance System) and the like in the vehicle are connected through the CAN bus and nodes for communication; the sunroof, doors, seats and the like are connected through the LIN communication bus and are connected to the CAN network through a gateway or a controller.
[0003] With the increasing requirement for communication rate, the application of vehicle-mounted Ethernet appears for transmitting signals such as images and videos, but the vehicle-mounted Ethernet is a point-to-point communication mode, and the main mode is as follows: the vehicle-mounted Ethernet is used as a backbone network to connect the core domain controllers together, such as power, ADAS, body, entertainment, and the like, and the gateway is converted into a CAN / LIN mode; in addition, when two ECUs (Electronic Control Unit) need to transmit video, image and high data transmission flow, the point-to-point communication is realized through the Ethernet communication mode.
[0004] However, the above communication mode has the following disadvantages:
[0005] The biggest disadvantage of the CAN / LIN bus communication mode is that the communication rate is not high, and the vehicle-mounted aspect
[0006] The communication rate of the CAN communication is generally not more than 500kbps, and the communication rate of the LIN bus is generally not more than 20kbps, which is difficult to transmit image and video signals; the local area Ethernet is a point-to-point communication mode, and many wire harnesses are needed according to the layout of the ECU in the vehicle-mounted aspect, which brings the problems of high cost and difficult layout. SUMMARY
[0007] To address the aforementioned technical problems, the first objective of this invention is to propose a communication control method for an automotive Ethernet bus. This invention employs a bus-type Ethernet, which can connect to the vehicle's main ECUs, domains, and control units, solving the problems of low speed, numerous wiring harnesses, and difficult layout in traditional vehicle communication. In terms of physical signal transmission, a multi-channel differential signal method is used to realize the transmission, sending, receiving, and timing control signals. The differential lines for timing control arbitrate the ID (Identity Document) to determine the transmission and reception timing. The arbitration covers the Ethernet data communication of the master node and the target node within the time period, balancing the data transmission and reception of each node, ensuring that there are no conflicts in the receiving and sending of each node under the bus architecture, and guaranteeing the reliability of vehicle communication.
[0008] The second objective of this invention is to provide an electronic device.
[0009] The technical solution adopted in this invention is as follows:
[0010] An embodiment of the first aspect of the present invention proposes a communication control method for an automotive Ethernet bus. The Ethernet bus uses a 4-core signal to form 3 differential signals. The differential signals include: a transmit differential signal line, a receive differential signal line, and a timing control differential signal line. The method includes the following steps: the timing control differential signal line receives ID information sent by a node and arbitrates the ID information to determine the transmission and reception timing; the master node that obtains arbitration authority sends a target address identifier and a target node ID to the timing control differential signal line via the transmit differential signal line to send data to other nodes; other nodes read the target node ID on the timing control differential signal line to determine whether they are the target node; if other nodes determine that they are the target node, they send information to the master node via the receive differential signal line within a first predetermined time range to reply to the master node; the master node and the target node communicate through the receive differential signal line and the transmit differential signal line; the communication between the master node and the target node ends within a second predetermined time range, and the timing control differential signal line re-arbitrates.
[0011] The communication control method for automotive Ethernet bus proposed above in this invention may also have the following additional technical features:
[0012] According to one embodiment of the present invention, the transmit differential signal line and the receive differential signal line adopt the MLT-3 channel coding method; the timing control differential signal line adopts the high-low level coding method.
[0013] According to one embodiment of the present invention, a timing control differential signal line receives ID information from a receiving node and arbitrates the ID information to determine the transmission and reception timing, including: detecting the level signal of the timing control differential signal line; if the level signal of the timing control differential signal line is a consecutive preset number of high-level signals, further determining whether an arbitration start marker appears on the timing control differential signal line; if the arbitration start marker appears, each node sequentially sends bits of the ID signal to the timing control differential signal line; converting the ID signal received on the timing control differential signal line into a logic signal; acquiring the logic signals of the transmitting differential signal line and the receiving differential signal line, and determining the transmission and reception timing based on the transmitting differential signal line... The logic signals of the transmitting differential signal line and the receiving differential signal line are arbitrated. If the logic signal of the transmitting differential signal line is the same as that of the receiving differential signal line, the bus contention for the next bit continues. If the logic signal of the transmitting differential signal line is high and the logic signal of the receiving differential signal line is low, the bus arbitration is terminated. If the logic signal of the transmitting differential signal line is high or low and the logic signal of the receiving differential signal line is negative, the current bit is determined to be an invalid arbitration bit and arbitration is performed again. It is determined whether all bits of the ID signal have been arbitrated. If the arbitration is completed, the node that obtains arbitration permission becomes the master node that obtains arbitration permission.
[0014] According to an embodiment of the present invention, the above-described communication control method further includes: if the level signal of the timing control differential signal line is not a consecutive preset number of high-level signals, or if the timing control differential signal line does not show an arbitration start marker, then each node does not respond.
[0015] According to one embodiment of the present invention, the smaller the number value corresponding to the ID information of a node, the higher its priority.
[0016] According to an embodiment of the present invention, the above-described communication control method further includes: if the master node fails to complete the transmission and reception of data within a second predetermined time, then after the master node has continuously acquired arbitration authority a preset number of times, it shall wait for a third predetermined time before participating in arbitration again.
[0017] A second aspect of the present invention provides an electronic device including a memory and a processor, wherein the memory stores a computer program or an embedded program that can run on the processor, and the processor executes the computer program or the embedded program to implement the steps of the method described in the first aspect of the present invention.
[0018] The beneficial effects of this invention are:
[0019] This invention employs a bus-based Ethernet architecture, which can connect to the main ECUs, domains, and control units of a vehicle. It solves the problems of low speed, numerous wiring harnesses, and difficult layout in traditional vehicle communication. In terms of physical signal transmission, it adopts a multi-channel differential signal method to realize the transmission, reception, and timing control signals. The ID is arbitrated on the differential lines of timing control to determine the transmission and reception timing. The Ethernet data communication of the master node and the target node within the time period under the arbitration is balanced, so that the data transmission and reception of each node does not conflict under the bus architecture, thus ensuring the reliability of vehicle communication. Attached Figure Description
[0020] Figure 1 This is a flowchart of a communication control method for an automotive Ethernet bus according to an embodiment of the present invention;
[0021] Figure 2 This is a schematic diagram illustrating the principle of differential allocation method used in an Ethernet bus according to an embodiment of the present invention;
[0022] Figure 3 This is a flowchart of a communication control method for an automotive Ethernet bus according to another embodiment of the present invention;
[0023] Figure 4 This is a schematic diagram of the connection of an automotive Ethernet bus according to another embodiment of the present invention;
[0024] Figure 5 This is a block diagram of a communication control device for an automotive Ethernet bus according to another embodiment of the present invention. Detailed Implementation
[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0026] Figure 1 This is a flowchart of a communication control method for an automotive Ethernet bus according to an embodiment of the present invention. Figure 2 This is a schematic diagram illustrating the principle of differential allocation method used in an Ethernet bus according to an embodiment of the present invention.
[0027] like Figure 2 As shown, the Ethernet bus uses 4 signal lines (A, B, C, and D) to form 3 differential signals. The differential signals include: transmit differential signal line TX, receive differential signal line RX, and timing control differential signal line TC.
[0028] Furthermore, in one embodiment of the present invention, the transmit differential signal line TX and the receive differential signal line RX adopt the MLT-3 (three-level coding) channel coding method, where a level transition indicates signal 1 and no level transition indicates signal 0; the timing control differential signal line TC adopts a high-low level coding method, where a high level indicates signal 0 and a low level indicates signal 1.
[0029] Specifically, the automotive Ethernet bus of this invention adopts a 100M Ethernet bus and uses four-core signal lines (A, B, C, and D lines). During signal modulation, a multi-path differential method is used to form a voltage signal differential with the reference line (A line), resulting in three differential signals. One of the signal lines, forming a transmit differential signal line TX with the reference line, uses three-level encoding for data transmission; the other signal line forms a receive differential signal line with the reference line.
[0030] RX uses three-level encoding for receiving data; the timing control differential signal line TC, formed by the other signal line and the reference line, uses two-level differential encoding for timing control of bus transmission and reception signals.
[0031] like Figure 2 As shown, assuming the three voltage levels on each signal line are from low to high as follows:
[0032] Given V1, V2, and V3, the possible voltage levels on line A are VA1, VA2, and VA3; the possible voltage levels on line B are VB1, VB2, and VB3; the possible voltage levels on line C are VC1, VC2, and VC3; and the possible voltage levels on line D are VD1, VD2, and VD3.
[0033] The logic for transmitting the differential signal line TX level is shown in the table below:
[0034]
[0035]
[0036] In this circuit, the node circuit monitors the A-line level, which is VA3. Therefore, the timing signals on the AD lines ignore the current bit. Since the timing signals only require two-level encoding, when the A-line level is VA3, the D-line level cannot form a positive level difference. In this case, the D-line outputs VD2, forming a negative differential level, indicating that the bit is invalid.
[0037] Understandably, a 6-core wire can also be used to transmit physical signals, with 2 cores forming a differential signal for transmitting; another 2 cores forming a differential signal for receiving data; and the remaining 2 cores forming a differential signal for timing control. Alternatively, any combination of 5-core wires can be used to transmit, receive, and timing control signals.
[0038] like Figure 1 As shown, the above-mentioned communication control method for automotive Ethernet bus includes the following steps:
[0039] S1, the timing control differential signal line receives the ID information sent by the receiving node and arbitrates the ID information to determine the transmission and reception timing.
[0040] Specifically, each node uses a unique ID (typically 8 bits). Nodes that need to send data send the ID to the timing control differential line TX in the arbitration section. Ethernet operates in half-duplex / full-duplex mode. In order to prevent conflicts between nodes RX and TX in the bus architecture, timing control is required when Ethernet nodes send data. Specifically, the ID is arbitrated by arbitrating the timing control level of the timing control differential signal line to determine the transmission and reception timing.
[0041] S2, the master node that has obtained arbitration authority sends the target address identifier and target node ID to the timing control differential signal line via the differential signal line TX in order to send data to other nodes.
[0042] S3, other nodes read the target node ID on the timing control differential signal line to determine whether they are the target node.
[0043] S4, if other nodes determine that they are the target node, they will send information to the master node through the differential signal line within the first specified time range to reply to the master node.
[0044] S5, the master node and the target node communicate via the receive differential signal line RX and the transmit differential signal line.
[0045] TX communicates.
[0046] Specifically, the node that successfully arbitrates (the master node) does so by sending a differential signal line.
[0047] When TX sends a message, the target node can reply with data via the differential signal line RX.
[0048] S6, communication between the master node and the target node ends within the second specified time, and the timing control differential signal line is re-arbitrated.
[0049] In embodiments of the present invention, the smaller the number value corresponding to the ID information of a node, the higher the priority. That is, when receiving ID information from multiple nodes, arbitration is performed according to the number value corresponding to the ID information from smallest to largest.
[0050] Specifically, each node uses a unique ID. Nodes that need to send data send their ID information to the timing control differential signal line TC during the arbitration segment. The ID is then arbitrated on the timing control differential signal line TC to determine the transmission and reception timing. The node that successfully arbitrates becomes the master node for the time period governed by that arbitration. Within the specified time range, it can send information to other nodes by sending information to the transmit differential signal line TX. After receiving the data, other nodes reply to the master node by sending information to the receive differential signal line RX within the specified time range.
[0051] More specifically, the master node that obtains arbitration privileges sends a target address identifier sequentially via the differential signal line TX, consisting of two low-level cycles, one high-level cycle, and one low-level cycle. Other nodes, upon receiving this identifier, begin monitoring whether they are the target node. The master node sends the target node ID; other nodes, upon detecting the ID on the TC, if it matches their own node, then they become the target node and gain communication privileges. After confirming the master and target nodes on the bus, during one-to-one communication between the master and target nodes, the master node indicates communication by pulling the AD line signal level high. During communication, if the A line level is at V3 and cannot be pulled high, the D line level is set to V2 or V1, creating a negative level, also indicating communication is in progress.
[0052] After each arbitration, data transmission and reception are completed within a specified time to release communication resources. After resource release, nodes that need to send data re-arbitrate their ID numbers to determine the master node for the next arbitration period, and this process repeats. The usage of continuous resources and broadcast replies in the transmission and reception sequence is controlled by controlling the time when IDs participate in arbitration, thereby achieving the goal of load balancing.
[0053] To ensure the continuity of Ethernet communication, data between communication nodes needs to be completed in a short period of time to free up communication resources for other nodes that need to communicate. After the resources are released, the nodes that need to send data re-arbitrate their ID numbers to determine the master node for the next arbitration period, and this cycle continues.
[0054] Therefore, this invention adopts a bus-type Ethernet, which can connect the main ECUs, domains and control units of the vehicle, solving the problems of low speed, many wiring harnesses and difficult layout in traditional vehicle communication. In terms of physical signal transmission, a multi-channel differential signal method is adopted to realize the transmission, sending, receiving and timing control signals. The differential lines of timing control arbitrate the ID (Identity Document) to determine the transmission and reception timing. The Ethernet data communication of the master node and the target node in the time period under the jurisdiction of the arbitration balances the data transmission and reception of each node, so that the receiving and sending of each node does not conflict under the bus architecture, thus ensuring the reliability of vehicle communication.
[0055] According to one embodiment of the present invention, such as Figure 3 As shown, the timing control differential signal line receives the ID information sent by the receiving node and arbitrates the ID information to determine the transmission and reception timing, specifically including:
[0056] S101, detects the level signal of the timing control differential signal line TC.
[0057] S102, determine whether the timing control differential signal line TC has a level signal of a consecutive preset number of high-level signals.
[0058] S103, if the level signal of the timing control differential signal line TC is a series of preset high-level signals, then further determine whether the timing control differential signal line has an arbitration start mark.
[0059] S104, if an arbitration start flag appears, each node sequentially sends the ID signal bits to the timing control differential signal line TC.
[0060] S105 converts the ID signal received on the timing control differential signal line TC into a logic signal.
[0061] S106: Obtain the logic signals of the transmit differential signal line TX and the receive differential signal line RX, and perform arbitration based on the logic signals of the transmit differential signal line TX and the receive differential signal line RX, wherein...
[0062] S107, if the logic signal of the transmitted differential signal line TX is the same as the logic signal of the received differential signal line RX, then continue the bus contention for the next bit.
[0063] In other words, if the data bit sent by the node is 0 and the data bit read back from the timing control line is 0, or if the data bit sent by the node is 1 and the data bit read back from the timing control line is 1, then the bus contention for the next bit continues.
[0064] S108, if the logic signal of the transmit differential signal line is high and the logic signal of the receive differential signal line is low, then exit bus arbitration;
[0065] S109: If the logic signal of the transmitted differential signal line is high or low and the logic signal of the received differential signal line is negative, then the current bit is determined to be an invalid arbitration bit and arbitration is performed again.
[0066] S110, determine whether all bits of the ID signal have completed arbitration.
[0067] S111, if the arbitration is completed, the node that acquires the arbitration authority becomes the master node that acquires the arbitration authority.
[0068] If the arbitration is not completed, return to step S104.
[0069] S112, if the level signal of the timing control differential signal line is not a consecutive preset number of high-level signals, or if the timing control differential signal line does not show an arbitration start indicator, then each node will not respond.
[0070] Specifically, timing control level signals can be detected on the AD line. These signals are emitted by the node that previously won the arbitration. If each node detects multiple consecutive high-level signals, and its previous state was non-arbitration, it is considered to be in arbitration preparation state; otherwise, it does not enter arbitration preparation state and does not need to respond to arbitration. If an arbitration start indicator appears immediately after entering the arbitration preparation state (e.g., one low-level cycle, one high-level cycle, and one low-level cycle in sequence), it indicates that arbitration is about to begin. If no arbitration start indicator appears, it does not enter arbitration preparation state and does not need to respond to arbitration.
[0071] During the arbitration period, each node sequentially sends the ID signal bits to the AD line (Timing Control Differential Signal Line TC). During transmission, the received signal level on the AD bus is detected and converted into a logic signal to determine whether arbitration was successful. Then, the received and transmitted logic signals are processed. If TX = 0 and RX = 0, bus contention continues; otherwise...
[0072] If TX=1 and RX=1, then bus contention continues; if TX=1 and RX=0, then bus arbitration is terminated, and communication privileges for that arbitration period are lost; if TX=1 / 0 and RX=negative level, then it is an invalid arbitration bit, and this bit is re-arbitrated.
[0073] After arbitration of one bit is completed, it is determined whether ID arbitration is complete. If arbitration is incomplete, the next arbitration bit is sent. If arbitration is complete, the node that obtains arbitration authority has the right to determine the target node and send data. The node that successfully obtains arbitration becomes the master node for the time period governed by that arbitration. Within the specified time range, the master node can send data to other nodes by sending information to the TX differential signal line; after receiving the data, other nodes can reply to the master node by sending information to the RX line within the specified time range.
[0074] In this invention, during the arbitration period, if the master node needs to change the target node, the master node sends a target address change identifier and address: the master node sends the target address change identifier, typically: 2 low-level cycles, 1 high-level cycle, 1 low-level cycle, followed by the master node sending the target node ID. The target address detects this identifier and begins to identify whether it will become the target address; immediately afterward, the master node sends the target address change identifier, and other nodes read the target node ID on the TC line, completing the node switch; the master node pulls the TC line high or negative, and continues the Ethernet message information exchange between the master node and the target node.
[0075] If the communication time within the arbitration scope expires or the communication ends prematurely, the master and slave nodes disconnect, and the original master node is responsible for re-initiating arbitration: After a continuous high-level signal on the AD line, an arbitration start flag is triggered, indicating that the next arbitration is about to begin. For example, if one low-level cycle, one high-level cycle, and one low-level cycle appear sequentially, the bus arbitration will restart. Figure 3 This is done in a certain way.
[0076] According to an embodiment of the present invention, the above-described communication control method may further include: if the master node fails to complete the transmission and reception of data within a second predetermined time, then after the master node has continuously acquired arbitration authority a preset number of times, it shall wait for a third predetermined time before participating in arbitration again.
[0077] Specifically, to ensure the timeliness of Ethernet communication, balance the data transmission and reception of each bus node, and prevent the same node from continuously occupying resources, if the master node fails to complete the information it wants to send or receive within an arbitration jurisdiction period, it will wait for a period of time after successfully arbitrating a certain number of times (typically more than 2 times) before participating in arbitration again, in order to avoid continuously preempting communication resources.
[0078] Understandably, nodes can determine the current communication load by detecting arbitration or data transmission status. When the bus load is too high, they can also consider reducing the transmission of non-critical business data or shortening the data transmission cycle to alleviate the problem.
[0079] In a specific example of the present invention, such as Figure 4As shown, the automotive Ethernet bus 501 is an automotive backbone bus-type communication network that provides a high communication rate and can connect multiple communication nodes (including: power domain gateway 502, body domain gateway 503, ADAS domain gateway 504, and other similar controllers or gateway modules); the communication gateways or controller units connected to the automotive Ethernet bus 501 can be associated with CAN / LIN / bus-type Ethernet subnet 505, and the bus-type Ethernet subnet can connect to camera module 506, radar module 507, and other similar controllers or gateway modules.
[0080] To implement the aforementioned communication control method for an automotive Ethernet bus, this invention provides a communication control device for an automotive Ethernet bus, see below. Figure 5 The device 601 includes: a bus-type Ethernet function module 602, an Ethernet bus function controller 603, a multi-channel differential level modulation 604, an AD voltage detection 605, a line connection part 606, and other function modules of the ECU node 607.
[0081] The automotive Ethernet bus communication control device 601 consists of an ECU node other functional module 607, a bus-type Ethernet functional module 602, and a wiring connection part 606. The modules interact with each other to realize the control and data information interaction functions required by the vehicle. The bus-type Ethernet functional module 602 consists of an Ethernet bus function controller 603, a multi-channel differential level modulation 604, and an AD voltage detection 605 to realize the vehicle's control function via bus-type Ethernet communication.
[0082] The bus-type Ethernet function module 602 enables data interaction with the multi-channel differential level modulator 604, performing data transmission and reception and signal modulation; the bus-type Ethernet function module 602 acquires data...
[0083] The voltage on the AD line determines the timing control requirements. The multi-channel differential level modulation module 604 uses a 4-core line to transmit information, transmitting three differential signals respectively. Two channels are used for transmitting (TX) and receiving (RX) information, and one channel is used for timing control (TC) of bus-type transceiver information. The Ethernet function module 602 arbitrates the ID on the differential line for timing control, determining the transmission and reception timing, arbitrating Ethernet data communication between the master node and the target node within the arbitrated time period, and balancing data transmission and reception across nodes. The ECU node other function module 607 implements other functions but interacts with the control module or differential level modulation module.
[0084] In summary, the communication control method for automotive Ethernet bus according to embodiments of the present invention adopts a bus-type Ethernet, which can connect the main ECUs, domains, and control units of the vehicle, solving the problems of low speed, numerous wiring harnesses, and difficult layout in traditional vehicle communication. In terms of physical signal transmission, a multi-channel differential signal method is adopted to realize the transmission of sending, receiving, and timing control signals. The ID is arbitrated on the differential lines of timing control to determine the transmission and reception timing. The Ethernet data communication of the master node and the target node in the time period under the jurisdiction of the arbitration is balanced, so that the data transmission and reception of each node does not conflict under the bus architecture, ensuring the reliability of vehicle communication.
[0085] Furthermore, the present invention also proposes an electronic device, including a memory and a processor, wherein the memory stores a computer program or embedded program that can run on the processor, and the processor executes the computer program or embedded program to implement the steps of the method described above in the present invention.
[0086] According to an embodiment of the present invention, when the processor runs a computer program or embedded program stored in the memory, it controls the timing control differential signal line to receive ID information sent by the receiving node, and arbitrates the ID information to determine the transmission and reception timing. The master node, having obtained arbitration authority, sends a target address identifier and a target node ID to the timing control differential signal line via a transmitting differential signal line to send data to other nodes. Other nodes read the target node ID on the timing control differential signal line to determine if they are the target node. If a node determines it is the target node, it sends information to the master node via a receiving differential signal line within a first predetermined time range to reply to the master node. The master node and the target node communicate via receiving and transmitting differential signal lines. Communication between the master node and the target node ends within a second predetermined time range, and the timing control differential signal line re-arbitrates. This solves the problems of low speed, numerous wiring harnesses, and difficult layout in traditional vehicle communication, and balances data transmission and reception among nodes, ensuring that there are no conflicts in the receiving and transmitting of each node under the bus architecture, thus guaranteeing the reliability of vehicle communication.
[0087] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. "A plurality of" means two or more, unless otherwise explicitly specified.
[0088] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the communication within the compartments of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0089] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples and features of different embodiments or examples described in this specification without contradiction. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described herein, as well as the features of the different embodiments or examples, without contradiction.
[0090] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any of the following techniques known in the art, or a combination thereof: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.
[0091] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.
[0092] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.
[0093] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.
[0094] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A communication control method for an Ethernet bus for an automobile, characterized by, The Ethernet bus adopts 4-core signal lines to form 3-way differential signal lines, the differential signal lines include: sending differential signal line, receiving differential signal line and timing control differential signal line, the method includes the following steps: The timing control differential signal line receives ID information sent by the node and arbitrates the ID information to determine the transmission timing; The master node with arbitration right sends target address identification and target node ID to the timing control differential signal line through the sending differential signal line to send data to other nodes; Other nodes read the target node ID on the timing control differential signal line to determine whether they are the target node; If other nodes determine that they are the target node, they send information to the master node through the receiving differential signal line within a first specified time range; The master node and the target node communicate through the receiving differential signal line and the sending differential signal line; The communication between the master node and the target node ends within a second specified time, and the timing control differential signal line arbitrates again.
2. The communication control method of an Ethernet bus for an automobile according to claim 1, characterized by, The sending differential signal line and the receiving differential signal line adopt MLT-3 channel coding method; the timing control differential signal line adopts high-low level coding method.
3. The communication control method of an Ethernet bus for an automobile according to claim 2, characterized by, The timing control differential signal line receives ID information sent by the node and arbitrates the ID information to determine the transmission timing, including: Detecting the level signal of the timing control differential signal line; If the level signal of the timing control differential signal line is a continuous preset number of high level signals, further judge whether the arbitration start identification appears on the timing control differential signal line; If the arbitration start identification appears, each node sends ID signal bit to the timing control differential signal line in turn; Convert the received ID signal on the timing control differential signal line into a logic signal; Get the logic signal of the sending differential signal line and the receiving differential signal line, and arbitrate according to the logic signal of the sending differential signal line and the receiving differential signal line, wherein, If the logic signal of the sending differential signal line is the same as the logic signal of the receiving differential signal line, continue the bus competition of the next bit; If the logic signal of the sending differential signal line is high and the logic signal of the receiving differential signal line is low, exit the bus arbitration; If the logic signal of the sending differential signal line is high or low and the logic signal of the receiving differential signal line is negative, judge that the current bit is an invalid arbitration bit and re-arbitrate; Judge whether all bit positions of the ID signal are arbitrated; If the arbitration is completed, the node with arbitration right is the master node with arbitration right.
4. The communication control method of an Ethernet bus for an automobile according to claim 3, characterized by Further comprising: If the level signal of the timing control differential signal line is not a continuous preset number of high level signals, or the arbitration start identification does not appear on the timing control differential signal line, each node does not respond.
5. The communication control method of an Ethernet bus for an automobile according to claim 1, characterized by, The smaller the number value corresponding to the ID information of the node, the higher the priority.
6. The communication control method of an Ethernet bus for an automobile according to any one of claims 1 to 5, characterized by, Further comprising: If the master node does not complete the data transmission and reception within the second specified time, the master node waits for a third specified time after participating in arbitration again after continuously obtaining arbitration right for a preset number of times.
7. An electronic device comprising a memory, a processor, said memory having stored therein a computer program or an embedded program operable on said processor, characterized in that, The processor implements the steps of the method of any one of claims 1-6 when executing the computer program or embedded program.
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