Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate including a device unit region, with multiple channel structures formed on the top of the substrate in the device unit region, with dielectric walls formed between adjacent channel structures, and along a first direction, the region where the channel structures are located includes an active region and a region to be cut; removing the channel structures in the region to be cut; removing the dielectric walls located on the sides of the region to be cut and covering the sidewalls of the channel structures; forming a dummy gate structure on the top of the substrate that spans the channel structures and the dielectric walls located between the channel structures; after removing the channel structures in the region to be cut and the dielectric walls located on the sides of the region to be cut and covering the sidewalls of the channel structures, forming source and drain doping layers in the channel stack on both sides of the dummy gate structure, wherein the source and drain doping layers on the sides of the region to be cut also extend along a second direction to cover a portion of the width of the dielectric wall end face. This improves the electrical connection performance between the source and drain interconnect structure and the source and drain doping layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the gradual advancement of semiconductor process technology, semiconductor process nodes continue to shrink in line with Moore's Law. To accommodate this reduction in process nodes and the development of highly integrated semiconductor devices, the critical dimensions of metal oxide semiconductor (MOS) devices are also shrinking, with gate length and gate pitch also shrinking to smaller sizes. Accordingly, semiconductor device manufacturing processes are also constantly being improved to meet people's expectations for device performance.

[0003] The reliability of SRAM devices is crucial to ensuring stable and safe operation of electrical applications. Currently, the manufacturing process and reliability of SRAM need to be improved. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to improving the performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate including a device unit region; a channel structure layer located on the substrate in the device unit region, wherein the channel structure extends along a first direction and is arranged in parallel along a second direction, wherein the second direction is perpendicular to the first direction; in the device unit region, the channel structure layer comprises a first type of channel structure layer and a second type of channel structure layer, wherein along the first direction, an end portion of the first type of channel structure layer is indented inwardly relative to an end portion of the second type of channel structure layer on the same side; a dielectric wall located adjacent to the channel structure layer. , and the dielectric wall covers the opposite side walls of the channel structure; a device gate structure is located on the top of the substrate and spans the channel structure layer and the dielectric wall, and the device gate structure covers part of the top and part of the side walls of the channel structure layer and the dielectric wall, as well as part of the top of the dielectric wall; source-drain doped layers are located in the channel structure layer on both sides of the device gate structure, and at a position where the end of the first type of channel structure layer is indented inwardly, the source-drain doped layers in the second type of channel structure layer also extend along the second direction to cover part of the width of the dielectric wall end surface.

[0006] Accordingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a device unit region, wherein a plurality of channel structures are formed on the top of the substrate in the device unit region, wherein the channel structures extend along a first direction and are arranged in parallel along a second direction, wherein the second direction is perpendicular to the first direction, wherein dielectric walls are formed between adjacent channel structures, wherein the dielectric walls cover opposite sidewalls of the channel structures, wherein along the first direction, the region where the channel structures are located includes an effective region and a region to be cut; removing the channel structures in the region to be cut; removing the dielectric walls located on the side of the region to be cut and covering the sidewalls of the channel structures; After removing the channel structure in the area to be cut, a dummy gate structure is formed on the top of the substrate, spanning the channel structure and the dielectric wall located between the channel structures, wherein the dummy gate structure covers part of the top and part of the sidewall of the channel structure, and part of the top of the dielectric wall; after removing the channel structure in the area to be cut and removing the dielectric wall located on the side of the area to be cut and covering the sidewall of the channel structure, a source-drain doped layer is formed in the channel stack on both sides of the dummy gate structure, wherein the source-drain doped layer on the side of the area to be cut further extends along the second direction to cover part of the width of the dielectric wall end face.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] An embodiment of the present invention provides a method for forming a semiconductor structure, wherein a dielectric wall located on the side of a region to be cut and covering the sidewall of a channel structure is removed. In the process of forming a source-drain doped layer in the channel stack on both sides of the pseudo-gate structure, the spatial position of the source-drain doped layer formed on the side of the region to be cut is increased, so that the source-drain doped layer on the side of the region to be cut also extends along the second direction to cover a portion of the width of the dielectric wall end surface. This is beneficial to increasing the volume of the source-drain doped layer on the side of the region to be cut, and correspondingly, also increases the contact area between the source-drain interconnection structure formed in a subsequent process and the source-drain doped layer located on the side of the region to be cut, thereby improving the electrical connection performance between the source-drain interconnection structure and the source-drain doped layer, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a structural schematic diagram corresponding to a semiconductor structure;

[0010] Figures 2 to 5 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0011] Figures 6 to 22 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0012] The performance of current semiconductor structures needs to be improved. This article analyzes the reasons why the performance of semiconductor structures needs to be improved, using a semiconductor structure as an example.

[0013] Figure 1 It is a structural schematic diagram corresponding to a semiconductor structure.

[0014] refer to Figure 1 , a substrate (not shown), including a device unit area 10A; a channel structure layer 11, located on the substrate of the device unit area 10A, the channel structure layer 11 along the first direction (such as Figure 1 X direction) and extends along the second direction (as shown in FIG. Figure 2 The first direction is perpendicular to the second direction. In the device unit area 10A, the channel structure layer 11 includes a first-type channel structure layer 21 and a second-type channel structure layer 22. Along the first direction, the end of the first-type channel structure layer 21 is retracted inward relative to the end of the second-type channel structure layer 22 on the same side; the dielectric wall 12 is located on the substrate between adjacent channel structure layers 11, and the dielectric wall 12 covers the sidewalls of the channel structure layer 11; the gate structure 13 is located on the top of the substrate and spans the channel structure layer 11 and the dielectric wall 12, and the gate structure 13 covers part of the top and part of the sidewalls of the channel structure layer 11 and the dielectric wall 12, as well as part of the top of the dielectric wall 12; the source and drain doping layers (not shown) are located in the channel structure layer 11 on both sides of the gate structure 13.

[0015] After research, it was found that at the position where the end of the first-type channel structure layer 21 is indented, the end of the second-type channel structure layer 22 protrudes outward relative to the end of the first-type channel structure layer 21, and the end of the dielectric wall 12 also protrudes outward relative to the end of the first-type channel structure layer 21. Since the dielectric wall 12 covers the sidewall of the second-type channel structure layer 22, in the process of forming the source-drain doped layer at the position where the end of the first-type channel structure layer 21 is indented, the dielectric wall 12 will block the formation space position of the source-drain doped layer in the second direction, so that the contact area between the source-drain doped layer and the source-drain interconnection structure formed in the subsequent process is reduced (such as Figure 1 The electrical connection performance between the source-drain interconnection structure and the source-drain doped layer is reduced, and the difficulty of forming the source-drain interconnection structure is increased, thereby reducing the performance of the semiconductor structure.

[0016] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, including a device unit area, wherein a plurality of channel structures are formed on the top of the substrate of the device unit area, wherein the channel structures extend along a first direction and are arranged in parallel along a second direction, wherein the second direction is perpendicular to the first direction, and dielectric walls are formed between adjacent channel structures, wherein the dielectric walls cover opposite sidewalls of the channel structures, and wherein the region where the channel structures are located along the first direction includes an effective region and a region to be cut; removing the channel structures in the region to be cut; removing the side portions of the region to be cut and covering the channel structures; a dielectric wall on the sidewall of the structure; after removing the channel structure in the area to be cut, forming a dummy gate structure on the top of the substrate spanning the channel structure and the dielectric wall located between the channel structures, the dummy gate structure covering part of the top and part of the sidewall of the channel structure, and part of the top of the dielectric wall; after removing the channel structure in the area to be cut and removing the dielectric wall located on the side of the area to be cut and covering the sidewall of the channel structure, forming a source-drain doped layer in the channel stack on both sides of the dummy gate structure, the source-drain doped layer on the side of the area to be cut also extending along the second direction to cover part of the width of the dielectric wall end face.

[0017] In the formation method provided by an embodiment of the present invention, the dielectric wall located on the side of the area to be cut and covering the sidewall of the channel structure is removed. In the process of forming the source-drain doped layer in the channel stack on both sides of the dummy gate structure, the spatial position of the source-drain doped layer formed on the side of the area to be cut is increased, so that the source-drain doped layer on the side of the area to be cut also extends along the second direction to cover a portion of the width of the dielectric wall end surface. Correspondingly, the contact area between the source-drain interconnection structure formed in the subsequent process and the source-drain doped layer located on the side of the area to be cut is increased, thereby improving the electrical connection performance between the source-drain interconnection structure and the source-drain doped layer, thereby improving the performance of the semiconductor structure.

[0018] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0019] Figures 2 to 3 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 2 It is a top view. Figure 3 yes Figure 2 Cross-sectional view along the ef direction, Figure 4 yes Figure 2 Cross-sectional view along the cd direction, Figure 5 yes Figure 2 Cross-sectional view along the ab direction.

[0020] The semiconductor structure includes: a substrate 202 including a device unit area 200A; a channel structure layer 250 located on the substrate 202 in the device unit area 200A, and the channel structure layer 250 is arranged along a first direction (eg Figure 2 X direction) and extends along the second direction (as shown in FIG. Figure 2 The first channel structure layer 250 is arranged in parallel with the first channel structure layer 2501 and the second channel structure layer 2502 in the device unit area 200A. The first channel structure layer 250 is arranged in parallel with the first channel structure layer 2501 and the second channel structure layer 2502 in the device unit area 200A. Along the first direction, the end of the first channel structure layer 2501 is retracted inward relative to the end of the second channel structure layer 2502 on the same side. The dielectric wall 201 is located on the substrate 202 between adjacent channel structure layers 250, and the dielectric wall 201 covers the opposite side walls of the channel structure layer 250. The device gate structure 251 is located between the first channel structure layer 2501 and the second channel structure layer 2502. The device gate structure 251 covers part of the top and part of the sidewalls of the channel structure layer 250 and the dielectric wall 201, as well as part of the top of the dielectric wall 201; the source-drain doped layer 221 is located in the channel structure layer 250 on both sides of the device gate structure 251, and at a position where the end of the first-type channel structure layer 2501 is indented inwardly, the source-drain doped layer 221 in the second-type channel structure layer 2502 also extends along the second direction to cover part of the width of the end face of the dielectric wall 201.

[0021] In this embodiment, the end of the first-type channel structure layer 2501 is retracted inward relative to the end of the second-type channel structure layer 2502 on the same side, and the dielectric wall 201 is located between adjacent channel structure layers 250. That is, at the position where the end of the first-type channel structure layer 2501 is retracted inward, the end of the dielectric wall 201 along the first direction is retracted inward relative to the end of the second-type channel structure layer 2502 on the same side, so that the source-drain doped layer 221 in the second-type channel structure layer 2502 also extends along the second direction to cover a portion of the width of the end surface of the dielectric wall 201, thereby increasing the volume of the source-drain doped layer 221. Accordingly, the contact area between the source-drain interconnect structure formed in the process of the semiconductor structure and the source-drain doped layer 221 is increased, thereby improving the electrical connection performance between the source-drain interconnect structure and the source-drain doped layer 221, thereby improving the performance of the semiconductor structure.

[0022] The substrate 202 provides a process operation basis for the formation process of the semiconductor structure.

[0023] In this embodiment, the material of the substrate 202 is silicon. In other embodiments, the substrate material may be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the substrate 100 may be a material suitable for process requirements or easy to integrate.

[0024] In this embodiment, the semiconductor structure is an SRAM device, the substrate 202 includes a memory cell area 200B, and the memory cell area 200B includes adjacent and center-symmetrical device cell areas 200A, and the device cell areas 200A each include a transmission gate transistor area 201G, a pull-down transistor area 201D and a pull-up transistor area 201U.

[0025] Specifically, the pass gate transistor region 201G and the pull-down transistor region 201D are adjacent to each other in the first direction, and the pass gate transistor region 201G and the pull-down transistor region 201D are adjacent to the pull-up transistor region 201U in the second direction.

[0026] The pass gate transistor region 201G is used to form a pass gate transistor, the pull-down transistor region 201D is used to form a pull-down transistor, and the pull-up transistor region 201U is used to form a pull-up transistor. The pass gate transistor 201G and the pull-down transistor 201D are both N-type transistors, and the pull-up transistor 101U is a P-type transistor.

[0027] In this embodiment, the semiconductor structure further includes a bottom fin 260 extending along the first direction and protruding from the top of the substrate 202 .

[0028] In this embodiment, the bottom fin 260 is an integral structure with the substrate 202. In other embodiments, the bottom fin may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving the purpose of accurately controlling the height of the bottom fin.

[0029] In this embodiment, the material of the bottom fin 260 is the same as that of the substrate 202, that is, silicon. In other embodiments, the material of the bottom fin 260 may be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium, and the material of the bottom fin may also be different from that of the substrate.

[0030] In this embodiment, along the normal direction of the surface of the substrate 202 , the channel structure layer 250 and the substrate 202 are spaced apart, and the channel structure layer 250 includes one or more spaced apart channel layers 2001 .

[0031] The top, sidewalls and bottom of the channel layer 2001 covered by the device gate structure 251 are used as channels. In this embodiment, the top, sidewalls and bottom of the channel layer 2001 can all be used as channels, which increases the area of the channel layer 2001 used as a channel, thereby increasing the operating current of the semiconductor device.

[0032] In this embodiment, the material of the channel layer 2001 includes silicon, germanium, silicon germanium, or a III-V semiconductor material. As an example, the material of the channel layer 2001 is silicon. In other embodiments, the material of the channel layer is determined by the type and performance of the transistor.

[0033] Along the first direction, the end of the first type of channel structure layer 2501 is indented inward relative to the end of the second type of channel structure layer 2502 on the same side. At the position where the end of the first type of channel structure layer 2501 is indented inward, in the formation process of forming the source-drain doped layer 221 in the second type of channel structure layer 2502, the spatial position of the source-drain doped layer 221 is increased, and the volume of the source-drain doped layer 221 is increased.

[0034] In this embodiment, the first type of channel structure layer 2501 is located in the pull-up transistor area 201U, and the second type of channel structure layer 2502 is located in the transfer gate transistor area 201G and the pull-down transistor area 201D. The transfer gate transistor area 201G and the pull-down transistor area 201D share the second type of channel structure layer 2502, and the first type of channel structure layer 2501 exposes part of the second type of channel structure layer 2502 of the transfer gate transistor area 201G.

[0035] Specifically, according to the layout design of the SRAM device, the end portion of the first-type channel structure layer 2501 is retracted inward relative to the end portion of the second-type channel structure layer 2502 on the same side.

[0036] In other embodiments, the channel structure layer may also be a fin protruding from the substrate.

[0037] The dielectric wall 201 is used to isolate the adjacent first-type channel structure layers 2501 and second-type channel structure layers 2502 in the device unit area 200A, thereby reducing the distance between the adjacent first-type channel structure layers 2501 and second-type channel structure layers 2502 as much as possible while electrically isolating the adjacent first-type channel structure layers 2501 and second-type channel structure layers 2502.

[0038] To this end, in this embodiment, the dielectric wall 201 is made of a dielectric material, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon boronitride and carbonitride, thereby ensuring that the dielectric wall 201 can perform an isolation function. In this embodiment, the dielectric wall 201 is made of silicon oxide.

[0039] In this embodiment, at the position where the end of the first-type channel structure layer 2501 is retracted inward, the end of the dielectric wall 201 along the first direction is flush with the sidewall of the device gate structure 251 .

[0040] Specifically, the end of the dielectric wall 201 along the first direction is flush with the side wall of the device gate structure 251. In the process of forming the source-drain doped layer 221, the spatial position of the source-drain doped layer 221 formed at the inwardly indented position of the end of the first type channel structure layer 2501 is increased, thereby improving the performance of the semiconductor structure.

[0041] In this embodiment, the semiconductor structure further includes an isolation layer 205 located on the substrate 202 where the channel structure layer 250 , the dielectric wall 201 and the device gate structure 251 are exposed. The isolation layer 205 covers a portion of the sidewall of the channel structure 200 .

[0042] The isolation layer 205 is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, an isolation layer 205 is usually formed between an NMOS transistor and a PMOS transistor.

[0043] To this end, the isolation layer 205 is a dielectric material, and the material of the isolation layer 205 includes one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide. As an example, the material of the isolation layer 205 is carbon-doped silicon oxide.

[0044] The source-drain doped layer 221 is used as the source region and the drain region of the transistor.

[0045] When forming an NMOS transistor, the source-drain doped layer 221 includes a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, and the stress layer provides tensile stress for the channel region of the NMOS transistor, thereby facilitating improvement of the carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions or Sb ions; when forming a PMOS transistor, the source-drain doped layer 221 includes a stress layer doped with P-type ions, the material of the stress layer is Si or SiGe, and the stress layer provides compressive stress for the channel region of the PMOS transistor, thereby facilitating improvement of the carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions or In ions.

[0046] It should be noted that at the location where the end of the first-type channel structure layer 2501 is indented, the source-drain doped layer 221 in the second-type channel structure layer 2502 extends along the second direction to cover the width of the end surface of the dielectric wall 201, and the proportion of the width of the dielectric wall 201 to the width of the dielectric wall 201 should not be too large or too small. If the proportion is too large, the process time for forming the source-drain doped layer 221 is increased, reducing process efficiency. At the same time, the probability of short circuit between the source-drain doped layers 221 in adjacent pull-up transistor regions 201U along the second direction is increased, thereby affecting the performance of the semiconductor structure. If the proportion is too small, the contact area between the source-drain doped layer 221 formed at the location where the end of the first-type channel structure layer 2501 is indented and the subsequently formed source-drain interconnect structure is reduced, increasing the difficulty of forming the source-drain interconnect structure and reducing the electrical connection performance between the source-drain interconnect structure and the source-drain doped layer 221, thereby affecting the performance of the semiconductor structure. To this end, in this embodiment, at the position where the end of the first type channel structure layer 2501 is indented inward, the source-drain doping layer 221 in the second type channel structure layer 2502 extends along the second direction to cover the width of the end face of the dielectric wall 201, accounting for 10% to 100% of the width of the dielectric wall 201.

[0047] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 230 located on the substrate 202 where the device gate structure 251 is exposed, and the interlayer dielectric layer 230 covers the sidewalls of the device gate structure 251 .

[0048] The interlayer dielectric layer 230 is used to isolate adjacent devices.

[0049] The interlayer dielectric layer 230 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0050] In this embodiment, the device gate structure 251 includes a gate dielectric layer surrounding and covering the channel structure layer, and a gate electrode layer covering the gate dielectric layer.

[0051] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0052] It should be noted that the gate dielectric layer may further include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the channel layer 2001. Specifically, the material of the gate oxide layer may be silicon oxide.

[0053] In this embodiment, the device gate structure 251 is a metal gate structure. Therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0054] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to electrically lead out the metal gate structure.

[0055] In other embodiments, the gate electrode layer may also include only a work function layer.

[0056] In this embodiment, the semiconductor structure further includes a sidewall spacer 252 located on the sidewall of the device gate structure 251 .

[0057] The sidewall spacers 252 are used to protect the sidewalls of the device gate structure 251. The sidewall spacers 252 can be a single-layer structure or a stacked-layer structure, and the material of the sidewall spacers 252 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall spacers 252 are a single-layer structure, and the material of the sidewall spacers 252 is silicon oxide.

[0058] Figures 6 to 22 It is a schematic structural diagram corresponding to each step in an embodiment of a method for manufacturing a semiconductor structure of the present invention.

[0059] refer to Figures 6 and 7 , Figure 6 It is a top view. Figure 7 yes Figure 6 A cross-sectional view along the AB direction is provided, which includes a device unit area 100A. A plurality of channel structures 100 are formed on the top of the substrate 102 of the device unit area 100A. The channel structures 100 are arranged along a first direction (eg, Figure 6 X direction) and extends along the second direction (as shown in FIG. Figure 6 The second direction is perpendicular to the first direction. Dielectric walls 101 are formed between adjacent channel structures 100. The dielectric walls 101 cover opposite sidewalls of the channel structure 100. Along the first direction, the region where the channel structure 100 is located includes an effective region 102A and a to-be-cut region 102B.

[0060] The substrate 102 provides a process operation basis for the formation process of the semiconductor structure.

[0061] In this embodiment, the formation method is used to form an SRAM device. Therefore, the material of the substrate 102 is silicon. In other embodiments, the substrate material may be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the substrate 102 may be a material suitable for process requirements or easy to integrate.

[0062] In this embodiment, in the step of providing a substrate 102, the substrate 102 includes a storage cell area 100B, and the storage cell area 100B includes adjacent and centrally symmetrical device cell areas 100A, and the device cell areas 100A each include a transmission gate transistor area 101G, a pull-down transistor area 101D and a pull-up transistor area 101U, and the area where the channel structure 100 in the pull-up transistor area 101U is located includes the area to be cut 102B, and the area to be cut 102B is adjacent to the pull-down transistor area 101D.

[0063] Specifically, the pass gate transistor region 101G and the pull-down transistor region 101D are adjacently arranged in the first direction, and the pass gate transistor region 101G and the pull-down transistor region 101D are adjacently arranged in the second direction to the pull-up transistor region 101U.

[0064] The pass gate transistor region 101G is used to form a pass gate transistor, the pull-down transistor region 101D is used to form a pull-down transistor, and the pull-up transistor region 101U is used to form a pull-up transistor. The pass gate transistor 101G and the pull-down transistor 101D are both N-type transistors, and the pull-up transistor 101U is a P-type transistor.

[0065] In this embodiment, the method for forming the semiconductor structure further includes: forming a bottom fin 160 extending along a first direction on the top of the substrate 102 .

[0066] The bottom fin 160 is an integral structure with the substrate 102. In other embodiments, the bottom fin may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving the purpose of accurately controlling the height of the bottom fin.

[0067] Accordingly, in this embodiment, the material of the bottom fin 160 is the same as that of the substrate 102, that is, silicon. In other embodiments, the material of the bottom fin 160 may be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium, and the material of the bottom fin may also be different from that of the substrate.

[0068] In this embodiment, in the step of providing the substrate 102 , along the normal direction of the surface of the substrate 102 , the channel structure 100 includes a plurality of channel stacks 1003 , each of the channel stacks 1003 including a channel layer 1001 and a sacrificial layer 1002 located on the channel layer 1001 .

[0069] In this embodiment, the material of the sacrificial layer 1002 includes silicon germanium; the material of the channel layer 1001 includes silicon, silicon germanium, germanium or Group III-V semiconductor material, and there is an etching selectivity ratio between the sacrificial layer 1002 and the channel layer 1001 .

[0070] The channel structure 100 provides a process basis for subsequently forming a channel layer 1001 with suspended spacing.

[0071] As an example, the number of the channel stacks 1003 is three. In other embodiments, the number of the channel stacks can be other numbers.

[0072] The dielectric wall 101 is used to isolate adjacent channel structures 100 in the device unit area 100A, thereby minimizing the distance between adjacent channel structures 100 as much as possible and electrically isolating adjacent channel structures 100, which is beneficial to improving the performance of the semiconductor structure.

[0073] To this end, in this embodiment, the dielectric wall 101 is made of a dielectric material, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon boron carbonitride, to ensure that the dielectric wall 101 can perform an isolation function. In this embodiment, the dielectric wall 101 is made of silicon oxide.

[0074] In this embodiment, the method for forming the semiconductor structure further includes: forming an isolation layer 105 on the substrate 102 where the channel structure 100 and the dielectric wall 101 are exposed, and the isolation layer 105 covers a portion of the sidewall of the bottom fin 160 .

[0075] The isolation layer 105 is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, an isolation layer 105 is usually formed between an NMOS transistor and a PMOS transistor.

[0076] To this end, the isolation layer 105 is a dielectric material, and the material of the isolation layer 105 includes one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide. As an example, the material of the isolation layer 105 is carbon-doped silicon oxide.

[0077] refer to Figures 8 to 10 , Figure 8 It is a top view. Figure 9 yes Figure 8 Cross-sectional view along CD direction, Figure 10 yes Figure 8 In the cross-sectional view along the AB direction, the trench structure 100 in the to-be-cut area 102B is removed.

[0078] The channel structure 100 in the to-be-cut region 102B is not required for forming devices, and therefore, the channel structure 100 in the to-be-cut region 102B is removed. Furthermore, removing the channel structure 100 in the to-be-cut region 102B provides a process foundation for subsequently removing the dielectric wall 101 in the to-be-cut region 102B, thereby increasing the process window for removing the dielectric wall 101 in the to-be-cut region 102B.

[0079] In this embodiment, in the step of removing the channel structure 100 in the to-be-cut region 102B, the channel structure 100 located in the to-be-cut region 102B is removed in the transfer gate transistor region 101G.

[0080] Specifically, as can be seen from the above, the storage cell area 100B is used to form 6 MOS transistors, including four N-type transistors and two P-type transistors. Therefore, in order not to form an extra P-type transistor in the pull-up transistor area 101U, it is necessary to remove the channel structure 100 located in the to-be-cut area 102B in the pull-up transistor area 101U.

[0081] In this embodiment, the process of removing the channel structure 100 in the to-be-cut area includes an isotropic wet etching process or a dry etching process.

[0082] Taking the dry etching process as an example, the dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is much greater than the lateral etching rate. In the process of removing the channel structure 100 in the area to be cut 102B, a fairly accurate graphic transfer can be obtained. At the same time, the dry etching process has high process controllability, which reduces the probability of damaging the channel structure 100 in the transfer gate transistor area 101G and the pull-down transistor area 101D.

[0083] refer to Figures 11 to 14 , Figure 11 It is a top view. Figure 12 yes Figure 11 Cross-sectional view along CD direction, Figure 13 yes Figure 11 Cross-sectional view along the AB direction, Figure 14 yes Figure 11 In the cross-sectional view along the EF direction, after removing the channel structure 100 in the area to be cut 102B, a dummy gate structure 110 is formed on the top of the substrate 102, spanning the channel structure 100 and the dielectric wall 101 located between the channel structures 100. The dummy gate structure 110 covers part of the top and part of the sidewall of the channel structure 100, as well as part of the top of the dielectric wall 101.

[0084] The dummy gate structure 110 is used to occupy a space for the subsequent formation of a device gate structure.

[0085] The material of the dummy gate structure 110 includes one or more of amorphous silicon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitride, silicon carbonitride, and amorphous carbon. As an example, the material of the dummy gate structure 110 is amorphous silicon.

[0086] Specifically, amorphous silicon has no crystal orientation. Therefore, in the subsequent process of removing the dummy gate structure 110 , the etching rate uniformity and etching effect uniformity of amorphous silicon are better, thereby improving the removal effect of the dummy gate structure 110 .

[0087] The dummy gate structure 110 may be a single-layer structure or a stacked-layer structure. As an example, the dummy gate structure 110 is a single-layer structure.

[0088] It should be noted that, according to process requirements, a gate oxide layer (not shown) may be formed between the dummy gate structure 110 and the channel structure 100. The gate oxide layer may be made of silicon oxide.

[0089] refer to Figures 15 to 17 , Figure 15 It is a top view. Figure 16 yes Figure 15Cross-sectional view along CD direction, Figure 17 yes Figure 15 In the cross-sectional view along the AB direction, the dielectric wall 101 located at the side of the to-be-cut region 102B and covering the sidewall of the trench structure 100 is removed.

[0090] It should be noted that, after removing the dielectric wall 101 located on the side of the to-be-cut region 102B and covering the sidewall of the channel structure 100, in the subsequent process of forming the source-drain doped layer in the channel structure 100 on both sides of the dummy gate structure 110, the spatial position of the source-drain doped layer formed on the side of the to-be-cut region 102B is increased, so that the source-drain doped layer on the side of the to-be-cut region 102B is also extended along the second direction (such as Figure 15 The end face of the dielectric wall 101 (shown in the Y direction) extends to cover part of the width, and accordingly, the contact area between the source-drain interconnection structure formed in the subsequent process and the source-drain doped layer located on the side of the to-be-cut area 102B is increased, thereby improving the electrical connection performance between the source-drain interconnection structure and the source-drain doped layer, thereby improving the performance of the semiconductor structure.

[0091] In this embodiment, after the dummy gate structure 110 is formed, the dielectric wall 101 on the side of the to-be-cut region 102B is removed.

[0092] On the one hand, compared with the solution of first removing the dielectric wall 101 on the side of the area to be cut 102B and then forming the dummy gate structure 110, this embodiment removes the dielectric wall 101 on the side of the area to be cut 102B after forming the dummy gate structure 110, eliminating the need for a photomask, reducing process steps, and lowering process costs.

[0093] On the other hand, after forming the dummy gate structure 110, the dielectric wall 101 on the side of the area to be cut 102B is removed, so that the side wall of the dummy gate structure 110 can be flush with the side wall of the dielectric wall. In the subsequent process of forming the source-drain doping layer in the channel structure 100 on both sides of the dummy gate structure 110, the spatial position of the source-drain doping layer formed on the side of the area to be cut 102B is increased, thereby improving the performance of the semiconductor structure.

[0094] In this embodiment, in the step of removing the dielectric wall 101 on the side of the to-be-cut region 102B, the dummy gate structure 110 is removed to expose the dielectric wall 101 on the side of the to-be-cut region 102B.

[0095] Specifically, the dummy gate structure 110 is removed to expose the dielectric wall 101 on the side of the to-be-cut area 102B, thereby increasing the spatial position for subsequently forming the source-drain doping layer in the channel structure 100 located in the transfer gate transistor area 101G, thereby reducing the process difficulty of forming the source-drain doping layer.

[0096] In this embodiment, after the trench structure 100 in the to-be-cut region 102B is removed, the dielectric wall 101 located on the side of the to-be-cut region 102B and covering the sidewall of the trench structure 100 is removed.

[0097] It should be noted that after removing the channel structure 100 in the area to be cut 102B, the process window for removing the dielectric wall 101 located on the side of the area to be cut 102B and covering the side wall of the channel structure 100 is increased, and the process difficulty of removing the dielectric wall 101 located on the side of the area to be cut 102B and covering the side wall of the channel structure 100 is reduced.

[0098] In this embodiment, a maskless etching method is used to remove the dielectric wall 101 located on the side of the to-be-cut area 102B and covering the sidewall of the trench structure 100 .

[0099] Specifically, the process steps of spin coating photoresist and masking are omitted, and the etching selectivity between the dielectric wall 101 and the channel structure 100 and the dummy gate structure 110 is utilized to remove the dielectric wall 101 located on the side of the to-be-cut area 102B and covering the sidewall of the channel structure 100 in a maskless manner, thereby reducing the process steps, improving the process efficiency, and reducing the process cost.

[0100] It should be noted that, in the process of removing the dielectric wall 101 located on the side of the to-be-cut area 102B and covering the side wall of the channel structure 100, since the dielectric wall 101 located in the to-be-cut area 102B is completely exposed to the plasma and has a larger contact area with the plasma, while the dielectric wall 101 located in the effective area 102A has a smaller contact area with the plasma, under the same etching rate, the dielectric wall 101 located in the to-be-cut area 102B is completely removed, while the dielectric wall 101 located in the effective area 102A is only partially removed.

[0101] In this embodiment, the process for removing the dielectric wall 101 located at the side of the to-be-cut region 102B and covering the sidewall of the trench structure 100 is a plasma dry etching process.

[0102] During the process of removing the dielectric wall 101 by using the plasma dry etching process, plasma is directly used to physically react with the dielectric wall 101, thereby achieving the purpose of removing the dielectric wall 101 located on the side of the to-be-cut area 102B and covering the sidewall of the trench structure 100.

[0103] refer to Figure 16After removing the channel structure 100 in the area to be cut 102B and the dielectric wall 101 located on the side of the area to be cut 102B and covering the sidewall of the channel structure 100, a source-drain doped layer 121 is formed in the channel structure 100 on both sides of the dummy gate structure 110. The source-drain doped layer 121 on the side of the area to be cut 102B is also formed along the second direction (such as Figure 18 The end surface of the dielectric wall 101 (shown in the Y direction) extends to cover part of the width.

[0104] The source-drain doped layer 121 is used as the source region and the drain region of the transistor.

[0105] When forming an NMOS transistor, the source / drain doped layer 121 includes a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, and the stress layer provides tensile stress to the channel region of the NMOS transistor, thereby facilitating improvement of the carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions or Sb ions; when forming a PMOS transistor, the source / drain doped layer 121 includes a stress layer doped with P-type ions, the material of the stress layer is Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, thereby facilitating improvement of the carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions or In ions.

[0106] In this embodiment, the source-drain doped layer 121 located on the side of the to-be-cut area 102B extends along the second direction to cover a portion of the width of the end face of the dielectric wall 101, so that the width of the source-drain doped layer 121 in the to-be-cut area 102B along the second direction becomes larger. Accordingly, in the process of forming the source-drain interconnection structure in the subsequent process, the contact area between the source-drain interconnection structure and the source-drain doped layer 121 is increased, thereby reducing the process difficulty of forming the source-drain interconnection structure. At the same time, the probability of short circuit between the source-drain interconnection structure and the subsequently formed device gate structure is also reduced.

[0107] It should be noted that the source-drain doped layer 121 on the side of the to-be-cut region 102B extends along the second direction to cover the width of the end face of the dielectric wall 101, and the proportion of the width of the dielectric wall 101 should not be too large or too small. If the proportion is too large, the process time for forming the source-drain doped layer 121 is increased, reducing the process efficiency. At the same time, the probability of short circuit between the source-drain doped layers 121 in adjacent pull-up transistor regions 101U along the second direction is increased, thereby affecting the performance of the semiconductor structure. If the proportion is too small, it is easy to cause the contact area between the source-drain doped layer 121 on the side of the to-be-cut region 102B and the subsequently formed source-drain interconnect structure to become smaller, increasing the process difficulty of forming the source-drain interconnect structure and reducing the electrical connection performance between the source-drain interconnect structure and the source-drain doped layer 121, thereby affecting the performance of the semiconductor structure. To this end, in this embodiment, the source / drain doped layer 121 on the side of the to-be-cut region 102B extends along the second direction to cover the width of the end surface of the dielectric wall 101 , accounting for 10% to 100% of the width of the dielectric wall 101 .

[0108] In this embodiment, the process of forming the source / drain doped layer 121 includes an epitaxial process. The epitaxial process has the characteristics of simple operation and low process cost, and can control the growth area of the source / drain doped layer 121 .

[0109] refer to Figures 19 to 22 , Figure 19 It is a top view. Figure 20 yes Figure 19 Cross-sectional view along CD direction, Figure 21 yes Figure 19 Cross-sectional view along the AB direction, Figure 22 yes Figure 19 In the cross-sectional view along the EF direction, after the source-drain doped layer 121 is formed, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer 130 on the substrate 102 exposed by the dummy gate structure 110, the interlayer dielectric layer 130 covering the sidewalls of the dummy gate structure 110; removing the dummy gate structure 110, forming a gate opening (not shown) between the interlayer dielectric layer 130, the gate opening exposing the channel stack 1003; removing the sacrificial layer 1002 exposed by the gate opening; after removing the sacrificial layer 1002 exposed by the gate opening, forming a device gate structure 151 in the gate opening that spans the channel layer 1001 and the dielectric wall 101.

[0110] The interlayer dielectric layer 130 is used to isolate adjacent devices. The interlayer dielectric layer 130 is also used to provide a process basis for removing the dummy gate structure 110 to form a gate opening.

[0111] The interlayer dielectric layer 130 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0112] The gate opening exposes the channel stack 1003 to prepare for the subsequent removal of the sacrificial layer 1002 . The gate opening also provides a spatial location for forming a device gate structure 151 .

[0113] In this embodiment, a selective wet etching process is used to remove the sacrificial layer 1002 exposed by the gate opening. The selective wet etching process is an etching process in which the etching rate of the sacrificial layer 1002 is lower than the etching rate of the channel layer 1001 .

[0114] The selective wet etching process has a lower etching rate for the sacrificial layer 1002 than for the sacrificial layer 1001, so that the channel layer 1001 and the sacrificial layer 1002 can form a larger etching selectivity ratio, which is beneficial for retaining the channel layer 1001 during the removal of the sacrificial layer 1002.

[0115] In this embodiment, the etching solution of the selective wet etching process includes a TMAH solution.

[0116] In this embodiment, the device gate structure 151 includes a gate dielectric layer (not shown) surrounding and covering the channel layer 1001 , and a gate electrode layer (not shown) located on the gate dielectric layer.

[0117] The device gate structure 151 is used to control the opening and closing of the semiconductor device channel.

[0118] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0119] It should be noted that the gate dielectric layer may further include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the channel layer 1001. Specifically, the material of the gate oxide layer may be silicon oxide.

[0120] In this embodiment, the device gate structure 151 is a metal gate structure. Therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0121] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to electrically lead out the metal gate structure.

[0122] In other embodiments, the gate electrode layer may also include only a work function layer.

[0123] In this embodiment, the method for forming the semiconductor structure further includes: forming a sidewall spacer 152 on the sidewall of the device gate structure 151 .

[0124] The sidewall spacers 152 are used to protect the sidewalls of the device gate structure 151. The sidewall spacers 152 can have a single-layer structure or a stacked-layer structure, and the material of the sidewall spacers 152 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall spacers 152 have a single-layer structure and are made of silicon oxide.

[0125] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate including a device unit region; A channel structure layer is located on the substrate in the device unit area, wherein the channel structure extends along a first direction and is arranged in parallel along a second direction, wherein the second direction is perpendicular to the first direction. In the device unit area, the channel structure layer includes a first-type channel structure layer and a second-type channel structure layer. Along the first direction, an end portion of the first-type channel structure layer is indented inward relative to an end portion of the second-type channel structure layer on the same side. a dielectric wall located on the substrate between adjacent channel structure layers, and the dielectric wall covers opposite sidewalls of the channel structure; a device gate structure, located on top of the substrate and spanning the channel structure layer and the dielectric wall, the device gate structure covering a portion of the top and sidewalls of the channel structure layer and the dielectric wall, and a portion of the top of the dielectric wall; The source-drain doped layer is located in the channel structure layer on both sides of the device gate structure, and at the position where the end of the first type of channel structure layer is indented inward, the source-drain doped layer in the second type of channel structure layer also extends along the second direction to cover part of the width or the entire width of the dielectric wall end surface.

2. The semiconductor structure according to claim 1, wherein At a position where the end of the first-type channel structure layer is indented inward, the end of the dielectric wall along the first direction is flush with the sidewall of the device gate structure.

3. The semiconductor structure according to claim 1, wherein: The substrate includes a memory cell region, and the memory cell region includes adjacent and centrally symmetrical device cell regions, and each of the device cell regions includes a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region; The first type of channel structure layer is located in the pull-up transistor area, and the second type of channel structure layer is located in the transfer gate transistor area and the pull-down transistor area. The transfer gate transistor area and the pull-down transistor area share the second type of channel structure layer, and the first type of channel structure layer exposes part of the second type of channel structure layer in the transfer gate transistor area.

4. The semiconductor structure according to claim 1, wherein: At the inwardly retracted position of the end of the first type channel structure layer, the source and drain doping layer in the second type channel structure layer extends along the second direction to cover the width of the dielectric wall end surface, accounting for 10% to 100% of the dielectric wall width.

5. The semiconductor structure according to claim 1, wherein The material of the dielectric wall includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride and silicon boron carbonitride.

6. The semiconductor structure according to claim 1, wherein The device gate structure is a metal gate structure; The device gate structure includes a gate dielectric layer and a gate electrode layer covering the gate dielectric layer; The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

7. The semiconductor structure according to claim 1, wherein: Along the normal direction of the substrate surface, the channel structure layer is spaced apart from the substrate, and the channel structure layer includes one or more spaced apart channel layers; the device gate structure surrounds and covers the top, side and bottom of the channel layer; Alternatively, the channel structure layer is a fin protruding from the substrate.

8. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, including a device unit region, wherein a plurality of channel structures are formed on a top portion of the substrate in the device unit region, wherein the channel structures extend along a first direction and are arranged in parallel along a second direction, wherein the second direction is perpendicular to the first direction, and dielectric walls are formed between adjacent channel structures, wherein the dielectric walls cover opposite sidewalls of the channel structures, and wherein the region where the channel structures are located along the first direction includes an active region and an area to be cut; removing the trench structure of the area to be cut; removing the dielectric wall located at the side of the to-be-cut area and covering the sidewall of the trench structure; After removing the channel structure in the area to be cut, forming a dummy gate structure on top of the substrate, spanning the channel structure and the dielectric wall located between the channel structures, wherein the dummy gate structure covers a portion of the top and sidewall of the channel structure and a portion of the top of the dielectric wall; After removing the channel structure of the area to be cut and the dielectric wall located on the side of the area to be cut and covering the sidewall of the channel structure, a source-drain doped layer is formed in the channel structure on both sides of the pseudo gate structure, and the source-drain doped layer on the side of the area to be cut also extends along the second direction to cover a partial width of the dielectric wall end surface.

9. The method for forming a semiconductor structure according to claim 8, wherein: After forming the dummy gate structure, removing the dielectric wall on the side of the to-be-cut area; In the step of removing the dielectric wall on the side of the to-be-cut region, the dummy gate structure is removed to expose the dielectric wall on the side of the to-be-cut region.

10. The method for forming a semiconductor structure according to claim 8, wherein: In the step of providing a substrate, the substrate includes a memory cell region, and the memory cell region includes adjacent and centrally symmetrical device cell regions, each of the device cell regions includes a transfer gate transistor region, a pull-down transistor region, and a pull-up transistor region, the region where the channel structure in the pull-up transistor region is located includes the to-be-cut region, and the to-be-cut region is adjacent to the pull-down transistor region; In the step of removing the channel structure in the area to be cut, in the transfer gate transistor area, the channel structure located in the area to be cut is removed.

11. The method for forming a semiconductor structure according to claim 8, wherein: The process of removing the trench structure in the area to be cut includes an isotropic wet etching process or a dry etching process.

12. The method for forming a semiconductor structure according to claim 8 or 11, wherein: After removing the trench structure in the area to be cut, removing the dielectric wall located at the side of the area to be cut and covering the sidewall of the trench structure; The dielectric wall located at the side of the to-be-cut area and covering the sidewall of the trench structure is removed by maskless etching.

13. The method for forming a semiconductor structure according to claim 8, wherein: In the step of forming source and drain doping layers in the channel stacks on both sides of the dummy gate structure, the source and drain doping layers on the side of the to-be-cut area extend along the second direction to cover the width of the dielectric wall end surface, accounting for 10% to 100% of the dielectric wall width.

14. The method for forming a semiconductor structure according to claim 8, wherein: In the step of providing a substrate, the channel structure includes a plurality of channel stacks, each of the channel stacks includes a channel layer and a sacrificial layer located on the channel layer; After forming the source-drain doped layer, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer on the substrate exposed by the dummy gate structure, the interlayer dielectric layer covering the sidewalls of the dummy gate structure; removing the dummy gate structure, forming a gate opening between the interlayer dielectric layers, the gate opening exposing the channel stack; removing the sacrificial layer exposed by the gate opening; after removing the sacrificial layer exposed by the gate opening, forming a device gate structure in the gate opening that spans the channel layer and the dielectric wall.

15. The method for forming a semiconductor structure according to claim 8, wherein: The process of forming the source-drain doping layer includes an epitaxial process.

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