semiconductor devices

Abstract

This disclosure provides a semiconductor device, including: a substrate, a support layer, and a plurality of lower electrodes; in a top view of the support layer and the plurality of lower electrodes, the plurality of lower electrodes are arranged separately from each other in a first direction and a second direction, the lower electrodes in the same column are aligned in the second direction, and any two adjacent columns of lower electrodes are staggered in the first direction; in the top view, there are four consecutive columns of lower electrodes at the outermost edge, which are arranged sequentially from the outside to the inside as a first column of lower electrodes, a second column of lower electrodes, a third column of lower electrodes, and a fourth column of lower electrodes, the first column of lower electrodes having a first bottom position, the second column of lower electrodes having a second bottom position, the third column of lower electrodes having a third bottom position, and the fourth column of lower electrodes having a fourth bottom position; wherein, the first bottom position and the third bottom position are aligned with each other in the first direction, the fourth bottom position is lower than the first bottom position, and the second bottom position is higher than the first bottom position.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor technology, and specifically relates to a semiconductor device. Background Technology

[0002] This section is intended to provide background or context for the embodiments set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section.

[0003] Dynamic random access memory (DRAM) is a volatile memory and an indispensable key component in many electronic products. DRAM is an array of a large number of memory cells used to store data, and each memory cell can be composed of a metal oxide semiconductor (MOS) transistor and a capacitor connected in series.

[0004] The capacitor structure forms a large array. To increase the density of the capacitor structure, its lower electrode is usually columnar or cup-shaped. The cup-shaped or columnar lower electrode array is arranged in this way. The lower electrodes at the edges and corners are prone to collapse or drift. Summary of the Invention

[0005] This disclosure provides a semiconductor device.

[0006] This disclosure provides a semiconductor device comprising: a substrate, a support layer, and a plurality of lower electrodes; in a top view of the support layer and the plurality of lower electrodes, the plurality of lower electrodes are arranged separately from each other in a first direction and a second direction, the lower electrodes in the same column are aligned in the second direction, and any two adjacent columns of lower electrodes are staggered in the first direction; in the top view, there are four consecutive columns of lower electrodes at the outermost edge, which are arranged sequentially from the outside to the inside as a first column of lower electrodes, a second column of lower electrodes, a third column of lower electrodes, and a fourth column of lower electrodes, wherein the first column of lower electrodes has a first bottom position, the second column of lower electrodes has a second bottom position, the third column of lower electrodes has a third bottom position, and the fourth column of lower electrodes has a fourth bottom position; wherein the first bottom position and the third bottom position are aligned with each other in the first direction, the fourth bottom position is lower than the first bottom position, and the second bottom position is higher than the first bottom position.

[0007] Some technical solutions disclosed herein provide a semiconductor device, including: a substrate, a support layer, and a plurality of lower electrodes; a top view of the support layer and the plurality of lower electrodes is located in the XOY plane, with the origin O at the corner of the lower electrode, the plurality of lower electrodes are arranged in multiple columns along the Y-axis, the positive direction of the Y-axis pointing from the origin O to the next lower electrode aligned along the Y-axis, the X-axis is perpendicular to the Y-axis, and the positive direction of the X-axis pointing from the origin O to a column of lower electrodes located in the central region; in the top view, the coordinates of the bottom lower electrode of the first column of lower electrodes along the positive X-axis are (0, 0), the coordinates of the bottom lower electrode of the second column of lower electrodes along the positive X-axis are (1, d), the coordinates of the bottom lower electrode of the second column of lower electrodes along the positive X-axis are (2, 0), the coordinates of the bottom lower electrode of the third column of lower electrodes along the positive X-axis are (3, -d), and the lower electrodes continue to be arranged in a cycle along the bottom of the positive X-axis, where the X coordinate represents the column number of the lower electrode and the Y coordinate represents the spatial position of the lower electrode on the Y-axis.

[0008] This disclosure provides a semiconductor device comprising: a substrate, a support layer, and multiple rows of lower electrodes; a top view of the support layer and the multiple rows of lower electrodes is located in the XOY plane, with the origin O located in the middle region of the support layer, and each electrode in each row of lower electrodes arranged along the Y-axis; starting from any corner lower electrode in at least one corner lower electrode and moving towards the Y-axis, the distance from the end lower electrode on the same side as the corner lower electrode in a series of lower electrodes to the X-axis monotonically decreases and then monotonically increases, the distance from the corner lower electrode to the X-axis is a first distance, the series of lower electrodes are located on the same side of the Y-axis, and the distance from the end lower electrode on the same side of the corner lower electrode in the series of lower electrodes to the X-axis is a second distance, the first distance being less than the second distance.

[0009] Some of the technical solutions disclosed herein help to improve the structural stability of the lower electrode in the corner region. Attached Figure Description

[0010] Figure 1 This is a top view of a portion of the structure of a semiconductor device according to an embodiment of this disclosure.

[0011] Figure 2 yes Figure 1 The semiconductor device shown is a cross-sectional view along line AA.

[0012] Figure 3 yes Figure 1 A variation of the cross-sectional view of the semiconductor device shown along line AA.

[0013] Figure 4 This is a top view of a portion of the structure of a semiconductor device according to an embodiment of the present disclosure, showing a schematic diagram of the center line connecting the outermost lower electrode.

[0014] Figure 5 This is a top view of a portion of the structure of a semiconductor device according to other embodiments of this disclosure.

[0015] Figure 6 This is an overlay schematic diagram of the layout structure of an embodiment of the present disclosure.

[0016] Figure 7 This is an overlay schematic diagram of the layout structure of another embodiment of this disclosure.

[0017] Figures 8 to 12 This is a schematic diagram of an intermediate state of a method for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0018] The attached markings are as follows: O, origin of coordinates; X, X-axis direction; Y, Y-axis direction; 1, 10, substrate; 11, base; 12, contact pad; 13, dielectric layer; 20, feature film layer; 2, 40, lower electrode; 21, dummy lower electrode; 22, effective lower electrode; 22a, invalid segment; 21a, effective segment; 30, mask layer; 14, 3, support layer; 31, opening area; 10a, opening; 50, masking layer; 50a, opening; L, center line connecting the lower electrodes on the same side of multiple rows of lower electrodes; x0, dimension of the edge region extending along the Y-axis direction in the X-axis direction; y0, dimension of the edge region extending along the X-axis direction in the Y-axis direction; 110, effective regular pattern; 120, invalid regular pattern; 200, mask pattern; 300, masking pattern; 300a, cutout area. Detailed Implementation

[0019] The present disclosure will be further described below with reference to the embodiments shown in the accompanying drawings.

[0020] This disclosure provides a semiconductor device, including: a substrate 1, a support layer 3, and a plurality of lower electrodes 2.

[0021] refer to Figure 5 In a top view of the support layer 3 and the plurality of lower electrodes 2, the plurality of lower electrodes 2 are arranged separately from each other in the first direction and the second direction, the lower electrodes 2 in the same column are aligned in the second direction, and any two adjacent columns of lower electrodes 2 are staggered in the first direction (the horizontal height of one column of lower electrodes 2 is different from the horizontal height of the other column of lower electrodes 2).

[0022] In the top view, there are four consecutive columns of lower electrodes 2 at the outermost edge, which are arranged in order from the outside to the inside as the first column of lower electrodes 2, the second column of lower electrodes 2, the third column of lower electrodes 2 and the fourth column of lower electrodes 2. The first column of lower electrodes 2 has a first bottom position, the second column of lower electrodes 2 has a second bottom position, the third column of lower electrodes 2 has a third bottom position and the fourth column of lower electrodes 2 has a fourth bottom position.

[0023] Wherein, the first bottom position and the third bottom position are aligned with each other in the first direction (with the same horizontal height), the fourth bottom position is lower than the first bottom position, and the second bottom position is higher than the first bottom position.

[0024] Figure 5 This shows the characteristics of the bottom positions of the four consecutive columns of lower electrodes 2 on the far left. Of course, the bottoms of the four consecutive columns of lower electrodes 2 on the far right can also satisfy the same characteristics.

[0025] If the top view is rotated 180°, then equivalently, the top positions of the four consecutive columns of lower electrodes 2 on the far left and / or the top positions of the four consecutive columns of lower electrodes 2 on the far right can also satisfy the same characteristics.

[0026] The inventors of this disclosure have discovered that, in related technologies, the lower electrode 2 at the outermost corner is prone to collapse or drift. (Reference) Figure 5 In this embodiment, the lower electrode 2 at the lower left corner is not the lowest position, and the density of the lower electrodes 2 around it is relatively large, which helps to improve the structural stability of the lower electrode at the lower left corner.

[0027] Continue to refer to Figure 4 In the top view, the lines connecting the bottom positions of each column of lower electrodes 2 are wavy lines, with the peaks of the wavy lines aligned with each other in the first direction and the troughs of the wavy lines aligned with each other in the first direction.

[0028] Specifically, in the top view, a lower electrode 2 is disposed between the crest of the wavy line and its nearest neighboring trough. The height difference between the crest and the trough is relatively small. Of course, in other embodiments, multiple lower electrodes 2 are disposed between the crest of the wavy line and its nearest neighboring trough.

[0029] Continue to refer to Figure 5The plurality of lower electrodes 2 are divided into effective lower electrodes 22 located in the central region and dummy lower electrodes 21 located in the edge region surrounding the central region. The support layer 3 is provided with a plurality of opening regions 31, the plurality of opening regions 31 exposing at least a portion of the outer peripheral surface of each of the effective lower electrodes 22. The support layer 3 completely surrounds the outer peripheral surface of the dummy lower electrodes 21, and the edge region is a closed ring.

[0030] In the top view, the area where the dummy lower electrode 21 is located to the left of the minimum enclosing rectangle of the effective lower electrode 22 has a first dimension x0 along the first direction, and the area where the dummy lower electrode 21 is located below the minimum enclosing rectangle has a second dimension y0 along the second direction. The first dimension x0 is smaller than the second dimension y0.

[0031] In this top view, the outer boundaries of the dummy lower electrodes 21 on the left and right sides of the effective lower electrode 22 are relatively flat, while the outer boundaries of the dummy lower electrodes 21 on the top and bottom sides of the effective lower electrode 22 are not flat. In order to improve the structural stability of the dummy lower electrodes 21 on the top and bottom sides of the effective lower electrode 22, the dimensions of the dummy lower electrodes 21 on the top and bottom sides of the effective lower electrode 22 in the second direction are relatively increased.

[0032] Continue to refer to Figure 5 In the top view, the support layer 3 has a wavy lower boundary, the crest of the wavy lower boundary is aligned with the crest of the wavy line in a second direction, and the trough of the wavy lower boundary is aligned with the trough of the wavy line in a second direction.

[0033] The outer boundary shape of the support layer 3 is adapted to the outer contour shape of the lower electrode 2, which can save the area occupied by the support layer 3 and provide good support for the lower electrode 2.

[0034] Continue to refer to Figure 2 The lower electrode 2 is a solid column.

[0035] Continue to refer to Figure 3 The lower electrode 2 is cup-shaped, and the opening direction of the cup-shaped lower electrode 2 is away from the substrate 1.

[0036] Furthermore, the semiconductor device also includes a dielectric layer (not shown) covering the lower electrode 2 and the support layer 3, and an upper electrode (not shown) covering the dielectric layer, wherein the upper electrode, the dielectric layer, and the multiple rows of lower electrodes 2 form a multiple row capacitor.

[0037] Based on the same inventive concept, and referring to Figure 5The present disclosure also provides a semiconductor device, including: a substrate 1, a support layer 3, and a plurality of lower electrodes 2; characterized in that, a top view of the support layer 3 and the plurality of lower electrodes 2 is located in the XOY plane, the origin O of the coordinate system is located at the lower electrode 2 at the far corner, the plurality of lower electrodes 2 are arranged in multiple columns along the Y-axis direction, the positive direction of the Y-axis points from the origin O to the next lower electrode 2 aligned along the Y-axis, the X-axis is perpendicular to the Y-axis, and the positive direction of the X-axis points from the origin O to a column of lower electrodes 2 located in the central region;

[0038] In the top view, the coordinates of the bottom lower electrode 2 in the first column along the positive X-axis are (0,0), the coordinates of the bottom lower electrode 2 in the second column along the positive X-axis are (1,d), the coordinates of the bottom lower electrode 2 in the second column along the positive X-axis are (2,0), and the coordinates of the bottom lower electrode 2 in the third column along the positive X-axis are (3,-d). The bottom lower electrodes 2 are arranged in a cycle along the positive X-axis, where the X coordinate represents the column number of the lower electrode 2 and the Y coordinate represents the spatial position of the lower electrode 2 on the Y-axis.

[0039] Figure 5 The diagram shows the case where the origin of the coordinate system is located at the lower left corner of electrode 2. It should be understood that the origin of the coordinate system can also be located at the lower right corner of electrode 2, or at the upper left corner of electrode 2, or at the upper right corner of electrode 2.

[0040] The lower electrode 2 at the outermost corner is prone to collapse or drift. (Reference) Figure 5 In this embodiment, the lower electrode 2 at the lower left corner is not the lowest position, and the density of the lower electrodes 2 around it is relatively large, which helps to improve the structural stability of the lower electrode at the lower left corner.

[0041] Continue to refer to Figure 5 The plurality of lower electrodes 2 are divided into effective lower electrodes 22 located in the central region and dummy lower electrodes 21 located in the edge region surrounding the central region. The support layer 3 is provided with a plurality of opening regions 31, the plurality of opening regions 31 exposing at least a portion of the outer peripheral surface of each of the effective lower electrodes 22. The support layer 3 completely surrounds the outer peripheral surface of the dummy lower electrodes 21, and the edge region is a closed ring.

[0042] In the top view, the area where the dummy lower electrode 21 is located on the left side of the smallest enclosing rectangle that surrounds all the effective lower electrodes 22 has a first dimension x0 along the first direction, and the area where the dummy lower electrode 21 is located below the smallest enclosing rectangle has a second dimension y0 along the second direction. The first dimension x0 is smaller than the second dimension y0.

[0043] In this top view, the outer boundaries of the dummy lower electrodes 21 on the left and right sides of the effective lower electrode 22 are relatively flat, while the outer boundaries of the dummy lower electrodes 21 on the top and bottom sides of the effective lower electrode 22 are not flat. In order to improve the structural stability of the dummy lower electrodes 21 on the top and bottom sides of the effective lower electrode 22, the dimensions of the dummy lower electrodes 21 on the top and bottom sides of the effective lower electrode 22 in the second direction are relatively increased.

[0044] Specifically, in the top view, the support layer 3 has a wavy lower boundary, the crest of which is aligned with the bottom lower electrode 2 of the column numbered 4n+2 in the second direction, and the trough of which is aligned with the bottom lower electrode 2 of the column numbered 4n+4 in the second direction, where n is a non-negative integer.

[0045] That is, there is a gap of 1 column between the column containing the peak and the column containing the trough of the wave, and then there is a gap of 2 or more columns between the columns containing the peak and the column containing the trough of the wave.

[0046] Based on the same inventive concept, and referring to Figures 1 to 4 The present disclosure also provides a semiconductor device, including: a substrate 1, a support layer 3 and multiple rows of lower electrodes 2; the top view of the support layer 3 and the multiple rows of lower electrodes 2 is located in the XOY plane, the origin O of the coordinate system is located in the middle region of the support layer 3, and each electrode in each row of lower electrodes 2 is arranged along the Y-axis direction;

[0047] Starting from any one of the corner lower electrodes 2 and moving towards the Y-axis, the distance from the end lower electrodes 2 on the same side as the corner lower electrode 2 of a series of consecutive lower electrodes 2 to the X-axis monotonically decreases and then monotonically increases. The distance from the corner lower electrode 2 to the X-axis is a first distance d1. The series of consecutive lower electrodes 2 are located on the same side of the Y-axis. The distance from the end lower electrode 2 on the same side as the corner lower electrode 2 of the series of consecutive lower electrodes 2 to the X-axis is a second distance d2. The first distance d1 is less than the second distance d2.

[0048] For example, in this top view, starting from the lower electrode 2 in the lower left corner and moving to the right, the distance from the lower endpoint of multiple consecutive columns of lower electrodes 2 to the x-axis first decreases monotonically and then increases monotonically. Furthermore, the lower endpoint of the column of lower electrodes 2 that is closest to the x-axis is lower than the lower electrode in the lower left corner.

[0049] For example, in this top view, starting from the lower electrode 2 in the lower right corner and moving to the left, the distance from the lower endpoint of multiple consecutive columns of lower electrodes 2 to the x-axis first decreases monotonically and then increases monotonically. Furthermore, the lower endpoint of the column of lower electrodes 2 that is closest to the x-axis is lower than the lower electrode in the lower right corner.

[0050] For example, in this top view, starting from the lower electrode 2 in the upper left corner and moving to the right, the distance from the upper endpoint of multiple consecutive lower electrodes 2 to the x-axis first decreases monotonically and then increases monotonically. Furthermore, the upper endpoint of the lower electrode 2 in the consecutive lower electrodes that is closest to the x-axis is higher than the lower electrode in the upper left corner.

[0051] For example, in this top view, starting from the lower electrode 2 in the upper right corner and moving to the left, the distance from the lower endpoint of multiple consecutive columns of lower electrodes 2 to the x-axis first decreases monotonically and then increases monotonically. Furthermore, the upper endpoint of the column of lower electrodes 2 that is closest to the x-axis is higher than the position of the lower electrode in the upper right corner.

[0052] It should be noted that the above optimization of the electrode position relationship in the four corner regions of the top view can be implemented in all four corner regions, or only in some of the corner regions.

[0053] The lower electrode 2 at the outermost corner is prone to collapse or drift. (Reference) Figure 1 and Figure 4 In this embodiment, the lower electrode 2 at the corner is not the outermost, and the density of the lower electrodes 2 around it is relatively large, which helps to improve the structural stability of the lower electrode at the corner.

[0054] Optionally, refer to Figure 1 In the top view, the center line L connecting the ends of the lower electrodes 2 on at least one side of the multiple lower electrodes 2 is wavy, and the extension direction of the wavy center line L is the X-axis direction.

[0055] Specifically, the repeating period of the wavy center line L is an isosceles triangle.

[0056] Continue to refer to Figure 1 At the point where the distance from the center line L of the wave-shaped curve to the X-axis reaches its maximum, the center line L of the wave-shaped curve forms an obtuse angle. The environment of the lower electrode 2 at this maximum distance point is closer to that of the lower electrode 2 in the central region, which is beneficial to improving the structural stability of the lower electrode 2 at this maximum distance point.

[0057] Furthermore, at the point where the distance from the center line L of the wave-shaped curve to the X-axis is at its minimum, the center line L of the wave-shaped curve forms an obtuse angle.

[0058] Continue to refer to Figure 1The multiple rows of lower electrodes 2 are divided into effective lower electrodes 22 located in the central region and dummy lower electrodes 21 located in the edge region surrounding the central region. The support layer 3 is provided with multiple opening regions 31, which expose at least part of the outer peripheral surface of the effective lower electrodes 22. The support layer 3 completely surrounds the outer peripheral surface of the dummy lower electrodes 21, and the edge region is a closed ring.

[0059] The dimension x0 of the edge region extending along the Y-axis direction in the edge region is smaller than the dimension y0 of the edge region extending along the X-axis direction in the edge region.

[0060] In this top view, the outer boundaries of the dummy lower electrodes 21 on the left and right sides of the effective lower electrode 22 are relatively flat, while the outer boundaries of the dummy lower electrodes 21 on the top and bottom sides of the effective lower electrode 22 are not flat. In order to improve the structural stability of the dummy lower electrodes 21 on the top and bottom sides of the effective lower electrode 22, the dimensions of the dummy lower electrodes 21 on the top and bottom sides of the effective lower electrode 22 in the second direction are relatively increased.

[0061] Continue to refer to Figure 4 In the top view, the center line connecting the outermost ring of lower electrodes 2 includes: two straight lines extending along the Y-axis, and a wavy line connecting the endpoints of the two straight lines on the same side.

[0062] Further reference Figure 1 The dimensions of the support layer 3 extending beyond the same side end of the multiple rows of lower electrodes 2 along the Y-axis direction are equal.

[0063] The shape of the lower boundary of the support layer 3 matches the shape of the line connecting the lower ends of the multiple rows of lower electrodes 2, which can effectively support the outermost lower electrode 2 and reduce the area occupied by the support layer 3.

[0064] refer to Figure 2 The lower electrode 2 is a solid column.

[0065] refer to Figure 3 The lower electrode 2 is cup-shaped, and the opening direction of the cup-shaped lower electrode 2 is away from the substrate 1.

[0066] Furthermore, the semiconductor device also includes a dielectric layer (not shown) covering the lower electrode 2 and the support layer 3, and an upper electrode (not shown) covering the dielectric layer, wherein the upper electrode, the dielectric layer, and the multiple rows of lower electrodes 2 form a multiple row capacitor.

[0067] Substrate 1 is, for example, a silicon substrate or other type of semiconductor substrate. A transistor (not shown) driving the lower electrode 2 and data lines (not shown) connecting the transistor are also disposed in substrate 1. Substrate 1 can be designed according to existing technology.

[0068] It should be noted that in the top view, the wavy center line L refers to the center line periodically rising and then falling monotonically, and does not limit the center line L to rising or falling linearly.

[0069] Based on the same inventive concept, and referring to Figure 6 The embodiments of this disclosure also provide a layout structure, including: a feature pattern, the feature pattern including a pattern array composed of a plurality of regular graphics; and a mask pattern 200 for masking the feature pattern to cover invalid regular graphics 120 located at the edge of the pattern array and expose the valid regular graphics 110 in the pattern array surrounded by the mask pattern 200.

[0070] The effective regular graphics 110 are arranged in multiple columns along the Y-axis direction, with four consecutive columns of effective regular graphics 110 at the outermost edge. They are arranged in order from the outside inward as the first column of effective regular graphics 110, the second column of effective regular graphics 110, the third column of effective regular graphics 110, and the fourth column of effective regular graphics 110. The first column of effective regular graphics 110 has a fifth bottom position, the second column of effective regular graphics 110 has a sixth bottom position, the third column of effective regular graphics 110 has a seventh bottom position, and the fourth column of effective regular graphics 110 has an eighth bottom position.

[0071] Wherein, the fifth bottom position and the seventh bottom position are aligned with each other in the X-axis direction, the eighth bottom position is lower than the fifth bottom position, and the sixth bottom position is higher than the fifth bottom position;

[0072] The origin of the coordinate system is located in the middle of the mask pattern, and the four consecutive columns of valid regular patterns 110 at the outermost edge are located on the same side of the Y-axis.

[0073] Specifically, the center line L1 connecting the effective regular patterns 110 on the same side of each column of effective regular patterns 110 is a wavy shape extending along the X-axis.

[0074] Specifically, the distance from any corner valid regular pattern in at least one corner valid regular pattern to the X-axis is the third distance d3; the distance from the end valid regular pattern on the same side of the column of valid regular patterns closest to the corner valid regular pattern to the X-axis is the fourth distance d4; and the distance from the X-axis to the peak or trough of the wavy center line L that is the largest distance from the X-axis is the fifth distance d5. The origin of the coordinate system is located in the middle of the mask pattern, and the fourth distance d4 is less than the third distance d3, and the third distance d3 is less than the fifth distance d5.

[0075] During the formation of the semiconductor device, an effective regular pattern 110 is transferred into the semiconductor device, for example, to form the lower electrode of a capacitor. A mask pattern 200 is transferred into the semiconductor device to define the distribution area of ​​the lower electrode. Thus, a lower electrode array as provided in the foregoing embodiments can be obtained.

[0076] Specifically, the shape of the regular graphic can be a square, a rhombus, or an ellipse.

[0077] Based on the same inventive concept, embodiments of this disclosure also provide a method for forming a semiconductor device, comprising:

[0078] A substrate is provided, and a feature film layer is formed on the substrate, the feature film layer defining a grid array on the substrate, the pattern of the grid array corresponding to the aforementioned feature patterns 110, 120;

[0079] A mask layer is formed on the feature film layer, the pattern of the mask layer corresponding to the aforementioned mask pattern 200, so that the mask layer covers the invalid cells located at the edges of the segmentation array and exposes the valid cells surrounded in the segmentation array; and the substrate is patterned with the mask layer and the feature film layer as masks to copy the pattern of the valid cells in the feature film layer to the substrate to form an aperture array on the substrate.

[0080] An array of apertures is used, for example, to form a capacitor array in a dynamic random access memory. Specifically, each aperture is used to form the lower electrode of a capacitor.

[0081] Further, refer to Figure 7 Some embodiments of this disclosure also provide a layout structure, including:

[0082] The aforementioned feature pattern and mask pattern 200; and,

[0083] Masking pattern 300 is used to mask the feature pattern defined by the masking pattern 200;

[0084] The feature pattern defined by the mask pattern 200 includes a plurality of valid regular patterns 110, and at least some of the valid regular patterns 110 are combined to form a pattern group, wherein the pattern group is composed of a plurality of valid regular patterns 110 arranged in close proximity; and the masking pattern 300 has a plurality of cutout areas 300a, each of the cutout areas 300a corresponding to a pattern group, wherein the cutout area 300a extends from the center of the pattern group toward each valid regular pattern 110 in the pattern group to expose the area between the plurality of valid regular patterns 110 in the pattern group, and exposes a portion of each valid regular pattern 110 in the pattern group.

[0085] Specifically, the hollow area is used, for example, to form the opening region 31 of the support layer 3.

[0086] Based on the same inventive concept, embodiments of this disclosure also provide a method for forming a semiconductor device, comprising:

[0087] A substrate is provided, and a feature film layer is formed on the substrate, the feature film layer defining a grid array on the substrate, the pattern of the grid array corresponding to the feature pattern as described above; a mask layer is formed on the feature film layer, the pattern of the mask layer corresponding to the mask pattern 200 as described above, such that the mask layer covers invalid grids located at the edges of the grid array and exposes the valid grids surrounded within the grid array; and the substrate is patterned using the mask layer and the feature film layer as masks to copy the pattern of the valid grids in the feature film layer to the substrate to form an aperture array in the substrate; the mask layer and the feature film layer are removed, and a lower electrode is formed on the inner wall of each aperture in the aperture array; a cover layer is formed on the substrate, the pattern of the cover layer corresponding to the cover pattern 300 as described above, such that the cover layer has a plurality of openings corresponding to the cutout area 300a; through the openings, at least the substrate material exposed in the openings is removed.

[0088] The hollow area 300a corresponds to the opening area 31 of the support layer 3.

[0089] In a specific example, first refer to Figure 8 A substrate 10 is provided, and a feature film layer 20 is formed on the substrate 10. The feature film layer 20 defines a grid array on the substrate 10. The pattern of the grid array corresponds to the feature pattern described above. The specific pattern of the feature pattern can be referred to the above description and will not be repeated here. That is, in this embodiment, the pattern of each grid in the grid array defined by the feature film layer 20 corresponds to the regular pattern described above.

[0090] Continue to refer to Figure 8A mask layer 30 is formed on the feature film layer 20, and the pattern in the mask layer 30 can refer to the mask pattern 200 as described above. That is, the mask layer 30 covers the invalid cells 22a located at the edges of the grid array and exposes the valid cells 21a surrounded in the grid array.

[0091] Next, refer to Figure 9 The substrate is patterned using the mask layer 30 and the feature film layer 20 as masks to replicate the effectively segmented pattern in the feature film layer 20 onto the substrate 10, thereby forming an opening 10a in the substrate 10. The pattern of the opening 10a formed in the substrate 10 can be a centrally symmetrical pattern, such as a circle. Specifically, the substrate 10 may include: a substrate 11, in which a storage transistor (not shown) is also formed; contact pads 12 and a dielectric layer 13 formed on the substrate 11, the contact pads 12 for connecting the storage transistor and a subsequently formed storage capacitor; and a support layer 14 interspersed in the dielectric layer 13 for supporting the subsequently formed storage capacitor. After the opening 10a is formed through the above steps, the opening 10a exposes the contact pads 12.

[0092] For details, please refer to the following: Figure 10 As shown, the mask layer and the feature film layer are removed, and a lower electrode 40 is formed on the inner wall of each opening 10a in the aperture array. The lower electrode 40 is electrically connected to the contact pad 12 in the substrate 10. As described above, the bottom of the contact pad 12 is connected to the storage transistor (not shown) in the substrate 10, and the top of the contact pad 12 is connected to the lower electrode 40 of the storage capacitor.

[0093] Next, refer to Figure 11 As shown, a masking layer 50 is formed on the substrate 10, and the pattern of the masking layer 50 corresponds to the masking pattern, so that the masking layer 50 has a plurality of openings 50a corresponding to the cutout area. At this time, the openings 50a partially expose the openings.

[0094] Next, refer to Figure 12 As shown, at least the substrate material exposed in the opening 50a is removed through the opening 50a. Specifically, through the opening 50a, the substrate material (including a portion of the support layer 14) directly below the opening 50a can first be removed using a dry etching process; then, the dielectric layer 13 can be removed using a wet etching process. During the removal of the dielectric layer 13, the etchant enters from the opening 50a and diffuses along a direction parallel to the surface of the substrate 10 to etch the portion of the dielectric layer 13 covered by the masking layer 50, thereby exposing the inner and outer surfaces of the lower electrode 40.

[0095] The various embodiments in this disclosure are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0096] The scope of protection of this disclosure is not limited to the embodiments described above. Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its scope and spirit. If such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, then the intent of this disclosure also includes such modifications and variations.

Claims

1. A semiconductor device, comprising: A substrate (1), a support layer (3) and a plurality of lower electrodes (2); characterized in that In a plan view of the support layer (3) and the plurality of lower electrodes (2), the plurality of lower electrodes (2) are arranged in a first direction and a second direction, and are separated from each other, the same column of lower electrodes (2) are arranged in alignment in the second direction, and any two adjacent columns of lower electrodes (2) are arranged in staggered arrangement in the first direction. In the plan view, there are four continuous columns of lower electrodes (2) at the edge, which are the first column of lower electrodes (2), the second column of lower electrodes (2), the third column of lower electrodes (2) and the fourth column of lower electrodes (2) in turn from outside to inside, the first column of lower electrodes (2) has a first bottom position, the second column of lower electrodes (2) has a second bottom position, the third column of lower electrodes (2) has a third bottom position, and the fourth column of lower electrodes (2) has a fourth bottom position. Wherein, the first bottom position and the third bottom position are aligned with each other in the first direction, the fourth bottom position is lower than the first bottom position, and the second bottom position is higher than the first bottom position. In the plan view, the connecting line of the bottom position of each column of lower electrodes (2) is a wavy connecting line, the wave crests of the wavy connecting line are aligned with each other in the first direction, the wave troughs of the wavy connecting line are aligned with each other in the first direction, the support layer (3) has a wavy lower boundary, the wave crests of the wavy lower boundary are aligned with the wave crests of the wavy connecting line in the second direction, the wave troughs of the wavy lower boundary are aligned with the wave troughs of the wavy connecting line in the second direction, and the outer boundary of the support layer (3) is adapted to the shape of the outer contour of the lower electrode (2).

2. The semiconductor device according to claim 1, wherein In the plan view, there is one lower electrode (2) between the wave crest and the nearest adjacent wave trough of the wavy connecting line.

3. The semiconductor device of claim 1, wherein The plurality of lower electrodes (2) are divided into effective lower electrodes (22) located in a middle region and dummy lower electrodes (21) located in an edge region surrounding the middle region, a plurality of opening regions (31) are provided on the support layer (3), the plurality of opening regions (31) expose part of the outer circumferential surface of each of at least part of the effective lower electrodes (22), the support layer (3) completely surrounds the outer circumferential surface of the dummy lower electrodes (21), and the edge region is a closed ring shape. In the plan view, the size of the area where the dummy lower electrode (21) on the left side of the minimum enclosing rectangle of the effective lower electrode (22) is in the first direction is a first size, and the size of the area where the dummy lower electrode (21) below the minimum enclosing rectangle is in the second direction is a second size, and the first size is smaller than the second size.

4. The semiconductor device of claim 1, wherein The lower electrode (2) is in the shape of a solid column; or the lower electrode (2) is in the shape of a cup, and the opening direction of the cup-shaped lower electrode (2) is away from the substrate (1).

5. The semiconductor device of claim 1, wherein The semiconductor device further comprises a dielectric layer covering the lower electrode (2) and the support layer (3), and an upper electrode covering the dielectric layer, and the upper electrode, the dielectric layer and a plurality of columns of lower electrodes (2) form a plurality of columns of capacitors.

6. A semiconductor device comprising: A substrate (1), a support layer (3) and a plurality of lower electrodes (2); characterized in that, in a top view of the support layer (3) and the plurality of lower electrodes (2), the coordinate origin O is located at the lower electrode (2) at the most corner, the plurality of lower electrodes (2) are arranged in multiple columns along the Y-axis direction, the positive direction of the Y-axis is directed to the next lower electrode (2) aligned along the Y-axis, the X-axis is perpendicular to the Y-axis, and the positive direction of the X-axis is directed to the lower electrode (2) in the center area; In the top view, the coordinates of the bottommost lower electrode (2) in the first column of lower electrodes (2) along the positive direction of the X-axis are (0, 0), the coordinates of the bottommost lower electrode (2) in the second column of lower electrodes (2) along the positive direction of the X-axis are (1, d), the coordinates of the bottommost lower electrode (2) in the third column of lower electrodes (2) along the positive direction of the X-axis are (2, 0), and the coordinates of the bottommost lower electrode (2) in the fourth column of lower electrodes (2) along the positive direction of the X-axis are (3, -d), and the bottommost lower electrode (2) is arranged in a cycle along the positive direction of the X-axis, wherein the X-coordinate represents the column number of the lower electrode (2), and the Y-coordinate represents the spatial position of the lower electrode (2) on the Y-axis; in the top view, the connecting line of the bottom position of each column of lower electrodes (2) is a wavy line, the wave crests of the wavy line are aligned with each other in the X-axis direction, the wave troughs of the wavy line are aligned with each other in the X-axis direction, the support layer (3) has a wavy lower boundary, the wave crests of the wavy lower boundary are aligned with the wave crests of the wavy line in the Y-axis direction, the wave troughs of the wavy lower boundary are aligned with the wave troughs of the wavy line in the Y-axis direction, and the outer boundary shape of the support layer (3) is adapted to the shape of the outer contour of the lower electrode (2).

7. The semiconductor device of claim 6, wherein, The plurality of lower electrodes (2) are divided into effective lower electrodes (22) located in a central area and dummy lower electrodes (21) located in an edge area surrounding the central area, a plurality of opening regions (31) are provided on the support layer (3), the plurality of opening regions (31) expose part of the outer circumferential surface of each of at least part of the effective lower electrodes (22), the support layer (3) completely surrounds the outer circumferential surface of the dummy lower electrodes (21), and the edge area is in the form of a closed ring; In the top view, the size of the area where the dummy lower electrode (21) on the left side of the smallest enclosing rectangle enclosing all the effective lower electrodes (22) is along a first direction is a first size, and the size of the area where the dummy lower electrode (21) below the smallest enclosing rectangle is along a second direction is a second size, and the first size is smaller than the second size.

8. The semiconductor device of claim 6, wherein, In the top view, the support layer (3) has a wavy lower boundary, the wave crests of the wavy lower boundary are aligned with the bottommost lower electrode (2) of a column of lower electrodes (2) with a column number of 4n+2 in the second direction, the wave troughs of the wavy lower boundary are aligned with the bottommost lower electrode (2) of a column of lower electrodes (2) with a column number of 4n+4 in the second direction, and n is a non-negative integer.

9. A semiconductor device comprising: A substrate (1), a support layer (3) and a plurality of columns of lower electrodes (2); characterized in that a plan view of the support layer (3) and the plurality of columns of lower electrodes (2) lies in an XOY plane, with a coordinate origin O located in a middle region of the support layer (3), and each column of lower electrodes (2) has electrodes arranged in the Y-axis direction. In the plan view, a center line of the end lower electrodes (2) on at least one side of each column of lower electrodes (2) is a wavy line, and the wave crests of the wavy center line (L) are aligned with each other in the X-axis direction.

10. The semiconductor device of claim 9, wherein, The repeating period of the wavy center line (L) is an isosceles triangle.

11. The semiconductor device of claim 10, wherein, At the position of the maximum distance of the wavy center line (L) from the X-axis, the wavy center line (L) forms an obtuse angle.

12. The semiconductor device of claim 10, wherein, At the position of the minimum distance of the wavy center line (L) from the X-axis, the wavy center line (L) forms an obtuse angle.

13. The semiconductor device of claim 10, wherein, The plurality of columns of lower electrodes (2) are divided into effective lower electrodes (22) located in a middle region and dummy lower electrodes (21) located in a peripheral region surrounding the middle region, a plurality of opening regions (31) are provided on the support layer (3), the plurality of opening regions (31) expose part of the outer circumferential surface of at least part of the effective lower electrodes (22), the support layer (3) completely surrounds the outer circumferential surface of the dummy lower electrodes (21), and the peripheral region is a closed ring shape.

14. The semiconductor device of claim 9, wherein, The size (x0) of the peripheral region in the X-axis direction is smaller than the size (y0) of the peripheral region in the Y-axis direction. In the plan view, the center line of the outermost circle of lower electrodes (2) includes two straight lines extending in the Y-axis direction and a wavy line connecting the end points on the same side of the two straight lines.

15. The semiconductor device of claim 9, wherein, ​ 16. The semiconductor device of claim 9, wherein, The support layer (3) is equal in size to the same side end electrode (2) of the plurality of columns of lower electrodes (2) in the Y-axis direction.

17. The semiconductor device of claim 9, wherein, The lower electrode (2) is in a solid column shape; or the lower electrode (2) is in a cup shape, and the opening direction of the cup-shaped lower electrode (2) is away from the substrate (1).

18. The semiconductor device of claim 9, wherein, The semiconductor device further comprises a dielectric layer covering the lower electrode (2) and the support layer (3), and an upper electrode covering the dielectric layer, and the upper electrode, the dielectric layer and the plurality of columns of lower electrodes (2) form a plurality of columns of capacitors.

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