Method of manufacturing split-gate flash memory device
By forming steep sidewall structures in the manufacturing of gated flash memory devices, the problems of incomplete morphology and uneven thickness are solved, improving the device's breakdown resistance and data storage reliability, and increasing the yield of flash memory devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2023-01-05
- Publication Date
- 2026-06-02
AI Technical Summary
In the manufacturing process of multi-gate flash memory devices, the sidewall morphology of the floating gate is incomplete and the thickness is uneven, which leads to device breakdown and data crosstalk problems. Moreover, traditional processes are difficult to form steep sidewalls on the floating gate.
By erasing a thicker first silicon nitride layer on the gate layer, etching to form steep first and second sidewalls, then forming a third sidewall on the side of the second sidewall, removing part of the thick silicon nitride layer, and finally forming the source line, the integrity of the sidewall morphology and the uniformity of the thickness are ensured.
This reduces the difficulty of etching the third sidewall, prevents the sidewall from peeling off from the side of the floating gate, improves the device's breakdown resistance and data storage reliability, and enhances the yield and reliability of flash memory devices.
Smart Images
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Abstract
Description
Technical Field
[0001] This application relates to the field of flash memory device manufacturing technology, and specifically to a method for manufacturing a gate-splitting flash memory device. Background Technology
[0002] In split-gate flash memory devices, the sidewalls (FGSP3) on the floating gate side serve as an isolation layer between the floating gate and the source line. Their morphology and thickness directly affect the degree of isolation between the floating gate and the source line. If the sidewall morphology is poor or the thickness uniformity is insufficient, it can easily cause device breakdown and crosstalk in the data stored in the floating gate. Before the sidewalls on the floating gate side are formed, the manufacturing process of split-gate flash memory devices requires the formation of two more sidewalls (FGSP1 and FGSP2). These two sidewalls are located on the side of the silicon nitride layer on the erase gate and on the side of the erase gate, respectively.
[0003] In the current traditional manufacturing process of gate-based flash memory devices, some logic integration processes (such as the filling process of the interlayer dielectric layer (ILD) and the formation process of contact holes (CT)) are required after the source line is formed. Therefore, the height of the basic storage cell of the flash memory device is limited. This results in the slope of the sidewalls FGSP1 and FGSP2 being too gentle (not steep enough). Consequently, it is difficult to form the sidewalls FGSP3 on the side of the floating gate by dry etching with height difference. Therefore, the sidewalls FGSP3 formed on the side of the floating gate currently have incomplete morphology, uneven thickness, and even peeling off from the side of the floating gate. This causes problems such as device breakdown and crosstalk of the data stored in the floating gate. Summary of the Invention
[0004] This application provides a method for manufacturing a multi-gate flash memory device, which can solve the problems of incomplete morphology, uneven thickness, or even peeling off from the side of the floating gate sidewall FGSP3, which can cause device breakdown and crosstalk of data stored in the floating gate.
[0005] On one hand, embodiments of this application provide a method for manufacturing a gate-splitting flash memory device, including:
[0006] A substrate is provided on which a gate oxide layer, a floating gate layer, a silicon oxide dielectric layer, an erase gate layer and a first silicon nitride layer are sequentially formed.
[0007] The first silicon nitride layer is etched down to the surface of the erase gate layer to form an opening in the erase gate layer;
[0008] A first sidewall is formed, the first sidewall covering the first silicon nitride layer on the opening sidewall;
[0009] At the opening location, the erase gate layer, the silicon oxide dielectric layer, and the surface of the floating gate layer are etched.
[0010] A second sidewall is formed, which covers a portion of the first sidewall, the side surface of the erase gate layer, and the side surface of the silicon oxide dielectric layer.
[0011] At the opening location, the floating gate layer is etched down to the surface of the gate oxide layer;
[0012] An ion implantation process is performed on the substrate at the opening location to form a source region in the substrate;
[0013] A third sidewall is formed, which covers a portion of the second sidewall and the side surface of the floating grid layer;
[0014] Etching removes a portion of the thickness of the first silicon nitride layer and a portion of the third sidewall;
[0015] A source line is formed, which fills the opening;
[0016] The first sidewall, the second sidewall, and the source line beyond the remaining thickness of the first silicon nitride layer are removed by CMP grinding.
[0017] Optionally, in the method for manufacturing the split-gate flash memory device, the step of forming a third sidewall that covers a portion of the second sidewall and the side surface of the floating gate layer includes:
[0018] A silicon oxide layer is formed, which covers the source region of the bottom wall of the opening, the second sidewall of the sidewall of the opening, and the side surface of the floating gate layer;
[0019] A second silicon nitride layer is formed, which covers the silicon oxide layer;
[0020] Remove the second silicon nitride layer on the bottom wall of the opening and the second silicon nitride layer at the top of the side wall of the opening;
[0021] Remove the silicon oxide layer on the bottom wall of the opening and the silicon oxide layer at the top of the side wall of the opening; at this time, the remaining silicon oxide layer covers the side surface of the floating gate layer and part of the second sidewall, and the remaining second silicon nitride layer covers the remaining silicon oxide layer; the remaining silicon oxide layer and the remaining second silicon nitride layer constitute the third sidewall.
[0022] Optionally, in the method for manufacturing the gated flash memory device, the step of etching away a portion of the first silicon nitride layer and a portion of the third sidewall includes:
[0023] A wet etching process is used to remove a portion of the first silicon nitride layer and the remaining second silicon nitride layer.
[0024] Optionally, in the manufacturing method of the gate-splitter flash memory device, the remaining silicon oxide layer has a thickness of [missing information].
[0025] Optionally, in the manufacturing method of the gate-splitting flash memory device, the thickness of the portion of the first silicon nitride layer etched away is [missing information].
[0026] Optionally, in the manufacturing method of the gated flash memory device, the angle between the tangent at any point on the second sidewall surface and the straight line in the vertical direction is between 0° and 5°.
[0027] Optionally, in the manufacturing method of the gated flash memory device, the angle between the tangent at any point on the first sidewall surface and the straight line in the vertical direction is between 0° and 5°.
[0028] Optionally, in the manufacturing method of the gate-splitter flash memory device, the thickness of the first silicon nitride layer is [missing information].
[0029]
[0030] Optionally, in the manufacturing method of the gated flash memory device, the first sidewall is made of silicon oxide; the second sidewall is made of silicon oxide.
[0031] Optionally, in the method for manufacturing the gate-splitting flash memory device, after removing the first sidewalls, second sidewalls, and source lines beyond the remaining thickness of the first silicon nitride layer using a CMP process, the method further includes:
[0032] An interlayer dielectric layer is formed, which covers the source line and the remaining thickness of the first silicon nitride layer;
[0033] Contact holes are formed in the interlayer dielectric layer;
[0034] A metal layer is formed in the contact hole to obtain a metal plug, which is electrically connected to the source line.
[0035] The technical solution of this application has at least the following advantages:
[0036] This application forms a relatively thick first silicon nitride layer on the erase gate layer, then forms a steep first sidewall on the side of the first silicon nitride layer, a steep second sidewall on the side of the erase gate, and a third sidewall on the side of the steep second sidewall. Next, a portion of the first silicon nitride layer is removed, and finally, a source line is formed, along with the removal of the first sidewall, second sidewall, and source line extending beyond the remaining thickness of the first silicon nitride layer. This reduces the etching difficulty of forming the third sidewall without affecting subsequent logic integration processes (such as the filling process of the interlayer dielectric layer (ILD) and the formation process of contact vias (CT)) which have height limitations. It also maintains the integrity of the third sidewall's morphology, improves the thickness uniformity of the third sidewall, avoids the third sidewall peeling off from the floating gate side, improves the device's breakdown resistance, avoids crosstalk problems in the data stored in the floating gate, and improves the yield and reliability of the flash memory device. Attached Figure Description
[0037] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0038] Figure 1 This is a flowchart of a method for manufacturing a gate-splitting flash memory device according to an embodiment of the present invention;
[0039] Figures 2-12 This is a schematic diagram of the semiconductor structure in each process step of manufacturing a gate-splitting flash memory device according to an embodiment of the present invention;
[0040] The reference numerals in the attached figures are explained as follows:
[0041] 100 - Substrate, 101 - Source region, 110 - Gate oxide layer, 120 - Floating gate layer, 130 - Silicon oxide dielectric layer, 140 - Erase gate layer, 150 - First silicon nitride layer, 151 - Remaining thickness of first silicon nitride layer, 160 - First sidewall, 170 - Second sidewall, 180 - Third sidewall, 181 - Remaining silicon oxide layer, 182 - Remaining second silicon nitride layer, 190 - Source line, 200 - Opening. Detailed Implementation
[0042] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0043] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0044] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0045] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0046] refer to Figure 1 , Figure 1 This is a flowchart of a method for manufacturing a gate-divided flash memory device according to an embodiment of the present invention, see reference. Figures 2-12 , Figures 2-12 This is a schematic diagram of the semiconductor structure in each process step of manufacturing a gated flash memory device according to an embodiment of the present invention.
[0047] This application provides a method for manufacturing a gate-splitting flash memory device, including:
[0048] Step S1: As Figure 2 As shown, a substrate 100 is provided, on which a gate oxide layer 110, a floating gate layer 120, a silicon oxide dielectric layer 130, an erase gate layer 140, and a first silicon nitride layer 150 are sequentially formed. Specifically, the substrate 100 can be one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The substrate 100 can also be gallium arsenide, gallium silicon compound, etc. The substrate 100 can also have a silicon-on-insulator or silicon-on-epitaxy layer structure. The substrate 100 can also be other semiconductor materials, which will not be listed here.
[0049] Preferably, the thickness of the first silicon nitride layer 150 is The thickness of the first silicon nitride layer 150 in this application is thicker than the thickness of the first silicon nitride layer 150 in the conventional process of flash memory devices. In this case, the height of the cell (flash memory device unit) exceeds the height required for the device in subsequent logic integration processes (such as the filling process of the interlayer dielectric layer ILD and the formation process of the contact hole CT).
[0050] Step S2: As Figure 3 As shown, the first silicon nitride layer 150 is etched to the surface of the erase gate layer 140 to form an opening 200 on the erase gate layer 140. Specifically, the size of the opening 200 defines the size of the opening of the subsequent floating gate layer 120.
[0051] In this embodiment, a wet etching process can be used to etch the first silicon nitride layer 150 to the surface of the erase gate layer 140 to form an opening 200 on the erase gate layer 140.
[0052] Step S3: As Figure 4 As shown, a first sidewall 160 is formed, which covers the first silicon nitride layer 150 on the sidewall of the opening 200. Specifically, the first sidewall 160 is made of silicon oxide.
[0053] In this embodiment, the first sidewall 160 is used to define the final length of the erase grid 140.
[0054] In this embodiment, the step of forming the first sidewall 160 may specifically include:
[0055] Step S3.1: Form a first silicon oxide material layer, the first silicon oxide material layer filling the opening 200 and covering the first silicon nitride layer 150;
[0056] Step S3.2: Use a dry etching process to etch away the first silicon oxide material layer on the first silicon nitride layer 150 and the first silicon oxide material layer at the middle position and bottom wall of the opening 200, leaving only the first silicon oxide material layer on the side wall of the opening 200, so as to obtain the first sidewall 160 covering the first silicon nitride layer 150 on the side wall of the opening 200.
[0057] Preferably, the angle α between the tangent at any point on the surface of the first sidewall 160 and the straight line in the vertical direction is between 0° and 5°, for example, 5°, 4°, 3°, 2°.
[0058] Step S4: As Figure 5 As shown, at the opening 200 position, the erase gate layer 140, the silicon oxide dielectric layer 130 and the surface of the floating gate layer 120 are etched.
[0059] In this embodiment, a dry etching process can be used to etch the erase gate layer 140, the silicon oxide dielectric layer 130, and the surface of the floating gate layer 120.
[0060] Step S5: As Figure 6 As shown, a second sidewall 170 is formed, which covers a portion of the first sidewall 160, the side surface of the erase gate layer 140, and the side surface of the silicon oxide dielectric layer 130. Specifically, the material of the second sidewall 170 is silicon oxide.
[0061] In this embodiment, the second sidewall 170 is used to define the final length of the floating grid layer 120 (floating grid).
[0062] In this embodiment, the step of forming the second sidewall 170 may specifically include:
[0063] Step S5.1: Form a second silicon oxide material layer, the second silicon oxide material layer filling the opening 200 and covering the first silicon nitride layer 150;
[0064] Step S5.2: Use a dry etching process to etch away the silicon oxide material layer on the first silicon nitride layer 150 and the second silicon oxide material layer on the middle and bottom wall of the opening 200, leaving only the second silicon oxide material layer on the side wall of the opening 200, so as to obtain the second sidewall 170 covering part of the first sidewall 160, the side surface of the erase gate layer 140 and the side surface of the silicon oxide dielectric layer 130.
[0065] Preferably, the angle β between the tangent at any point on the surface of the second sidewall 170 and the straight line in the vertical direction is between 0° and 5°, for example, 3° or 2°.
[0066] Step S6: As Figure 7 As shown, at the opening 200 location, the floating gate layer 120 is etched to the surface of the gate oxide layer 110.
[0067] In this embodiment, a dry etching process can be used to etch the floating gate layer 120 to the surface of the gate oxide layer 110.
[0068] Step S7: As Figure 8 As shown, an ion implantation process is performed on the substrate 100 at the opening 200 location to form a source region 101 in the substrate 100.
[0069] Furthermore, after forming the source region 101, the manufacturing method of the gate-splitting flash memory device may further include: as follows Figure 9 As shown, at the opening 200, the gate oxide layer 110 is etched to the surface of the source region 101 using a dry etching process.
[0070] Step S8: As Figure 10 As shown, a third sidewall 180 is formed, which covers a portion of the side surface of the second sidewall 170 and the floating grid layer 120. Specifically, the step of forming the third sidewall 180 may include:
[0071] A silicon oxide layer is formed, which covers the source region 101 on the bottom wall of the opening 200, the second sidewall 170 on the sidewall of the opening 200, and the side surface of the floating gate layer 120.
[0072] A second silicon nitride layer is formed, which covers the silicon oxide layer;
[0073] The second silicon nitride layer on the bottom wall of the opening 200 and the second silicon nitride layer at the top of the side wall of the opening 200 are removed by a dry etching process.
[0074] The silicon oxide layer on the bottom wall of the opening 200 and the silicon oxide layer at the top of the side wall of the opening 200 are removed by a dry etching process. At this time, the remaining silicon oxide layer 181 covers the side surface of the floating gate layer 120 and part of the second sidewall 170, and the remaining second silicon nitride layer 182 covers the remaining silicon oxide layer 181. The remaining silicon oxide layer 181 and the remaining second silicon nitride layer 182 constitute the third sidewall 180.
[0075] Preferably, the remaining silicon oxide layer 181 has a thickness of
[0076] Step S9: As Figure 11 As shown, etching removes a portion of the first silicon nitride layer and a portion of the third sidewall 180.
[0077] In this embodiment, the step of etching away a portion of the thickness of the first silicon nitride layer and a portion of the third sidewall 180 may specifically include: using a wet etching process to remove a portion of the thickness of the first silicon nitride layer and the remaining second silicon nitride layer 182.
[0078] Preferably, the thickness of the portion of the first silicon nitride layer etched away is [thickness value missing].
[0079] In this embodiment, the remaining silicon oxide layer 181 serves as the final third sidewall.
[0080] Preferably, the third sidewall 180 (the remaining silicon oxide layer 181) is used to isolate the floating gate layer 120 and the source line 190 formed in step S10.
[0081] Step S10: As Figure 12 As shown, a source line 190 is formed, which fills the opening 200. The source line 190 is in direct contact with the source region 101 on the bottom wall of the opening 200.
[0082] Step S11: As Figure 12 As shown, the first sidewall 160, the second sidewall 170, and the source line 190 beyond the remaining thickness of the first silicon nitride layer 151 are removed by CMP grinding.
[0083] Furthermore, after removing the first sidewall 160, the second sidewall 170, and the source line 190 from the surface of the first silicon nitride layer 151 beyond its remaining thickness using a CMP process, the method for manufacturing the gate-splitter flash memory device may further include the following steps:
[0084] Step S12: Form an interlayer dielectric layer, which covers the source line and the remaining thickness of the first silicon nitride layer;
[0085] Step S13: Form contact holes in the interlayer dielectric layer;
[0086] Step S14: Fill the contact hole with a metal layer to obtain a metal plug, which is electrically connected to the source line.
[0087] Because part of the thickness of the first silicon nitride layer has been etched away in step S9, making the height of the cell meet the design requirements of the device height, the formation of the interlayer dielectric layer, contact holes and metal plugs (execution of steps S12-S14) will not be affected by the height of the cell (memory cell).
[0088] In summary, in this application, a relatively thick first silicon nitride layer 150 is formed on the erase gate layer 140, followed by the formation of a steep first sidewall 160 on the side of the first silicon nitride layer 150, a steep second sidewall 170 on the side of the erase gate 140, and then a third sidewall on the side of the steep second sidewall 170. A portion of the first silicon nitride layer and a portion of the third sidewall 180 are then removed to obtain the final third sidewall (the remaining silicon oxide layer 181). Finally, a source line 190 is formed, and the surface of the first silicon nitride layer 151 exceeding its remaining thickness is removed. The three sidewalls, 160, 170, and 190, reduce the etching difficulty of forming the third sidewall without affecting the height limitations of subsequent logic integration processes (such as the filling process of interlayer dielectric layers, the formation process of contact holes, and the formation process of metal plugs). This also maintains the integrity of the third sidewall's morphology, improves the thickness uniformity of the third sidewall, avoids the third sidewall peeling off from the side of the floating gate, improves the device's breakdown resistance, avoids crosstalk problems in the data stored in the floating gate, and improves the yield and reliability of flash memory devices.
[0089] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for manufacturing a gate-splitting flash memory device, characterized in that, include: A substrate is provided on which a gate oxide layer, a floating gate layer, a silicon oxide dielectric layer, an erase gate layer and a first silicon nitride layer are sequentially formed, wherein the thickness of the first silicon nitride layer is 2500 Å to 3000 Å; The first silicon nitride layer is etched down to the surface of the erase gate layer to form an opening in the erase gate layer; A first sidewall is formed, the first sidewall covering the first silicon nitride layer on the opening sidewall; At the opening location, the erase gate layer, the silicon oxide dielectric layer, and the surface of the floating gate layer are etched. A second sidewall is formed, which covers a portion of the first sidewall, the side surface of the erase gate layer, and the side surface of the silicon oxide dielectric layer. At the opening location, the floating gate layer is etched down to the surface of the gate oxide layer; An ion implantation process is performed on the substrate at the opening location to form a source region in the substrate; A third sidewall is formed, which covers a portion of the second sidewall and the side surface of the floating grid layer; Etching removes a portion of the thickness of the first silicon nitride layer and a portion of the third sidewall; A source line is formed, and the source line fills the opening; The first sidewall, the second sidewall, and the source line beyond the remaining thickness of the first silicon nitride layer are removed by CMP grinding.
2. The method for manufacturing a gate-divided flash memory device according to claim 1, characterized in that, The step of forming a third sidewall that covers a portion of the second sidewall and the side surface of the floating grid layer includes: A silicon oxide layer is formed, which covers the source region of the bottom wall of the opening, the second sidewall of the sidewall of the opening, and the side surface of the floating gate layer; A second silicon nitride layer is formed, which covers the silicon oxide layer; Remove the second silicon nitride layer on the bottom wall of the opening and the second silicon nitride layer at the top of the side wall of the opening; Remove the silicon oxide layer on the bottom wall of the opening and the silicon oxide layer at the top of the side wall of the opening; at this time, the remaining silicon oxide layer covers the side surface of the floating gate layer and part of the second sidewall, and the remaining second silicon nitride layer covers the remaining silicon oxide layer; the remaining silicon oxide layer and the remaining second silicon nitride layer constitute the third sidewall.
3. The method for manufacturing a gate-splitting flash memory device according to claim 2, characterized in that, The step of etching away a portion of the thickness of the first silicon nitride layer and a portion of the third sidewall includes: A wet etching process is used to remove a portion of the first silicon nitride layer and the remaining second silicon nitride layer.
4. The method for manufacturing a gate-splitting flash memory device according to claim 2, characterized in that, The remaining silicon oxide layer has a thickness of 100 Å to 300 Å.
5. The method for manufacturing a gate-splitting flash memory device according to claim 1 or 3, characterized in that, The thickness of the portion of the first silicon nitride layer removed by etching is 500 Å to 800 Å.
6. The method for manufacturing a gate-divided flash memory device according to claim 1, characterized in that, The angle between the tangent at any point on the surface of the second side wall and the vertical line is between 0° and 5°.
7. The method for manufacturing a gate-divided flash memory device according to claim 1, characterized in that, The angle between the tangent at any point on the surface of the first sidewall and the vertical line is between 0° and 5°.
8. The method for manufacturing a gate-divided flash memory device according to claim 1, characterized in that, The first sidewall is made of silicon oxide; the second sidewall is made of silicon oxide.
9. The method for manufacturing a gate-divided flash memory device according to claim 1, characterized in that, After removing the first sidewall, second sidewall, and source line from the surface of the first silicon nitride layer exceeding its remaining thickness using a CMP process, the method for manufacturing the gate-splitter flash memory device further includes: An interlayer dielectric layer is formed, which covers the source line and the remaining thickness of the first silicon nitride layer; Contact holes are formed in the interlayer dielectric layer; A metal layer is formed in the contact hole to obtain a metal plug, which is electrically connected to the source line.