Combination write enable mask and credit return field

Abstract

The credit return field is used in a credit-based flow control system to indicate that one or more credits are being returned from a receiving device to a sending device. Based on the number of credits available, the sending device determines whether to send or wait until more credits are returned. The write enable mask allows the use of a wide data field even when a small amount of data is written. The novel data packet uses a combination write enable mask and credit return field. In one mode, the field contains a write enable mask. In another mode, the field contains credit return data. If the field contains credit return data, a default value (e.g., all ones) is used for the write enable mask. The mode can be selected based on another value in the data packet.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Application No. 17 / 007,701, filed August 31, 2020, which is incorporated herein by reference in its entirety.

[0003] Statement regarding government support

[0004] This invention was developed with the support of the U.S. government under DARPA Contract No. HR00111830003. The U.S. government owns certain rights to this invention. Technical Field

[0005] Embodiments of this disclosure generally relate to network protocols, and more specifically to networking using packet structures with a combined write enable mask and a credit return field, and more specifically to a combined write enable mask and credit return field in a credit-based flow control system, which in selected embodiments can be implemented in packet-based communication in chiplet systems. Background Technology

[0006] Various conventional packet-based networking systems utilize packet structures that include write-enabled masks. Upon receiving data, the write-enabled mask is examined to determine which parts of the data should be written and which should be ignored. To return credits, various conventional packet-based networking systems send separate credit return packets.

[0007] Chiplets are an emerging technology for integrating various processing functionalities. Generally, a chiplet system consists of discrete modules (each referred to as a "chiplet") integrated on an interposer layer and, in many instances, interconnected via one or more established networks as needed to provide the required functionality to the system. The interposer layer and the contained chiplets may be packaged together for easy interconnection with other components of a larger system. Each chiplet may contain one or more individual integrated circuits or "chips" (ICs), which may be combined with discrete circuit components and coupled together to a corresponding substrate for attachment to the interposer layer. Most or all of the chiplets in the system will be individually configured to communicate via one or more established networks.

[0008] Chipsets, configured as individual modules within a system, differ from a system implemented on a single chip containing different device blocks (e.g., intellectual property (IP) blocks) on a substrate (e.g., a single die), such as a system-on-a-chip (SoC) or multiple discrete packaged devices integrated on a printed circuit board (PCB). Generally, chiplets offer better performance (e.g., lower power consumption, reduced latency, etc.) than discrete packaged devices, and offer greater manufacturing benefits than a single die chip. These manufacturing benefits may include higher yields or reduced development costs and time.

[0009] A chiplet system may comprise, for example, one or more application (or processor) chiplets and one or more support chiplets. Here, the distinction between application chiplets and support chiplets is merely a reference to possible design scenarios for chiplet systems. Thus, for example, a synthetic vision chiplet system may comprise (by example only) application chiplets for generating synthetic vision output, and support chiplets such as memory controller chiplets, sensor interface chiplets, or communication chiplets. In typical use cases, synthetic vision designers may design the application chiplets and obtain support chiplets from other sources. Therefore, design expenditures (e.g., in terms of time or complexity) are reduced by avoiding the design and manufacture of the functionality embodied in the support chiplets. Chiplets also support the tight integration of IP blocks that might otherwise be difficult, such as IP blocks manufactured using different processing technologies or with different feature sizes (or utilizing different contact technologies or pitches). Therefore, assemblies or IC assemblies of multiple ICs with different physical, electrical, or communication characteristics can be assembled in a modular manner to provide an assembly that implements the desired functionality. Chiplet systems also facilitate adaptation to the needs of different larger systems that will be incorporated into chiplet systems. In one example, an IC or other assemblies can be optimized for power, speed, or heat generation for a specific function, as might be the case with sensors. Compared to attempting integration with other devices on a single die, the IC or other components can be integrated more easily. Furthermore, by reducing the overall size of the die, the yield of small chips is often higher than that of more complex single-die devices. Attached Figure Description

[0010] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0011] Figure 1A and 1B An example of a chiplet system according to an embodiment is illustrated.

[0012] Figure 2 Components of an example of a memory controller chiplet according to an embodiment are illustrated.

[0013] Figure 3 An example is illustrated of routing between chiplets in a chiplet layout using a chiplet protocol interface (CPI) network according to an embodiment.

[0014] Figure 4 This is a block diagram of a data packet including a combined write enable mask and credit return field, according to some embodiments of this disclosure.

[0015] Figure 5 This is a block diagram of credit packets suitable for use in a system using credit-based flow control, according to some embodiments of this disclosure.

[0016] Figure 6 This is a flowchart illustrating the operation of a method performed by a circuit to process data packets using a combination of write enable mask and credit return fields, according to some embodiments of the present disclosure.

[0017] Figure 7 This is a flowchart illustrating the operation of a method performed by a circuit to process data packets using a combination of write enable mask and credit return fields, according to some embodiments of the present disclosure.

[0018] Figure 8 This is a flowchart illustrating the operation of a method performed by a circuit to process data packets using a combination of write enable mask and credit return fields, according to some embodiments of the present disclosure.

[0019] Figure 9 This is a flowchart illustrating the operation of a method performed by a circuit to process data packets using a combination of write enable mask and credit return fields, according to some embodiments of the present disclosure.

[0020] Figure 10 This is a block diagram of an example computer system operable according to embodiments of the present disclosure. Detailed Implementation

[0021] Embodiments of this disclosure relate to systems and methods for creating and processing data packets using a combination of a write enable mask and a credit return field. Such systems and methods provide efficiency in network communication. While such efficiency can be beneficial in a variety of systems, the example systems discussed herein are chiplet-based memory systems that can be implemented to provide such efficiency, at least in part, when storing or accessing memory devices via packet-based networks. A write enable mask allows a first device to send a data packet containing a write command and a fixed number of bytes (e.g., four bytes) of data conforming to a transmission protocol, without causing a receiving device to write all the data bytes. A write enable mask is an important feature that allows applications to control data writing at the byte level rather than at a protocol-specific minimum size. However, in many cases, a write enable mask only indicates that all bytes will be written. For example, when transmitting data files much larger than the size of a single data packet, many data packets are sent with the write enable mask fully set.

[0022] In a credit-based flow control system, a credit return field is used to indicate that one or more credits are being returned from a receiving device to a sending device. Based on the number of available credits, the sending device determines whether to continue sending or wait until more credits are returned. The credit return field can be a field in a data packet carrying other data (e.g., when using two-way communication, such as in a Voice over Internet Protocol (VoIP) application) or can be in a separate credit packet specifically sent for the purpose of returning credits.

[0023] The novel data packet uses a combination of write-enabled mask and credit return field. In one mode, this field contains the write-enabled mask. In another mode, this field contains credit return data. If this field contains credit return data, then the default value (e.g., all ones) is used for the write-enabled mask. The mode can be selected based on another value in the data packet.

[0024] One benefit of the embodiments disclosed herein is that it supports smaller packet sizes compared to packets containing both a write enable field and a credit return field. Furthermore, it reduces network traffic compared to packets containing only the write enable field and sending credit return data as a separate credit packet. Therefore, it reduces the processing loops spent handling network traffic and credit returns. Additionally, it reduces the power consumed when handling network traffic and credit returns. The performance of systems including communication devices is also improved due to reduced networking overhead. Other benefits will be apparent to those skilled in the art who will receive the benefits of this disclosure.

[0025] Figure 1A and 1B An example of a chiplet system 110 according to an embodiment is illustrated. Figure 1AThis is an illustration of a chiplet system 110 mounted on a peripheral board 105, which can be connected to a wider range of computer systems, for example, via peripheral component interconnect (PCIe). The chiplet system 110 includes a package substrate 115, an interposer 120, and four chips: an application chiplet 125, a host interface chiplet 135, a memory controller chiplet 140, and a memory device chiplet 150. Other systems may include numerous additional chipsets to provide additional functionality, as will be apparent from the following discussion. The package of the chiplet system 110 is illustrated with a cap or cover plate 165, but other packaging techniques and structures used for chiplet systems may be used. Figure 1B This is a block diagram for the purpose of clearly labeling the components in a chiplet system.

[0026] Application chip 125 is described as including a network on chip (NOC) 130 to support a chiplet network 155 for inter-chiplet communication. In an example embodiment, NOC 130 may be included on application chip 125. In an example, NOC 130 may be defined in response to selected supporting chips (e.g., chips 135, 140, and 150), allowing the designer to select an appropriate number or switch of chiplet network connections for NOC 130. In an example, NOC 130 may reside on a single chiplet or even within interposer 120. In the example discussed herein, NOC 130 implements a chiplet protocol interface (CPI) network.

[0027] CPI is a packet-based network that supports virtual channels to enable flexible and high-speed interaction between chiplets. CPI bridges the chiplet-internal network to chiplet network 155. For example, the Advanced Extensible Interface (AXI) is a widely used specification for designing intra-chip communication. However, the AXI specification covers a large number of physical design options, such as the number of physical channels, signal timing, and power. Within a single chip, these options are typically selected to meet design goals such as power consumption and speed. However, to achieve flexibility in chiplet systems, adapters such as CPI are used to intersect between various AXI design options that can be implemented in various chiplets. By implementing a mapping from physical channels to virtual channels and encapsulating time-based signaling using packetization protocols, CPI bridges the chiplet-internal network across chiplet network 155.

[0028] CPI can use a variety of different physical layers to transmit packets. A physical layer may contain simple conductive connections, or it may contain drivers to increase voltage, or otherwise facilitate signal transmission over longer distances. An example of such a physical layer may contain an Advanced Interface Bus (AIB), which in various instances may be implemented in intermediate layer 120. The AIB uses source-synchronous data transfer with a forwarding clock to transmit and receive data. Packets are transmitted across the AIB at Single Data Rate (SDR) or Double Data Rate (DDR) relative to the transmitted clock. The AIB supports various channel widths. When operating in SDR mode, the AIB channel width is a multiple of 20 bits (20, 40, 60, ...), and for DDR mode, the AIB channel width is a multiple of 40 bits (40, 80, 120, ...). The AIB channel width includes both transmitted and received signals. Channels can be configured with a symmetrical number of transmit (TX) and receive (RX) inputs / outputs (I / O), or with an asymmetrical number of transmitters and receivers (e.g., all transmitters or all receivers). The channel can act as either a master or slave device for the AIB, depending on which chip provides the master clock. The AIB I / O unit supports three timing modes: asynchronous (i.e., non-timing), SDR, and DDR. In various instances, the non-timing mode is used for the clock and some control signals. SDR mode can use a dedicated SDR-only I / O unit or a dual-purpose SDR / DDR I / O unit.

[0029] In this example, the CPI packet protocol (e.g., point-to-point or routable) can use symmetrical receive and transmit I / O units within an AIB channel. The CPI streaming protocol allows for more flexible use of AIB I / O units. In this example, a streaming AIB channel can configure I / O units as all TX, all RX, or half TX and half RX. The CPI packet protocol can use AIB channels in SDR or DDR operating modes. In this example, AIB channels are configured in increments of 80 I / O units (i.e., 40 TX and 40 RX) for SDR mode and in increments of 40 I / O units for DDR mode. The CPI streaming protocol can use AIB channels in either SDR or DDR operating modes. Here, in this example, AIB channels are configured in increments of 40 I / O units for both SDR and DDR modes. In this example, a unique interface identifier is assigned to each AIB channel. This identifier is used during CPI reset and initialization to determine paired AIB channels across neighboring chiplets. In this example, the interface identifier is a 20-bit value comprising a seven-bit chiplet identifier, a seven-bit column identifier, and a six-bit link identifier. The AIB physical layer uses an AIB out-of-band shift register to transmit the interface identifier. Bits 32 to 51 of the shift register are used to transmit the 20-bit interface identifier in both directions across the AIB interface.

[0030] AIB defines a stacked group of AIB channels as an AIB channel column. An AIB channel column has a certain number of AIB channels, plus auxiliary channels. The auxiliary channels contain signals used for AIB initialization. All AIB channels within a column (except for the auxiliary channels) have the same configuration (e.g., all TX, all RX, or half TX and half RX, and the same number of data I / O signals). In this example, AIB channels are numbered sequentially in ascending order, starting with the AIB channel adjacent to the AUX channel. The AIB channel adjacent to the AUX channel is defined as AIB channel zero.

[0031] Generally, the CPI interface on an individual chiplet may include serialization-deserialization (SERDES) hardware. SERDES interconnects are well-suited for scenarios requiring high-speed signaling and low signal counts. However, SERDES can introduce additional power consumption and longer latency for multiplexing and demultiplexing, error detection or correction (e.g., using block-level cyclic redundancy check (CRC)), link-level retries, or forward error correction. However, when low latency or power consumption is a primary concern for ultra-short-distance chiplet-to-chiplet interconnects, parallel interfaces that allow data transmission with minimal latency can be utilized. CPIs contain elements designed to minimize both latency and power consumption in these ultra-short-distance chiplet interconnects.

[0032] For flow control, CPI employs a credit-based technique. The receiving side of application chip 125, such as the sender of memory controller chip 140, provides credits indicating available buffers. In this example, the CPI receiver contains buffers for each virtual channel for a given transmit time unit. Therefore, if the CPI receiver supports five messages and a single virtual channel in time, the receiver has five buffers arranged in five rows (e.g., one row per unit time). If four virtual channels are supported, the receiver has twenty buffers arranged in five rows. Each buffer holds the payload of one CPI packet.

[0033] When a sender transmits to a receiver, the sender decrements its available credits based on the transmission. Once the receiver has exhausted all its credits, the sender stops sending packets to the receiver. This ensures that the receiver always has an available buffer to store transmissions.

[0034] When the receiver processes the received packet and releases the buffer, it communicates the available buffer space back to the sender. The sender can then use this credit to allow the transmission of additional information.

[0035] The paper also describes a chiplet mesh network 160 that uses direct chiplet-to-chiplet technology without requiring NOC 130. The chiplet mesh network 160 can be implemented in CPI or another chiplet-to-chiplet protocol. The chiplet mesh network 160 typically implements a chiplet pipeline, where one chiplet acts as an interface to the pipeline, while other chipslets in the pipeline interface only interface with themselves.

[0036] Additionally, dedicated device interfaces, such as one or more industry-standard memory interfaces 145 (e.g., synchronous memory interfaces, such as DDR5, DDR6), can also be used to interconnect chiplets. Connections from chiplet systems or individual chiplets to external devices (e.g., larger systems can be connected via a desired interface (e.g., a PCIe interface)). In an example, an external interface may be implemented via a host interface chiplet 135, which, in the depicted example, provides a PCIe interface external to the chiplet system 110. Such interfaces are typically used when industry practice or standards have converged on them. The illustrated example of connecting a memory controller chiplet 140 to the DDR interface 145 of a dynamic random access memory (DRAM) device 150 is an example of this industry practice.

[0037] Among the various possible supporting chiplets, the memory controller chiplet 140 is likely to be present in the chiplet system 110 due to the ubiquitous use of memory for computer processing and the application of advanced technologies to memory devices. Therefore, using the memory device chiplet 150 and the memory controller chiplet 140, both designed by other designers, allows chiplet system designers to obtain robust products manufactured by established companies. Generally, the memory controller chiplet 140 provides a memory device-specific interface for reading, writing, or erasing data. The memory controller chiplet 140 often provides additional features such as error detection, error correction, maintenance operations, or atomic operation execution. For some types of memory, maintenance operations are often specific to the memory device 150, such as garbage collection in NAND flash or storage-class memory, or temperature regulation (e.g., cross-temperature management) in NAND flash memory. In instances, maintenance operations may involve logic-to-physical (L2P) mapping or management to provide an indirection hierarchy between the physical and logical representations of data. In other types of memory, such as DRAM, some memory operations, such as refresh, may be controlled at certain times by the host processor or memory controller, and at other times by the DRAM memory device or logic associated with one or more DRAM devices, such as interface chips (in this example, buffers).

[0038] Atomic operations are data manipulations that can be performed, for example, by the memory controller chiplet 140. In other chiplet systems, atomic operations can be performed by other chipsets. For example, an atomic operation can be specified as an "increment" in a command by the application chiplet 125, the command containing a memory address and possibly an increment value. Upon receiving the command, the memory controller chiplet 140 retrieves a number from the specified memory address, increments the number by the amount specified in the command, and stores the result. Upon successful completion, the memory controller chiplet 140 provides the application chiplet 125 with an indication that the command was successful. Atomic operations avoid transmitting data across the chiplet network 160, thereby reducing latency in executing such commands.

[0039] Atomic operations can be categorized into built-in atoms or programmable (e.g., custom) atoms. Built-in atoms are a finite set of operations that are implemented immutably in the hardware. Programmable atoms are applets that can run on programmable atomic units (PAUs) (e.g., custom atomic units (CAUs)) of the memory controller chiplet 140. Figure 1 illustrates an example of a memory controller chiplet that illustrates a PAU.

[0040] The memory device chiplet 150 may be or include any combination of volatile memory devices or non-volatile memory. Examples of volatile memory devices include, but are not limited to, random access memory (RAM), such as DRAM, synchronous DRAM (SDRAM), graphics dual data rate type 6 SDRAM (GDDR6 SDRAM), etc. Examples of non-volatile memory devices include, but are not limited to, NAND flash memory, memory-class memory (e.g., phase-change memory or memristor-based technology), ferroelectric RAM (FeRAM), etc. The illustrated example includes memory device 150 as a chiplet; however, memory device 150 may reside elsewhere, such as in different packages on board 105. For many applications, multiple memory device chipsets may be provided. In the example, these memory device chipsets may each implement one or more memory technologies. In the example, the memory chiplet may include multiple stacked memory dies of different technologies, such as stacked or additionally communicating with one or more DRAM devices or one or more SRAM devices. The memory controller 140 can also be used to coordinate the operation between multiple memory chips in the chiplet system 110; for example, utilizing one or more memory chips in one or more tiers of cache memory and using one or more additional memory chips as main memory. The chiplet system 110 may also include multiple memory controllers 140, which can be used to provide memory control functionality for individual processors, sensors, networks, etc. For example, the chiplet architecture of the chiplet system 110 offers the advantage of allowing adaptation to different memory storage technologies and different memory interfaces through updated chiplet configurations without requiring redesign of the rest of the system architecture.

[0041] Figure 2 The diagram illustrates components of an example of a memory controller chiplet 205 according to an embodiment. The memory controller chiplet 205 includes a cache 210, a cache controller 215, an off-die memory controller 220 (e.g., for communicating with off-die memory 275), a network communication interface 225 (e.g., for interfacing with a chiplet network 285 and communicating with other chiplets), and a set of atomic and merge operations 250. For example, this set of components may include a write merge unit 255, a dangerous unit (260), a built-in atomic unit 265, or a PAU 270. The various components are illustrated logically and may not necessarily be implemented. For example, a built-in atomic unit 265 may include different means along the path to off-die memory. For example, a built-in atomic unit may be in an interface means / buffer on the memory chiplet, as discussed above. In contrast, programmable atomic operations 270 may be implemented in a separate processor on the memory controller chiplet 205 (but in various instances, may be implemented elsewhere, such as on the memory chiplet itself).

[0042] The off-die memory controller 220 is directly coupled to the off-die memory 275 (e.g., via a bus or other communication connection) to provide write operations to, and read operations from, the one or more off-die memories, such as off-die memory 275 and off-die memory 280. In the depicted example, the off-die memory controller 220 is also coupled to outputs to the atom and merge unit 250 and inputs to the cache controller 215 (e.g., a memory-side cache controller).

[0043] In the instance configuration, the cache controller 215 is directly coupled to the cache 210 and can be coupled to the network communication interface 225 for input (e.g., incoming read or write requests) and coupled to the off-die memory controller 220 as an output.

[0044] Network communication interface 225 includes packet decoder 230, network input queue 235, packet encoder 240, and network output queue 245 to support packet-based chiplet network 285, such as CPI. Chiplet network 285 can provide packet routing between and within processors, memory controllers, mixed-thread processors, configurable processing circuitry, or communication interfaces. In this packet-based communication system, each packet typically contains destination and source addressing, as well as any data payload or instructions. In instances, depending on the configuration, chiplet network 285 can be implemented as a collection of crossbars with a folded Clos configuration, or as a mesh network providing additional connectivity.

[0045] In various instances, the chiplet network 285 may be part of an asynchronous switching architecture. Here, data packets may be routed along any of various paths, such that any selected data packet may arrive at the addressed destination at any time among multiple different times, depending on the route. Furthermore, the chiplet network 285 may be implemented at least partially as a synchronous communication network, such as a synchronous mesh communication network. Two configurations of the communication network are used, for example, according to this disclosure, upon careful consideration.

[0046] The memory controller chip 205 can receive packets having, for example, a source address, a read request, and a physical address. In response, the off-die memory controller 220 or the cache controller 215 reads data from the specified physical address (which may be in off-die memory 275 or cache 210) and assembles a response packet into a source address containing the requested data. Similarly, the memory controller chip 205 can receive packets having a source address, a write request, and a physical address. In response, the memory controller chip 205 writes data to the specified physical address (which may be in cache 210 or off-die memory 275 or 280) and assembles a response packet into a source address containing confirmation that data has been stored in memory.

[0047] Therefore, where possible, the memory controller chiplet 205 can receive read and write requests via chiplet network 285 and process the requests using cache controller 215, which interfaces with cache 210. If cache controller 215 cannot process the request, then off-chip memory controller 220 processes the request by communicating with off-chip memory 275 or 280, atomic and merge operations 250, or both. As described above, one or more cache levels can also be implemented in off-chip memory 275 or 280; and in some such instances, they can be directly accessed by cache controller 215. Data read by off-chip memory controller 220 can be cached in cache 210 by cache controller 215 for later use.

[0048] Atom and merge operation 250 is coupled to receive (as input) the output of off-die memory controller 220 and provides the output to cache 210, network communication interface 225, or directly to chiplet network 285. Memory danger clear (reset) unit 260, write merge unit 265, and built-in (e.g., predetermined) atom operation unit 265 can each be implemented as a state machine with other combinational logic circuitry (such as adders, shifters, comparators, AND gates, OR gates, XOR gates, or any suitable combination thereof) or other logic circuitry. These components may also include one or more registers or buffers to store operands or other data. PAU 270 may be implemented as one or more processor cores or control circuitry, and various state machines with other combinational logic circuitry or other logic circuitry, and may also include one or more registers, buffers, or memories to store addresses, executable instructions, operands, and other data, or may be implemented as a processor.

[0049] Write merging unit 255 receives read data and request data, and merges the request data and read data to create a single unit having the read data and the source address to be used in the response or return data packet. Write merging unit 255 provides the merged data to the write port of cache 210 (or equivalently, to cache controller 215 for writing to cache 210). Optionally, write merging unit 255 provides the merged data to network communication interface 225 for encoding and preparing response or return data packets for transmission on chiplet network 285.

[0050] When requested data is used for a built-in atomic operation, the built-in atomic operation unit 265 receives the request and reads the data from the write merging unit 265 or directly from the off-chip memory controller 220. The atomic operation is performed, and using the write merging unit 255, the resulting data is written to the cache 210 or provided to the network communication interface 225 to encode and prepare response or return packets for transmission on the chiplet network 285.

[0051] Built-in atomic operation unit 265 handles predefined atomic operations, such as fetch and increment or compare and swap. In examples, these operations perform simple read-modify-write operations on a single memory location of 32 bytes or less. An atomic memory operation is initiated from a request packet transmitted via chiplet network 285. The request packet has a physical address, atomic operator type, operand size, and optionally up to 32 bytes of data. The atomic operation performs a read-modify-write operation on a cache line of cache 210, thereby filling the cache memory as necessary. The atomic operator response can be a simple complete response or a response with up to 32 bytes of data. Example atomic memory operators include fetch and AND, fetch and OR, fetch and XOR, fetch and add, fetch and subtract, fetch and increment, fetch and decrement, fetch and minimum, fetch and maximum, fetch and swap, and compare and swap. In various example embodiments, 32-bit and 64-bit operations and operations on 16 or 32 bytes of data are supported. The methods disclosed herein are also compatible with hardware that supports larger or smaller operations and more or less data.

[0052] Built-in atomic operations may also involve requests for "standard" atomic operations on the requested data, such as relatively simple single-loop integer atoms, such as fetch and increment or compare and swap, whose throughput will be the same as regular memory read or write operations that do not involve atomic operations. For these operations, cache controller 215 can typically preserve cache lines in cache 210 by setting a danger bit (in hardware) so that the cache line cannot be read by another process during translation. Data is obtained from off-chip memory 275 or cache 210 and provided to built-in atomic operation unit 265 to perform the requested atomic operation. After the atomic operation, in addition to providing the obtained data to packet encoder 240 to encode outgoing packets for transmission on chiplet network 285, built-in atomic operation unit 265 also provides the obtained data to write merging unit 255, which writes the obtained data back to cache circuitry 210. After the obtained data is written to cache 210, memory danger clearing unit 260 clears any corresponding danger bits that were set.

[0053] The PAU 270 implements high-performance (high throughput and low latency) programmable atomic operations (also known as "custom atomic operations"), comparable to the performance of built-in atomic operations. Instead of performing multiple memory accesses, in response to an atomic operation request specifying a programmable atomic operation and a memory address, the circuitry in the memory controller chiplet 205 transmits the atomic operation request to the PAU 270 and sets a danger bit in a memory danger register corresponding to the memory address used in the atomic operation to ensure that no other operation (read, write, or atomic) is performed on that memory line. The danger bit is then cleared after the atomic operation is complete. The additional, direct data path provided to the PAU 270 for performing programmable atomic operations allows for additional write operations without being limited by the bandwidth of the communication network and without increasing any congestion on the communication network.

[0054] The PAU 270 includes a multi-threaded processor, such as a RISC-VIS-based multi-threaded processor, with one or more processor cores and further featuring an extended instruction set for performing programmable atomic operations. When equipped with an extended instruction set for performing programmable atomic operations, the PAU 270 can be embodied as one or more hybrid-threaded processors. In some example implementations, the PAU 270 provides bucket-style transient thread switching to maintain a high instruction-per-clock rate.

[0055] Programmable atomic operations can be executed by PAU 270, which relate to requests for programmable atomic operations on requested data. Users can prepare programming code to provide such programmable atomic operations. For example, a programmable atomic operation can be a relatively simple multi-loop operation, such as floating-point addition, or it can be a relatively complex multi-instruction operation, such as a Bloom filter insert. Programmable atomic operations can be the same as or different from predetermined atomic operations, as long as they are defined by the user and not the system vendor. For these operations, cache controller 215 can preserve cache lines in cache 210 by setting a danger bit (in hardware), preventing the cache lines from being read by another process during translation. Data is obtained from cache 210 or off-chip memory 275 or 280 and provided to PAU 270 to execute the requested programmable atomic operation. After the atomic operation, PAU 270 provides the obtained data to network communication interface 225 to directly encode outgoing data packets containing the obtained data for transmission on chiplet network 285. Additionally, PAU270 provides the obtained data to cache controller 215, which then writes the obtained data to cache 210. After writing the obtained data to cache 210, cache control circuit 215 clears any corresponding dangerous bits that were set.

[0056] In the selected example, the approach taken for programmable atomic operations is to provide multiple general-purpose custom atomic request types, which can be sent from a source of origin, such as a processor or other system component, to the memory controller chiplet 205 via chiplet network 285. Cache controller 215 or off-die memory controller 220 recognizes the request as a custom atom and forwards the request to PAU 270. In a representative embodiment, PAU 270: (1) is a programmable processing element capable of efficiently performing user-defined atomic operations; (2) performs load and store operations on memory, arithmetic and logical operations, and control flow decisions; and (3) facilitates interaction with such controllers 215, 220 using a RISC-V ISA with a new set of dedicated instructions, thereby performing user-defined operations atomically. In a desirable example, the RISC-V ISA contains a complete instruction set supporting high-level language operators and data types. The PAU 270 can utilize a RISC-V ISA, but will typically support a more limited instruction set and a limited register file size to reduce the die size of the cell when included within the memory controller chiplet 205.

[0057] As mentioned above, before writing read data to cache 210, the memory danger clearing unit 260 clears the set danger bits of the reserved cache lines. Therefore, when the write merging unit 255 receives a request and read data, the memory danger clearing unit 260 can send a reset or clear signal to cache 210 to reset the set memory danger bits of the reserved cache lines. Furthermore, resetting this danger bit also releases pending read or write requests involving the specified (or reserved) cache line, thereby providing the pending read or write requests to the inbound request multiplexer for selection and processing.

[0058] Figure 3 This illustration depicts an example of routing between chiplets in chiplet layout 300 using a chiplet protocol interface (CPI) network according to an embodiment. Chiplet layout 300 includes chiplets 310A, 310B, 310C, 310D, 310E, 310F, 310G, and 310H. Chipslets 310A through 310H are interconnected by a network including nodes 330A, 330B, 330C, 330D, 330E, 330F, 330G, and 330H. Each of chiplets 310A through 310H includes a hardware transceiver labeled 320A through 320H.

[0059] CPI packets can be transferred between chiplets 310 using the Advanced Interface Bus (AIB). The AIB provides physical layer functionality. The physical layer uses source-synchronous data transfer with a forwarding clock to transmit and receive data. Packets are transmitted across the AIB relative to the transmitted clock in SDR or DDR. The AIB supports various channel widths. When operating in SDR mode, the AIB channel width is a multiple of 20 bits (20, 40, 60, ...), and for DDR mode, the AIB channel width is a multiple of 40 bits (40, 80, 120, ...). The AIB channel width includes both transmitted and received signals. Channels can be configured with a symmetrical number of transmit (TX) and receive (RX) inputs / outputs (I / O), or an asymmetrical number of transmitters and receivers (e.g., all transmitters or all receivers). A channel can act as an AIB master or slave, depending on which chiplet provides the master clock.

[0060] The AIB adapter provides interfaces to the AIB link layer and to the AIB physical layer (PHY). The AIB adapter provides a data hierarchy register, a power-on reset sequencer, and a control signal shift register.

[0061] The AIB physical layer consists of AIB I / O units. AIB I / O units (implemented in some embodiments by hardware transceiver 320) can be input-only, output-only, or bidirectional. An AIB channel consists of a set of AIB I / O units, the number of which depends on the AIB channel configuration. A receive signal on one chiplet is connected to a transmit signal on a pair of chipsets. In some embodiments, each column includes an auxiliary (AUX) channel and data channels numbered 0 to N.

[0062] AIB channels are typically configured as half TX data and half RX data, all TX data, or all RX data plus associated clock and promiscuous control. In some example implementations, the number of TX data signals relative to the number of RX data signals is determined at design time and cannot be configured as part of system initialization.

[0063] The CPI packet protocol (point-to-point and routable) uses symmetrical receive and transmit I / O units within the AIB channel. The CPI streaming protocol allows for more flexible use of AIB I / O units. In some example implementations, the I / O units for streaming mode can be configured as all TX, all RX, or half TX and half RX.

[0064] Data packets are routed within chip 310 via network node 330. Node 330 can determine the next node 330 to forward a received data packet to based on one or more data fields of the data packet. For example, source or destination address, source or destination port, virtual channel, or any suitable combination thereof can be hashed to select consecutive network nodes or available network paths. This method of path selection can be used to balance network traffic.

[0065] Therefore, in Figure 3 The diagram illustrates the data path from chiplet 310A to chiplet 310D. Data packets are sent from hardware transceiver 320A to network node 330A; forwarded by network node 330A to network node 330C; forwarded by network node 330C to network node 330D; and delivered by network node 330D to hardware transceiver 320D of chiplet 310D.

[0066] Figure 3 The diagram also illustrates a second data path from chiplet 310A to chiplet 310G. Data packets are sent from hardware transceiver 320A to network node 330A; forwarded by network node 330A to network node 330B; forwarded by network node 330B to network node 330D; forwarded by network node 330D to network node 330C; forwarded by network node 330C to network node 330E; forwarded by network node 330E to network node 330F; forwarded by network node 330F to network node 330H; forwarded by network node 330H to network node 330G; and delivered by network node 330G to hardware transceiver 320G of chiplet 310G. (The last sentence appears to be a fragment and doesn't translate directly.) Figure 3 Visually, it is evident that multiple paths through the network can be used for data transmission between any pair of chiplets.

[0067] The AIB I / O unit supports three timing modes: asynchronous (i.e., non-timing), SDR, and DDR. Non-timing mode is used for clock and some control signals. SDR mode can use a dedicated SDR-only I / O unit or a dual-purpose SDR / DDR I / O unit.

[0068] The CPI packet protocol (point-to-point and routable) can use the AIB channel in either SDR or DDR operating mode. In some example implementations, the AIB channel will increment by 80 I / O units (i.e., 40 TX and 40 RX) for SDR mode and by 40 I / O units for DDR mode.

[0069] The CPI streaming protocol can use AIB channels in either SDR or DDR operating mode. In some example implementations, the AIB channels are incremented by 40 I / O units for both modes (SDR and DDR).

[0070] A unique interface identifier is assigned to each AIB channel. This identifier is used during CPI reset and initialization to determine the paired AIB channels across neighboring chiplets. In some example embodiments, the interface identifier is a 20-bit value comprising a seven-bit chiplet identifier, a seven-bit column identifier, and a six-bit link identifier. The AIB physical layer uses an AIB out-of-band shift register to transmit the interface identifier. Bits 32 to 51 of the shift register are used to transmit the 20-bit interface identifier in both directions across the AIB interface.

[0071] AIB defines a stacked set of AIB channels as an AIB channel column. For example... Figure 3 As shown, the AIB channel column has a certain number of AIB channels, plus auxiliary channels. The auxiliary channels contain signals for AIB initialization. All AIB channels within the column (except the auxiliary channels) have the same configuration (e.g., all TX, all RX, or half TX and half RX, and the same number of data I / O signals). The AIB channel column is arranged in a specific orientation around the periphery of the chiplet to allow interoperability between chiplets. Although Figure 3 The diagram shows each of the chiplets 310 with a hardware transceiver 320, but it should be noted that each side of the chiplet may have zero or more hardware transceivers.

[0072] In some implementations, AIB channels are numbered in ascending order, starting with the AIB channel adjacent to the AUX channel. AIB channels adjacent to the AUX are defined as AIB channel zero.

[0073] Figure 3 An example is provided to illustrate eight chiplets 310 connected by a network comprising eight nodes 330. More or fewer chiplets 310 and more or fewer nodes 330 can be included in the chiplet network, thus allowing the creation of networks of chiplets of any size.

[0074] Figure 4 This is a block diagram of a data packet 400 including a combined write enable mask and credit return fields, according to some embodiments of this disclosure. The data packet 400 is divided into flow control units (micro-pieces), each comprising 36 bits. A first micro-piece of the data packet 400 includes a CP field 405, a path field 410, a statistics field 415, a destination identifier (DID) field 420, a sequence continuation (SC) field 425, a length field 430, and a command field 435. Each remaining micro-piece includes a credit return (CR) / write enable mask (WEM) field (e.g., CR / WEM fields 440 and 450) and a data field (e.g., data fields 445 and 455). Instance field sizes are discussed below as illustrative examples; although field sizes may differ for the chosen application and do not limit the characteristics of the data packet.

[0075] The CP field 405 is a two-bit field that indicates whether the CR / WEM fields of subsequent micro-fragments in the packet contain CR data, WEM data, or should be ignored, and whether the path field 410 should be used to control packet ordering. In some implementations, a value of 0 or 1 in the CP field 405 indicates that CR / WEM fields 440 and 450 contain credit return data; a value of 2 or 3 in the CP field 405 indicates that CR / WEM fields 440 and 450 contain WEM data; a value of 0 indicates that the path field 410 should be ignored; a value of 1 or 3 indicates that the path field 410 should be used to determine the path of packet 400; and a value of 2 indicates that a single path ordering will be used. In some implementations, a one-bit field is used. Alternatively, the high-order bit of the CP field 405 may be considered a one-bit field that controls whether CR / WEM fields 440 and 450 contain credit return data or WEM data. In some implementations, the one-bit field interpreted as the control field is a portion of the controlled field. For example, CR / WEM fields 440 and 450 can be made self-controlled by extending them by one bit to include the selection bit.

[0076] The path field 410 is an eight-bit field. When the CP field 405 indicates that the path field 410 is used to determine the path for packet 400, it ensures that all packets with the same value for the path field 410 take the same path through the network. Therefore, the order of the packets remains unchanged between the sender and receiver. If the CP field 405 indicates that a single path sorting will be used, then the path for each packet is determined as if the path field 410 were set to zero. Therefore, all packets take the same path and the order remains unchanged, regardless of the actual value of the path field 410 for each packet. If the CP field 405 indicates that the path field 410 will be ignored, then packets are routed without considering the value of the path field 410, and packets can be received by the receiver in a different order than when they were sent by the sender. However, this avoids network congestion and allows for higher throughput in the device.

[0077] The response status is stored in statistics field 415 (four-digit field). In some example implementations, status zero indicates that the request was successfully processed, status one indicates an address error, status two indicates an unsupported request, status three indicates an uncorrectable data error, and values ​​four through fifteen are reserved.

[0078] The DID field 420 stores a twelve-bit DID. The DID uniquely identifies the destination (e.g., a destination chip) within the network. It ensures the sequential delivery of the entire sequence of data packets with the 1-bit SC field 425 set. The length field 430 is a five-bit field indicating the number of fragments comprising data packet 400. The interpretation of the length field 430 can be non-linear. For example, a value 0-22 can be interpreted as 0-22 fragments in data packet 400, and a value 23-27 can be interpreted as 33-37 fragments in data packet 400 (i.e., 10 more than the indicated value). Other values ​​for the length field 430 can be defined by the vendor, not the protocol.

[0079] The command of data packet 400 is stored in command field 435, a seven-bit field. The command can be a write command, a read command, a predefined atomic operation command, a custom atomic operation command, a read response, an acknowledgment response, or a vendor-specific command. Additionally, the command can indicate the virtual channel of data packet 400. For example, different commands can be used for different virtual channels, or bits 1, 2, 3, or 4 of the seven-bit command field 435 can be used to indicate the virtual channel, and the remaining bits can be used to indicate the command.

[0080] Memory access commands can further identify the number of bytes to be written or accessed, the memory space to be accessed (e.g., off-die memory 375 or instruction memory for custom atomic operations), or any suitable combination thereof. In some example embodiments, the command may instruct additional bits on a subsequent microchip to identify the command. For instance, a multi-byte command containing a larger command can be sent using a vendor-specific command in the seven-bit command field 435 and some or all of the 32-bit data field 445.

[0081] If WEM is enabled, then CR / WEM fields 440 and 450 are four-bit masks indicating whether each of the corresponding bytes of the 32 data bits in the microchip will be written. Therefore, the size of a single microchip is always 36 bits, but it can contain 0-32 data bits to be written. If CR is enabled, then two bits of CR / WEM fields 440 and 450 identify whether the credit return is for virtual channel 0, 1, 2, or 3, and the other two bits of CR / WEM fields 440 and 450 indicate whether the number of credits to be returned is 0, 1, 2, or 3.

[0082] Figure 5This is a block diagram of a credit packet 500 suitable for use in a system using credit-based flow control, according to some embodiments of this disclosure. The credit packet 500 includes a single 36-bit microchip. The microchip contains four credit return fields 505, 510, 515, and 520, a length field 530, and reserved fields 525 and 535. The length field 530 is set to zero to indicate that no additional microchips constitute the credit packet 500. The reserved fields 525 and 535 are unused and should be set to zero.

[0083] Each of the credit return fields 505 to 520 is a five-bit field. If credit is being returned to a low virtual channel, the first bit of credit return fields 505 to 520 is set to zero. If credit is being returned to a high virtual channel, the first bit of credit return fields 505 to 520 is set to one. The remaining four bits of each credit return field 505 to 520 indicate the number of credits being returned (0 to 15). Therefore, CR0 credit return field 520 returns 0 to 15 credits to virtual channel 0 or 4; CR1 credit return field 515 returns 0 to 15 credits to virtual channel 1 or 5; CR2 credit return field 510 returns 0 to 15 credits to virtual channel 2 or 6; and CR3 credit return field 505 returns 0 to 15 credits to virtual channel 3 or 7.

[0084] Therefore, credit returns for credit-based flow control can be implemented by using the CR / WEM fields 440 and 450 of packet 400 when sending other packets (e.g., acknowledgment packets) or by using packet 500. In systems using credit-based flow control that do not support combined write enable mask and credit return fields, packet 400 must be modified to include an additional credit return field or an additional network packet, such as credit packet 500, must be sent to return credit.

[0085] Figure 6 This is a flowchart illustrating the operation of a method 600, performed by circuitry according to some embodiments of the present disclosure, which processes data packets using a combination of write enable mask and credit return fields. Method 600 includes operations 610, 620, and 630. By way of example and not limitation, method 600 is described as being used by the apparatus of Figures 1-3. Figures 4 to 5 The package is executed.

[0086] In operation 610, the circuit (e.g., chiplet 210D) receives a packet from a source (e.g., chiplet 210A) that includes a first field and a second field. In some example embodiments, the packet is a data packet 400, the first field is a CP field 405, and the second field is a CR / WEM field 440.

[0087] In operation 620, if the first field has a first value, then the circuit interprets the second field as a write-enabled mask. For example, chip 210A can send data packet 400, where the CP field 405 contains a 1-bit indicating that the CR / WEM field 440 is WEM. WEM indicates that some of the data field 445 will be written to memory, but some of the data field 445 will be discarded.

[0088] In operation 630, if the first field has a second value, then the second field is interpreted as a credit return value. For example, chip 210A can transmit data packet 400, where the CP field 405 contains a 0 bit indicating that the CR / WEM field 440 contains a credit return value. Therefore, chip 210D receiving packets increments the available credit of the virtual channel on which it transmits packets, as indicated by the value in the command field 435. In some example embodiments, there are multiple CR / WEM fields 440, 450, and each of the multiple CR / WEM fields 440, 450 is interpreted as a credit return value based on the first field having a second value.

[0089] Figure 7 This is a flowchart illustrating the operation of method 700, performed by circuitry according to some embodiments of the present disclosure, which processes data packets using a combination of write-enable mask and credit return fields. Method 700 includes operations 610 and 620 and operations 710 and 720 of method 600. By way of example and not limitation, method 700 is described as being used by the apparatus of Figures 1 to 3. Figures 4 to 5 The package is executed.

[0090] After receiving the packet in operation 610 and determining in operation 620 that the second field has been interpreted as a write enable mask, method 700 is executed. In operation 710, the circuitry identifies masked data by applying the write enable mask to the third field of the packet. For example, four bits of the CR / WEM field 440 may be used at the byte level to mask the 32-bit data field 445.

[0091] In operation 720, the circuit writes masking data to memory. For example, the masking data can be written to off-die memory 375. Therefore, by using method 700, masking data can be written to memory without the need for a dedicated write-enabled mask field in data packet 400.

[0092] Figure 8 This is a flowchart illustrating the operation of method 800, performed by circuitry according to some embodiments of the present disclosure, which utilizes a combination of write-enable mask and credit return fields to process data packets. Method 800 includes operations 610 and 630 of method 600, as well as operations 810 and 820. By way of example and not limitation, method 800 is described as being used by the apparatus of Figures 1 to 3. Figures 4 to 5The package is executed.

[0093] Method 800 is executed after receiving the packet in operation 610 and determining in operation 630 to interpret the second field as a credit return field. In operation 810, the circuitry modifies the credit data (e.g., data representing the credit of a channel) based on the credit return value. The credit balance can be stored in a register file with one entry for each channel. For example, the four-bit CR / WEM field 440 indicates a value from 0 to 15 and adds the corresponding number of credits to the credit balance of the circuitry transmitting the data packet. In another instance, the CR / WEM field 440 is considered a credit return field only when at least one credit is returned. Therefore, the 4-bit value of the CR / WEM field 440 can be interpreted as a value from 1 to 16. In another instance, the first two bits of the CR / WEM field 440 specify one of four virtual channels to supplement credits at the sender, and the second two bits specify the number of credits to be returned (0 to 3). In yet another example embodiment, the CR / WEM field 440 is used to look up the number of credits returned in a lookup table, thereby allowing any number of credits to be returned, as long as the encoding used by the transmitting and receiving circuits is agreed upon.

[0094] In operation 820, data is written from the third field of the packet to memory without applying a mask. For example, all 32 bits of data field 445 can be written to off-chip memory 375 without applying a mask. Therefore, by using method 800, credit return data can be provided in packet 400 without requiring a dedicated credit return field.

[0095] Figure 9 This is a flowchart illustrating the operation of a method 900, performed by circuitry according to some embodiments of the present disclosure, for processing data packets using a combination of write enable mask and credit return fields. Method 900 includes operations 910, 920, 930, 940, and 950. By way of example and not limitation, method 900 is described as being used by the apparatus of Figures 1 to 3. Figures 4 to 5 The package is executed.

[0096] In operation 910, the circuit (e.g., chip 210D) receives multiple packets from a source (e.g., chip 210A), each comprising a first field, a second field, and a third field including data. In some example embodiments, each packet has the form of a data packet 400, the first field being a CP field 405, the second field being a CR / WEM field 440, and the third field being a data field 445.

[0097] In operation 920, the circuit determines whether the first field of the first packet has a first value or a second value. For example, chip 210A can send data packet 400, where the CP field 405 contains a 1-bit field indicating whether the CR / WEM field 440 is a WEM or a credit return value.

[0098] In response to determining that the first field of the first packet has a first value (e.g., indicating that the CR / WEM field 440 will be interpreted as the WEM value 2 or 3), the circuit interprets the second field of the first packet as WEM, identifies the masked data by applying WEM to the third field of the first packet, and writes the masked data to memory (operation 930).

[0099] In operation 940, the circuit determines whether the second field of the second packet has a first value or a second value. In response to determining in operation 950 that the first field of the second packet has a second value, the circuit interprets the second field of the second packet as a credit return value and modifies the credit data based on the credit return value. In some example embodiments, data is written from the third field of the second packet to memory without applying a mask.

[0100] Therefore, by using method 900, an enable mask is written for use in the first data packet and provides credit return data in the second data packet, without requiring a dedicated credit return field and using the same packet format for both data packets.

[0101] Figure 10A block diagram illustrating an example machine 1000 is provided, which may utilize, be in, or be used to implement any or more of the techniques (e.g., methods) discussed herein. As described herein, an example may include, or be operated by, logic or multiple components or mechanisms in machine 1000. A circuit system (e.g., a processing circuit system) is a collection of circuits implemented in the tangible entity of machine 1000, which includes hardware (e.g., simple circuits, gates, logic, etc.). The membership of a circuit system may be flexible over time. A circuit system includes members that can perform a specified task individually or in combination during operation. In an example, the hardware of a circuit system may be designed in an immutable manner to perform a specific operation (e.g., hardwiring). In an example, the hardware of a circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) that include machine-readable media that are physically modified (e.g., invariant magnetic properties of concentrated particles, electrically movable placement, etc.) to encode instructions for a specific operation. When connecting physical components, the fundamental electrical properties of the hardware components are altered, for example, from an insulator to a conductor, or vice versa. Instructions enable embedded hardware (e.g., an execution unit or loading mechanism) to hardware-create parts of a circuit system via variable connections to perform specific operations when in operation. Thus, in an example, a machine-readable medium element is part of the circuit system or communicatively coupled to other components of the circuit system during device operation. In an example, any one of the physical components can be used in more than one part of more than one circuit system. For example, under operation, an execution unit may be used at one point in time in a first circuit of a first circuit system and reused by a second circuit of the first circuit system, or reused at a different time by a third circuit of a second circuit system. Further examples of these components of machine 1000 are given below.

[0102] In alternative embodiments, machine 1000 may act as a standalone device or be connectable (e.g., networked) to other machines. In a networked deployment, machine 1000 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, machine 1000 may act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 1000 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network appliance, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) instructions specifying actions to be taken by said machine. Furthermore, while only a single machine is described, the term "machine" should also be considered as encompassing any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methods discussed herein, such as cloud computing, Software as a Service (SaaS), or other computer cluster configurations.

[0103] Machine (e.g., computer system) 1000 may include a hardware processor 1002 (e.g., a central processing unit (CPU), graphics processing unit (GPU), hardware processor core, or any combination thereof), main memory 1004, static memory (e.g., firmware, microcode memory or storage device, basic input / output (BIOS), unified extensible firmware interface (UEFI), etc.) 1006, and mass storage device 1008 (e.g., hard disk drive, tape drive, flash memory device, or other block device), some or all of which may communicate with each other via interconnect (e.g., bus) 1030. Machine 1000 may further include a display unit 1010, an alphanumeric input device 1012 (e.g., keyboard), and a user interface (UI) navigation device 1014 (e.g., mouse). In an example, the display unit 1010, input device 1012, and UI navigation device 1014 may be a touchscreen display. Machine 1000 may additionally include a storage device (e.g., a drive unit) 1008, a signal generating device 1018 (e.g., a speaker), a network interface device 1020, and one or more sensors 1016, such as a Global Positioning System (GPS) sensor, a compass, an accelerometer, or other sensors. Machine 1000 may include an output controller 1028, for example, serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection, to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0104] The registers of processor 1002, main memory 1004, static memory 1006, or mass storage device 1008 may be or contain machine-readable medium 1022, on which one or more data structures or sets of instructions 1024 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein may be stored. Instructions 1024 may also reside wholly or at least partially in any of the registers of processor 1002, main memory 1004, static memory 1006, or mass storage device 1008 during execution by machine 1000. In an example, one or any combination of hardware processor 1002, main memory 1004, static memory 1006, or mass storage device 1008 may constitute machine-readable medium 1022. While machine-readable medium 1022 is described as a single medium, the term "machine-readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store the one or more instructions 1024.

[0105] The term "machine-readable medium" can include any medium capable of storing, encoding, or carrying instructions for execution by machine 1000 and causing machine 1000 to perform any one or more of the technologies disclosed herein, or any medium capable of storing, encoding, or carrying data structures used by or associated with such instructions. Examples of non-limiting machine-readable media can include solid-state memory, optical media, magnetic media, and signals (e.g., radio frequency signals, other photon-based signals, sound signals, etc.). In examples, non-transitory machine-readable media includes machine-readable media having a plurality of particles having an invariant (e.g., rest) mass and therefore being composed of matter. Thus, a non-transitory machine-readable medium is a machine-readable medium that does not contain transiently propagating signals. Specific examples of non-transitory machine-readable media can include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0106] In this example, information stored or otherwise provided on the machine-readable medium 1022 may represent instructions 1024, such as instructions 1024 themselves or a format from which instructions 1024 may be derived. This format from which instructions 1024 may be derived may include source code, encoded instructions (e.g., in compressed or encrypted form), packaged instructions (e.g., split into multiple packages), etc. The information representing instructions 1024 in the machine-readable medium 1022 may be processed by a processing circuitry system into instructions to perform any of the operations discussed herein. For example, deriving instructions 1024 from information (e.g., processed by a processing circuitry system) may include: compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamically or statically linking), encoding, decoding, encrypting, decrypting, packaging, depackaging, or otherwise manipulating information into instructions 1024.

[0107] In an example, the derivation of instruction 1024 may involve assembling, compiling, or decompiling information (e.g., by a processing circuit system) to create instruction 1024 from some intermediate or preprocessed format provided by machine-readable medium 1022. When information is provided in multiple parts, the information may be combined, decapsulated, and modified to create instruction 1024. For example, information may be contained in multiple compressed source code packages (or object code, or binary executable code, etc.) on one or more remote servers. The source code packages may be encrypted when transmitted over a network and, if necessary, decrypted, decompressed, assembled (e.g., linked), and compiled or decompiled at the local machine (e.g., into a stand-alone executable library, etc.) and executed by the local machine.

[0108] Instruction 1024 can further utilize any of a plurality of transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.) to transmit or receive on the communication network 1026 via the network interface device 1020 using a transmission medium. Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone (POTS) networks, and wireless data networks (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series standards, referred to as… The IEEE 802.16 series of standards are called This includes standards such as IEEE 802.15.4 series and peer-to-peer (P2P) networks. In an example, network interface device 1020 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to communication network 1026. In an example, network interface device 1020 may include multiple antennas to perform wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmitting medium" should be considered as any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 1000, and containing digital or analog communication signals or other intangible media used to facilitate communication of this software. The transmitting medium is a machine-readable medium.

[0109] In the foregoing description, some exemplary embodiments of this disclosure have been described. It will be apparent that various modifications may be made to this disclosure without departing from the broader scope and spirit of this disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense. The following is a non-exhaustive list of examples of embodiments of this disclosure.

[0110] Example 1 is a system comprising: a memory controller configured to execute instructions to perform operations, including: receiving, across a network, a plurality of packets including a first field, a second field, and a third field including data from a source; determining whether the first field of a first packet has a first value or a second value; in response to determining that the first field of the first packet has the first value, interpreting the second field of the first packet as a write enable mask, identifying masked data by applying the write enable mask to the third field of the first packet, and writing the masked data to memory; determining whether the first field of a second packet has the first value or the second value; and in response to determining that the first field of the second packet has the second value, interpreting the second field of the second packet as a credit return value and modifying credit data based on the credit return value.

[0111] In Example 2, the subject matter according to Example 1 includes the memory controller being on a first chiplet, and the memory being on a second chiplet.

[0112] In Example 3, the subject matter according to Examples 1 and 2 includes the memory controller communicating with the memory via a dual data rate (DDR) memory interface.

[0113] In Example 4, the subject matter according to Examples 1 to 3 includes: the memory controller is on a first chiplet; the memory is on a second chiplet; and the memory controller communicates with the memory chiplet via a network.

[0114] In Example 5, the subject matter described in Examples 1 to 4 includes: the first field is a 2-digit field; and the second field is a 4-digit field.

[0115] In Example 6, the subject matter described in Examples 1 to 5 includes, wherein: the first field is a 1-bit field; and the second field is a 4-bit field.

[0116] In Example 7, the subject matter according to Examples 1 to 6 includes, wherein: the system further includes a memory storing data of each of a plurality of channels, the data of the channels representing the credit of the channels; the packet further includes a third field identifying the channels among the plurality of channels; and the operation further includes modifying the credit data of the identified channel based on the credit return value if the first field has the second value.

[0117] In Example 8, the subject matter according to Examples 1 to 7 includes, wherein the operation further includes: in response to determining that the first field of the second packet has the second value, writing the third field to the memory without applying a mask.

[0118] Example 9 is a non-transitory machine-readable medium storing instructions that, when executed by a system, cause the system to perform operations including: receiving, via a memory controller, multiple packets from a source across a network, including a first field, a second field, and a third field including data; determining whether the first field of a first packet has a first value or a second value; in response to determining that the first field of the first packet has the first value, interpreting the second field of the first packet as a write-enabled mask, identifying masked data by applying the write-enabled mask to the third field of the first packet, and writing the masked data into memory; determining whether the first field of a second packet has the first value or the second value; and in response to determining that the first field of the second packet has the second value, interpreting the second field of the second packet as a credit return value and modifying credit data based on the credit return value.

[0119] In Example 10, the subject matter according to Example 9 includes the memory controller being on a first chiplet, and the memory being on a second chiplet.

[0120] In Example 11, the subject matter according to Examples 9 and 10 includes the memory controller communicating with the memory chiplet via a dual data rate (DDR) memory interface.

[0121] In Example 12, the subject matter according to Examples 9 to 11 includes the following: the memory controller is on a first chiplet; the memory is on a second chiplet; and the memory controller communicates with the memory chiplet via a network.

[0122] In Example 13, the subject matter according to Examples 9 to 12 includes, wherein: the first field is a 2-digit field; and the second field is a 4-digit field.

[0123] In Example 14, the subject matter according to Examples 9 to 13 includes, wherein: the first field is a 1-bit field; and the second field is a 4-bit field.

[0124] In Example 15, the subject matter according to Examples 9 to 14 includes, wherein: the system further includes a memory storing data of each of a plurality of channels, the data of the channels representing the credit of the channels; the packet further includes a third field identifying the channels among the plurality of channels; and the operation further includes modifying the credit data of the identified channel based on the credit return value if the first field has the second value.

[0125] Example 16 is a method comprising: receiving, via a memory controller, multiple packets from a source comprising a first field, a second field, and a third field comprising data across a network; determining whether the first field of a first packet has a first value or a second value; in response to determining that the first field of the first packet has the first value, interpreting the second field of the first packet as a write enable mask, identifying masked data by applying the write enable mask to the third field of the first packet, and writing the masked data to a memory; determining whether the first field of a second packet has the first value or the second value; and in response to determining that the first field of the second packet has the second value, interpreting the second field of the second packet as a credit return value and modifying credit data based on the credit return value.

[0126] In Example 17, the subject matter according to Example 16 includes the memory controller being on a first chiplet, and the memory being on a second chiplet.

[0127] In Example 18, the subject matter according to Examples 16 and 17 includes the memory controller communicating with the memory chiplet via a dual data rate (DDR) memory interface.

[0128] In Example 19, the subject matter according to Examples 16 to 18 includes the following: the memory controller is on a first chiplet; the memory is on a second chiplet; and the memory controller communicates with the memory chiplet via a network.

[0129] In Example 20, the subject matter described in Examples 16 to 19 includes, wherein: the first field is a 2-digit field; and the second field is a 4-digit field.

[0130] Example 21 is at least one machine-readable medium containing instructions that, when executed by a processing circuitry system, cause the processing circuitry system to perform operations to implement any one of Examples 1 to 20.

[0131] Example 22 is a device that includes components for implementing any one of Examples 1 to 20.

[0132] Example 23 is a system for implementing any one of Examples 1 to 20.

[0133] Example 24 is a method for implementing any of Examples 1 through 20.

[0134] Example 25 is any of the memory devices of Examples 1 to 8 that are adapted and configured to perform operations according to any of the methods of Examples 16 to 20.

[0135] Example 26 is any of the memory devices of Examples 1 to 8, which is incorporated into an electronic system that further includes a host processor and a communication bus extending between the host processor and the memory controller.

[0136] Example 27 is any of the memory devices of Examples 1 to 8 that have been modified to include any structure presented in another of Examples 1 to 8.

[0137] Example 28 is an electronic system comprising a host processor and a communication interface extending between the host processor and a memory controller, configured to perform operations according to any of the methods of Examples 16 to 20 or 24.

[0138] Example 29 is any of the methods in Examples 16 to 20 or 24, modified to include the operations described in any of the other examples in Examples 16 to 20.

[0139] Example 30 is any of the methods of Examples 16 to 20, 24 or 29, which are implemented at least in part by using instructions stored as physical state in one or more machine-readable storage devices.

[0140] Example 31 is any of the devices of Examples 1 to 8, 21 to 23, or 25 to 27, which further includes a machine-readable storage device configured to store instructions as a physical state, wherein the instructions can be used to perform one or more operations of the device.

Claims

1. A system for data packets, comprising: a memory controller configured to execute instructions to perform operations, including: receiving from a source across a network: a first packet and a second packet, each of the first packet and the second packet including a first field, a second field, and a third field including data; determining whether the first field of the first packet has a first value or a second value; in response to determining that the first field of the first packet has the first value, interpreting the second field of the first packet as a write enable mask, identifying masked data by applying the write enable mask to the third field of the first packet, and writing the masked data to a memory; determining whether the first field of the second packet has the first value or the second value; and in response to determining that the first field of the second packet has the second value, interpreting the second field of the second packet as a credit return value and modifying credit data based on the credit return value.

2. The system of claim 1, wherein the memory controller is on a first chiplet, and wherein the memory is on a second chiplet.

3. The system of claim 1, wherein the memory controller communicates with the memory through a double data rate (DDR) memory interface.

4. The system of claim 1, wherein: the memory controller is on a first chiplet; the memory is on a second chiplet; and the first chiplet communicates with the second chiplet through the network.

5. The system of claim 1, wherein: the first field is a 2-bit field; and the second field is a 4-bit field.

6. The system of claim 1, wherein: the first field is a 1-bit field; and the second field is a 4-bit field.

7. The system of claim 1, wherein: the system further comprises a second memory storing data for each of a plurality of channels, the data for each channel representing credits for the channel; the second packet further includes a fourth field identifying a channel of the plurality of channels; and the operations further comprise, in response to determining that the first field of the second packet has the second value, then: modifying the data for the identified channel based on the credit return value.

8. The system of claim 1, wherein the operations further comprise: in response to determining that the first field of the second packet has the second value, writing the third field of the second packet to the memory without applying a mask.

9. A non-transitory machine-readable medium storing instructions that, when executed by a system, cause the system to perform operations including: receiving from a source across a network, by a memory controller: a first packet and a second packet, each of the first packet and the second packet including a first field, a second field, and a third field including data; determining whether the first field of the first packet has a first value or a second value; ​ in response to determining that the first field of the first packet has the first value, interpreting the second field of the first packet as a write enable mask, identifying masked data by applying the write enable mask to the third field of the first packet, and writing the masked data to a memory; determining whether the first field of the second packet has the first value or the second value; and in response to determining that the first field of the second packet has the second value, interpreting the second field of the second packet as a credit return value and modifying credit data based on the credit return value.

10. The non-transitory machine readable medium of claim 9, wherein the memory controller is on a first chiplet and wherein the memory is on a second chiplet.

11. The non-transitory machine readable medium of claim 9, wherein the memory controller communicates with the memory through a double data rate (DDR) memory interface.

12. The non-transitory machine readable medium of claim 9, wherein: the memory controller is on a first chiplet; the memory is on a second chiplet; and the first chiplet communicates with the second chiplet through the network.

13. The non-transitory machine readable medium of claim 9, wherein: the first field is a 2-bit field; and the second field is a 4-bit field.

14. The non-transitory machine readable medium of claim 9, wherein: the first field is a 1-bit field; and the second field is a 4-bit field.

15. The non-transitory machine readable medium of claim 9, wherein: the system further comprises a second memory storing data for each of a plurality of channels, the data for each channel representing credits for the channel; the second packet further comprises a fourth field identifying a channel of the plurality of channels; and the operations further comprise, in response to determining that the first field of the second packet has the second value, then: modifying the data for the identified channel based on the credit return value.

16. A method for data packets, comprising: receiving, by a memory controller from a source across a network: a first packet and a second packet, each of the first packet and the second packet comprising a first field, a second field, and a third field comprising data; determining whether the first field of the first packet has a first value or a second value; in response to determining that the first field of the first packet has the first value, interpreting the second field of the first packet as a write enable mask, identifying masked data by applying the write enable mask to the third field of the first packet, and writing the masked data to a memory; determining whether the first field of the second packet has the first value or the second value; and in response to determining that the first field of the second packet has the second value, interpreting the second field of the second packet as a credit return value and modifying credit data based on the credit return value.

17. The method of claim 16, wherein the memory controller is on a first chiplet, and wherein the memory is on a second chiplet.

18. The method of claim 16, wherein the memory controller communicates with the memory through a double data rate (DDR) memory interface.

19. The method of claim 16, wherein: the memory controller is on a first chiplet; the memory is on a second chiplet; and the first chiplet communicates with the second chiplet through the network.

20. The method of claim 16, wherein: the first field is a 2-bit field; and the second field is a 4-bit field.

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