Memory

Abstract

An embodiment of the present disclosure provides a memory, including: bit lines extending in a first direction and word lines extending in a second direction; column selection circuits arranged in the first direction and a plurality of memory modules; column selection lines extending in the first direction, the column selection lines being electrically connected to the column selection circuits, and the column selection circuits driving the corresponding amplification units via the column selection lines; a read / write control driving circuit, the read / write control driving circuit and the column selection circuits being respectively located on adjacent sides of the plurality of memory modules; global data lines extending in the second direction and electrical connection lines extending in a third direction, the global data lines being electrically connected to the read / write control driving circuit via the electrical connection lines, and the read / write control driving circuit being configured to drive the memory modules corresponding to the global data lines, so that data is written into the memory cells via the global data lines, or data is read out from the memory cells and transmitted to the global data lines. The embodiments of the present disclosure can improve the storage performance of the memory.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and particularly to a memory. Background Art

[0002] A semiconductor memory consists of many repeated memory cells. Each memory cell generally includes a capacitor and a transistor. The gate of the transistor is connected to a word line, the drain is connected to a bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.

[0003] Semiconductor memories can be divided into non-volatile memories and volatile memories. As a volatile memory, Dynamic Random Access Memory (DRAM) has advantages such as high storage density and fast read / write speed, and is widely used in various electronic systems. DRAM can be divided into DouBLe Data Rate (DDR) dynamic random access memory, Graphics DouBLe Data Rate (GDDR) dynamic random access memory, and Low Power DouBLe Data Rate (LPDDR) dynamic random access memory. Summary of the Invention

[0004] Embodiments of the present disclosure provide a memory, which is at least beneficial to improving the storage performance of the memory.

[0005] According to some embodiments of the present disclosure, some embodiments of the present disclosure provide a memory, including: bit lines extending along a first direction and word lines extending along a second direction; column selection circuits arranged along the first direction and a plurality of storage modules, the storage modules including: a storage array arranged along the first direction and an amplifier array, the storage array including at least one storage cell, the amplifier array including at least one amplification unit, each of the bit lines being electrically connected to one end of a corresponding one of the amplification units, each of the word lines being electrically connected to a corresponding one of the storage cells; column selection lines extending along the first direction, the column selection lines being electrically connected to the column selection circuits, and the column selection circuits driving corresponding ones of the amplification units via the column selection lines; a read / write control driving circuit, the read / write control driving circuit and the column selection circuit being respectively located on adjacent sides of the plurality of storage modules; a global data line extending along the second direction and an electrical connection line extending along a third direction, the global data line being electrically connected to the read / write control driving circuit via the electrical connection line, and the read / write control driving circuit being configured to drive the storage module corresponding to the global data line, so that data is written into the storage cell via the global data line, or, data is read out from the storage cell and the data is transmitted to the global data line.

[0006] In some embodiments, along the first direction, the plurality of storage modules are sorted in ascending order of natural numbers, the storage modules in odd positions are defined as first storage modules, and the storage modules in even positions are defined as second storage modules; the global data line includes: a first global data line corresponding to the first storage modules; a second global data line corresponding to the second storage modules; the electrical connection line includes: a first electrical connection line electrically connecting the first global data line and the read / write control driving circuit; a second electrical connection line electrically connecting the second global data line and the read / write control driving circuit.

[0007] In some embodiments, each of the first global data lines corresponds to all of the first storage modules; each of the second global data lines corresponds to all of the second storage modules.

[0008] In some embodiments, the number of the first global data lines and the number of the second global data lines are both multiple, wherein each of the first global data lines corresponds to a partial number of the first storage modules, and each of the second global data lines corresponds to a partial number of the second storage modules.

[0009] In some embodiments, the read-write control driving circuit includes: a plurality of read-write control driving units arranged along the first direction, and each read-write control driving unit is electrically connected to at least one of the first global data lines and at least one of the second global data lines.

[0010] In some embodiments, the global data lines electrically connected to different read-write control driving units are distributed at intervals.

[0011] In some embodiments, there are multiple global data lines, and all the global data lines are distributed at the edges of multiple storage modules.

[0012] In some embodiments, the multiple storage modules are divided into at least two module regions arranged along the first direction, each module region includes at least two storage modules, and the global data lines of different module regions are independent of each other; the read-write control driving circuit includes: at least two read-write control driving modules arranged along the first direction, each read-write control driving module is located on one side of the corresponding module region, and the read-write control driving module is electrically connected to the corresponding global data line via the electrical connection line.

[0013] In some embodiments, the read-write control driving circuit is configured such that when the word line corresponding to the module region is enabled, the read-write control driving module corresponding to the module region drives the storage modules in the module region via the global data line.

[0014] In some embodiments, there are multiple global data lines in the same module region, and the multiple global data lines are divided into at least two groups, and each group of global data lines corresponds to at least two adjacent storage modules.

[0015] In some embodiments, for the same module region, all the global data lines are arranged adjacent to each other, or the global data lines of different groups are arranged at intervals.

[0016] In some embodiments, for the same module region, the read-write control driving module includes a plurality of read-write control driving units arranged along the first direction, and each read-write control driving unit is electrically connected to at least one group of the global data lines.

[0017] In some embodiments, the number of storage modules included in each module region is the same.

[0018] In some embodiments, the third direction is the same as the second direction.

[0019] In some embodiments, the first direction is perpendicular to the second direction.

[0020] In some embodiments, it further includes: a row decoding circuit, which is configured to select the memory cell electrically connected to the word line through the word line; the row decoding circuit is located on a side of the read / write control driving circuit away from the plurality of memory modules.

[0021] The technical solutions provided by the embodiments of the present disclosure have the following advantages:

[0022] The embodiments of the present disclosure provide a memory with excellent structural performance. The column selection circuit and the plurality of memory modules are arranged along the first direction. The read / write control driving circuit and the column selection circuit are respectively located on adjacent sides of the plurality of memory modules. The global data line extends along the second direction, and the electrical connection line extends along the third direction. Moreover, the global data line is electrically connected to the read / write control driving circuit via the electrical connection line. The read / write control driving circuit is configured to drive the memory module corresponding to the global data line. Since the read / write control driving circuit and the column selection circuit are located on adjacent sides of the plurality of memory modules, the chip layout corresponding to the memory is more flexible. In addition, the global data line and the electrical connection line form a T-shaped structure, and the signal transmission paths required for the read / write control driving circuit to drive the memory modules at the head and tail are less different, improving the RC delay characteristics of the read / write control driving circuit, which is beneficial to improving the read / write speed of the memory. Description of the Drawings

[0023] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the drawings in the figures do not constitute a proportional limitation.

[0024] Figure 1 It is a schematic structural diagram of a memory;

[0025] Figure 2 It is a schematic structural diagram of the memory provided by some embodiments of the present disclosure;

[0026] Figure 3 It is a schematic structural diagram of the memory module in the memory provided by some embodiments of the present disclosure;

[0027] Figure 4 It is a schematic circuit diagram of the amplification unit and the memory cell in the memory provided by some embodiments of the present disclosure;

[0028] Figure 5 It is a schematic layout diagram of each data trace in the memory provided by some embodiments of the present disclosure;

[0029] Figures 6 to 11 It is several schematic structural diagrams of the memory provided by some embodiments of the present disclosure. Detailed Embodiments

[0030] Figure 1 It is a schematic structural diagram of a memory. Refer to Figure 1 , the memory includes: a plurality of memory banks (also known as memory bodies) 10, each memory bank 10 includes a plurality of memory modules, and each memory module (also known as a section) includes a memory array 11 and a sense amplifier array 12. The memory array 11 includes a plurality of memory cells arranged in the x direction, and the sense amplifier array 12 includes a plurality of amplification units arranged in the x direction. The memory cells and the amplification units in the same column form a section. It can be understood that the column is defined as the column along the y direction, and the row is defined as the row along the x direction; a read / write control drive circuit 14, a column selection circuit (ydec) 13, and a row decoding circuit 15; a plurality of word lines WL extending in the x direction, and each word line WL is connected to the memory array 11 of the corresponding row; a plurality of bit lines BL extending in the y direction, and each bit line BL is connected to the memory array 11 of the corresponding column; column selection lines CSL (column select lines) extending in the y direction, and each column selection line csl is connected to the amplification unit in the sense amplifier array 12 of the corresponding column; a global data line Gdata extending in the y direction, the global data line is electrically connected to the amplification unit and is also electrically connected to the read / write control drive circuit 14. The read / write control drive circuit 14 is used to drive the memory module corresponding to the global data line Gdata; the row decoding circuit 15 is used to provide a voltage to the word line WL so that the corresponding word line WL is enabled.

[0031] In the above memory, the read / write control drive circuit 14 is located on one side of each memory bank 10, and the row decoding circuit 15 is located on the other side of each memory bank 10. This has certain limitations on the size and shape of the chip, affecting the optimization of chip packaging or manufacturing efficiency. Moreover, the above memory also has a problem that the RC delay of the read / write control drive circuit 14 driving different memory modules varies greatly. Specifically, the memory module closest to the read / write control drive circuit 14 is defined as the first memory module, and the memory module farthest from the read / write control drive circuit 14 is defined as the second memory module. The distance between the connection point of the same global data line Gdata to the first memory module and the connection point to the second memory module is relatively large, which results in a large difference in the time delay of the read / write control drive circuit driving the first memory module and the second memory module, and the time required for the read / write control drive circuit 14 to drive the second memory module is relatively long, which has an adverse effect on the read / write speed of the memory.

[0032] Embodiments of the present disclosure provide a memory, in which the read / write control drive circuit and the column selection circuit are respectively arranged on the adjacent sides of a plurality of memory modules to solve the RC delay problem, and make the chip design more flexible, improving the storage performance of the memory.

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will elaborate on each embodiment of the present disclosure in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are presented to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0034] Figure 2 Schematic structural diagram of a memory provided for some embodiments of the present disclosure Figure 3 Schematic structural diagram of a storage module in a memory provided for some embodiments of the present disclosure Figure 4 Schematic circuit diagram of an amplification unit and a storage unit in a memory provided for some embodiments of the present disclosure Figure 5 Schematic layout diagram of each data trace in a memory provided for some embodiments of the present disclosure Figures 6 to 11 Schematic diagrams of several structures of a memory provided for some embodiments of the present disclosure. It can be understood that the storage unit described herein refers to an array unit arranged by a basic storage unit composed of multiple capacitors and transistors.

[0035] Referring to Figure 2 and Figure 3 , a memory provided by an embodiment of the present disclosure includes: bit lines BL extending along a first direction Y and word lines WL extending along a second direction X1; column selection circuits 103 arranged along the first direction Y and multiple storage modules 102. The storage module 102 includes: a storage array 112 arranged along the first direction Y and an amplifier array 122. The storage array 112 includes at least one storage unit 21, and the amplifier array 122 includes at least one amplification unit 22. Each bit line BL is electrically connected to one end of a corresponding amplification unit 22, and each word line WL is electrically connected to a corresponding storage unit 21; a column selection line CSL extending along the first direction Y, and the column selection line CSL is electrically connected to the column selection circuit 103. The column selection circuit 103 drives a corresponding amplification unit 22 via the column selection line CSL; a read / write control drive circuit 101, where the read / write control drive circuit 101 and the column selection circuit 103 are respectively located on adjacent sides of multiple storage modules 102; a global data line Gdata extending along the second direction X1 and an electrical connection line CL1 extending along a third direction X2. The global data line Gdata is electrically connected to the read / write control drive circuit 103 via the electrical connection line. The read / write control drive circuit 103 is used to drive a storage module 102 corresponding to the global data line, so that data is written into the storage unit 21 via the global data line, or data is read from the storage unit 21 and transmitted to the global data line.

[0036] It should be noted that Figure 2 only one bit line BL and one word line WL are schematically shown. In fact, the memory includes multiple bit lines BL and multiple word lines WL. Figure 3 only one bit line BL and one column selection line CSL are schematically shown in one memory cell. In fact, multiple bit lines BL and multiple column selection lines CSL are connected in one memory cell.

[0037] In the above embodiments, the column selection circuit 103 and the read / write control driving circuit 101 are respectively located on the adjacent sides of multiple memory modules 102, so that the shape and size of the memory can be adjusted more flexibly, optimizing the production and manufacturing efficiency. Moreover, the arrangement direction of the read / write control driving circuit 101 and the memory module 102 is different from the extending direction of the global data line Gdata, so that the signal transmission paths required for the read / write control driving circuit 101 to drive different memory modules 102 are less different, thereby improving the RC delay characteristic and being beneficial to improving the read / write speed. In addition, by using the above memory, different memory modules 102 have the opportunity to be driven by the read / write control driving circuit 101 via the electrical connection line CL, which is beneficial to reducing the structural complexity of the read / write control driving circuit 101, reducing the size of the read / write control driving circuit 101, and saving the chip area of the memory.

[0038] In some embodiments, the memory can be a DRAM memory, such as a DDR (double data rate) 4 DRAM memory or a DDR5 DRAM memory. In other embodiments, the memory can also be an SRAM (Static Random-Access Memory) memory, a NAND memory, a NOR memory, a FeRAM memory or a PcRAM memory.

[0039] Reference Figure 3 , Figure 3 For Figure 2An enlarged schematic diagram of two adjacent memory modules 102. Each memory module 102 is referred to as a section. The memory array 112 may include a plurality of memory cells 21 arranged along the second direction X1, and the amplifier array 122 may include a plurality of amplifier units 22 arranged along the second direction X1. In some embodiments, each amplifier unit 22 may be electrically connected to a memory cell 21 in the same memory module 102 to amplify the data read out from the memory cell 21 during a read operation. In other embodiments, the amplifier unit 22 may also be electrically connected to a memory cell 21 in an adjacent memory module 102 to amplify the data read out from the memory cell 21 during a read operation. It can be understood that the embodiments of the present disclosure do not particularly limit the electrical connection correspondence between the memory cells and the amplifier units in the memory module, as long as the amplifier unit can amplify the data read out from the memory cell.

[0040] In some embodiments, the memory cell 21 may be a DRAM memory cell.

[0041] Reference Figure 4 , Figure 4 is a functional module schematic diagram of the amplifier unit 22 and the memory cell 21. The amplifier unit 22 is also referred to as a first-stage sense amplifier (FSA, First sense amplifier). The amplifier unit 22 has a control terminal, a first terminal, and a second port. The control terminal is used to be electrically connected to the column selection line CSL to receive a column selection signal. The first terminal is electrically connected to the bit line BL, and the second terminal is electrically connected to the local data line Ldata (Local Data Line). The memory cell 21 is electrically connected to the word line WL and the bit line BL. If the word line WL is enabled, the memory cell 21 electrically connected to the word line WL can perform a read operation, and data transmission occurs between the corresponding memory cell 21 and the bit line BL. Specifically, when the control terminal receives the column selection signal, the first terminal and the second terminal are turned on to enable data to be transmitted between the bit line BL and the local data line Ldata.

[0042] The bit line BL is electrically connected to the memory cells 21 arranged along the first direction Y in a plurality of memory arrays 112. All the memory cells 21 arranged along the first direction Y are electrically connected to the same bit line BL. It can be understood that the bit line BL may be presented in the form of a bus, and the same bit line BL refers to the same bit line bus.

[0043] The word line WL is electrically connected to the memory cells 21 arranged along the second direction X1 in a plurality of memory arrays 112. That is, the same word line WL is electrically connected to a row of memory cells 21 arranged along the second direction X1 in the same memory array 112. It can be understood that the word line WL may be presented in the form of a bus, and the same word line WL refers to the same word line bus.

[0044] The column selection circuit 103, commonly known as the YDEC circuit, is used to provide a column selection signal to the amplification unit 22 to select the amplification unit 22, so that data can be transmitted between the bit line BL and the local data line Ldata. The column selection line CSL is electrically connected to the column selection circuit 103 via the electrical connection line CL, and is used to provide a column selection signal to the control end of the corresponding amplification unit 22 to select the corresponding amplification unit 22, so that the amplification unit 22 can realize the functions of data transmission and amplification.

[0045] The electrical connection line CL is used to electrically connect the read / write control drive circuit 101 and the global data line Gdata (Global Data Line), so that the read / write control drive circuit 101 is electrically connected to the corresponding storage module 102. In some embodiments, the third direction X2 can be the same as the second direction X1, that is, the extending direction of the electrical connection line CL can be the same as the extending direction of the word line WL, and the first direction Y can be perpendicular to the third direction X2. In this way, the length of the electrical connection line CL can be made as short as possible, so that the path required for the read / write control drive circuit 101 to drive the storage module 102 is as short as possible, which is beneficial to further improving the read / write performance of the memory.

[0046] Each storage module 102 arranged along the first direction Y can be defined as a section. In some embodiments, the read / write control drive circuit 101 can be arranged at the middle position on one side of the multiple storage modules 102, which is beneficial to further shortening the signal transmission time difference required for the read / write control drive circuit 101 to drive the sections at the head end and the tail end, so as to further improve the overall performance of the memory. The column selection line CSL is used to conduct multiple bit lines BL and the corresponding local data lines Ldata in the same section. Each section includes multiple column selection lines CSL, and may also include a conventional column selection line CSL and a redundant column selection line CSL. When the memory is working. One column selection line CSL in each section will be selected and turned on.

[0047] As analyzed above, in some embodiments, the memory may further include: local data lines Ldata, each local data line Ldata extends along the second direction X1, and the same local data line Ldata is electrically connected to the second end of the amplification unit 22 in the same amplifier array 122. It can be understood that one amplifier array 122 can be connected to multiple local data lines Ldata

[0048] In some embodiments, the memory may further include complementary bit lines, and correspondingly, the memory may further include: local complementary data lines.

[0049] In some embodiments, refer to Figure 3 and Figure 4, the storage module 102 may further include: a local read / write conversion circuit 132, which is electrically connected to the second end of the amplification unit 22. Specifically, the local read / write conversion circuit 132 is electrically connected to the second end of the amplification unit 22 through local data lines. The local read / write conversion circuit 132 is used to implement data transmission between the local data lines and the global data line Gdata. More specifically, multiple local read / write conversion circuits 132 may be electrically connected to the same global data line Gdata. The read / write control driving circuit 101 driving the storage module 102 means that, in the writing stage, the read / write control driving circuit 101 drives the corresponding local read / write conversion circuit 132 of the storage module 102 to perform data transmission from the local data lines to the global data line Gdata, and in the reading stage, the read / write control driving circuit 101 drives the corresponding local read / write conversion circuit 132 of the storage module 192 to perform data transmission from the global data line Gdata to the local data lines.

[0050] Reference Figure 3 , the local read / write conversion circuit 132 may be arranged on one side of the amplifier array 122, and the local read / write conversion circuits 132 of each storage module 102 are arranged on the same side of the corresponding amplifier array 132. In this way, the length of the global data line Gdata can be saved, which is beneficial to improving the read / write speed. In some other embodiments, the local read / write conversion circuit 132 may be arranged within the amplifier array 122, that is, the local read / write conversion circuit 132 is arranged between any adjacent amplification units 22, and the local read / write conversion circuits 132 of different storage modules 102 are arranged at the same position of the corresponding amplifier array 122. For example, the local read / write conversion circuit 132 of each storage module 102 is arranged between the fifth amplification unit 22 and the sixth amplification unit 22, or the local read / write conversion circuit 132 of each storage module 102 is arranged between the tenth amplification unit 22 and the eleventh amplification unit 22.

[0051] Refer to Figure 5 , Figure 5 is a layout schematic diagram of each data trace in the memory provided by the embodiments of the present disclosure. The data traces include a global data line Gdata, an electrical connection line CL, a column selection line CSL, a bit line BL, and a word line WL. Among them, the bit line BL, the global data line Gdata, and the column selection line CSL have the same trace direction, and the electrical connection line CL and the word line WL have the same trace direction.

[0052] In some embodiments, reference Figure 2, the memory may further include: a row decoding circuit 104, which is used to select a memory cell 21 electrically connected to a word line WL through the word line WL, so that the memory cell 21 electrically connected to the word line WL performs read and write operations. Specifically, the row decoding circuit 104 and the read / write control driving circuit 101 may be located on the same side of a plurality of memory modules 102, and the row decoding circuit 104 may be located on the side of the read / write control driving circuit 101 away from the plurality of memory modules 102.

[0053] In some embodiments, the row decoding circuit 104 and the read / write control driving circuit 101 may be on the same layer of the memory. In other embodiments, the row decoding circuit 104 and the read / write control driving circuit 101 may also be on different layers of the memory.

[0054] In the first direction Y, the plurality of memory modules 102 are sorted in ascending order of natural numbers. The memory modules 102 in odd positions are defined as first memory modules, and the memory modules 102 in even positions are defined as second memory modules; the global data line Gdata includes: a first global data line G1, which corresponds to the first memory module; a second global data line G2, which corresponds to the second memory module; the electrical connection line CL includes: a first electrical connection line CL1, which electrically connects the first global data line G1 and the read / write control driving circuit 101; a second electrical connection line CL2, which electrically connects the second global data line G2 and the read / write control driving circuit 101. The first global data line G1 and the second global data line G2 are independent of each other, and the first electrical connection line CL1 and the second electrical connection line CL2 are independent of each other; wherein, both the first electrical connection line CL1 and the second electrical connection line CL2 extend along the third direction X2.

[0055] Specifically, in some embodiments, referring to Figure 2 , each first global data line G1 may correspond to all first memory modules, and each second global data line G2 may correspond to all second memory modules, that is, the read / write control driving circuit 101 can simultaneously drive all first memory modules through the same first global data line G1, and the read / write control driving circuit 101 can simultaneously drive all second memory modules through the same second global data line G2, which is beneficial to reducing the number of the first global data line 1 and the second global data line G2 and reducing the power consumption of the memory.

[0056] In other embodiments, referring to Figure 6, the number of the first global data line G1 and the second global data line G2 can both be multiple. Each first global data line G1 corresponds to a partial number of the first storage modules, and each second global data line G2 corresponds to a partial number of the second storage modules. That is, the read / write control driving circuit 101 only needs to drive a partial number of the first storage modules or a partial number of the second storage modules each time, which is beneficial to reducing the load that the read / write control driving circuit 101 needs to drive each time and improving the signal transmission speed. For example, one of the first global data lines G1 is connected to the storage modules 102 sorted as 1, 5, 9, and 13, and one of the second global data lines G2 is connected to the storage modules 102 sorted as 2, 6, 10, and 14; another first global data line G1 is connected to the storage modules 102 sorted as 3, 7, and 11, and another second global data line G2 is connected to the storage modules 102 sorted as 4, 8, and 12.

[0057] In some embodiments, with reference to Figure 7 , Figure 7 FIG. is a schematic diagram of different structures of the memory provided by the embodiments of the present disclosure. The read / write control driving circuit (not labeled) may include: a plurality of read / write control driving units 111 arranged along the first direction Y, and each read / write control driving unit 111 is electrically connected to at least one first global data line G1 and at least one second global data line G2 via an electrical connection line CL. In this way, different areas can be driven by different read / write control driving units 111, making the driving method of different areas in the memory more flexible.

[0058] In some embodiments, the global data lines Gdata electrically connected to different read / write control driving units 111 are distributed at intervals. For example, a partial number of the global data lines Gdata are distributed at the edges of the plurality of storage modules 102, and the remaining global data lines Gdata are distributed in the middle area of the plurality of storage modules 102. Since the different global data lines Gdata are distributed at intervals, signal interference between different global data lines Gdata can be avoided, which is beneficial to further improving the storage performance of the memory.

[0059] It can be understood that in some embodiments, there can be multiple global data lines Gdata, and all the global data lines Gdata can be distributed at the edges of the plurality of storage modules 102.

[0060] In some embodiments, with reference to Figure 3 、 Figures 8 to 11 , Figures 8 to 11Schematic diagrams of different structures of a memory provided in some embodiments of the present disclosure. A plurality of memory modules 102 may be divided into at least two module regions I arranged along a first direction Y. Each module region I includes a plurality of memory modules 102. The read / write control driving circuit 101 may include a column selection circuit: at least two read / write control driving modules 110 arranged along the first direction Y. Each read / write control driving module 110 is located on one side of the corresponding module region I. The read / write control driving module 110 is electrically connected to the corresponding global data line Gdata via an electrical connection line CL. It should be noted that Figures 8 to 11 the amplifier array, memory cells, amplification units, word lines, and bit lines are not shown schematically. Only the memory array is shown in a box, and the amplifier array between adjacent memory arrays is not shown. For the arrangement of the amplifier array, memory cells, amplification units, word lines, and bit lines, reference may be made to the corresponding descriptions in the foregoing Figures 2 to 7 description.

[0061] Specifically, the number of memory modules 102 included in each module region I may be the same. In addition, the memory may also be divided into a high-address storage block U and a low-address storage block V. The layouts of the high-address storage block U and the low-address storage block V both include a plurality of memory modules 102.

[0062] Memory cells 21 in different module regions I are connected to different word lines. That is to say, there is a situation where the word lines in one module region I are enabled while the word lines in the remaining module regions I are not enabled. In this situation, since different module regions I have independent global data lines Gdata, the read / write control driving module 110 can only select the global data line Gdata corresponding to the module region I corresponding to the enabled word line WL to drive the memory modules 102 in that module region I, and the remaining module regions I do not need to be driven by the read / write control driving module 110, which can save more power consumption. And, compared with the scheme in which each global data line is electrically connected to the memory modules in all module regions, each module region I has independent global data lines Gdata, so that the length of each global data line Gdata is reduced, which is beneficial to reducing the resistance of the global data line Gdata; and the load on each global data line Gdata is reduced, which is beneficial to reducing heat loss and power consumption. It can be understood that the load includes the memory modules 102 electrically connected to the global data line Gdata.

[0063] As Figure 8 shown, in some embodiments, the number of module regions I may be 2. As Figure 11 shown, in other embodiments, the number of module regions I may also be 3. It can be understood that the number of module regions I can be reasonably set according to actual situations, and the embodiments of the present disclosure do not limit the number of module regions I.

[0064] In some embodiments, the read / write control driving circuit 101 may be configured such that when the word line WL corresponding to module region I is enabled, the read / write control driving module 110 corresponding to module region I drives the memory module 102 within module region I via the global data line Gdata. As can be seen from the foregoing, this is conducive to reducing the power consumption of the memory.

[0065] Reference Figure 8 and Figure 9 , in some embodiments, the same module region I may have multiple global data lines Gdata, and the multiple global data lines Gdata are divided into at least two groups, and each group of global data lines Gdata corresponds to at least two adjacent memory modules 102. The memory modules 102 corresponding to the two groups of global data lines Gdata can be respectively driven by the read / write control driving circuit 101, so that the driving mode selection of different memory modules 102 is more flexible; in addition, each group of global data lines Gdta corresponds to at least two adjacent memory modules 102, ensuring that adjacent memory modules 102 can be driven simultaneously.

[0066] Specifically, in some embodiments, reference Figure 8 , for the same module region I, all the global data lines Gdata may be arranged adjacent to each other. In this way, there is no need to consider the layout interference problem between the global data line Gdata and the column selection line CSL.

[0067] In other embodiments, reference Figure 9 , for the same module region I, different groups of global data lines Gdata may be arranged at intervals. Since the different groups of global data lines Gdata are spaced from each other, the problem of signal interference between different groups of global data lines Gdata can be avoided.

[0068] Reference Figure 10 , in some embodiments, for the same module region I, the read / write control driving module (not labeled) may include a plurality of read / write control driving units 111 arranged along the first direction Y, and each read / write control driving unit 111 is electrically connected to at least one group of global data lines Gdata. In this way, different memory modules 102 within the same module region I can be independently driven by different read / write control driving units 111. Moreover, the global data lines Gdata connected to different read / write control driving units 111 may be arranged at intervals, which is conducive to avoiding signal interference between different groups of global data lines Gdata and further improving the storage performance of the memory. It should be noted that Figure 10 only two module regions I are schematically shown herein, and the number of module regions I is not limited in the embodiments of the present disclosure. The module region I may be three, four or even more.

[0069] It should be noted that, in some embodiments, the global data lines Gdtata of different module regions I can be independent of each other. In some embodiments, as Figure 11 shown, the global data line Gdtata can correspond to at least two module regions I, and at least some of the memory modules 102 within at least two module regions I connected to the same global data line Gdtata share the global data line Gdtata. In this way, adjacent module regions I can share the global data line Gdtata, which is beneficial to reducing the number of global data lines Gdtata, and adjacent module regions I can share the read / write control driving module 110.

[0070] The embodiments of the present disclosure provide a memory with excellent structural performance. The column selection circuit 103 and the read / write control driving circuit 101 are arranged on different sides of multiple memory modules 102, making the chip design of the memory more flexible, beneficial to saving chip area, and shortening the time required for the column selection signal to be transmitted to the amplification unit 22 far from the read / write control driving circuit 101, which is beneficial to improving the RC delay problem and enhancing the read / write performance of the memory.

[0071] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure. In actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the scope defined in the claims.

Claims

1. A memory, characterized in that, Including: Bit lines extending along a first direction and word lines extending along a second direction; Column selection circuits arranged along the first direction and a plurality of storage modules, the storage modules including: a storage array arranged along the first direction and an amplifier array, the storage array including at least one storage cell, the amplifier array including at least one amplification unit, each of the bit lines being electrically connected to one end of a corresponding one of the amplification units, and each of the word lines being electrically connected to a corresponding one of the storage cells; Column selection lines extending along the first direction, the column selection lines being electrically connected to the column selection circuits, and the column selection circuits driving corresponding ones of the amplification units via the column selection lines; A read / write control driving circuit, the read / write control driving circuit and the column selection circuit being respectively located on adjacent sides of the plurality of storage modules; A plurality of global data lines extending along the first direction and a plurality of electrical connection lines extending along a third direction, the plurality of global data lines being electrically connected to the read / write control driving circuit via the plurality of electrical connection lines, and the read / write control driving circuit being configured to drive a plurality of the storage modules corresponding to the global data lines, so that data is written into the storage cells via the global data lines, or data is read out from the storage cells and transmitted to the global data lines; The read / write control driving circuit includes: a plurality of read / write control driving units arranged along the first direction; wherein each of the read / write control driving units is electrically connected to at least two global data lines, and each of the read / write control driving units is electrically connected to at least two of the storage modules via the at least two global data lines.

2. The memory according to claim 1, characterized in that, In the first direction, the plurality of storage modules are sorted in ascending order of natural numbers, and the storage modules in odd positions are defined as first storage modules, and the storage modules in even positions are defined as second storage modules; The global data lines include: a first global data line corresponding to the first storage modules; a second global data line corresponding to the second storage modules; The electrical connection lines include: a first electrical connection line electrically connecting the first global data line and the read / write control driving circuit; a second electrical connection line electrically connecting the second global data line and the read / write control driving circuit.

3. The memory according to claim 2, characterized in that, Each of the first global data lines corresponds to all of the first storage modules; each of the second global data lines corresponds to all of the second storage modules.

4. The memory according to claim 2, characterized in that, The number of the first global data lines and the second global data lines is each a plurality, wherein each of the first global data lines corresponds to a partial number of the first storage modules, and each of the second global data lines corresponds to a partial number of the second storage modules.

5. The memory according to claim 4, characterized in that, Each of the read / write control driving units is electrically connected to at least one of the first global data lines and at least one of the second global data lines.

6. The memory according to claim 4, characterized in that, The global data lines electrically connected to different read / write control driving units are distributed at intervals.

7. The memory according to claim 1, characterized in that, All the global data lines are distributed at the edges of the multiple storage modules.

8. The memory according to claim 1, characterized in that, The multiple storage modules are divided into at least two module regions arranged along the first direction. Each module region includes at least two of the storage modules, and the global data lines of different module regions are independent of each other; The read / write control driving circuit includes: At least two read / write control driving modules arranged along the first direction. Each read / write control driving module is located on one side of the corresponding module region, and the read / write control driving module is electrically connected to the corresponding global data line via the electrical connection line.

9. The memory according to claim 8, characterized in that, The read / write control driving circuit is configured such that when the word line corresponding to the module region is enabled, the read / write control driving module corresponding to the module region drives the storage modules within the module region via the global data line.

10. The memory according to claim 8, characterized in that, The same module region has multiple global data lines, and the multiple global data lines are divided into at least two groups. Each group of global data lines corresponds to at least two adjacent storage modules.

11. The memory according to claim 10, characterized in that, For the same module region, all the global data lines are arranged adjacent to each other, or the global data lines of different groups are arranged at intervals.

12. The memory according to claim 10, characterized in that, For the same module region, the read / write control driving module includes multiple read / write control driving units arranged along the first direction, and each read / write control driving unit is electrically connected to at least one group of the global data lines.

13. The memory according to claim 8, characterized in that, The number of storage modules included in each module region is the same.

14. The memory according to claim 1, characterized in that, The third direction is the same as the second direction.

15. The memory according to claim 1 or 14, characterized in that, The first direction is perpendicular to the second direction.

16. The memory according to claim 1, characterized in that,It further includes: A row decoding circuit for selecting the storage unit electrically connected to the word line through the word line; the row decoding circuit is located on the side of the read / write control driving circuit away from the multiple storage modules.

17. The memory according to claim 1, wherein, Each amplification unit includes a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected to the column selection line to receive a column selection signal. The first terminal is electrically connected to the bit line, and the second terminal is electrically connected to the local data line.

18. The memory according to claim 17, wherein, The memory further includes: a local read / write conversion circuit. The local read / write conversion circuit is electrically connected to the second terminal of the amplification unit through the local data line, and the local read / write conversion circuit is electrically connected to the global data line.

19. The memory according to claim 18, wherein, Each global data line is electrically connected to multiple local read / write conversion circuits.

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