Method of manufacturing a semiconductor element structure with patterns of different heights

Abstract

This disclosure provides a method for fabricating a semiconductor device structure, including forming a target layer on a semiconductor substrate and forming an energy-sensitive layer on the target layer. The method also includes performing a first energy processing process to form a first processing portion in the energy-sensitive layer, and performing a second energy processing process to form a second processing portion in the energy-sensitive layer. The method further includes removing the first processing portion and the second processing portion to form a first opening and a second opening in the energy-sensitive layer, and transferring the first opening and the second opening to the target layer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 17 / 550,321 (i.e., priority date "December 14, 2021"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a method for fabricating a semiconductor device structure. More particularly, it relates to a method for fabricating a semiconductor device structure with patterns of different heights. Background Technology

[0003] Semiconductor components are crucial for many modern applications. With advancements in electronics, semiconductor components are becoming increasingly smaller while simultaneously incorporating more functions and a greater number of integrated circuits. Due to the miniaturization of semiconductor components, various types and sizes of semiconductor components performing different functions are integrated and packaged into a single module. Furthermore, multiple manufacturing processes are employed to integrate various types of semiconductor components together.

[0004] However, the manufacturing and integration of semiconductor devices involves many complex steps and operations. Integration within semiconductor devices is becoming increasingly complex. This increased complexity in the manufacturing and integration of semiconductor devices can introduce defects. Therefore, continuous improvement of semiconductor device manufacturing processes is necessary to address these defects.

[0005] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" reveals the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] In some embodiments of this disclosure, a method for fabricating a semiconductor device structure is provided. The method includes forming a target layer on a semiconductor substrate and forming an energy-sensitive layer on the target layer. The method also includes performing a first energy processing process to form a first processing portion in the energy-sensitive layer, and performing a second energy processing process to form a second processing portion in the energy-sensitive layer. The method further includes removing the first processing portion and the second processing portion to form a first opening and a second opening in the energy-sensitive layer, and transferring the first opening and the second opening to the target layer.

[0007] In one embodiment, the first energy processing process and the second energy processing process are electron beam (e-beam) writing processes. In one embodiment, the fabrication technique for the first processing portion includes applying a first energy to the energy-sensitive layer, and the fabrication technique for the second processing portion includes applying a second energy to the energy-sensitive layer, wherein the first energy is different from the second energy. In one embodiment, the first processing portion and the second processing portion have different heights. In one embodiment, the method further includes removing the energy-sensitive layer after transferring the first opening and the second opening to the target layer. In one embodiment, the energy-sensitive layer includes a crosslinked compound having a crosslinked functional group. In one embodiment, the crosslinked functional group includes a double bond.

[0008] In one embodiment, the first processing portion penetrates the energy-sensitive layer. In one embodiment, a bottom surface of the second processing portion is higher than a bottom surface of the energy-sensitive layer. In one embodiment, the first opening exposes the target layer. In one embodiment, a bottom surface of the second opening is higher than a top surface of the target layer. In one embodiment, the first and second openings are transferred to the target layer by a dry etching process to form a third and a fourth opening. In one embodiment, the third opening exposes the semiconductor substrate. In one embodiment, the bottom surface of the fourth opening is higher than the top surface of the semiconductor substrate.

[0009] In another embodiment of this disclosure, a method for fabricating a semiconductor device is provided. The method includes forming a target layer on a semiconductor substrate and forming an energy-sensitive layer on the target layer. The method also includes performing a first energy processing process to form a plurality of first processing portions in the energy-sensitive layer, and performing a second energy processing process to form a plurality of second processing portions in the energy-sensitive layer. The method further includes removing the first processing portions and the second processing portions to form a plurality of first openings and a plurality of second openings in the energy-sensitive layer, respectively, and transferring the first openings and the second openings to the target layer to form a plurality of third openings and a plurality of fourth openings, respectively. Furthermore, the method includes transferring the third openings and the fourth openings to the semiconductor substrate to form a plurality of fifth openings and a plurality of sixth openings, respectively, and filling the fifth openings and the sixth openings with an isolation structure.

[0010] In one embodiment, the isolation structure has different heights in different cross-sections. In one embodiment, the first energy processing process and the second energy processing process are electron beam writing processes. In one embodiment, the fabrication technique of the first processing portion includes applying a first energy to the energy-sensitive layer, and the fabrication technique of the second processing portion includes applying a second energy to the energy-sensitive layer, wherein the second energy is greater than the first energy. In one embodiment, the first processing portion has a first height, and the second processing portion has a second height, wherein the second height is greater than the first height. In one embodiment, the first processing portion extends along a first direction, and the second processing portion extends along a second direction different from the first direction. In one embodiment, the first processing portions are parallel to each other, and each second processing portion is located between and in direct contact with any two adjacent first processing portions.

[0011] In one embodiment, the method further includes removing the energy-sensitive layer after forming the third and fourth openings in the target layer. In one embodiment, the method further includes removing the target layer after forming the fifth and sixth openings in the semiconductor substrate. In one embodiment, the target layer is removed before forming the isolation structure. In one embodiment, the energy-sensitive layer comprises a crosslinked compound having a crosslinked functional group. In one embodiment, the crosslinked functional group comprises a double bond. In one embodiment, the bottom surface of the first processed portion is higher than the bottom surface of the second processed portion. In one embodiment, the bottom surface of the first opening in the energy-sensitive layer is higher than the bottom surface of the second opening in the energy-sensitive layer. In one embodiment, the bottom surface of the third opening in the target layer is higher than the bottom surface of the fourth opening in the target layer. In one embodiment, the bottom surface of the fifth opening in the semiconductor substrate is higher than the bottom surface of the sixth opening in the semiconductor substrate.

[0012] This disclosure provides embodiments of a method for fabricating a semiconductor device structure. The method includes sequentially forming a target layer and an energy-sensitive layer on a semiconductor substrate, and forming a first processing portion and a second processing portion in the energy-sensitive layer. The method also includes removing the first and second processing portions to form a first opening and a second opening, and transferring the first and second openings to the target layer. In some embodiments, the first and second processing portions have different heights. Therefore, the same pattern transfer process can be used to form openings with different heights (i.e., depths) in the target layer. This reduces the fabrication cost and time of the semiconductor device structure and allows for greater design flexibility.

[0013] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages forming the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0014] This disclosure can be read in conjunction with the following figures and detailed description for better understanding. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of each feature may be arbitrarily enlarged or reduced.

[0015] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device structure, based on some embodiments.

[0016] Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor device structure, based on some embodiments.

[0017] Figure 3 This is a cross-sectional view showing, according to some embodiments, an intermediate stage in the sequential formation of a target layer and an energy-sensitive layer on a semiconductor substrate during the formation of a semiconductor device structure.

[0018] Figure 4 This is a cross-sectional view showing, according to some embodiments, an optional intermediate stage during the formation of a semiconductor device structure, in which a patterned hard mask is formed over the energy-sensitive layer.

[0019] Figure 5 This is a cross-sectional view showing, according to some embodiments, an intermediate stage of a first energy processing process to form a first processing portion in the energy-sensitive layer.

[0020] Figure 6 This is a cross-sectional view showing, according to some embodiments, an optional intermediate stage during the formation of a semiconductor device, in which another patterned hard mask is formed over the energy-sensitive layer.

[0021] Figure 7 This is a cross-sectional view showing, according to some embodiments, an intermediate stage of a second energy processing process to form a second processing portion in the energy-sensitive layer.

[0022] Figure 8This is a cross-sectional view showing, according to some embodiments, an intermediate stage in which the first processing portion and the second processing portion are removed to form a first opening and a second opening.

[0023] Figure 9 This is a cross-sectional view showing, according to some embodiments, an intermediate stage in the transfer of the first opening and the second opening to the target layer.

[0024] Figure 10 This is a top view showing, according to some embodiments, an intermediate stage in which a first processing portion is formed in the energy-sensitive layer (which is located above a target layer and a semiconductor substrate).

[0025] Figure 11 The diagram shows a cross-sectional view of the intermediate stage in which the first processing section is formed in the energy-sensitive layer, wherein Figure 11 It is along Figure 10 It is drawn by the line A-A'.

[0026] Figure 12 This is a top view showing an intermediate stage in which a second processing portion is formed in the energy-sensitive layer, according to some embodiments.

[0027] Figure 13 The diagram shows a cross-sectional view of the intermediate stage in which the second processing section is formed within the energy-sensitive layer, wherein... Figure 13 It is along Figure 12 The line B-B' is drawn.

[0028] Figure 14 A cross-sectional view showing the intermediate stage of removing the first processing portion to form a first opening in the energy-sensitive layer, wherein... Figure 14 It is along Figure 10 It is drawn using the same line A-A'.

[0029] Figure 15 A cross-sectional view showing the intermediate stage of removing the second processing portion to form a second opening in the energy-sensitive layer, wherein... Figure 15 It is along Figure 12 The line B-B' is drawn.

[0030] Figure 16 A cross-sectional view showing the intermediate stage of transferring the first opening into the target layer to form the third opening in the target layer, wherein... Figure 16 It is along Figure 10 It is drawn using the same line A-A'.

[0031] Figure 17 A cross-sectional view showing the intermediate stage of transferring the second opening into the target layer to form the fourth opening in the target layer, wherein... Figure 17 It is along Figure 12 It is drawn using the same line B-B'.

[0032] Figure 18 A cross-sectional view showing the intermediate stage of transferring the third opening into the semiconductor substrate to form the fifth opening in the semiconductor substrate, wherein... Figure 18 It is along Figure 10 It is drawn using the same line A-A'.

[0033] Figure 19 A cross-sectional view showing the intermediate stage of transferring the fourth opening into the semiconductor substrate to form the sixth opening in the semiconductor substrate, wherein... Figure 19 It is along Figure 12 It is drawn using the same line B-B'.

[0034] Figure 20 This is a top view showing, according to some embodiments, the intermediate stage between the fifth and sixth openings filled with an isolation structure.

[0035] Figure 21 The diagram shows a cross-sectional view of the intermediate stage where the isolation structure fills the fifth and sixth openings, wherein... Figure 21 It is along Figure 20 It is drawn by the line A-A'.

[0036] Figure 22 The diagram shows a cross-sectional view of the intermediate stage where the isolation structure fills the fifth and sixth openings, wherein... Figure 22 It is along Figure 20 The line B-B' is drawn.

[0037] The reference numerals in the attached figures are explained as follows:

[0038] 10: Method

[0039] 30: Method

[0040] 100: Semiconductor Component Structure

[0041] 101: Semiconductor substrate

[0042] 103: Target Layer

[0043] 105: Energy-sensitive layer

[0044] 107: Patterned Hard Mask

[0045] 110: Opening

[0046] 111: First Energy Processing Process

[0047] 113: First Processing Section

[0048] 117: Patterned Hard Mask

[0049] 120: Opening

[0050] 121: Second Energy Processing Process

[0051] 123: Second Processing Section

[0052] 130a: Open

[0053] 130b: Open

[0054] 140a: Open

[0055] 140b: Opening

[0056] 200: Semiconductor Component Structure

[0057] 201: Semiconductor substrate

[0058] 203: Target Layer

[0059] 205: Energy-sensitive layer

[0060] 207: First Processing Section

[0061] 209: Second Processing Section

[0062] 210a: Open

[0063] 210b: Open

[0064] 220a: Open

[0065] 220b: Open

[0066] 230a: Open

[0067] 230b: Open

[0068] 235: Isolation Structure

[0069] 235a: First part of the isolation structure

[0070] 235b: Part Two

[0071] A-A': line

[0072] B-B': Line

[0073] H1: Height

[0074] H2: Height

[0075] H3: Height

[0076] H4: Height

[0077] H5: Height

[0078] H6: Height

[0079] H7: Height

[0080] H8: Height

[0081] S11: Steps

[0082] S13: Steps

[0083] S15: Steps

[0084] S17: Steps

[0085] S19: Steps

[0086] S21: Steps

[0087] S31: Steps

[0088] S33: Steps

[0089] S35: Steps

[0090] S37: Steps

[0091] S39: Steps

[0092] S41: Steps

[0093] S43: Steps

[0094] S45: Steps

[0095] X: Direction

[0096] Y: direction Detailed Implementation

[0097] The following discloses various embodiments or examples of different components for implementing the embodiments of this disclosure. Specific examples of elements and their arrangements are described below to simplify the embodiments of this disclosure. These are merely examples and should not be construed as limiting the scope of the embodiments of this disclosure. For example, when the description refers to a first component being formed "on" or "on" a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where other components are formed between them without direct contact. Furthermore, reference numerals and / or designations may be repeated in different embodiments of this disclosure. These repetitions are for simplification and clarity and are not intended to limit the relationship between the different embodiments and / or structures discussed.

[0098] Furthermore, spatial terms used here, such as "below," "below," "lower," "above," "higher," and similar terms, are used to facilitate the description of the relationship between one element or component shown in the diagram and another. These spatial relation terms are used to cover different orientations of the elements in use or operation, beyond the orientation depicted in the diagram. The device may be rotated to different orientations (90 degrees or other orientations), and the spatial relation adjectives used therein can be interpreted in the same way.

[0099] Figure 1 This is a flowchart illustrating a method 10 for fabricating a semiconductor device structure 100 according to some embodiments, and method 10 includes steps S11, S13, S15, S17, S19, and S21. A brief introduction follows. Figure 1 Steps S11 to S21, then combined Figures 3 to 9 Please provide a detailed explanation. For example... Figure 1 As shown, method 10 begins with step S11, forming a target layer on a semiconductor substrate.

[0100] Next, in step S13, an energy-sensitive layer is formed on the target layer. In some embodiments, the energy-sensitive layer includes a crosslinked compound having a crosslinking functional group. In some embodiments, the crosslinking functional group includes a double bond. In step S15, a first energy processing process is performed to form a first processed portion in the energy-sensitive layer, and in step S17, a second energy processing process is performed to form a second processed portion in the energy-sensitive layer.

[0101] In some embodiments, the first energy processing process and the second energy processing process are electron beam (e-beam) writing processes. In some embodiments, the fabrication technique of the first processing portion includes applying a first energy to an energy-sensitive layer, and the fabrication technique of the second processing portion includes applying a second energy to the energy-sensitive layer, wherein the first energy is different from the second energy. In some embodiments, the first processing portion and the second processing portion have different heights due to the different energy levels applied in the first and second energy processing processes.

[0102] Subsequently, in step S19, the first processing portion and the second processing portion are removed to form a first opening and a second opening in the energy-sensitive layer. In step S21, the first opening and the second opening are transferred to the target layer. In some embodiments, the first opening and the second opening are transferred by a dry etching process. In some embodiments, the same pattern transfer process is used to transfer the first opening and the second opening with different heights (i.e., depths) to the target layer.

[0103] Figure 2This is a flowchart illustrating a method 30 for fabricating a semiconductor device structure 200 according to some embodiments, and method 30 includes steps S31, S33, S35, S37, S39, S41, S43, and S45. A brief introduction follows. Figure 2 Steps S31 to S45, then combined Figures 10 to 22 Please provide a detailed explanation. For example... Figure 2 As shown, method 30 begins with step S31, forming a target layer on a semiconductor substrate.

[0104] Next, in step S33, an energy-sensitive layer is formed on the target layer. In some embodiments, the energy-sensitive layer includes a crosslinked compound having a crosslinking functional group. In some embodiments, the crosslinking functional group includes a double bond. In step S35, a first energy processing process is performed to form a plurality of first processed portions in the energy-sensitive layer, and in step S37, a second energy processing process is performed to form a plurality of second processed portions in the energy-sensitive layer.

[0105] In some embodiments, the first energy processing process and the second energy processing process are electron beam writing processes. In some embodiments, the fabrication technique of the first processing portion includes applying a first energy to an energy-sensitive layer, and the fabrication technique of the second processing portion includes applying a second energy to the energy-sensitive layer, wherein the first energy is different from the second energy. In some embodiments, the first processing portion has a first height, the second processing portion has a second height, and the first height and the second height are different due to the different energy levels applied in the first and second energy processing processes.

[0106] Subsequently, in step S39, the first processing portion and the second processing portion are removed to form a plurality of first openings and a plurality of second openings in the energy-sensitive layer. In step S41, the first openings and the second openings are transferred to the target layer to form a plurality of third openings and a plurality of fourth openings. In some embodiments, the first openings and the second openings are transferred by a dry etching process. In some embodiments, the same pattern transfer process is used to transfer the first openings and the second openings with different heights (i.e., depths) to the target layer.

[0107] Next, in step S43, the third and fourth openings are transferred to the semiconductor substrate to form a plurality of fifth and sixth openings. In some embodiments, the third and fourth openings are transferred using a dry etching process. In some embodiments, the third and fourth openings with different heights (i.e., depths) are transferred to the semiconductor substrate using the same pattern transfer process. In step S45, the fifth and sixth openings in the semiconductor substrate are filled with an isolation structure. In some embodiments, the isolation structure has different heights in different cross-sections.

[0108] Figures 3 to 9 This is shown according to some embodiments by means of Figure 1 Method 10 forms a semiconductor device structure 100 ( Figure 9 Cross-sectional views of each stage. For example... Figure 3 As shown, according to some embodiments, a target layer 103 is formed on a semiconductor substrate 101, and an energy-sensitive layer 105 is formed on the target layer 103. The corresponding steps are as follows: Figure 1 Method 10 is shown as steps S11 to S13.

[0109] The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Optionally or additionally, the semiconductor substrate 101 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0110] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator (SIO) substrate, which may include a substrate, a buried oxide layer on the substrate, and a semiconductor layer on the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SIO substrate can be fabricated using separation by implantation oxygen (SIMOX), wafer bonding, and / or another suitable method.

[0111] In some embodiments, the target layer 103 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or another suitable material. However, any suitable material may be used. In some embodiments, the fabrication technique of the target layer 103 may include a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on coating process, or another suitable method.

[0112] Furthermore, in some embodiments, the energy-sensitive layer 105 comprises a crosslinked compound having a crosslinking functional group. In some embodiments, the crosslinking functional group comprises a double bond. In some embodiments, the crosslinked compound has a hydrogen-bonded group, a polymerizable diacetylene group, or a combination thereof. Similar to the method of forming the target layer 103, the fabrication technique of the energy-sensitive layer 105 may include a deposition process, such as a CVD process, a PVD process, an ALD process, a spin-coating process, or another suitable method.

[0113] Next, as Figure 4 As shown, according to some embodiments, a patterned hard mask 107 is formed on the energy-sensitive layer 105. The fabrication technique of the patterned hard mask 107 may include deposition and patterning steps. In some embodiments, the patterned hard mask 107 includes an opening 110 that exposes a portion of the energy-sensitive layer 105, and the patterned hard mask 107 serves as a mask for subsequent energy processing.

[0114] In some embodiments, a patterned hard mask 107 may be optionally formed depending on the energy source of the subsequent energy processing step. For example, if the energy source of the subsequent energy processing step is visible light, ultraviolet (UV), deep ultraviolet (DUV), extreme ultraviolet (EUV), or X-rays, then a patterned hard mask 107 is formed as a mask in the energy processing step. If the energy source of the subsequent energy processing step is an electron beam or an ion beam, the formation of the patterned hard mask 107 may be omitted.

[0115] Furthermore, in some embodiments, the patterned hard mask 107 comprises silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, metal oxide, or another suitable material. In some embodiments, the patterned hard mask 107 is selected to have a lower etch rate than the energy-sensitive layer 105.

[0116] Subsequently, as Figure 5 As shown, according to some embodiments, a first energy processing process 111 is performed to form a first processing portion 113 in the energy-sensitive layer 105. In some embodiments, the portion of the energy-sensitive layer 105 exposed by the opening 110 is converted into the first processing portion 113. The corresponding steps are described in... Figure 1 Step S15 is shown in method 10. As described above, according to some embodiments, the energy source for the first energy processing process 111 includes visible light, UV, DUV, EUV, X-rays, electron beams, ion beams, or another suitable energy source.

[0117] In some embodiments, the energy used in the first energy processing step 111 is selected such that the first processing portion 113 penetrates the energy-sensitive layer 105. In other words, the height of the first processing portion 113 is the same as the height (e.g., height H1) of the energy-sensitive layer 105. However, other energy levels can be used during the first energy processing step 111 such that the resulting bottom surface of the first processing portion 113 is higher than the bottom surface of the energy-sensitive layer 105. After the first processing portion 113 is formed, the patterned hard mask 107 can be removed. For example, the patterned hard mask 107 can be removed by a wet etching process or an ashing process.

[0118] Next, as Figure 6 As shown, according to some embodiments, another patterned hard mask 117 is formed on the energy-sensitive layer 105. Similar to... Figure 4 The patterned hard mask 107 shown, and the fabrication technique of the patterned hard mask 117 may include deposition and patterning steps. In some embodiments, the patterned hard mask 117 includes an opening 120 that exposes a portion of the energy-sensitive layer 105, and the patterned hard mask 117 serves as a mask for subsequent energy processing.

[0119] In some embodiments, a patterned hard mask 117 may be optionally formed depending on the energy source of the subsequent energy processing step. For example, if the energy source of the subsequent energy processing step is visible light, UV, DUV, EUV, or X-rays, a patterned hard mask 117 is formed as a mask in the energy processing step. If the energy source of the subsequent energy processing step is an electron beam or ion beam, the formation of the patterned hard mask 117 may be omitted. Some materials used to form the patterned hard mask 117 are similar to or the same as those used to form the patterned hard mask 107, and their details will not be repeated here. In some embodiments, the patterned hard mask 117 is selected to have a lower etch rate than the energy-sensitive layer 105.

[0120] Subsequently, as Figure 7 As shown, according to some embodiments, a second energy processing process 121 is performed to form a second processing portion 123 in the energy-sensitive layer 105. In some embodiments, the portion of the energy-sensitive layer 105 exposed by the opening 120 is converted into the second processing portion 123. The corresponding steps are described in... Figure 1 Step S17 is shown in method 10. As described above, according to some embodiments, the energy source for the second energy processing 121 includes visible light, UV, DUV, EUV, X-rays, electron beams, ion beams, or another suitable energy source.

[0121] In some embodiments, the energy (i.e., energy level) used in the first energy processing process 111 is greater than the energy (i.e., energy level) used in the second energy processing process 121, such that the height Hl of the first processing section 113 (refer to...) Figure 5 The height H2 of the second processing portion 123 is greater than that of the first processing portion 113. In some embodiments, the bottom surface of the second processing portion 123 is higher than the bottom surface of the energy-sensitive layer 105 (i.e., the top surface of the target layer 103). In some embodiments, the bottom surface of the second processing portion 123 is higher than the bottom surface of the first processing portion 113. After the second processing portion 123 is formed, the patterned hard mask 117 can be removed.

[0122] Then, as Figure 8 As shown, according to some embodiments, the first processing portion 113 and the second processing portion 123 are removed to form openings 130a and 130b in the energy-sensitive layer 105. The corresponding steps are as follows: Figure 1 This is shown as step S19 in method 10. In some embodiments, the bottom surface of opening 130b is higher than the bottom surface of opening 130a. In some embodiments, the first processing portion 113 and the second processing portion 123 are removed by an etching process. The etching process may include a wet etching process, a dry etching process, or a combination thereof.

[0123] Next, as Figure 9As shown, according to some embodiments, openings 130a and 130b in the energy-sensitive layer 105 are transferred to the target layer 103, thereby forming openings 140a and 140b in the target layer 103. The corresponding steps are described in... Figure 1 The method 10 shown is step S21. In some embodiments, openings 130a and 130b are transferred to the target layer 103 by an etching process (such as a dry etching process). In some embodiments, the bottom surface of opening 140b is higher than the bottom surface of opening 140a. After forming openings 140a and 140b, the energy-sensitive layer 105 can be removed to obtain the semiconductor device structure 100.

[0124] Figure 11 , Figures 13 to 19 ,and Figures 21 to 22 This is shown according to some embodiments by means of Figure 2 Method 30 forms semiconductor device structure 200 ( Figures 20 to 22 Cross-sectional views of each stage. For example... Figures 10 to 12 Display respectively Figure 11 and Figure 13 A top view of the structure, and Figure 20 show Figure 21 and Figure 22 A top view of the structure.

[0125] Figure 11 It is along Figure 10 It is drawn by the line A-A'. Figure 13 It is along Figure 12 The line B-B' is drawn. Figure 14 , Figure 16 ,and Figure 18 It is along Figure 10 It is drawn using the same line A-A'. Figure 15 , Figure 17 ,and Figure 19 It is along Figure 12 It is drawn using the same line B-B'. Figure 21 It is along Figure 20 The line A-A' is drawn, and Figure 22 It is along Figure 20 The line B-B' is drawn.

[0126] like Figure 10 and Figure 11 As shown, according to some embodiments, a target layer 203 and an energy-sensitive layer 205 are sequentially formed on a semiconductor substrate 201. The corresponding steps are as follows: Figure 2 The steps S31 to S33 are shown in method 30. Some details of the semiconductor substrate 201 are similar to or the same as those of the semiconductor substrate 101 of the semiconductor element structure 100, and will not be repeated here.

[0127] Furthermore, some materials and processes used to form the target layer 203 and the energy-sensitive layer 205 are similar to or the same as those used to form the target layer 103 and the energy-sensitive layer 105 of the semiconductor device structure 100, and their details will not be repeated here. Refer to [reference needed] for further details. Figure 10 and Figure 11 According to some embodiments, after forming the energy-sensitive layer 205, a first energy processing process is performed to form a plurality of first processing portions 207 in the energy-sensitive layer 205. The corresponding steps are as follows: Figure 2 The method shown in the diagram is step S35.

[0128] In some embodiments, the first processing portions 207 extend along the same direction (e.g., the X direction). In some embodiments, the first processing portions 207 are parallel to each other. In some embodiments, the first processing portions 207 have a height H3, and the bottom surface of the first processing portions 207 is higher than the bottom surface of the energy-sensitive layer 205.

[0129] In some embodiments, a patterned hard mask (not shown) may be optionally formed for use in the first energy processing process, depending on the energy source of the first energy processing process. In some embodiments, the energy source of the first energy processing process includes visible light, UV, DUV, EUV, X-rays, electron beams, ion beams, or another suitable energy source. If a patterned hard mask is used to form the first processing portion 207, the patterned hard mask may be removed after the first processing portion 207 has been formed.

[0130] Next, as Figure 12 and Figure 13 As shown, according to some embodiments, a second energy processing process is performed to form a plurality of second processing portions 209 in the energy-sensitive layer 205. The corresponding steps are as follows: Figure 2 The method shown in the diagram is step S37. Similar to the energy source of the first energy processing process, according to some embodiments, the energy source of the second energy processing process includes visible light, UV, DUV, EUV, X-rays, electron beams, ion beams, or another suitable energy source.

[0131] In some embodiments, the first processing portions 207 are parallel to each other, and each second processing portion 209 is located between and in direct contact with any two adjacent first processing portions 207. Furthermore, in some embodiments, the energy used in the second energy processing step is selected such that each second processing portion 209 penetrates the energy-sensitive layer 205. In other words, the height of the second processing portion 209 is the same as the height of the energy-sensitive layer 205 (e.g., height H4). However, other energy levels may be used during the second energy processing step, such that the resulting bottom surface of the second processing portion 209 is higher than the bottom surface of the energy-sensitive layer 205.

[0132] In some embodiments, the energy used in the second energy processing process is greater than the energy used in the first energy processing process, such that the height H4 of the second processing portion 209 is greater than the height H3 of the first processing portion 207 (refer to...). Figure 11 In some embodiments, the bottom surface of the first processing portion 207 is higher than the bottom surface of the energy-sensitive layer 205 (i.e., the top surface of the target layer 203). In some embodiments, the bottom surface of the first processing portion 207 is higher than the bottom surface of the second processing portion 209. If a patterned hard mask is used to form the second processing portion 209, the patterned hard mask can be removed after the second processing portion 209 is formed.

[0133] Subsequently, as Figure 14 and Figure 15 As shown, according to some embodiments, the first processing portion 207 and the second processing portion 209 are removed to form a plurality of openings 210a and 210b in the energy-sensitive layer 205, respectively. The corresponding steps are described in... Figure 2 This is shown as step S39 in method 30. In some embodiments, the bottom surface of opening 210a is higher than the bottom surface of opening 210b.

[0134] In some embodiments, the height of opening 210a is substantially the same as the height H3 of the first processing portion 207, and the height of opening 210b is substantially the same as the height H4. In some embodiments, the first processing portion 207 and the second processing portion 209 are removed by an etching process. The etching process may include a wet etching process, a dry etching process, or a combination thereof.

[0135] Then, as Figure 16 and Figure 17 As shown, according to some embodiments, the openings 210a and 210b in the energy-sensitive layer 205 are transferred to the target layer 203 to form a plurality of openings 220a and 220b in the target layer 203, respectively. The corresponding steps are described in... Figure 2The method 30 shown is step S41. In some embodiments, the openings 220a and 220b are transferred to the target layer 203 by an etching process (such as a dry etching process).

[0136] In some embodiments, the bottom surface of the opening 220a is higher than the bottom surface of the opening 220b. In some embodiments, the opening 220a has a height H5, the opening 220b has a height H6, and the height H6 is greater than the height H5. After the openings 220a and 220b are formed, the energy-sensitive layer 205 can be removed.

[0137] Next, as Figure 18 and Figure 19 As shown, according to some embodiments, the openings 220a and 220b in the target layer 203 are transferred to the semiconductor substrate 201 to form a plurality of openings 230a and 230b in the semiconductor substrate 201, respectively. The corresponding steps are described in... Figure 2 The method 30 shown is step S43. In some embodiments, the openings 230a and 230b are transferred to the semiconductor substrate 201 by an etching process (such as a dry etching process).

[0138] In some embodiments, the bottom surface of opening 230a is higher than the bottom surface of opening 230b. In some embodiments, opening 230a has a height H7, opening 230b has a height H8, and height H8 is greater than height H7. After forming openings 230a and 230b, target layer 203 can be removed.

[0139] Subsequently, as Figures 20 to 22 As shown, according to some embodiments, the isolation structure 235 is filled into the openings 230a and 230b in the semiconductor substrate 201. The corresponding steps are as follows: Figure 2 The method 30 shown is illustrated as step S45. In some embodiments, the isolation structure 235 has a first portion 235a filled into the opening 230a and a second portion 235b filled into the opening 230b.

[0140] In some embodiments, the isolation structure 235 has different heights (i.e., depths) in different cross-sections. For example, the isolation structure 235 has different heights (i.e., depths) along the top view ( Figure 20 The section taken along line A-A' of the top view has a height H7, and the isolation structure 235 has a height H8 in the section taken along line B-B' of the top view. In some embodiments, the height H8 is greater than the height H7.

[0141] In some embodiments, the isolation structure 235 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant dielectric material, or another suitable material. The fabrication technology of the isolation structure 235 may include a deposition and planarization process. The deposition process may include CVD, PVD, ALD, spin-coating, or another suitable method. The planarization process may include a chemical mechanical planarization (CMP) process.

[0142] In some embodiments, a planarization process is performed until the top surface of the semiconductor substrate 201 is exposed. After forming the isolation structure 235, a semiconductor device structure 200 is obtained. In some embodiments, the isolation structure 235 surrounds a plurality of island-shaped active areas (AA).

[0143] This disclosure provides embodiments of a method for fabricating semiconductor device structures with patterns of different heights. The method includes sequentially forming a target layer (e.g., target layers 103 and 203) and an energy-sensitive layer (e.g., energy-sensitive layers 105 and 205) on a semiconductor substrate (e.g., semiconductor substrates 101 and 201), and forming (a plurality of) first processing portions (e.g., first processing portions 113 and 207) and (a plurality of) second processing portions (e.g., second processing portions 123 and 209) in the energy-sensitive layer. The method also includes removing the first and second processing portions to form (a plurality of) first openings (e.g., openings 130a and 210a) and (a plurality of) second openings (e.g., openings 130b and 210b), and transferring the first and second openings to the target layer, or even to the semiconductor substrate.

[0144] In some embodiments, the first processing portion and the second processing portion have different heights. Therefore, openings with different heights (i.e., depths) can be transferred to the target layer or semiconductor substrate using the same pattern transfer process. As a result, the fabrication cost and time of semiconductor device structures (e.g., semiconductor device structures 100 and 200) can be reduced, and greater design flexibility can be achieved.

[0145] In one embodiment of this disclosure, a method for fabricating a semiconductor device structure is provided. The method includes forming a target layer on a semiconductor substrate and forming an energy-sensitive layer on the target layer. The method also includes performing a first energy processing process to form a first processing portion in the energy-sensitive layer, and performing a second energy processing process to form a second processing portion in the energy-sensitive layer. The method further includes removing the first processing portion and the second processing portion to form a first opening and a second opening in the energy-sensitive layer, and transferring the first opening and the second opening to the target layer.

[0146] In another embodiment of this disclosure, a method for fabricating a semiconductor device structure is provided. The method includes forming a target layer on a semiconductor substrate and forming an energy-sensitive layer on the target layer. The method also includes performing a first energy processing process to form a plurality of first processing portions in the energy-sensitive layer, and performing a second energy processing process to form a plurality of second processing portions in the energy-sensitive layer. The method further includes removing the first processing portions and the second processing portions to form a plurality of first openings and a plurality of second openings in the energy-sensitive layer, respectively, and transferring the first openings and the second openings to the target layer to form a plurality of third openings and a plurality of fourth openings, respectively. Furthermore, the method includes transferring the third openings and the fourth openings to the semiconductor substrate to form a plurality of fifth openings and a plurality of sixth openings, respectively, and filling the fifth openings and the sixth openings with an isolation structure.

[0147] The embodiments disclosed herein have several advantageous features. By forming processed portions of different heights in the energy-sensitive layer, openings of different heights (or depths) can be transferred to the target layer using the same pattern transfer process. As a result, manufacturing costs and time can be reduced, and greater design flexibility can be achieved.

[0148] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0149] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for fabricating a semiconductor device structure, comprising: A target layer is formed on a semiconductor substrate; An energy-sensitive layer is formed on top of the target layer; A first energy processing process is performed to form multiple first processing sections in the energy-sensitive layer; A second energy processing process is performed to form a plurality of second processing portions in the energy-sensitive layer, wherein the first processing portion has a first height and the second processing portion has a second height, wherein the second height is greater than the first height; Remove the first processing portion and the second processing portion to form a plurality of first openings and a plurality of second openings in the energy-sensitive layer, wherein the bottom surface of the first opening in the energy-sensitive layer is higher than the bottom surface of the second opening in the energy-sensitive layer; The first opening and the second opening are transferred to the target layer to form a plurality of third openings and a plurality of fourth openings, respectively, wherein the bottom surface of the third opening in the target layer is higher than the bottom surface of the fourth opening in the target layer; The third opening and the fourth opening are transferred to the semiconductor substrate to form a plurality of fifth openings and a plurality of sixth openings, respectively, wherein the bottom surface of the fifth opening in the semiconductor substrate is higher than the bottom surface of the sixth opening in the semiconductor substrate; and The fifth and sixth openings are filled with an isolation structure. The first energy processing process and the second energy processing process are electron beam writing processes.

2. The method for fabricating a semiconductor element structure as described in claim 1, wherein the isolation structure has different heights in different cross-sections.

3. The method for fabricating a semiconductor device structure as described in claim 1, wherein the fabrication technique of the first processing portion includes applying a first energy to the energy-sensitive layer, and the fabrication technique of the second processing portion includes applying a second energy to the energy-sensitive layer, wherein the second energy is greater than the first energy.

4. The method for fabricating a semiconductor device structure as claimed in claim 1, wherein the first processing portion extends along a first direction, and the second processing portion extends along a second direction different from the first direction.

5. The method for fabricating a semiconductor device structure as claimed in claim 4, wherein the first processing portions are parallel to each other, and wherein each second processing portion is located between and in direct contact with any two adjacent first processing portions.

6. The method for fabricating a semiconductor device structure as described in claim 1, further comprising: After the third and fourth openings are formed in the target layer, the energy-sensitive layer is removed.

7. The method for fabricating a semiconductor device structure as described in claim 6, further comprising: After the fifth and sixth openings are formed in the semiconductor substrate, the target layer is removed.

8. The method for fabricating a semiconductor device structure as claimed in claim 7, wherein the target layer is removed before forming the isolation structure.

9. The method for preparing a semiconductor device structure as described in claim 1, wherein the energy-sensitive layer comprises a cross-linked compound having a cross-linked functional group.

10. The method for preparing a semiconductor device structure as described in claim 9, wherein the crosslinking functional group comprises a double bond.

11. The method for fabricating a semiconductor device structure as claimed in claim 1, wherein the bottom surface of the first processing portion is higher than the bottom surface of the second processing portion.

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