A shield gate semiconductor device structure preparation method and shield gate semiconductor device structure

Abstract

The application provides a shield gate semiconductor device structure preparation method and a shield gate semiconductor device structure. The method comprises the following steps: etching and removing the first oxide layer located in the upper space of the cell area groove and the surface of the semiconductor material layer, and etching and removing part of the semiconductor material layer between the second oxide layer and the groove; etching and removing the gate polysilicon until the remaining gate polysilicon thickness in the source lead-out area groove reaches a preset thickness; and selectively etching and removing the remaining gate polysilicon located in the source lead-out area groove until there is no gate polysilicon residue in the source lead-out area groove, and then removing the photoresist. According to the application, the gate polysilicon in the source lead-out area groove is etched until the gate polysilicon etching is complete, the problem of the gate polysilicon residue on the sidewall of the source lead-out area groove is avoided, the risk of the short circuit between the gate and the source is avoided, and the yield and reliability are improved.

Description

Technical Field

[0001] The embodiments of this application belong to the field of integrated circuit technology, and in particular relate to a method for fabricating a shielded gate semiconductor device structure and the shielded gate semiconductor device structure. Background Technology

[0002] The on-resistance and parasitic capacitance of a power MOSFET are contradictory parameters. To reduce the on-resistance, the silicon wafer area must be increased; however, an increase in silicon wafer area leads to an increase in parasitic capacitance. Therefore, for a given silicon wafer area, only by adopting new process technologies can the parasitic capacitance be reduced. Shielded gate MOSFETs effectively solve the contradiction between on-resistance and parasitic capacitance.

[0003] Aside from the gate structure, the rest is a standard power MOSFET using the Trench process. The gate is divided into upper and lower parts, with the lower part shielded by a special material. The lower part is internally connected to the upper gate, and the shielding layer of the lower gate is connected to the source, thereby reducing the parasitic Miller capacitance of the drain gate and significantly shortening the duration of the Miller plateau during switching, thus reducing switching losses. Simultaneously, this structure alters the shape of the internal electric field, transforming the traditional triangular electric field into a more compressed trapezoidal electric field. This allows for further reduction in the thickness of the epitaxial layer, lowering on-resistance and thermal resistance.

[0004] However, due to the specific characteristics of shielded gate semiconductor devices, the trenches must be etched quite deeply, and the oxide layer at the bottom of the trench is also relatively thick. The higher the device voltage, the deeper the trench and the thicker the oxide layer at the bottom. This results in fewer oxygen atoms reaching the bottom of the trench during the growth of the thermal oxide layer in the deep trench compared to the surface, leading to a thinner oxide layer closer to the bottom. Furthermore, the difference in crystal orientation at the bottom of the trench causes the oxide layer to be even thinner at the corners. This results in a significant difference in the oxide layer thickness between the top of the semiconductor material between the trenches and the corners, causing considerable challenges for product design and subsequent processes.

[0005] To solve the above technical problems, such as Figure 1As shown, the existing technology solves this problem by first thermally oxidizing the first oxide layer at the bottom of the trench and then depositing a second oxide layer. However, when the thickness of the thick oxide layer exceeds the preset thickness, and the second oxide layer accounts for a higher proportion of the total oxide layer thickness, the oxide layer of the source polysilicon lead-out region will also be etched during the etching of the thick oxide layer, and pits will be generated on the trench sidewalls of the source lead-out region. When the gate polysilicon is deposited, the gate polysilicon will enter the pits. Subsequent processes cannot completely remove the gate polysilicon in the pits, and the risk of gate-source short circuit is higher, resulting in uncontrollable yield risk. Summary of the Invention

[0006] In order to partially solve or alleviate the technical problems in the prior art, this application provides a method for fabricating a shielded gate semiconductor device structure and a shielded gate semiconductor device structure.

[0007] One technical solution adopted in this application embodiment to partially solve or alleviate the technical problems of the prior art is: This application embodiment provides a method for fabricating a shielded gate semiconductor device, the method comprising:

[0008] A second oxide layer and a first oxide layer are formed sequentially from the outside to the inside on the inner surfaces of the trench in the cell region and the trench in the source lead-out region, respectively.

[0009] Polycrystalline silicon source is deposited in the spaces formed by the second oxide layer in the cell trench and the source lead-out trench, respectively.

[0010] The source polysilicon on the surface of the semiconductor material layer is etched away, and a portion of the source polysilicon located in the upper space of the trench in the cell region is selectively etched away.

[0011] Etching removes the first and second oxide layers from the surface of the semiconductor material layer, the cell trenches, and the source lead-out trenches;

[0012] Etching removes the semiconductor material layer between trenches, including part of the source polysilicon in the cell trench and the source lead-out trench.

[0013] A third oxide layer is formed on the upper surface of the semiconductor material layer, the exposed surface of the cell trench, the exposed surface of the source lead-out trench, and the exposed surface of the source polysilicon, respectively, and then the third oxide layer is removed.

[0014] A fourth oxide layer is formed on the upper surface of the semiconductor material layer, the exposed surface of the cell trench, the exposed surface of the source lead-out trench, and the exposed surface of the source polysilicon.

[0015] Deposit gate polysilicon in the cell trench and the source lead-out trench;

[0016] The gate polysilicon on the surface of the semiconductor material layer is etched away, and the gate polysilicon in the source lead-out trench is selectively etched away until there is no gate polysilicon residue in the source lead-out trench.

[0017] In a preferred embodiment of this application, the first oxide layer is formed by thermal growth, and the second oxide layer is formed by chemical vapor deposition.

[0018] In a preferred embodiment of this application, the total thickness of the first oxide layer and the second oxide layer is between 1000 Å and 8000 Å, and the ratio of the thickness of the first oxide layer to the thickness of the second oxide layer is between 0.2 and 1.8.

[0019] In a preferred embodiment of this application, the etching rate of the first oxide layer is less than that of the second oxide layer.

[0020] In a preferred embodiment of this application, after etching to remove the first oxide layer and the second oxide layer in the cell trench and the source lead-out trench, the height difference between the top of the remaining source polysilicon in the cell trench and the bottom of the corresponding second oxide layer in the cell trench is between 5000A and 15000A, and the height difference between the top of the remaining source polysilicon in the source lead-out trench and the bottom of the corresponding second oxide layer in the source lead-out trench is between 3000A and 12000A.

[0021] In a preferred embodiment of this application, after etching away the semiconductor material layer between the trenches, and after removing part of the source polysilicon in the cell trench and the source lead-out trench, the height difference between the top of the remaining source polysilicon in the cell trench and the bottom of the top of the second oxide layer is between 500A and 1500A, and the height difference between the top of the remaining source polysilicon in the source lead-out trench and the bottom of the top of the second oxide layer is between 0A and 1000A.

[0022] In a preferred embodiment of this application, the thickness of the semiconductor material layer between the etched trenches is between 3000 Å and 10000 Å.

[0023] In a preferred embodiment of this application, a third oxide layer with a thickness of 200 Å to 1000 Å is grown at a temperature of 950°C to 1100°C, and a fourth oxide layer with a thickness of 200 Å to 1200 Å is grown at a temperature of 950°C to 1100°C.

[0024] Compared with the prior art, the embodiments of this application provide a method for fabricating a shielded gate semiconductor device structure by adding the following steps between the process of depositing source polysilicon and oxidizing gate polysilicon: etching away the surface of the semiconductor material layer, the first oxide layer and the second oxide layer in the cell trench and the source lead-out trench; etching away the semiconductor material layer between the trenches, and a portion of the source polysilicon in the cell trench and the source lead-out trench; and etching away the exposed surface of the cell trench and the source lead-out region on the upper surface of the semiconductor material layer. A third oxide layer is formed on the exposed surface of the trench and the exposed surface of the source polysilicon, respectively, and then the third oxide layer is removed. A fourth oxide layer is formed on the exposed surface of the cell trench, the exposed surface of the source lead-out trench, and the exposed surface of the source polysilicon on the upper surface of the semiconductor material layer. Gate polysilicon is deposited in the cell trench and the source lead-out trench. The gate polysilicon on the surface of the semiconductor material layer is etched away, and the gate polysilicon located in the source lead-out trench is selectively etched away until no gate polysilicon remains in the source lead-out trench. This embodiment of the application avoids the problem of gate polysilicon remaining on the sidewalls of the source lead-out trench by etching away the gate polysilicon until the gate polysilicon in the source lead-out trench is completely etched away, thus avoiding the risk of gate-source short circuit and improving yield and reliability.

[0025] Secondly, embodiments of this application also provide a shielded gate semiconductor device structure, prepared by the above-described fabrication method, the structure comprising:

[0026] The cell trench has a second oxide layer and a first oxide layer disposed sequentially from the outside to the inside on the lower part of the inner surface. A fourth oxide layer is disposed on the upper part of the inner surface. A source polysilicon is disposed in the space enclosed by the second oxide layer. A gate polysilicon is disposed in the space enclosed by the fourth oxide layer. A fourth oxide layer is disposed on the top surface of the source polysilicon. The gate polysilicon covers the top surface of the source polysilicon.

[0027] The source lead-out region trench has a first oxide layer and a second oxide layer on its inner surface, and a source polysilicon is disposed in the space enclosed by the second oxide layer. A fourth oxide layer is disposed on the top surface of the source polysilicon.

[0028] In particular, the top of the second oxide layer in the cell trench and the source lead-out trench is lower than the top of the first oxide layer.

[0029] In a preferred embodiment of this application, the total thickness of the first oxide layer and the second oxide layer is between 1000 Å and 8000 Å.

[0030] In a preferred embodiment of this application, the thickness of the fourth oxide layer is between 200 Å and 1200 Å.

[0031] Compared with the prior art, the shielded gate semiconductor device structure provided in the second aspect has the same beneficial effects as the shielded gate semiconductor device structure fabrication method provided in the first aspect, and will not be repeated here. Attached Figure Description

[0032] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0033] Figure 1 This is a schematic diagram of a shielded gate semiconductor device structure fabricated using existing technology.

[0034] Figure 2 A flowchart illustrating the fabrication method of the shielded gate semiconductor device provided in this application embodiment;

[0035] Figure 3-12 This is a schematic diagram of the structure corresponding to each process step in the embodiments of this application;

[0036] Figure 13 This is a schematic diagram of a device structure including a shielded gate semiconductor device structure according to an embodiment of this application. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0038] like Figure 1 As shown, Figure 1 This refers to the structure of a shielded gate semiconductor device fabricated using existing technology. Figure 1 The specific fabrication steps of the shielded gate semiconductor device structure shown are as follows:

[0039] Step S01: First, multiple cell trenches and source lead-out trenches are formed by photolithography on the epitaxial layer. Then, a second oxide layer and a first oxide layer are formed sequentially from the outside to the inside on the inner surface of the cell trenches and source lead-out trenches.

[0040] Step S02: Deposit source polysilicon in the trenches of the cell region and the trenches of the source lead-out region. Then, etch the source polysilicon on the surface of the semiconductor material layer until there is no source polysilicon residue on the surface of the semiconductor material layer. Perform photolithography etching on the source polysilicon in the cell region to remove the photoresist.

[0041] Step S03: Etch away the first oxide layer and the second oxide layer in the cell trench and the source lead-out trench of the semiconductor material layer.

[0042] Step S04: A third oxide layer is formed on the upper surface of the semiconductor material layer, the exposed surface of the cell trench, the exposed surface of the source lead-out trench, and the exposed surface of the source polysilicon, respectively, and then the third oxide layer is removed.

[0043] Step S05: A fourth oxide layer is formed on the upper surface of the semiconductor material layer, the exposed surface of the cell trench, the exposed surface of the source lead-out trench, and the exposed surface of the source polysilicon, respectively.

[0044] Step S05: Deposit gate polysilicon in the cell trench and the source lead-out trench;

[0045] Step S06: Etch the gate polysilicon on the surface of the semiconductor material layer.

[0046] As can be seen from the above process flow, since the shielded gate semiconductor device contains both cell regions and source lead-out regions, when the total thickness of the first oxide layer and the second oxide layer exceeds 1000 Å, and the second oxide layer accounts for a higher proportion of the total thickness, the etching rate of the second oxide layer is faster. When etching the first oxide layer and the second oxide layer, the first oxide layer and the second oxide layer of the source lead-out region will also be etched together. Therefore, pits 21 will be generated on the trench sidewalls of the source lead-out region. When the gate polysilicon is deposited, it will be deposited into the pits 21. Subsequent processes cannot completely remove the gate polysilicon in the pits 21, so the risk of gate and source short circuit is higher. This leads to uncontrollable yield risk and unavoidable reliability risk of the shielded gate semiconductor device.

[0047] like Figure 2 As shown, Figure 2 A method for fabricating a shielded gate semiconductor device structure provided in this application includes:

[0048] Step S21: A second oxide layer and a first oxide layer are formed sequentially from the outside to the inside on the inner surfaces of the cell trench and the source lead-out trench, respectively.

[0049] Step S22: Deposit source polycrystalline silicon in the spaces formed by the second oxide layer surrounding the trenches in the cell region and the trenches in the source lead-out region, respectively;

[0050] Step S23: Etch away the source polysilicon on the surface of the semiconductor material layer and selectively etch away a portion of the source polysilicon located in the upper space of the trench in the cell region.

[0051] Step S24: Etch away the first oxide layer and the second oxide layer in the cell trench and the source lead-out trench of the semiconductor material layer.

[0052] Step S25: Etch away the semiconductor material layer between the trenches, and part of the source polysilicon in the cell trench and the source lead-out trench.

[0053] Step S26: A third oxide layer is formed on the upper surface of the semiconductor material layer, the exposed surface of the cell trench, the exposed surface of the source lead-out trench, and the exposed surface of the source polysilicon, respectively, and then the third oxide layer is removed.

[0054] Step S27: A fourth oxide layer is formed on the upper surface of the semiconductor material layer, the exposed surface of the cell trench, the exposed surface of the source lead-out trench, and the exposed surface of the source polysilicon, respectively.

[0055] Step S28: Deposit gate polysilicon in the cell trench and the source lead-out trench;

[0056] Step S29: Etch away the gate polysilicon on the surface of the semiconductor material layer, and selectively etch away the gate polysilicon in the source lead-out trench until there is no gate polysilicon residue in the source lead-out trench.

[0057] refer to Figure 2 and Figure 3 The processes for forming cell trenches 32 and source lead-out trenches 31 on the semiconductor material layer 33 are well-known to those skilled in the art and will not be described in detail here. The semiconductor material layer can be a substrate 33 or an epitaxial layer 33. After forming cell trenches 32 and source lead-out trenches 31 directly on the semiconductor material layer 33 by photolithography etching, a first oxide layer 35 is first formed on the inner surface of the cell trenches 32 and source lead-out trenches 31 by thermal growth process. Then, a second oxide layer 34 is formed on the outer surface of the first oxide layer 35 by chemical vapor deposition process. The first oxide layer 35 and the second oxide layer 34 are referred to as thick oxide layers, and the total thickness of the first oxide layer 35 and the second oxide layer 34 is between 1000 Å and 8000 Å. The ratio of the thickness of the first oxide layer 35 to the thickness of the second oxide layer 34 is between 0.2 and 1.8. Generally, the number of cell trenches 32 is greater than the number of source lead-out trenches 31.

[0058] refer to Figure 2 , Figure 4 and Figure 5In the cell trench 32 and the source lead-out trench 31, the space formed by the second oxide layer 34 is respectively deposited with source polysilicon 41. Then the source polysilicon 41 is etched back until the top of the source polysilicon 41 is not higher than the top of the trench. That is, the source polysilicon 41 on the surface of the semiconductor material layer 33 is etched back so that there is no source polysilicon 41 on the surface of the semiconductor material layer 33.

[0059] refer to Figure 2 and Figure 6 As shown, photoresist 61 is applied to the source lead-out region to perform photolithography on the source polysilicon 41 in the upper space of the cell trench 32, leaving a portion of the source polysilicon 41 in the cell trench 32, and then the photoresist 61 is removed.

[0060] refer to Figure 2 and Figure 7 The first oxide layer 35 and the second oxide layer 34 located in the upper space of the cell trench 32 and the source lead-out region 31 and on the surface of the semiconductor material layer 33 are etched away. Since the etching rate of the first oxide layer 35 is less than that of the second oxide layer 34, after etching, the top of the first oxide layer is higher than the top of the second oxide layer 34. After etching away the first oxide layer 35 and the second oxide layer 34 located in the cell trench 32, the height difference between the top of the remaining source polysilicon 41 in the cell trench 32 and the bottom of the corresponding top of the second oxide layer 34 in the cell trench 32 is between 5000A and 15000A. The height difference between the top of the remaining source polysilicon 41 in the source lead-out region trench 31 and the bottom of the corresponding top of the second oxide layer 34 in the source lead-out region trench 31 is between 3000A and 12000A.

[0061] refer to Figure 1 and Figure 8 As shown, the semiconductor material layer 33 between the trenches is etched away. Part of the source polysilicon in the cell trench 32 and the source lead-out trench 31 is removed. The height difference from the top of the source polysilicon 41 to the top and bottom of the second oxide layer 34 in the cell trench 32 is between 500A and 1500A. The height difference from the top of the source polysilicon to the top and bottom of the second oxide layer in the source lead-out trench is between 0A and 1000A. The etch-back thickness of the semiconductor layer 33 between the trenches is between 3000A and 10000A. The specific etch-back thickness of the semiconductor layer 33 between the trenches depends on the height difference from the bottom of the second oxide layer 34 to the semiconductor layer 33 between the trenches in the source lead-out trench 32.

[0062] refer to Figure 2 and Figure 9 As shown, in Figure 8Based on the above, a third oxide layer (not shown) is formed on the surface of the semiconductor material layer 33, the exposed surface of the cell trench 32, the exposed surface of the source lead-out trench 31, and the exposed surface of the source polysilicon 41. The third oxide layer (not shown) is then removed. The third oxide layer (not shown) can process the morphology of the surface it contacts and improve the purity of the surface it contacts. The thickness of the third oxide layer is 200 Å to 1000 Å, and the process temperature is between 950℃ and 1100℃.

[0063] After removing the third oxide layer (not shown), a fourth oxide layer 91 is re-formed at the location of the third oxide layer (not shown), namely: on the surface of the semiconductor material layer 33, the inner surface of the cell trench 32, the inner surface of the source lead-out trench 31, and the top of the source polysilicon 41. The thickness of the fourth oxide layer 91 is 200 Å to 1200 Å, and the process temperature is between 950°C and 1100°C.

[0064] refer to Figure 2 and Figure 10 As shown, gate polysilicon 10 is deposited in the upper space of the cell trench 32. The process of depositing polysilicon 10 is a well-known technology in the art and will not be described in detail here.

[0065] refer to Figure 2 and Figure 11 As shown, the gate polysilicon 10 is etched back until there is no gate polysilicon 10 residue on the surface of the semiconductor material layer 33, and the thickness of the remaining gate polysilicon 93 in the source lead-out trench 31 is between 0A and 5000A.

[0066] refer to Figure 2 and Figure 12 ,exist Figure 11 Based on the photoresist 12, photolithography is performed on the remaining gate polysilicon 93 in the upper space of the source lead-out trench 31 until the remaining gate polysilicon 93 in the source lead-out trench 31 is completely etched. Then the photoresist 12 is removed. At this time, there is no remaining gate polysilicon 93 in the source lead-out trench 31. In this embodiment of the application, by etching away the gate polysilicon until the gate polysilicon in the source lead-out trench is completely etched, the problem of gate polysilicon remaining on the sidewall of the source lead-out trench can be avoided, the risk of gate-source short circuit can be avoided, and the yield and reliability can be improved.

[0067] The shielded gate semiconductor device structure prepared by the above process steps in the embodiments of this application is as follows: Figure 12 As shown, the shielded gate semiconductor device structure includes:

[0068] The cell trench 32 and the inner surface of the lower part of the cell trench 31 are provided with a second oxide layer 34 and a first oxide layer 35 from the outside to the inside. The inner surface of the upper part of the cell trench 31 is provided with a fourth oxide layer 91. The source polysilicon 41 is provided in the space enclosed by the second oxide layer 34. The gate polysilicon 10 is provided in the space enclosed by the fourth oxide layer 91. The top surface of the source polysilicon 41 is provided with a fourth oxide layer 41. The gate polysilicon 10 covers the top surface of the source polysilicon 41.

[0069] The source lead-out region trench 31 has a first oxide layer 35 and a second oxide layer 34 disposed on its inner surface, and a source polysilicon 41 disposed in the space enclosed by the second oxide layer 34. A fourth oxide layer 91 is disposed on the top surface of the source polysilicon 41.

[0070] In the cell region trench 32 and the source lead-out region trench 31, the top of the second oxide layer 34 is lower than the top of the first oxide layer 35. The total thickness of the first oxide layer 35 and the second oxide layer 34 is between 1000 Å and 8000 Å, and the thickness of the fourth oxide layer 91 is between 200 Å and 1200 Å.

[0071] Subsequently, an oxide layer 16 is formed on the entire surface of the semiconductor material layer 33. Ion implantation is performed sequentially to form a well 13. Photolithography is used to form an implantation region 14 in the well 13. Dielectric layers 15 and 20 are deposited. Contact holes 17 and 18 are formed by photolithography and etching. Ions are implanted into the contact holes 17 and 18 and activated. Subsequently, multilayer metals are deposited in the contact holes 17 and 18 to form lead electrodes, and finally a semiconductor device structure with a shielded gate is formed.

[0072] This application provides a shielded gate semiconductor device structure to avoid the problem of polysilicon residue on the sidewall of the source lead-out trench, thereby avoiding the risk of gate-source short circuit and improving yield and reliability.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a shielded gate semiconductor device, characterized in that, The method includes: A second oxide layer and a first oxide layer are formed sequentially from the outside to the inside on the inner surfaces of the trench in the cell region and the trench in the source lead-out region, respectively. Polycrystalline silicon source is deposited in the spaces formed by the second oxide layer in the cell trench and the source lead-out trench, respectively. The source polysilicon on the surface of the semiconductor material layer is etched away, and a portion of the source polysilicon located in the upper space of the trench in the cell region is selectively etched away. Etching removes the first and second oxide layers from the surface of the semiconductor material layer, the cell trenches, and the source lead-out trenches; Etching removes the semiconductor material layer between trenches, including part of the source polysilicon in the cell trench and the source lead-out trench. A third oxide layer is formed on the upper surface of the semiconductor material layer, the exposed surface of the cell trench, the exposed surface of the source lead-out trench, and the exposed surface of the source polysilicon, respectively, and then the third oxide layer is removed. A fourth oxide layer is formed on the upper surface of the semiconductor material layer, the exposed surface of the cell trench, the exposed surface of the source lead-out trench, and the exposed surface of the source polysilicon. Deposit gate polysilicon in the cell trench and the source lead-out trench; The gate polysilicon on the surface of the semiconductor material layer is etched away, and the gate polysilicon in the source lead-out trench is selectively etched away until there is no gate polysilicon residue in the source lead-out trench.

2. The method for fabricating a shielded gate semiconductor device as described in claim 1, characterized in that, The first oxide layer is formed by thermal growth, and the second oxide layer is formed by chemical vapor deposition.

3. The method for fabricating a shielded gate semiconductor device as described in claim 1, characterized in that, The total thickness of the first oxide layer and the second oxide layer is between 1000 Å and 8000 Å, and the ratio of the thickness of the first oxide layer to the thickness of the second oxide layer is between 0.2 and 1.

8.

4. A method for fabricating a shielded gate semiconductor device as described in any one of claims 1 to 3, characterized in that, The etching rate of the first oxide layer is less than that of the second oxide layer.

5. The method for fabricating a shielded gate semiconductor device as described in claim 1, characterized in that, After the etching removes the first and second oxide layers from the surface of the semiconductor material layer, the cell trench, and the source lead-out trench, the height difference between the top of the remaining source polysilicon in the cell trench and the bottom of the corresponding second oxide layer in the cell trench is between 5000A and 15000A, and the height difference between the top of the remaining source polysilicon in the source lead-out trench and the bottom of the corresponding second oxide layer in the source lead-out trench is between 3000A and 12000A.

6. The method for fabricating a shielded gate semiconductor device as described in claim 1, characterized in that, After the etching removes the semiconductor material layer between the trenches, and after part of the source polysilicon in the cell trench and the source lead-out trench, the height difference between the top of the remaining source polysilicon in the cell trench and the bottom of the top of the second oxide layer is between 500A and 1500A, and the height difference between the top of the remaining source polysilicon in the source lead-out trench and the bottom of the top of the second oxide layer is between 0A and 1000A.

7. The method for fabricating a shielded gate semiconductor device as described in claim 1, characterized in that, The thickness of the semiconductor material layer between the etched trenches is between 3000 Å and 10000 Å.

8. A method for fabricating a shielded gate semiconductor device according to any one of claims 1, 5-7, characterized in that, A third oxide layer with a thickness of 200 Å to 1000 Å is grown at a temperature of 950℃ to 1100℃, and a fourth oxide layer with a thickness of 200 Å to 1200 Å is grown at a temperature of 950℃ to 1100℃.

9. A shielded gate semiconductor device structure, characterized in that, The structure is prepared by the preparation method according to claims 1 to 8, and includes: The cell trench has a second oxide layer and a first oxide layer disposed sequentially from the outside to the inside on the lower part of the inner surface. A fourth oxide layer is disposed on the upper part of the inner surface. A source polysilicon is disposed in the space enclosed by the second oxide layer. A gate polysilicon is disposed in the space enclosed by the fourth oxide layer. A fourth oxide layer is disposed on the top surface of the source polysilicon. The gate polysilicon covers the top surface of the source polysilicon. The source lead-out region trench has a first oxide layer and a second oxide layer on its inner surface, and a source polysilicon is disposed in the space enclosed by the second oxide layer. A fourth oxide layer is disposed on the top surface of the source polysilicon. In particular, the top of the second oxide layer in the cell trench and the source lead-out trench is lower than the top of the first oxide layer.

10. The shielded gate semiconductor device structure as described in claim 9, characterized in that, The total thickness of the first oxide layer and the second oxide layer is between 1000 Å and 8000 Å.

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