An epitaxial structure of a semiconductor device and a method for manufacturing the same, and a semiconductor device

Abstract

Embodiments of the present application disclose an epitaxial structure of a semiconductor device, a preparation method of the epitaxial structure and the semiconductor device. The epitaxial structure comprises a substrate and a multilayer epitaxial layer on one side of the substrate. The multilayer epitaxial layer comprises a cap layer away from the substrate. The thickness D of the cap layer is positively correlated with the diameter d of the substrate. The epitaxial structure provided by the embodiments of the present application can adapt to the stress suffered when growing on substrates of different sizes by setting the cap layer and adjusting the thickness of the cap layer according to the size of the substrate, thereby improving the consistency and stability of the performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics technology, and in particular to an epitaxial structure of a semiconductor device and its fabrication method, and a semiconductor device. Background Technology

[0002] Group III nitride materials possess unique advantages in realizing optoelectronic devices and high electron mobility transistors, and their research has undergone a long development process. Due to the lattice mismatch between GaN and AlGaN, the AlGaN barrier layer exhibits significant tensile stress, and AlGaN is a strong piezoelectric material, resulting in a strong piezoelectric polarization field within the AlGaN barrier layer. Under the influence of this piezoelectric polarization field, a high carrier density can be achieved at the AlGaN / GaN heterojunction interface without any doping, which is one of the key advantages of GaNHEMT devices compared to devices made of other materials. In fact, AlGaN / GaNHEMTs have broad application prospects in communications, radar, sensing, and automation.

[0003] However, piezoelectric properties can also function in the opposite way: under the influence of an electric field, mechanical stress is generated within the piezoelectric material. Depending on the direction of the electric field, the mechanical stress within the piezoelectric material can be tensile or compressive stress; this phenomenon is called the inverse piezoelectric polarization effect. Under the influence of an electric field, the tensile stress generated by the inverse piezoelectric polarization effect is superimposed on the stress caused by the original lattice mismatch, leading to an increase in the elastic energy density of the AlGaN barrier layer. When the total elastic energy density in the barrier layer exceeds the material's tolerance limit, lattice fracture occurs to release the stress, thereby affecting the reliability of the device. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide an epitaxial structure of a semiconductor device and a method for fabricating the same, and a semiconductor device thereof. By setting a cap layer and reasonably setting the thickness of the cap layer according to the size of the substrate, the epitaxial structure can adapt to the stress caused by warping when growing on substrates of different sizes, thereby improving the consistency and stability of the semiconductor device performance.

[0005] In a first aspect, embodiments of the present invention provide an epitaxial structure for a semiconductor device, including a substrate and a multilayer epitaxial layer located on one side of the substrate.

[0006] The multilayer epitaxial layer includes a cap layer on the side away from the substrate, wherein the thickness D of the cap layer is positively correlated with the diameter d of the substrate.

[0007] Optionally, the thickness D of the cap layer is positively correlated with the degree of warpage of the substrate.

[0008] Optionally, the cap layer includes a GaN layer;

[0009] The thickness D of the cap layer and the diameter d of the substrate satisfy d / 5 < D < 2d, where the unit of D is nm and the unit of d is inch.

[0010] Optionally, the cap layer includes an AlGaN layer;

[0011] The thickness D of the cap layer and the diameter d of the substrate satisfy d / 4 < D < 2.5d, where the unit of D is nm and the unit of d is inch.

[0012] Optionally, the cap layer includes an AlGaN layer, and the atomic ratio of Al component in the AlGaN layer is A%;

[0013] The thickness D of the cap layer and the atomic ratio A% of Al component in the AlGaN layer satisfy (A / 20 + 0.5) < D < (A + 5), where the unit of D is nm.

[0014] Optionally, the cap layer includes an AlGaN layer, and the atomic ratio of Al component in the AlGaN layer is A%;

[0015] The thickness D of the cap layer, the diameter d of the substrate and the atomic ratio A% of Al component in the AlGaN layer satisfy d / 4 < D < 2.5d, (A / 20 + 0.5) < D < (A + 5), where the unit of D is nm and the unit of d is inch.

[0016] Optionally, if the size of the substrate is greater than or equal to the size threshold, the growth rate of the thickness of the cap layer decreases as the size of the substrate increases.

[0017] Optionally, the multi-layer epitaxial layer further includes an intermediate epitaxial layer located between the cap layer and the substrate;

[0018] The intermediate epitaxial layer includes a nucleation layer, a buffer layer, a channel layer and a barrier layer which are stacked.

[0019] In a second aspect, an embodiment of the present invention provides a semiconductor device, including the epitaxial structure according to any one of the first aspect.

[0020] In a third aspect, a method for preparing an epitaxial structure of a semiconductor device provided by an embodiment of the present invention is used to prepare the epitaxial structure according to any one of the first aspect; including:

[0021] Providing a substrate;

[0022] Preparing a multi-layer epitaxial layer on one side of the substrate, and the multi-layer epitaxial layer includes a cap layer on the side far from the substrate, where the thickness D of the cap layer is positively correlated with the diameter d of the substrate.

[0023] Optionally, a multilayer epitaxial layer is formed on one side of the substrate, including:

[0024] An intermediate epitaxial layer is prepared on one side of the substrate;

[0025] A cap layer is prepared on the side of the intermediate epitaxial layer away from the substrate;

[0026] The process of fabricating a cap layer on the side of the intermediate epitaxial layer away from the substrate includes:

[0027] A cap layer is grown on the side of the intermediate epitaxial layer away from the substrate by continuously introducing growth gas; or, a cap layer is grown on the side of the intermediate epitaxial layer away from the substrate by pulsed introduction of growth gas.

[0028] The epitaxial structure of the semiconductor device provided in this embodiment of the invention includes a substrate and multiple epitaxial layers located on one side of the substrate. The multiple epitaxial layers include a cap layer on the side away from the substrate, and the thickness D of the cap layer is positively correlated with the diameter d of the substrate. By setting the cap layer and reasonably setting its thickness based on the substrate size, the epitaxial structure provided in this embodiment of the invention can compensate for the different stresses caused by different warpages during epitaxial layer growth on substrates of different sizes. This improves the consistency of semiconductor device performance on substrates of different sizes and enhances the reliability of the semiconductor device. Attached Figure Description

[0029] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0030] Figure 1 This is a schematic diagram of the epitaxial structure of a semiconductor device provided in an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of the epitaxial structure of a semiconductor device in the prior art;

[0032] Figure 3 This is a schematic diagram of the epitaxial structure of another semiconductor device in the prior art;

[0033] Figure 4 This is a schematic diagram of the epitaxial structure of another semiconductor device provided in an embodiment of the present invention;

[0034] Figure 5 This is a schematic diagram of the epitaxial structure of another semiconductor device provided in an embodiment of the present invention;

[0035] Figure 6 This is a schematic diagram of the epitaxial structure of another semiconductor device provided in an embodiment of the present invention;

[0036] Figure 7 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0037] Figure 8 This is a schematic flowchart illustrating a method for fabricating an epitaxial structure of a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be fully described below with reference to the accompanying drawings in the embodiments of this invention, through specific implementation methods. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort fall within the protection scope of this invention.

[0039] Figure 1 This is a schematic diagram of the epitaxial structure of a semiconductor device provided in an embodiment of the present invention, as shown below. Figure 1 As shown, an embodiment of the present invention provides an epitaxial structure for a semiconductor device. The epitaxial structure 10 includes a substrate 100 and a multilayer epitaxial layer 200 located on one side of the substrate 100. The multilayer epitaxial layer 200 includes a cap layer 210 on the side away from the substrate 100, wherein the thickness D of the cap layer 210 is positively correlated with the diameter d of the substrate 100.

[0040] The main growth methods for the epitaxial structure 10 of semiconductor devices include metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), and liquid phase epitaxy (LPE). Most of these methods require heating the substrate 100 to a certain temperature before epitaxial growth of the semiconductor material, followed by cooling and removal after the growth process is complete. The substrate 100 is typically made of one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon, or any other material capable of growing group III nitrides. New crystals are grown on the substrate 100 to form multiple epitaxial layers 200, typically made of AlN and GaN. Multiple epitaxial layers 200 are formed on the substrate 100, and the material of the epitaxial layers 200 is generally a group III-V compound.

[0041] The multilayer epitaxial layer 200 includes a cap layer 210 on the side away from the substrate 100. The cap layer 210 can serve as a passivation layer, improving current collapse. Specifically, the cap layer 210 can be made of GaN, AlGaN, InGaN, AlInGaN, etc., with GaN or AlGaN being preferred.

[0042] Specifically, because substrates of different sizes exhibit varying warpage after epitaxial growth, the stress on the epitaxial layer also differs. Larger substrates tend to have greater warpage, resulting in higher stress on the epitaxial layer, which is further amplified by reverse piezoelectric polarization under an electric field. This leads to a problem: for the same epitaxial growth, different substrate sizes result in varying stresses on the epitaxial layer, ultimately causing significant differences in the reliability and consistency of devices fabricated from substrates of different sizes, thus affecting yield. In this embodiment of the invention, the thickness D of the cap layer 210 and the diameter d of the substrate 100 are positively correlated; that is, as the size d of the substrate 100 increases, the thickness D of the cap layer 210 also increases. This embodiment of the invention does not impose specific numerical limits on the increase in the size d of the substrate 100 and the thickness D of the cap layer 210; the size d of the substrate 100 and the thickness D of the cap layer 210 satisfy a linear inequality. The thickness of the cap layer 210 is reasonably set based on the size d of the substrate 100. The thickness of the cap layer 210 compensates for the stress introduced by substrates 100 of different sizes during the production of the epitaxial layer 200, so that the stress on the epitaxial layer 200 grown on substrates 100 of different sizes can be comparable, thereby improving the consistency of semiconductor device performance.

[0043] The degree of warpage can be characterized by the surface curvature of the substrate when warpage occurs. When the degree of warpage is large, the height difference between the substrate edge and the center is greater, and the substrate deformation is more severe. The inventors discovered that the different stresses introduced during epitaxial growth of different substrate sizes can be expressed as the degree of substrate warpage. Therefore, the thickness of the cap layer 210 is positively correlated with the degree of warpage of the substrate 100, that is, the greater the degree of warpage of the substrate 100, the thicker the cap layer 210 should be; conversely, the smaller the degree of warpage of the substrate 100, the thinner the cap layer 210 should be.

[0044] Furthermore, the thickness D of the cap layer 210 can satisfy 1nm ≤ D ≤ 20nm. For example, the thickness of the cap layer 210 can be 1nm, 20nm, or any value between 1nm and 20nm, such as 2nm, 5nm, 8nm, 10nm, and 16nm. This embodiment of the invention does not limit the specific thickness of the cap layer 210. Within the thickness range of the cap layer 210 and based on the size of the substrate 100, the thickness of the cap layer 210 is controlled. The thickness of the cap layer 210 compensates for the stress introduced by substrates 100 of different sizes during the production of the epitaxial layer 200, ensuring that the stress experienced by the epitaxial layer 200 grown on substrates 100 of different sizes is comparable, thus improving the consistency of semiconductor device performance. Simultaneously, it ensures that the fabrication process of the cap layer 210 is simple, without increasing the fabrication difficulty due to excessively high or low thicknesses. Furthermore, by setting the cap layer 210, the surface states can be reduced, the surface leakage current of subsequent semiconductor devices can be reduced, and current collapse can be suppressed, thereby improving device performance and reliability.

[0045] In summary, the epitaxial structure provided by the embodiments of the present invention, by setting a cap layer and setting the thickness of the cap layer according to the warpage of the substrate, or by using different cap layer thicknesses, can be used to compensate for the stress introduced by substrates of different sizes during the growth of epitaxial layers, so that the stress on the epitaxial layers grown on substrates of different sizes can be comparable, thereby improving the consistency of the performance of semiconductor devices made on substrates of different sizes and improving the reliability of semiconductor devices.

[0046] Figure 2 This is a schematic diagram of the epitaxial structure of a semiconductor device in the prior art. Figure 3 This is a schematic diagram of the epitaxial structure of another semiconductor device in the prior art, combined with... Figure 2 and Figure 3 As shown, the epitaxial structure 01 in the prior art includes a substrate 010 and a multilayer epitaxial layer 020 located on one side of the substrate 010. During actual growth, the substrate 010 and the epitaxial layer 020 will experience different warpages, such as... Figure 2 As shown, some processes can cause the epitaxial structure 01 of a semiconductor device to deform towards the epitaxial layer 020. For example... Figure 3 As shown, some processes can cause the epitaxial structure 01 of a semiconductor device to deform towards the substrate 010. Regardless of whether the epitaxial structure of the semiconductor device deforms towards the epitaxial layer 020 or towards the substrate 010, poor deformation uniformity leads to unreliability and instability of the semiconductor device.

[0047] The present invention provides an epitaxial structure for a semiconductor device that can solve the above-mentioned problems. Figure 4 This is a schematic diagram of the epitaxial structure of another semiconductor device provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of the epitaxial structure of another semiconductor device provided in an embodiment of the present invention. (Combined with...) Figure 4 and Figure 5 As shown, the epitaxial layer 200 consists of a middle multilayer epitaxial layer 220 and a cap layer 210 on the side away from the substrate 100; the lattice constant of the surface layer of the middle multilayer epitaxial layer 220 is greater than the lattice constant of the cap layer 210; or, the lattice constant of the middle multilayer epitaxial layer 220 is less than the lattice constant of the cap layer 210.

[0048] Since the thickness of the cap layer 210 is positively correlated with the degree of warpage of the substrate 100, the warpage can be finely adjusted by the difference in lattice constant between the material of the cap layer 210 and the surface layer of the multilayer epitaxial layer 220, thereby improving the consistency of epitaxial warpage between different substrates 100 and thus improving the consistency of stress on the barrier layer.

[0049] Specifically, the middle multi-layer epitaxial layer 220 is bonded to the substrate 100, and a tensile stress towards the multi-layer epitaxial layer 220 is generated between the multi-layer epitaxial layer 220 and the substrate 100, resulting in a warping phenomenon as shown in Figure 2 . Due to the different sizes of the substrate, the consistency of this warping will deteriorate. To alleviate this phenomenon, a material with a lattice constant smaller than that of the surface layer of the multi-layer epitaxial layer 220 can be selected as the cap layer 210. At this time, a certain tensile stress towards the middle multi-layer epitaxial layer 220 is also generated between the middle multi-layer epitaxial layer 220 and the cap layer 210, which can alleviate the tensile stress generated between the middle multi-layer epitaxial layer 220 and the substrate 100 and weaken the warping trend of the epitaxial structure 10 of the semiconductor device.

[0050] Alternatively, a tensile stress towards the substrate 100 is generated between the multi-layer epitaxial layer 220 and the substrate 100, resulting in a warping phenomenon as shown in Figure 3 . Due to the different sizes of the substrate 100, the consistency of this warping will also deteriorate. To alleviate this phenomenon, a material with a lattice constant larger than that of the surface layer of the multi-layer epitaxial layer 220 can be selected as the cap layer 210. At this time, a certain tensile stress towards the cap layer 210 is also generated between the middle multi-layer epitaxial layer 220 and the cap layer 210, which can alleviate the tensile stress generated between the middle multi-layer epitaxial layer 220 and the substrate 100 and weaken the warping trend of the epitaxial structure 10 of the semiconductor device.

[0051] In summary, by reasonably setting the thickness of the cap layer and the lattice constant of the cap layer, it is ensured that different stresses caused by different-sized substrates and different warping due to the mismatch between the lattice constants of the substrate and the epitaxial layer can be compensated, thereby improving the consistency of the performance of semiconductor devices made on different-sized substrates and enhancing the reliability of semiconductor devices.

[0052] Continuing to refer to Figure 1 shown, the cap layer 210 may include a GaN layer;

[0053] The thickness D of the cap layer 210 and the diameter d of the substrate 100 satisfy a binary linear inequality relationship, preferably d / 5 < D < 2d, where the unit of D is nm and the unit of d is inch.

[0054] Among them, when growing the epitaxial layer 200 on substrates 100 of different sizes, the epitaxial structure 10 will warp. Therefore, the warping trend of the epitaxial structure 10 can be alleviated by setting the corresponding relationship between the thickness of the cap layer 210 and the size of the substrate 100.

[0055] Specifically, the diameter d of the substrate 100 can be a positive integer. For example, it can be 2 feet, 3 feet, 4 feet, 6 feet, 8 feet, etc. The embodiments of the present invention do not limit the specific size of the substrate. Among them, the material of the cap layer 210 can be a GaN layer. The thickness D of the cap layer 210 and the diameter d of the substrate 100 satisfy d / 5 < D < 2d, where the unit of D is nm and the unit of d is inches. Exemplarily, the thickness D of the cap layer 210 can be any value greater than d / 5 and less than 2d. For example, it can be d3 / 5, 1d, or 1.5d, etc. When the thickness D of the GaN layer is within the above range, the warping tendency of the epitaxial structure 10 can be alleviated. When the cap layer 210 is a GaN layer, the thickness D of the cap layer 210 can be adjusted based on the size of the substrate 100 to compensate for the different stresses introduced by substrates 100 of different sizes, ensuring the reliability and consistency of semiconductor devices.

[0056] Continuing to refer to Figure 1 As shown, the cap layer 210 can include an AlGaN layer;

[0057] The thickness D of the cap layer 210 and the diameter d of the substrate 100 satisfy a binary linear inequality relationship, preferably d / 4 < D < 2.5d, where the unit of D is nm and the unit of d is inches.

[0058] Among them, when growing the epitaxial layer 200 on substrates 100 of different sizes, the epitaxial structure 200 will warp. In order to alleviate the warping tendency of the epitaxial structure 10, the specific thickness of the cap layer 210 is determined based on the size of the substrate 100. The diameter d of the substrate 100 can be a positive integer. For example, it can be 2 feet, 3 feet, 4 feet, 6 feet, 8 feet, etc. The embodiments of the present invention do not limit the specific size of the substrate. Among them, the material of the cap layer 210 can be an AlGaN layer. The thickness D of the cap layer 210 and the diameter d of the substrate 100 satisfy d / 4 < D < 2.5d, where the unit of D is nm and the unit of d is inches. Exemplarily, the thickness D of the cap layer 210 can be any value greater than d / 4 and less than 2.5d. For example, it can be d / 2, 1d, or 1.5d, etc. When the thickness D of the AlGaN layer is within the above range, the warping tendency of the epitaxial structure 10 can be alleviated. When the cap layer 210 is an AlGaN layer, the thickness D of the cap layer 210 can be adjusted based on the size of the substrate 100 to compensate for the different stresses introduced by substrates 100 of different sizes, ensuring the reliability and consistency of semiconductor devices.

[0059] Continuing to refer to Figure 1 As shown, the cap layer 210 includes an AlGaN layer, and the atomic ratio of the Al component in the AlGaN layer is A%;

[0060] The thickness D of the cap layer 210 and the atomic ratio A% of the Al component in the AlGaN layer satisfy (A / 20 + 0.5) < D < (A + 5), where the unit of D is nm.

[0061] Among them, the material of the cap layer 210 can be an AlGaN layer. When the components in the AlGaN layer change, the thickness D of the cap layer 210 also needs to be adjusted adaptively. Specifically, the atomic ratio A% of the AL component in the AlGaN layer will change according to product requirements during preparation. The thickness D of the cap layer 210 and the atomic ratio A% of the Al component in the AlGaN layer satisfy (A / 20 + 0.5) < D < (A + 5), where the unit of D is nm. Exemplarily, the thickness D of the cap layer 210 can be any value greater than A / 20 + 0.5 and less than A + 5, such as A + 2, A + 3, or A + 4, etc. By adjusting the thickness of the cap layer 210 through the atomic proportion of the AL element in the material of the cap layer 210, it is ensured that the cap layer 210 can better relieve the warping trend of the epitaxial structure 10.

[0062] Continue to refer to Figure 1 As shown, the cap layer 210 includes an AlGaN layer, and the atomic ratio of the Al component in the AlGaN layer is A%;

[0063] The thickness D of the cap layer 210, the diameter d of the substrate 100, and the atomic ratio A% of the Al component in the AlGaN layer satisfy d / 4 < D < 2.5d, (A / 20 + 0.5) < D < (A + 5), where the unit of D is nm and the unit of d is inches.

[0064] Among them, the cap layer 210 can be an AlGaN layer, and the thickness D of the cap layer 210 is adjusted adaptively according to the size of the substrate 100 and the atomic ratio A% of the Al component in the AlGaN layer. Specifically, the thickness D of the cap layer 210 satisfies d / 4 < D < 2.5d, and at the same time, the thickness D of the cap layer 210 satisfies (A / 20 + 0.5) < D < (A + 5). That is, the thickness of the cap layer 210 is adjusted adaptively according to the size of the substrate 100 and the atomic ratio A% of the Al component in the AlGaN layer, and further adjusts the thickness of the cap layer 210 to be more suitable for the epitaxial structure 10 of the semiconductor device, further relieving the warping trend of the epitaxial structure 10.

[0065] On the basis of the above embodiments, optionally, if the size of the substrate is greater than or equal to the size threshold, the growth rate of the thickness of the cap layer 210 decreases as the size of the substrate increases. Through research by the inventor, it is found that when the size of the substrate increases to a certain extent, the thickness of the cap layer 210 that needs to be matched tends to level off. With this setting in the embodiments of the present invention, the matching degree of the cap layer 210 to the substrate size is better, further improving the reliability of the semiconductor device.

[0066] Figure 6This is a schematic diagram of the epitaxial structure of another semiconductor device provided in an embodiment of the present invention. The multilayer epitaxial layer 200 further includes an intermediate epitaxial layer 220 located between the cap layer 210 and the substrate 100.

[0067] The intermediate epitaxial layer 220 includes a nucleation layer 221, a buffer layer 222, a channel layer 223, and a barrier layer 224 stacked together.

[0068] The intermediate epitaxial layer 220 includes a nucleation layer 221, a buffer layer 222, a channel layer 223, and a barrier layer 224 stacked together. Specifically, the nucleation layer 221 and the buffer layer 222 can be made of nitrides, specifically GaN, AlN, or other nitrides. The nucleation layer 221 and the buffer layer 222 can be used to match the material of the substrate 100 and the epitaxial channel layer 223. The channel layer 223 can be made of GaN or other semiconductor materials, such as InAlN. The barrier layer 250 can be made of any semiconductor material capable of forming a heterojunction structure 225 with the channel layer 223, including gallium-based compound semiconductor materials or nitride semiconductor materials, such as InxAlyGazN1-xyz, where 0≤x≤1, 0≤y≤1, and 0≤z≤1. The barrier layer 224, together with the underlying channel layer 223, forms the heterojunction structure 225.

[0069] Based on the same inventive concept, embodiments of the present invention also provide a semiconductor device, which includes the epitaxial structure of the semiconductor devices included in the above embodiments. Further, Figure 7 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention is shown below. Figure 7 As shown, a semiconductor device 1 includes an epitaxial structure 10 and an electrode structure 20 located on the side of the epitaxial structure 10 away from the substrate 100.

[0070] The semiconductor device 1 further includes an electrode structure 20 on the side of the epitaxial structure 10 away from the substrate 100. The electrode structure 20 includes a source 21, a gate 22, and a drain 23. The source 21 and drain 23 are located on the side of the cap layer 260 away from the substrate 100, and the source 21 and drain 23 form ohmic contacts with the cap layer 260. For example, the source 21 and drain 23 can be made of conductive metals, such as titanium, aluminum, nickel, or gold. The gate 22 is located between the source 21 and drain 23, forming a Schottky contact with the cap layer 260. The gate 23 can also be made of conductive metals, such as nickel or gold.

[0071] It should be understood that the embodiments of the present invention ensure good performance of semiconductor device products from the perspective of epitaxial layer structure design of semiconductor devices. Semiconductor devices include, but are not limited to: high-power gallium nitride high electron mobility transistors (HEMTs) operating under high voltage and high current conditions; silicon-on-insulator (SOI) transistors; gallium arsenide (GaAs)-based transistors; and metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), and metal-insulator-semiconductor heterojunction field-effect transistors (MESFETs). Transistor (MISHFET) or other field-effect transistors.

[0072] This invention also provides a method for fabricating the epitaxial structure of a semiconductor device. Figure 8 This is a schematic flowchart of a method for fabricating an epitaxial structure of a semiconductor device according to an embodiment of the present invention, as shown below. Figure 8 As shown, the method for fabricating the epitaxial structure of a semiconductor device provided in this embodiment of the invention may include:

[0073] S110 provides a substrate.

[0074] For example, the substrate material can be one or more combinations of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon. The substrate can be prepared by atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, metal-organic compound vapor deposition, low-pressure chemical vapor deposition, high-density plasma chemical vapor deposition, etc.

[0075] S120. A multilayer epitaxial layer is prepared on one side of the substrate. The multilayer epitaxial layer includes a cap layer on the side away from the substrate, wherein the thickness D of the cap layer is positively correlated with the diameter d of the substrate.

[0076] For example, epitaxial layer growth methods include metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), and liquid phase epitaxy (LPE), etc., in which the epitaxial layer is grown on a substrate. The multilayer epitaxial layer includes a cap layer on the side away from the substrate, wherein the cap layer can be GaN, AlGaN, InGaN, AlInGaN, etc. The thickness of the cap layer is positively correlated with the diameter of the substrate. By reasonably setting the thickness of the cap layer according to the substrate size, the stress introduced by substrates of different sizes during epitaxial layer production can be compensated, ensuring that the stress experienced by epitaxial layers grown on substrates of different sizes is comparable, thus improving the consistency of semiconductor device performance. Simultaneously, a reasonable cap layer thickness also ensures that the cap layer fabrication process is simple, without increasing fabrication difficulty due to excessively high or low thicknesses. Furthermore, by setting a cap layer, surface states can be reduced, reducing surface leakage current in subsequent semiconductor devices and suppressing current collapse, thereby improving device performance and reliability.

[0077] In summary, the method for fabricating the epitaxial structure of a semiconductor device provided in this embodiment of the invention compensates for the stress introduced by substrates of different sizes by having a positive correlation between the thickness of the cap layer and the diameter of the substrate. This ensures that the stress experienced by the epitaxial layers grown on substrates of different sizes is comparable, thereby improving the consistency of the performance of semiconductor devices fabricated on substrates of different sizes and enhancing the reliability of the semiconductor devices.

[0078] Optionally, a multilayer epitaxial layer is fabricated on one side of the substrate, including:

[0079] An intermediate epitaxial layer is prepared on one side of the substrate;

[0080] A cap layer is prepared on the side of the intermediate epitaxial layer away from the substrate.

[0081] For example, multiple epitaxial layers are sequentially formed on one side of a substrate, which may include semiconductor materials based on III-V compounds. An intermediate epitaxial layer is sequentially grown on one side of the substrate, and this intermediate epitaxial layer includes a nucleation layer, a buffer layer, and a barrier layer. The cap layer can be GaN, AlGaN, InGaN, AlInGaN, etc. By setting different cap layer thicknesses, the stress introduced during epitaxial layer growth on different substrates can be alleviated, thereby improving the consistency of device performance on substrates of different sizes. Simultaneously, it can reduce surface states, reduce surface leakage current in subsequent semiconductor devices, suppress current collapse, and thus improve device performance and reliability.

[0082] The process of fabricating a cap layer on the side of the intermediate epitaxial layer away from the substrate includes:

[0083] A cap layer is grown on the side of the intermediate epitaxial layer away from the substrate by continuously introducing growth gas; or, a cap layer is grown on the side of the intermediate epitaxial layer away from the substrate by pulsed introduction of growth gas.

[0084] For example, there are many ways to grow the cap layer. Specifically, the cap layer can be an in-situ grown cap layer, such as growing GaN in MOCVD; the cap layer can also be grown ex-situ, such as growing GaN using molecular beam epitaxy or MBE and other equipment; the cap layer can also be a combination of in-situ and ex-situ growth, such as growing a certain thickness of GaN in MOCVD, then removing it from MOCVD and placing it in other equipment to grow another certain thickness of GaN. The cap layer can be grown continuously by simultaneously and continuously introducing Ga and N, ensuring a simple cap layer fabrication process. The cap layer can also be grown using a pulsed growth method with continuous Ga and intermittent N introduction, or a pulsed growth method with continuous N and intermittent Ga introduction, or a pulsed growth method with intermittent Ga and N introduction. Preparing the cap layer using a pulsed growth method can reduce pre-reactions during the fabrication process and reduce crystal defects that may occur during epitaxial layer growth.

[0085] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Features of various embodiments of the present invention can be partially or wholly coupled or combined with each other, and can cooperate and be technically driven in various ways. Various obvious changes, readjustments, combinations, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An epitaxial structure for a semiconductor device, characterized in that, It includes a substrate and a multi-layer epitaxial layer located on one side of the substrate. The multi-layer epitaxial layer includes a cap layer on the side away from the substrate. Among them, There is a positive correlation between the thickness D of the cap layer and the diameter d of the substrate. The cap layer includes a GaN layer. The thickness D of the cap layer and the diameter d of the substrate satisfy d / 5 < D < 2d, where the unit of D is nm and the unit of d is inch.

2. The epitaxial structure according to claim 1, characterized in that, There is a positive correlation between the thickness D of the cap layer and the warping degree of the substrate.

3. The epitaxial structure according to claim 1, characterized in that, The cap layer includes an AlGaN layer. The thickness D of the cap layer and the diameter d of the substrate satisfy d / 4 < D < 2.5d, where the unit of D is nm and the unit of d is inch.

4. The epitaxial structure according to claim 1, characterized in that, The cap layer includes an AlGaN layer, and the atomic ratio of Al component in the AlGaN layer is A%. The thickness D of the cap layer and the atomic ratio A% of Al component in the AlGaN layer satisfy (A / 20 + 0.5) < D < (A + 5), where the unit of D is nm.

5. The epitaxial structure according to claim 3, characterized in that, The cap layer includes an AlGaN layer, and the atomic ratio of Al component in the AlGaN layer is A%. The thickness D of the cap layer, the diameter d of the substrate, and the atomic ratio A% of Al component in the AlGaN layer satisfy d / 4 < D < 2.5d, (A / 20 + 0.5) < D < (A + 5), where the unit of D is nm and the unit of d is inch.

6. The epitaxial structure according to claim 1, characterized in that, If the size of the substrate is greater than or equal to the size threshold, the growth rate of the thickness of the cap layer decreases with the increase of the substrate size.

7. The epitaxial structure according to claim 1, characterized in that, The multi-layer epitaxial layer further includes an intermediate epitaxial layer located between the cap layer and the substrate. The intermediate epitaxial layer includes a nucleation layer, a buffer layer, a channel layer, and a barrier layer arranged in a stacked manner.

8. A semiconductor device, characterized in that, It includes the epitaxial structure according to any one of claims 1-7.

9. A method for fabricating an epitaxial structure of a semiconductor device, used to fabricate the epitaxial structure according to any one of claims 1-8; characterized in that, It includes: Providing a substrate. Preparing a multi-layer epitaxial layer on one side of the substrate. The multi-layer epitaxial layer includes a cap layer on the side away from the substrate. Among them, there is a positive correlation between the thickness D of the cap layer and the diameter d of the substrate. The cap layer includes a GaN layer. The thickness D of the cap layer and the diameter d of the substrate satisfy d / 5 < D < 2d, where the unit of D is nm and the unit of d is inch.

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