Programmable gain amplifier and gain control method

Abstract

A programmable gain amplifier is used to provide gain to an input signal to generate an output signal, which includes an operational amplifier and a capacitor array. The capacitor array includes first, second and third capacitors arranged in parallel and selectively coupled to an input terminal or a ground terminal of the operational amplifier according to first, second and third switches, respectively, wherein the first, second and third capacitors have first, second and third capacitance values, respectively, wherein the third capacitance value is equal to the first capacitance value plus the second capacitance value. In a first configuration, the first switch and the second switch are operated in a first conductive state and the third switch is operated in a second conductive state. When transitioning from the first configuration to a second configuration, the third switch is operated in the first conductive state and the first switch and the second switch are operated in the second conductive state. The gain values provided in the first configuration and the second configuration are equal.

Description

TECHNICAL FIELD

[0001] The present application relates to an amplifier and a gain control method, in particular, to a programmable gain amplifier and a gain control method thereof. BACKGROUND

[0002] When a programmable gain amplifier (PGA) adjusts gain, because the switching of internal elements of the PGA will produce different disturbances to affect the stability of the PGA, how to reduce the disturbance when adjusting the gain has become an important issue in the field. SUMMARY

[0003] A PGA is disclosed for providing a gain value to an input signal to generate an output signal, which includes an operational amplifier and a capacitor array. The capacitor array includes first, second and third capacitors arranged in parallel and selectively coupled to an input terminal or a ground terminal of the operational amplifier according to first, second and third switches, respectively, wherein the first, second and third capacitors have first, second and third capacitance values, respectively, and wherein the third capacitance value is equal to the first capacitance value plus the second capacitance value. In a first state, the first switch and the second switch are operated in a first conductive state and the third switch is operated in a second conductive state. When transitioning from the first state to a second state, the third switch is operated in the first conductive state and the first switch and the second switch are operated in the second conductive state. The gain values provided in the first state and the second state are equal.

[0004] A gain control method is disclosed for providing a gain value to an input signal to generate an output signal. The gain control method includes the following steps: receiving the input signal via a capacitor array, wherein the capacitor array is coupled to an input terminal of an operational amplifier, includes first, second and third capacitors arranged in parallel and selectively coupled to the input terminal or a ground terminal of the operational amplifier according to first, second and third switches, respectively, wherein the first, second and third capacitors have first, second and third capacitance values, respectively, and wherein the third capacitance value is equal to the first capacitance value plus the second capacitance value; in a first state, operating the first switch and the second switch in a first conductive state and operating the third switch in a second conductive state; when transitioning from the first state to a second state, operating the third switch in the first conductive state and operating the first switch and the second switch in a second conductive state, wherein the gain values provided in the first state and the second state are equal; and according to the second state, outputting the output signal using the operational amplifier.

[0005] Compared with the prior art, the PGA and the gain control method of the present application can flexibly adjust the gain value using a method that produces less disturbance, thereby increasing the stability of the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0006] The various forms of the application can best be understood by reading the detailed description together with the accompanying drawings, in which:

[0007] Figure 1 A schematic diagram of a PGA for some embodiments of the application.

[0008] Figure 2 A schematic diagram of a capacitance array in different configurations for some embodiments of the application.

[0009] Figure 3 A schematic diagram of a capacitance array in different configurations for other embodiments of the application.

[0010] Figure 4 A schematic diagram of a PGA for other embodiments of the application.

[0011] Figure 5 A schematic diagram of a capacitance array in different configurations for other embodiments of the application.

[0012] Figure 6 A timing diagram of capacitance array configuration changes for some embodiments of the application. DETAILED DESCRIPTION

[0013] Figure 1 A schematic diagram of a PGA 10 is shown for some embodiments of the application. The PGA 10 is configured to provide a gain value to an input signal Sin to generate an output signal Sout. The PGA 10 includes a capacitance array A, an operational amplifier OP, a capacitance CFB and a resistance R.

[0014] The capacitance array A includes capacitances CI, C2, C3 to Cx and corresponding switches SI, S2, S3 to Sx, where x is a positive integer. In some embodiments, the capacitance array A includes at least three capacitances. The capacitances CI to Cx each include a first terminal configured to receive the input signal Sin and a second terminal configured to be coupled to the input terminal Nl or the ground terminal of the operational amplifier OP according to the switches SI to Sx.

[0015] The capacitance CFB and the resistance R are coupled across the output terminals Nl and N2 of the operational amplifier OP, respectively. The operational amplifier OP is configured to output the output signal Sout at the output terminal N2.

[0016] The gain value of the PGA 10 is controlled by the on / off states of the switches S1-Sx. Details are described as follows.

[0017] The capacitance values of the capacitors C1-Cx in the capacitor array A are not all the same. In some embodiments, the capacitance values of the capacitors C1-Cx are partially the same but partially different. In the present application, depending on the configuration of the switches S1-Sx, when the capacitors C1-Cx are connected to the input terminal N, they operate as a capacitor array Al, and when the capacitors C1-Cx are connected to the ground terminal, they operate as a capacitor array A2. The sum of the capacitance values of the capacitor array Al and the capacitor array A2 is equal to the capacitance value of the capacitor array A. In other words, the changes of the capacitor array Al and the capacitor array A2 are interrelated. In the following, an embodiment is described in which the capacitor array A contains six capacitors, but the present application is not limited thereto, and various numbers of capacitors are within the scope of the present application.

[0018] Reference is made to Figure 2 . Figure 2 A schematic diagram of an embodiment in which the capacitor array Al and the capacitor array A2 are switched from configuration Fl to configuration F2 is shown. The capacitance values of the capacitors C1-C6 are 2.5, 5, 5, 10, 20, and 40 units, respectively. The capacitance value of the capacitor C4 is equal to the sum of the capacitance values of the capacitors C2 and C3. In some embodiments, the capacitance values of the capacitors C2 and C3 are not equal. The above values are used to represent the ratios of the capacitance values among the capacitors and are not limited to any unit, for example, the above units can be 1 pF, 10 pF, or other suitable units.

[0019] In different configurations of the PGA 10, the switches S1-Sx have different on / off states to control the capacitance values of the capacitor array Al and the capacitor array A2. In some embodiments, the configurations of the capacitor array Al and the capacitor array A2 are represented by a six-bit binary number B, in which the six bits of the binary number B represent which of the capacitors C1-C6 operate as part of the capacitor array Al (or the capacitor array A2). In the binary number B, "0" represents that a particular capacitor does not operate as part of the capacitor array Al (or the capacitor array A2), and "1" represents that a particular capacitor operates as part of the capacitor array Al (or the capacitor array A2). For example, when the binary number B of the capacitor array Al is "110000", it means that the capacitors C1 and C2 operate as part of the capacitor array Al, so that the total capacitance value of the capacitor array Al in this configuration is the sum of the capacitance values of the capacitors C1 and C2. Conversely, in the configuration in which the binary number B of the capacitor array Al is "110000", the binary number B of the capacitor array A2 is "001111", so that the total capacitance value of the capacitor array A2 in this configuration is the sum of the capacitance values of the capacitors C3-C6.

[0020] For ease of understanding, when switches S1-Sx are switched to connect capacitors C1-Cx to input terminal N1, the first on state is referred to. When switches S1-Sx are switched to connect capacitors C1-Cx to ground, the second on state is referred to.

[0021] Please refer to Figure 2 In configuration Fl of PGA 10, the sequence B of capacitor array Al is "011000", which has a total capacitance value of 10 (0+5+5+0+0+0=10) units. In configuration F2, the sequence B of capacitor array Al is "000100", which also has a total capacitance value of 10 (0+0+0+10+0+0=10) units. The capacitance values of the two configurations are the same, but the operation is that the number of capacitors of capacitor array Al is changed from 2 to 1.

[0022] When PGA 10 is switched from configuration Fl to configuration F2, capacitor C1 and capacitor C2 are switched from operating as part of capacitor array Al to operating as part of capacitor array A2, and capacitor C4 is switched from operating as part of capacitor array A2 to operating as part of capacitor array Al, where switches S2, S3 are switched from the first on state to the second on state, and switch S4 is switched from the second on state to the first on state. The total capacitance value of capacitor array Al does not change between configuration Fl and configuration F2. In some embodiments, the process of switching from configuration Fl to configuration F2 is referred to as "handover". After the handover, capacitor array Al has more capacitors of lower capacitance values available for subsequent switching. Thus, even when the capacitance value of capacitor array Al has been adjusted to a large value, PGA 10 can still adjust the gain value with fine resolution.

[0023] Correspondingly, the adjustment of capacitor array A2 corresponds to capacitor array Al. Specifically, capacitors C1-C6 can be shared as part of capacitor array Al and capacitor array A2, which are operated as part of capacitor array Al or capacitor array A2. Thus, in configuration Fl-F2 of PGA 10, the sequence B of capacitor array A2 can be represented as "100111" and "111011", respectively, which is exactly the opposite of the sequence B of capacitor array A2.

[0024] In some embodiments, when PGA 10 is switched from configuration Fl to configuration F2, because the total capacitance value of capacitor array Al and capacitor array A2 does not change, the transition is also referred to as a minimum difference transition.

[0025] In some embodiments, PGA 10 only switches two switches (changes the coupling state of two capacitors) when adjusting the gain value. Please refer to Figure 3A schematic diagram illustrating an embodiment of the transition of the capacitance array Al and the capacitance array A2 from configuration F3 to configuration F4 of the PGA 10.

[0026] In configuration F3 of the PGA 10, the sequence B of the capacitance array Al is "100000". When the capacitance array Al is transitioned from configuration F3 to configuration F4, the switch Sl is switched from the first conductive state to the second conductive state, and the switch S2 is switched from the second conductive state to the first conductive state, causing the sequence B of the capacitance array Al to be transitioned to "010000". In this transition, only one switch is switched from the first conductive state to the second conductive state, and only one switch is switched from the second conductive state to the first conductive state. The transition of the capacitance array A2 corresponds to that of the capacitance array Al, which is not described herein.

[0027] In some embodiments, the transition from configuration F3 to configuration F4 is also referred to as a minimum switching transition, because only two switches of the capacitance array Al are switched. Generally, the more switches that are switched, the greater the disturbance, which affects the stability of the circuit. Therefore, compared to the prior art, the PGA 10 of the present application generates less disturbance when adjusting the gain value, so that the circuit is more stable.

[0028] In some embodiments, the PGA 10 uses both the minimum difference transition and the minimum switching transition when adjusting the gain value.

[0029] Reference Figure 4 . Figure 4 A schematic diagram of the PGA 10 according to other embodiments of the present application is shown. In other embodiments, the capacitance array A of the PGA 10 further includes a compensation capacitance Cnl, a compensation capacitance Cn2, a switch Snl, and a switch Sn2. The capacitances Cnl-Cn2 each include a first end to receive an input signal Sin and a second end connected to the switch Snl-Sn2, respectively. The capacitances Cnl-Cn2 are arranged in parallel and are selectively coupled to the input end Nl of the operational amplifier OP or to ground according to the switch Snl-Sn2, respectively.

[0030] Similar to the capacitances Cl-Cx, the capacitances Cnl-Cn2 are operable as part of the capacitance array Al or the capacitance array A2 according to the switch Snl-Sn2, wherein the switch Snl-Sn2 is conductive to the input end Nl, which is also referred to as the first conductive state, and is conductive to ground, which is also referred to as the second conductive state.

[0031] The compensation capacitances Cnl and Cn2 are used to exhibit a transient state after the overall capacitance value of the capacitance array Al is changed, and then transition to a steady state from the transient state, wherein the transient state is divided into three transient TTl-TT3 operations (as shown in FIG. 6). Figure 5(As shown). The three transient states TT1 to TT3 correspond to... Figure 5 The first, second, and third columns of the capacitor array A1 in configuration F6 of PGA 10 are sequence B. In the first transient TT1, compensation capacitors Cn1 and Cn2 first compensate for the capacitance values ​​in capacitor array A1 that have changed due to the switching conduction states of switches S1 to Sx. Then, in the second transient TT2, compensation capacitors Cn1 and Cn2 gradually eliminate the compensated capacitance values. Finally, in the third transient TT3, the compensated capacitance values ​​of compensation capacitors Cn1 and Cn2 are completely eliminated. It is worth noting that... Figure 5 The sequence of transients TT1 to TT3 shown represents the result after the transformation in that transient state. Please refer to the following for operation details. Figure 5 .

[0032] exist Figure 5 In the embodiment, capacitor array A is described using four capacitors C1 to C4 and compensation capacitors Cn1 and Cn2. However, the invention is not limited to this, and the number of various compensation capacitors is within the scope of the invention. For example, the number of compensation capacitors can be one or more.

[0033] like Figure 5 As shown, capacitors C1 to C4 and compensation capacitors Cn1 and Cn2 have capacitance values ​​of 2.5, 5, 5, 10, 1.25 and 1.25 units, respectively.

[0034] In configuration F5, switch S2 is in the first conducting state, and the other switches are in the second conducting state. Capacitor array A1 has a capacitance value of 5 (0+5+0+0+0+0=5) units. When switching from configuration F5 to configuration F6, switch S2 switches from the first conducting state to the second conducting state, switch S1 switches from the second conducting state to the first conducting state, and the conducting states of the other switches remain unchanged, so that capacitor array A1 has a capacitance value of 2.5 (2.5+0+0+0+0+0=2.5) units.

[0035] After switching from configuration F5 to configuration F6, the total capacitance of capacitor array A1 decreases by 2.5 units (5-2.5=2.5) due to the switching between switches S1 and S2. At this point, it enters the change state F6' of configuration F6 (please refer to...). Figure 6 Compensation capacitors Cn1 and Cn2 are used to compensate for the 2.5-unit reduction in capacitance array A1 during the first transient state TT1 immediately after switching to configuration F6. Therefore, switches Sn1 and Sn2 switch from the second conducting state to the first conducting state, increasing the capacitance value of capacitor array A1 by 2.5 units. Then, entering the second transient state TT2, the compensated 2.5 units are gradually reduced to 0. Figure 5As shown, switch Sn1 and switch Sn2 are switched from the second on state to the first on state in the first transient state TT1, then switch Sn2 is switched from the first on state to the second on state in the second transient state TT2, and finally switch Sn1 is switched from the first on state to the second on state to enter the third transient state TT3. After the switching of the third transient state TT3 is completed, the stable state of configuration F6 is entered. The total capacitance value of the capacitor array Al is converted from 5 units to 3.75 units and then to 2.5 units via the conversion of the three transient states TT1-TT3 in the above-mentioned time period.

[0036] In other words, the compensation capacitor Cn1 and the compensation capacitor Cn2 are used to extend the time (i.e. Figure 6 the time covered by the change state F6') of the conversion of the total capacitance value of the capacitor array Al, so that the change of the capacitance value of each stage of the capacitor array Al is reduced, thereby reducing the disturbance caused by the conversion of the capacitance value and improving the stability of the PGA 10 circuit.

[0037] The sum of the capacitance values of the compensation capacitor Cn1 and the compensation capacitor Cn2 is equal to the smallest one of the capacitance values of the capacitors C1-C4. In some embodiments, the sum of the capacitance values of the compensation capacitor Cn1 and the compensation capacitor Cn2 is smaller than the smallest one of the capacitance values of the capacitors C1-C4. In some embodiments, the capacitance values of the compensation capacitor Cn1 and the compensation capacitor Cn2 are not equal.

[0038] In other embodiments, the sum of the capacitance values of the compensation capacitor Cn1 and the compensation capacitor Cn2 is greater than the smallest one of the capacitance values of the capacitors C1-C4, but smaller than a threshold value, wherein the threshold value is used to indicate that the change of the corresponding capacitance value of the PGA 10 is negligible.

[0039] In some embodiments, the capacitor array A contains more than two compensation capacitors, and the capacitance values of these compensation capacitors are equal. The capacitance values of these compensation capacitors are m-n times the smallest one of the capacitance values of the capacitors C1-Cx, wherein m and n are positive integers greater than 1.

[0040] In summary, Figures 1 to 5 , Figure 5 The compensation method provided by the embodiments can combine the minimum difference conversion and the minimum switching conversion described above. That is, whether the total capacitance values of the capacitor array Al and the capacitor array A2 change or not, the compensation method provided by the embodiments can be used to convert the configuration. Figure 5 The compensation method provided by the embodiments can be used to convert the configuration.

[0041] The above description merely illustrates certain embodiments of the present application and is not intended to limit the scope of the present application. The skilled person in the art will readily understand that the present application can be implemented in other ways without departing from the spirit and scope of the present application. The equivalent embodiments of the present application are still within the spirit and scope of the present application, and various modifications, substitutions and changes can be made without departing from the spirit and scope of the present application.

[0042] SYMBOL DESCRIPTION

[0043] 10: programmable gain amplifier

[0044] A: capacitor array

[0045] OP: operational amplifier

[0046] CFB: capacitor

[0047] R: resistor

[0048] Sin: input signal

[0049] Sout: output signal

[0050] C1: capacitor

[0051] C2: capacitor

[0052] C3: capacitor

[0053] C4: capacitor

[0054] C5: capacitor

[0055] C6: capacitor

[0056] Cx: capacitor

[0057] Cn1: compensation capacitor

[0058] Cn2: compensation capacitor

[0059] S1: switch

[0060] S2: switch

[0061] S3: switch

[0062] S1x: switch

[0063] Sn1: switch

[0064] Sn2: switch

[0065] N1: input terminal

[0066] N2: output terminal

[0067] F1: configuration

[0068] F2: configuration

[0069] F3: configuration

[0070] F4: configuration

[0071] F5: configuration

[0072] F6: configuration

[0073] F6': change configuration

[0074] B: sequence

[0075] TT1: transient

[0076] TT2: transient

[0077] TT3: transient

Claims

1. A programmable gain amplifier (PGA) for providing a gain value to an input signal to generate an output signal, comprising: an operational amplifier to output the output signal; an operational amplifier (OP AMP) having an input terminal and a ground terminal; a capacitor array comprising a first capacitor, a second capacitor and a third capacitor arranged in parallel and selectively coupled to the input terminal or the ground terminal of the OP AMP according to a first switch, a second switch and a third switch, respectively, wherein the first capacitor, the second capacitor and the third capacitor have a first capacitance value, a second capacitance value and a third capacitance value, respectively, wherein the third capacitance value is equal to the first capacitance value plus the second capacitance value, wherein in a first configuration, the first switch and the second switch are operated in a first conductive state and the third switch is operated in a second conductive state, and when transitioning from the first configuration to a second configuration, the third switch is operated in the first conductive state and the first switch and the second switch are operated in the second conductive state, wherein the gain value provided in the first configuration is equal to the gain value provided in the second configuration, and in the capacitor array, a number of capacitors not coupled to the OP AMP in the first configuration is different from a number of capacitors not coupled to the OP AMP in the second configuration; wherein in the first conductive state, the first switch, the second switch and / or the third switch are switched to connect the corresponding first capacitor, second capacitor and / or third capacitor to the input terminal of the OP AMP; wherein in the second conductive state, the first switch, the second switch and / or the third switch are switched to connect the corresponding first capacitor, second capacitor and / or third capacitor to the ground terminal of the OP AMP.

2. The PGA of claim 1, wherein when the first switch, the second switch and / or the third switch are operated in the first conductive state, the first switch, the second switch and / or the third switch are operated with the corresponding first capacitor, second capacitor and / or third capacitor as a first capacitor array, respectively, and when the first switch, the second switch and / or the third switch are operated in the second conductive state, the first switch, the second switch and / or the third switch are operated with the corresponding first capacitor, second capacitor and / or third capacitor as a second capacitor array, respectively.

3. The PGA of claim 2, wherein in a third configuration, the second switch is operated in the first conductive state and the first switch and the third switch are operated in the second conductive state, wherein when transitioning from the third configuration to a fourth configuration, the third switch is operated in the first conductive state and the first switch and the second switch are operated in the second conductive state, and wherein the gain value provided in the third configuration is not equal to the gain value provided in the fourth configuration.

4. The programmable gain amplifier of claim 3, wherein the array of capacitors further comprises a first compensation capacitor selectively coupled to the input terminal or the ground terminal according to a first compensation switch, wherein the first compensation capacitor has a compensation capacitance value, wherein the compensation capacitance value is less than or equal to the first capacitance value.

5. The programmable gain amplifier of claim 4, wherein during a first time period after switching the first capacitor from operating as the first array of capacitors to operating as the second array of capacitors, the first compensation switch is to switch from the second conductive state to the first conductive state and then to the second conductive state during the first time period, wherein during the first time period the second capacitor and the third capacitor operate as the second array of capacitors.

6. A gain control method for providing a gain value to an input signal to generate an output signal, comprising: receiving the input signal via an array of capacitors, wherein the array of capacitors is coupled to an input terminal of an operational amplifier, comprises a first capacitor, a second capacitor, and a third capacitor arranged in parallel and selectively coupled to the input terminal of the operational amplifier or a ground terminal according to a first switch, a second switch, and a third switch, respectively, wherein the first capacitor, the second capacitor, and the third capacitor have a first capacitance value, a second capacitance value, and a third capacitance value, respectively, wherein the third capacitance value is equal to the first capacitance value plus the second capacitance value; in a first configuration, operating the first switch and the second switch in a first conductive state and operating the third switch in a second conductive state; when transitioning from the first configuration to a second configuration, operating the third switch in the first conductive state and operating the first switch and the second switch in the second conductive state, wherein the gain value provided in the first configuration is equal to the gain value provided in the second configuration, and wherein a number of capacitors in the array of capacitors that are not coupled to the operational amplifier in the first configuration is different from a number of capacitors in the array of capacitors that are not coupled to the operational amplifier in the second configuration; and outputting, according to the second configuration, the output signal using the operational amplifier; wherein in the first conductive state, the first switch, the second switch, and / or the third switch switch to connect the corresponding first capacitor, the second capacitor, and / or the third capacitor to the input terminal of the operational amplifier; wherein in the second conductive state, the first switch, the second switch, and / or the third switch switch to connect the corresponding first capacitor, the second capacitor, and / or the third capacitor to the ground terminal of the operational amplifier.

7. The gain control method of claim 6, wherein when the first switch, the second switch, and / or the third switch are operated in the first conductive state, the first switch, the second switch, and / or the third switch correspondingly operate the first capacitor, the second capacitor, and / or the third capacitor as a first array of capacitors, and ​ When the first switch, the second switch and / or the third switch is operated in the second conducting state, the first switch, the second switch and / or the third switch respectively corresponds to the first capacitor, the second capacitor and / or the third capacitor operating as a second capacitor array.

8. The gain control method according to claim 7, further comprising: in a third state, operating the second switch in the first conducting state, and operating the first switch and the third switch in the second conducting state; and when transitioning from the third state to a fourth state, operating the third switch in the first conducting state, and operating the first switch and the second switch in the second conducting state, wherein the gain values provided in the third state and the fourth state are not equal.

9. The gain control method according to claim 8, wherein the capacitor array further comprises a first compensation capacitor selectively coupled to the input terminal or the ground terminal according to a first compensation switch, wherein the first compensation capacitor has a compensation capacitor value.

10. The gain control method according to claim 9, further comprising: when transitioning from the third state to the fourth state, switching the first compensation switch from the first conducting state to the second conducting state and then to the first conducting state.

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