Display substrate, preparation method thereof and display device

Abstract

A display substrate, a manufacturing method thereof and a display device, the display substrate comprising a source-drain metal layer on a base (10), an insulating layer on the source-drain metal layer, and a touch metal layer on the insulating layer, the source-drain metal layer comprising first traces, the touch metal layer comprising second traces, a projection of the first traces on the base (10) overlapping a projection of the second traces on the base (10), the first traces and the second traces forming a double-layer trace structure.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate, a method for preparing the same, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate. On a plane perpendicular to the display substrate, the display substrate includes a source / drain metal layer on a substrate, an insulating layer on the source / drain metal layer, and a touch metal layer on the insulating layer. The source / drain metal layer includes a first trace, and the touch metal layer includes a second trace. The orthographic projection of the first trace on the substrate and the orthographic projection of the second trace on the substrate have an overlapping area. The first trace and the second trace form a double-layer trace structure.

[0005] In an exemplary embodiment, the display substrate includes a display area, a bonding area located on one side of the display area, and a border area located on other sides of the display area. The bonding area includes a first fan-out area and a bonding pin area.

[0006] The first trace includes a first power line, and the second trace includes a first auxiliary power line. The first power line is located in the frame area and the first fan-out area, and extends from the first fan-out area to the bonding pin area. The first auxiliary power line is located in the frame area and the first fan-out area. The orthographic projection of the first power line on the substrate and the orthographic projection of the first auxiliary power line on the substrate have an overlapping area.

[0007] The first power line and the first auxiliary power line are electrically connected through a groove or through-hole penetrating the insulation layer.

[0008] In an exemplary embodiment, the touch metal layer includes a first touch metal layer and a second touch metal layer;

[0009] The first auxiliary power line is disposed on the same layer as the first touch metal layer; or...

[0010] The first auxiliary power line is disposed on the same layer as the second touch metal layer; or...

[0011] The first auxiliary power line includes a first sub-trace and a second sub-trace. The first sub-trace is disposed on the same layer as the first touch metal layer, and the second sub-trace is disposed on the same layer as the second touch metal layer.

[0012] In an exemplary embodiment, the border area includes at least one isolation dam, which is disposed around the display area;

[0013] The orthographic projection of the first auxiliary power line on the substrate does not overlap with the orthographic projection of the isolation dam on the substrate, and the distance between the first auxiliary power line and the display area is greater than the distance between the isolation dam and the display area.

[0014] In an exemplary embodiment, the border area includes at least one isolation dam, which is disposed around the display area;

[0015] The orthographic projection of the first auxiliary power line on the substrate at least partially covers the orthographic projection of the isolation dam on the substrate.

[0016] In an exemplary embodiment, the insulating layer includes an encapsulation structure layer, a buffer layer, and a touch insulating layer; the groove includes a first groove and a third groove, the first groove penetrating the touch insulating layer and the buffer layer, and the third groove penetrating the encapsulation structure layer.

[0017] In an exemplary embodiment, the orthographic projection of the first groove on the substrate covers the orthographic projection of the third groove on the substrate.

[0018] In an exemplary embodiment, the source / drain metal layer includes a first source / drain metal layer and a second source / drain metal layer;

[0019] The first power line is disposed on the same layer as the first source / drain metal layer; or...

[0020] The first power line is disposed on the same layer as the second source / drain metal layer; or...

[0021] The first power line includes a third sub-trace and a fourth sub-trace. The third sub-trace is disposed in the same layer as the first source / drain metal layer, and the fourth sub-trace is disposed in the same layer as the second source / drain metal layer.

[0022] In an exemplary embodiment, the display substrate includes a display area and a bonding area located on one side of the display area. The bonding area, along a direction away from the display area, sequentially includes a first fan-out area, a bending area, a driver chip area, and a bonding pin area.

[0023] The first trace includes a second power line, the second trace includes a second auxiliary power line, the second power line is located in the display area and the first fan-out area, and extends from the first fan-out area to the bonding pin area, the second auxiliary power line is located in the bonding area and is located on the side of the bending area away from the display area, and there is an overlapping area between the orthographic projection of the second power line on the substrate and the orthographic projection of the second auxiliary power line on the substrate;

[0024] The second power line and the second auxiliary power line are electrically connected through a groove or through-hole penetrating the insulation layer.

[0025] In an exemplary embodiment, the touch metal layer includes a first touch metal layer and a second touch metal layer;

[0026] The second auxiliary power line is disposed on the same layer as the first touch metal layer; or...

[0027] The second auxiliary power line is disposed on the same layer as the second touch metal layer; or...

[0028] The second auxiliary power line includes a fifth sub-trace and a sixth sub-trace. The fifth sub-trace is disposed on the same layer as the first touch metal layer, and the sixth sub-trace is disposed on the same layer as the second touch metal layer.

[0029] In an exemplary embodiment, in the bonding area, the second power cable includes a first lateral connecting portion extending along a first direction and a first longitudinal connecting portion extending along a second direction; the second auxiliary power cable includes a second lateral connecting portion extending along the first direction and a second longitudinal connecting portion extending along the second direction.

[0030] Both the first lateral connecting portion and the second lateral connecting portion are disposed between the bending area and the driving chip area. The orthographic projection of the first lateral connecting portion on the substrate and the orthographic projection of the second lateral connecting portion on the substrate overlap in an area; the orthographic projection of the first longitudinal connecting portion on the substrate and the orthographic projection of the second longitudinal connecting portion on the substrate also overlap in an area.

[0031] In an exemplary embodiment, the first longitudinal connecting portion includes a plurality of first branches and a plurality of second branches. The first branches extend from the end of the first transverse connecting portion along the first direction to the bonding pin area. The second branches extend from the first transverse connecting portion to the display area. The second longitudinal connecting portion extends from the end of the second transverse connecting portion along the first direction to the bonding pin area. The orthographic projection of the first branch on the substrate and the orthographic projection of the second longitudinal connecting portion on the substrate have an overlapping area.

[0032] In an exemplary embodiment, the source / drain metal layer includes a first source / drain metal layer and a second source / drain metal layer;

[0033] The second power line is disposed in the same layer as the first source / drain metal layer; or,

[0034] The second power line is disposed in the same layer as the second source / drain metal layer; or,

[0035] The second power line includes a seventh sub-trace and an eighth sub-trace. The seventh sub-trace is disposed in the same layer as the first source / drain metal layer, and the eighth sub-trace is disposed in the same layer as the second source / drain metal layer.

[0036] In an exemplary embodiment, the display substrate includes a display area and a bonding area located on one side of the display area. The bonding area includes a driver chip area and a bonding pin area, and an input / output trace located between the driver chip area and the bonding pin area. The driver chip area includes driver chip pins, the bonding pin area includes bonding pins, and the input / output trace connects the driver chip pins and the bonding pins.

[0037] The first trace includes a first input / output trace, and the second trace includes a second input / output trace. The orthographic projections of the first input / output trace on the substrate and the orthographic projections of the second input / output trace on the substrate have an overlapping area.

[0038] In an exemplary embodiment, the touch metal layer includes a first touch metal layer and a second touch metal layer;

[0039] The second input / output traces are disposed on the same layer as the first touch metal layer; or...

[0040] The second input / output traces are disposed on the same layer as the second touch metal layer; or...

[0041] The second input / output trace includes a ninth sub-trace and a tenth sub-trace. The ninth sub-trace is disposed on the same layer as the first touch metal layer, and the tenth sub-trace is disposed on the same layer as the second touch metal layer.

[0042] In an exemplary embodiment, an insulating layer is included between the source / drain metal layer and the touch metal layer, and the first input / output trace and the second input / output trace are electrically connected through a groove or via penetrating the insulating layer.

[0043] In an exemplary embodiment, an insulating layer is included between the source / drain metal layer and the touch metal layer. The first input / output trace and the second input / output trace are isolated through the insulating layer and electrically connected through the driver chip pin and the bonding pin.

[0044] In an exemplary embodiment, the source / drain metal layer includes a first source / drain metal layer and a second source / drain metal layer;

[0045] The first input / output traces are disposed on the same layer as the first source / drain metal layer; or...

[0046] The first input / output traces are disposed on the same layer as the second source / drain metal layer; or...

[0047] The first input / output trace includes an eleventh sub-trace and a twelfth sub-trace. The eleventh sub-trace is disposed on the same layer as the first source / drain metal layer, and the twelfth sub-trace is disposed on the same layer as the second source / drain metal layer.

[0048] This disclosure also provides a display device, including a display substrate as described in any of the preceding embodiments.

[0049] This disclosure also provides a method for preparing a display substrate, including:

[0050] A source / drain metal layer is formed, the source / drain metal layer including a first trace;

[0051] An insulating layer is formed on the source / drain metal layer;

[0052] A touch metal layer is formed on the insulating layer. The touch metal layer includes a second trace. The orthographic projection of the first trace on the substrate and the orthographic projection of the second trace on the substrate have an overlapping area. The first trace and the second trace form a double-layer trace structure.

[0053] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0054] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0055] Figure 1This is a schematic diagram of the structure of a display device;

[0056] Figure 2 This is a schematic diagram of the structure of a display substrate;

[0057] Figure 3 This is a schematic diagram of the bonding area and the frame area in a display substrate;

[0058] Figure 4 This is a schematic cross-sectional view of a display area in a display substrate.

[0059] Figure 5 This is a schematic diagram of an equivalent circuit for a pixel driving circuit.

[0060] Figure 6 This is a timing diagram of a pixel driving circuit.

[0061] Figure 7a This is a schematic diagram of a planar structure of a display substrate, which is an exemplary embodiment of the present disclosure.

[0062] Figures 7b to 7g for Figure 7a A sectional view of region A-A' in the middle;

[0063] Figures 7h to 7j for Figure 7a A sectional view of region B-B' in the middle;

[0064] Figure 8a A schematic diagram showing the formation of a light-emitting structure layer pattern according to an exemplary embodiment of this disclosure;

[0065] Figure 8b for Figure 8a A sectional view of region A-A' in the middle;

[0066] Figure 8c for Figure 8a A sectional view of region B-B' in the middle;

[0067] Figure 9 This is a schematic diagram showing the encapsulation structure layer pattern formed according to an exemplary embodiment of the present disclosure;

[0068] Figure 10a This is a schematic diagram showing the formation of a touch insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0069] Figure 10b for Figure 10a A sectional view of region A-A' in the middle;

[0070] Figure 10c for Figure 10a A sectional view of region B-B' in the middle;

[0071] Figure 11aThis is a schematic diagram of the patterned encapsulation structure layer in the first groove, as an exemplary embodiment of the present disclosure.

[0072] Figure 11b for Figure 11a A sectional view of region A-A' in the middle;

[0073] Figure 12a A schematic diagram of the planar structure of the touch electrode and touch lead after forming the second touch metal layer pattern in an exemplary embodiment of this disclosure;

[0074] Figure 12b for Figure 12a A sectional view of the D-D' region;

[0075] Figure 12c and Figure 12d A schematic diagram of the structure of the first and second groove regions after forming the second touch metal layer pattern in an exemplary embodiment of this disclosure;

[0076] Figure 13a This is a schematic diagram of a planar structure of a display substrate containing a bonding pin area and a driver chip pin area, which is an exemplary embodiment of the present disclosure.

[0077] Figures 13b to 13e for Figure 13a A cross-sectional view of the C-C' region. Detailed Implementation

[0078] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0079] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0080] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0081] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0082] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0083] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0084] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0085] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0086] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0087] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0088] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0089] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0090] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a pixel array. The timing controller is connected to the data signal driver, the scan signal driver, and the light emission signal driver. The data signal driver is connected to multiple data signal lines (D1 to Dn), the scan signal driver is connected to multiple scan signal lines (S1 to Sm), and the light emission signal driver is connected to multiple light emission signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emission device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, at least one light emission signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data signal driver to the data signal driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan signal driver to the scan signal driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light emission signal driver to the light emission signal driver. The data signal driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data signal driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan signal driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. The light emission signal driver can generate transmit signals to be provided to light emission signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0091] Figure 2 This is a schematic diagram of the structure of a display substrate. (Example) Figure 2As shown, the display substrate may include a display area 100 and a non-display area surrounding the display area 100. The non-display area may include a bonding area 200 on one side of the display area 100 and a border area 300 on the other sides of the display area 100. In an exemplary embodiment, the display area 100 may include a plurality of sub-pixels arranged in a matrix. The sub-pixels may include pixel driving circuits and light-emitting devices. The bonding area 200 may include at least an isolation dam and a bonding circuit that connects the signal lines of the plurality of sub-pixels to an external driving device. The border area 300 may include at least an isolation dam, a gate driver on array (GOA) circuit, and power lines that transmit voltage signals to the plurality of sub-pixels. The bonding area 200 and the isolation dam of the border area 300 form a ring structure surrounding the display area 100.

[0092] Figure 3 This is a schematic diagram of the bonding area and the bezel area in a display substrate. Figure 3 As shown, in an exemplary embodiment, in a plane parallel to the display substrate, the bonding area 200 may be located on one side of the display area 100. The bonding area 200 may include a first fan-out area 211, a bending area 212, a second fan-out area 213, an anti-static area 214, a driver chip area 215, and a bonding pin area 216 arranged sequentially along a direction away from the display area 100. The first fan-out area 211 may include at least multiple data connection lines, multiple touch leads, a second power line, and a first power line. The multiple data connection lines are configured to connect to the data lines of the display area 100 in a fan-out routing manner. The multiple touch leads are configured to connect to the touch electrodes of the display area 100. The first power line (VSS) is configured to connect to the low-voltage power line of the bezel area 300, and the second power line (VDD) is configured to connect to the high-voltage power line of the display area 100. The bending area 212 may include a composite insulating layer with grooves, configured to bend the bonding area 200 to the back of the display area 100. The second fan-out area 213 may include multiple data connection lines led out in a fan-out routing manner. The anti-static area 214 may include anti-static circuitry, configured to prevent electrostatic damage to the display substrate by eliminating static electricity. The driver chip area 215 may include an integrated circuit (IC), configured to connect to the multiple data connection lines. The bonding pin area 216 may include multiple bonding pads, configured to bond to an external flexible printed circuit (FPC).

[0093] In an exemplary embodiment, the isolation dam may include a first isolation dam 410 and a second isolation dam 420. At least a portion of the first isolation dam 410 and the second isolation dam 420 may be disposed in the first fan-out area 211. The first isolation dam 410 and the second isolation dam 420 may extend along a direction parallel to the edge of the display area. The distance between the first isolation dam 410 and the edge of the display area is less than the distance between the second isolation dam 420 and the edge 110 of the display area. The isolation dam is configured to block the organic layer in the encapsulation structure layer to prevent the organic layer from flowing to the bending area.

[0094] In an exemplary embodiment, within a plane parallel to the display substrate, the bezel region 300 may include a circuit region, an isolation dam region, and a crack dam region sequentially arranged along a direction away from the display region 100. The circuit region may include at least a gate driving circuit, which is connected to the first scan line and the second scan line of the pixel driving circuit in the display region 100. The isolation dam region may include at least a first power line, a first isolation dam 410, and a second isolation dam 420. The first power line extends along a direction parallel to the edge of the display region and is connected to the first power line VSS of the pixel driving circuit in the display region 100. The first isolation dam 410 and the second isolation dam 420 extend along a direction parallel to the edge of the display region. The first isolation dam 410 and the second isolation dam 420 of the bezel region 300 are integrally formed with the first isolation dam 410 and the second isolation dam 420 of the bonding region 200, and are synchronously fabricated using the same patterning process to form a ring structure surrounding the display region 100. The crack dam area includes multiple cracks set on the composite insulation layer. The multiple cracks are configured to reduce the stress on the display area 100 and the circuit area during the cutting process, and to cut the cracks so as to propagate them in the direction of the display area 100 and the circuit area, thereby avoiding affecting the film structure of the display area 100 and the circuit area.

[0095] Figure 4 This is a cross-sectional structural diagram of a display area in a display substrate, illustrating the structure of four sub-pixels in the display area. Figure 4 As shown, on a plane perpendicular to the display substrate, each sub-pixel in the display area may include a driving structure layer 501 disposed on the substrate 10, a light-emitting structure layer 502 disposed on the side of the driving structure layer 501 away from the substrate, and an encapsulation structure layer 503 disposed on the side of the light-emitting structure layer 502 away from the substrate.

[0096] In an exemplary embodiment, the driving structure layer 501 of each sub-pixel may include a pixel driving circuit composed of multiple transistors and a storage capacitor. In an exemplary embodiment, the driving structure layer 501 may include: a first insulating layer disposed on a substrate, a semiconductor layer disposed on the first insulating layer, a second insulating layer covering the semiconductor layer, a first gate metal layer disposed on the second insulating layer, a third insulating layer covering the first gate metal layer, a second gate metal layer disposed on the third insulating layer, a fourth insulating layer covering the second gate metal layer, a source / drain metal layer disposed on the fourth insulating layer, and a planarization layer covering the source / drain metal layer. The semiconductor layer may include at least multiple transistors, the first gate metal layer may include at least the gate electrodes of multiple transistors and the first electrode of the storage capacitor, the second gate metal layer may include at least the second electrode of the storage capacitor, and the source / drain metal layer may include at least the first and second electrodes of multiple transistors.

[0097] In an exemplary embodiment, the light-emitting structure layer 502 of each sub-pixel may include a light-emitting device composed of multiple film layers. These multiple film layers may include an anode 21, a pixel definition layer 22, an organic light-emitting layer 23, and a cathode 24. The anode 21 is connected to the pixel driving circuit, the organic light-emitting layer 23 is connected to the anode 21, and the cathode 24 is connected to the organic light-emitting layer 23. The organic light-emitting layer 23 emits light of a corresponding color under the drive of the anode 21 and the cathode 24. The encapsulation structure layer 503 may include a first encapsulation layer 31, a second encapsulation layer 32, and a third encapsulation layer 33 stacked together. The first encapsulation layer 31 and the third encapsulation layer 33 may be made of inorganic materials, while the second encapsulation layer 32 may be made of organic materials. The second encapsulation layer 32 is disposed between the first encapsulation layer 31 and the third encapsulation layer 33 to prevent external moisture from entering the light-emitting structure layer 502.

[0098] In an exemplary embodiment, the display area may further include a touch structure layer, which may include: a buffer layer disposed on a third encapsulation layer, a first touch metal layer disposed on the buffer layer, a touch insulating layer covering the first touch metal layer, a second touch metal layer disposed on the touch insulating layer, and a touch protective layer covering the second touch metal layer.

[0099] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 5 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. (Example) Figure 5 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C, and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, first power supply line VSS, and second power supply line VDD).

[0100] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5, respectively. The second node N2 is connected to the second terminal of the first transistor, the first terminal of the second transistor T2, the control terminal of the third transistor T3, and the second terminal of the storage capacitor C, respectively. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively.

[0101] In an exemplary embodiment, the first end of the storage capacitor C is connected to the second power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0102] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3 to initialize the charge of the control electrode of the third transistor T3.

[0103] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to its second electrode.

[0104] The control electrode of the third transistor T3 is connected to the second node N2, meaning the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The third transistor T3 determines the amount of driving current flowing between the second power line VDD and the first power line VSS based on the potential difference between its control electrode and its first electrode.

[0105] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, scanning transistor, etc. When a conduction-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0106] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the second power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the second power supply line VDD and the first power supply line VSS.

[0107] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When a conduction level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0108] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the first power line VSS, where the signal of the first power line VSS is a low-level signal, and the signal of the second power line VDD is a continuously high-level signal. The first scan signal line S1 is the scan signal line in the pixel driving circuit of this display row, and the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of this display row and the first scan signal line S1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and realize a narrow bezel of the display panel.

[0109] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0110] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light emission signal line E, and the initial signal line INIT extend in the horizontal direction, while the first power line VSS, the second power line VDD, and the data signal line D extend in the vertical direction.

[0111] In an exemplary embodiment, the light-emitting device may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0112] Figure 6 This is a timing diagram of a pixel driving circuit. The following is a breakdown of the circuit's operation. Figure 5 The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Figure 5 The pixel driving circuit includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C, and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, second power supply line VDD, and first power supply line VSS). All 7 transistors are P-type transistors.

[0113] In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0114] In the first stage A1, also known as the reset stage, the signal on the second scan signal line S2 is low, while the signals on the first scan signal line S1 and the light-emitting signal line E are high. The low signal on the second scan signal line S2 turns on the first transistor T1, and the initial signal line INIT is supplied to the second node N2 to initialize the storage capacitor C, clearing the original data voltage in the capacitor. The high signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7; during this stage, the OLED does not emit light.

[0115] The second stage, A2, is called the data writing stage or threshold compensation stage. During this stage, the signal on the first scan signal line S1 is low, while the signals on the second scan signal line S2 and the light-emitting signal line E are high. The data signal line D outputs a data voltage. Because the second terminal of the storage capacitor C is low, the third transistor T3 is turned on. The low signal on the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The turn-on of the second transistor T2 and the fourth transistor T4 allows the data voltage output from the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second terminal of the storage capacitor C (second node N2) is Vd - |Vth|, where Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, providing the initial voltage of the initial signal line INIT to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light. The signal of the second scan signal line S2 is a high-level signal, causing the first transistor T1 to turn off. The signal of the light emission signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0116] The third stage, A3, is called the light-emitting stage. During this stage, the light-emitting signal line E is at a low level, while the first scan signal line S1 and the second scan signal line S2 are at a high level. The low level of the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the second power line VDD then provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0117] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0118] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0119] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the second power supply line VDD.

[0120] Long range uniformity (LRU) is an indicator that characterizes the difference in display brightness across different areas within a panel at 255 grayscale levels, and is a crucial parameter for evaluating display quality. LRU is commonly evaluated using the "9-point method" and the "135-point method." For example, the "9-point method" uses the ratio of the minimum to the maximum brightness values ​​at nine specified points on the panel to evaluate uniformity; the closer the ratio is to 1, the better the uniformity. LRU is positively correlated with the panel's RC loading; the higher the loading, the worse the uniformity. With the development of AMOLED, customers are placing increasingly stringent requirements on LRU, and with display products trending towards larger sizes, panel loading is constantly increasing. Therefore, effectively reducing panel loading is of paramount importance.

[0121] The voltage (VSS) required by the pixel driving circuits in display area 100 is introduced from the bonding pads in bonding area 200, passes through bonding area 200, enters bezel area 300, and is delivered to the first power line VSS of each pixel driving circuit through the ring-shaped power line in bezel area 300. Due to the impedance of the power lines, there is a voltage drop during signal transmission. Therefore, the voltage of the power lines farther from bonding area 200 is lower than the voltage of the power lines closer to bonding area 200. This voltage loss reduces the uniformity of display brightness in the display area, which has become a significant factor affecting high-quality display.

[0122] To improve the uniformity of display brightness, this disclosure provides a display substrate. On a plane perpendicular to the display substrate, the display substrate includes a source / drain metal layer on a substrate, an insulating layer on the source / drain metal layer, and a touch metal layer on the insulating layer. The source / drain metal layer includes a first trace, and the touch metal layer includes a second trace. The orthographic projection of the first trace on the substrate and the orthographic projection of the second trace on the substrate have an overlapping area. The first trace and the second trace form a double-layer trace structure.

[0123] In some exemplary embodiments, such as Figures 7a to 7g As shown, on a plane parallel to the display substrate, the display substrate includes a display area 100, a bonding area 200 located on one side of the display area 100, and a frame area 300 located on the other sides of the display area 100.

[0124] On a plane perpendicular to the display substrate, the display substrate includes a source / drain metal layer on the substrate 10, an insulating layer on the source / drain metal layer, and a touch metal layer on the insulating layer. The source / drain metal layer includes a first power line VSS, and the touch metal layer includes a first auxiliary power line 506. The first power line VSS is located in the bezel region 300 and the first fan-out region, and extends from the first fan-out region 211 to the bonding pin region 216. The first auxiliary power line 506 is located in the bezel region 300 and the first fan-out region 211. The orthographic projection of the first power line VSS on the substrate 10 overlaps with the orthographic projection of the first auxiliary power line 506 on the substrate 10. The first power line VSS and the first auxiliary power line 506 are electrically connected through a groove or via penetrating the insulating layer.

[0125] The display substrate of this disclosure reduces the wiring resistance by forming a double-layer wiring structure between the first power line VSS and the first auxiliary power line 506, thereby reducing the panel load and improving the panel uniformity.

[0126] In an exemplary embodiment, such as Figure 12a and Figure 12b As shown, the touch metal layer includes a first touch metal layer and a second touch metal layer. The first touch metal layer includes a connecting bridge 600, and the second touch metal layer includes a first electrode and a second electrode. The first electrode includes a plurality of first sub-electrodes 601 arranged along a first direction D1. Two adjacent first sub-electrodes 601 along the first direction D1 are electrically connected to a connecting bridge 600 through vias. The second electrode includes a plurality of second sub-electrodes 602 arranged along a second direction D2, and two adjacent second sub-electrodes 602 are interconnected along the second direction D2. The first direction D1 and the second direction D2 intersect.

[0127] In other exemplary embodiments, the connecting bridge 600 may also be disposed in the second touch metal layer, and the first electrode and the second electrode may be disposed in the first touch metal layer, which is not a limitation of this disclosure.

[0128] In an exemplary embodiment, the first electrode may be a driving electrode and the second electrode may be a sensing electrode; or, the first electrode may be a sensing electrode and the second electrode may be a driving electrode, and this disclosure does not limit this.

[0129] In an exemplary embodiment, both the first electrode and the second electrode are constructed using a metal mesh structure. In the exemplary embodiment, the metal mesh patterns of the first electrode and the second electrode are identical. This identical metal mesh pattern means that the metal traces of the metal mesh have the same orientation and line width.

[0130] In an exemplary embodiment, the first electrode and the second electrode may be made of at least one of copper (Cu), silver (Ag), aluminum (Al), titanium (Ti), or nickel (Ni), and this disclosure does not limit the materials used.

[0131] In this embodiment, a metal mesh is used as the touch electrode. Compared with indium tin oxide (ITO) in related technologies, metal materials have better ductility and are less prone to breakage, thus improving the bending performance of the touch display substrate and making it more suitable for flexible touch functionality. Additionally, it reduces costs. Furthermore, the first and second electrodes are disposed on the same layer and made of the same material, with identical patterns. This allows the substrate 10 to be covered with a metal mesh of the same pattern, which can improve the problem of poor anti-aliasing and optical moiré caused by interference between different layers of metal mesh due to differences in linewidth, resulting in a better anti-aliasing effect.

[0132] In an exemplary embodiment, the connecting bridge 600 may be a metal mesh structure, and the number of connecting bridges 600 is limited according to actual needs. This disclosure does not impose any limitation on this.

[0133] In this embodiment, a metal mesh is used as a connecting bridge. Compared with indium tin oxide (ITO) in related technologies, metal materials have better ductility and are less prone to breakage. Therefore, the bending performance of the touch display substrate can be improved, making the touch substrate more suitable for realizing flexible touch functions. In addition, it can also reduce costs and avoid the shadowing problem of using solid metal.

[0134] In an exemplary embodiment, such as Figure 7b and Figure 7e As shown, the first auxiliary power line 506 is disposed on the same layer as the first touch metal layer. An encapsulation structure layer 503 and a buffer layer 504 are disposed between the first touch metal layer and the source / drain metal layer. The first power line VSS and the first auxiliary power line 506 are electrically connected through grooves or vias penetrating the encapsulation structure layer 503 and the buffer layer 504. Figures 7b to 7e As shown, since the groove or via is located on the side of the isolation dam away from the display area, the encapsulation structure layer through which the groove or via penetrates includes a first encapsulation layer and a third encapsulation layer, which is an inorganic material / inorganic material stacked structure, excluding the second encapsulation layer.

[0135] In an exemplary embodiment, the groove includes a fourth groove (not shown in the figure), which penetrates the buffer layer 504 and the encapsulation structure layer 503; or, the via includes a sixth via (not shown in the figure), which penetrates the buffer layer 504 and the encapsulation structure layer 503.

[0136] In some exemplary embodiments, the border area 300 includes a first isolation dam 410 and a second isolation dam 420, both of which are disposed around the display area 100. The distance between the first isolation dam 410 and the display area 100 is less than the distance between the second isolation dam 420 and the display area 100.

[0137] In an exemplary embodiment, the orthographic projection of the fourth groove (or the sixth via) on the substrate 10 does not overlap with the orthographic projections of the first isolation dam and the second isolation dam on the substrate 10, and the distance between the fourth groove (or the sixth via) and the display area 100 is greater than the distance between the second isolation dam and the display area 100.

[0138] In an exemplary embodiment, such as Figure 7c and Figure 7f As shown, the first auxiliary power line 506 is disposed on the same layer as the second touch metal layer. An encapsulation structure layer 503, a buffer layer 504 and a touch insulation layer 505 are disposed between the second touch metal layer and the source / drain metal layer. The first power line VSS and the first auxiliary power line 506 are electrically connected through grooves or vias that penetrate the encapsulation structure layer 503, the buffer layer 504 and the touch insulation layer 505.

[0139] In an exemplary embodiment, the groove includes a first groove (not shown) and a third groove (not shown), the first groove penetrating the touch insulating layer 505 and the buffer layer 504, and the third groove penetrating the encapsulation structure layer 503; or, the via includes a third via (not shown) and a fifth via (not shown), the third via penetrating the touch insulating layer 505 and the buffer layer 504, and the fifth via penetrating the encapsulation structure layer 503.

[0140] In an exemplary embodiment, the orthographic projection of the first groove on the substrate 10 covers the orthographic projection of the third groove on the substrate 10; or, the orthographic projection of the third via on the substrate 10 covers the orthographic projection of the fifth via on the substrate 10.

[0141] In an exemplary embodiment, the orthographic projection of the first groove (or the third via) on the substrate 10 does not overlap with the orthographic projections of the first isolation dam 410 and the second isolation dam 420 on the substrate 10, and the distance between the first groove (or the third via) and the display area 100 is greater than the distance between the second isolation dam 420 and the display area 100.

[0142] In an exemplary embodiment, such as Figure 7d and Figure 7gAs shown, the first auxiliary power line 506 includes a first sub-trace 5061 and a second sub-trace 5062. The first sub-trace 5061 is disposed on the same layer as the first touch metal layer, and the second sub-trace 5062 is disposed on the same layer as the second touch metal layer. An encapsulation structure layer 503 and a buffer layer 504 are disposed between the first touch metal layer and the source / drain metal layer. A touch insulating layer 505 is disposed between the first touch metal layer and the second touch metal layer. The first power line VSS and the first sub-trace 5061 are electrically connected through a groove or via penetrating the encapsulation structure layer 503 and the buffer layer 504. The first sub-trace 5061 and the second sub-trace 5062 are electrically connected through a groove or via penetrating the touch insulating layer 505.

[0143] In an exemplary embodiment, the groove includes a fourth groove (not shown in the figure), which penetrates the buffer layer 504 and the encapsulation structure layer 503; or, the via includes a sixth via (not shown in the figure), which penetrates the buffer layer 504 and the encapsulation structure layer 503.

[0144] The groove also includes a fifth groove (not shown in the figure), which penetrates the touch insulating layer 505; or, the via includes a seventh via (not shown in the figure), which penetrates the touch insulating layer 505.

[0145] In an exemplary embodiment, the orthographic projection of the fourth groove (or the sixth via) on the substrate 10 does not overlap with the orthographic projections of the first isolation dam 410 and the second isolation dam 420 on the substrate 10, and the distance between the fourth groove (or the sixth via) and the display area 100 is greater than the distance between the second isolation dam 420 and the display area 100.

[0146] The orthographic projection of the fifth groove (or the seventh via) on the substrate 10 does not overlap with the orthographic projections of the first isolation dam and the second isolation dam on the substrate 10. The distance between the fifth groove (or the seventh via) and the display area 100 is greater than the distance between the second isolation dam and the display area 100.

[0147] In an exemplary embodiment, the orthographic projection of the fourth groove on the substrate 10 covers the orthographic projection of the fifth groove on the substrate 10; or, the orthographic projection of the sixth through hole on the substrate 10 covers the orthographic projection of the seventh through hole on the substrate 10.

[0148] In some exemplary embodiments, such as Figures 7b to 7d As shown, the orthographic projection of the first auxiliary power line 506 on the substrate 10 does not overlap with the orthographic projections of the first isolation dam 410 and the second isolation dam 420 on the substrate 10, and the distance between the first auxiliary power line 506 and the display area 100 is greater than the distance between the second isolation dam 420 and the display area 100.

[0149] In other exemplary embodiments, such as Figures 7e to 7gAs shown, the orthographic projection of the first auxiliary power line 506 on the substrate 10 covers the orthographic projections of the first isolation dam 410 and the second isolation dam 420 on the substrate 10.

[0150] In some exemplary embodiments, such as Figures 7b to 7g As shown, the source / drain metal layer includes a single-layer source / drain metal layer.

[0151] In some other exemplary embodiments, the source / drain metal layer includes a first source / drain metal layer and a second source / drain metal layer (not shown in the figure).

[0152] The first power line VSS can be disposed on the same layer as the first source / drain metal layer; or...

[0153] The first power line VSS can be placed on the same layer as the second source / drain metal layer; or...

[0154] The first power line VSS may include a third sub-trace and a fourth sub-trace. The third sub-trace is disposed on the same layer as the first source / drain metal layer, and the fourth sub-trace is disposed on the same layer as the second source / drain metal layer.

[0155] To improve the uniformity of display brightness, this disclosure also provides a display substrate, such as... Figure 7a , Figures 7h to 7j As shown, on a plane parallel to the display substrate, the display substrate includes a display area 100 and a bonding area 200 located on one side of the display area 100. The bonding area 200 includes a first fan-out area 211, a bending area 212, a driver chip area 215 and a bonding pin area 216 in sequence along a direction away from the display area 100.

[0156] On a plane perpendicular to the display substrate, the display substrate includes a source / drain metal layer on the substrate 10, an insulating layer on the source / drain metal layer, and a touch metal layer on the insulating layer. The source / drain metal layer includes a second power line VDD, and the touch metal layer includes a second auxiliary power line 507. The second power line VDD is located in the display area 100 and the first fan-out area 211, and extends from the first fan-out area 211 to the bonding pin area 216. The second auxiliary power line 507 is located in the bonding area 200 and on the side of the bending area 212 away from the display area 100. The orthographic projection of the second power line VDD on the substrate 10 and the orthographic projection of the second auxiliary power line 507 on the substrate 10 have an overlapping area.

[0157] The second power line VDD and the second auxiliary power line 507 are electrically connected through a groove or via that penetrates the insulation layer.

[0158] The display substrate of this disclosure reduces the wiring resistance by forming a double-layer wiring structure with the second power line VDD and the second auxiliary power line 507, thereby reducing the panel load and improving the panel uniformity.

[0159] In some exemplary embodiments, the display substrate may form a double-layer trace structure using only the first power line VSS and the first auxiliary power line 506; in other exemplary embodiments, the display substrate may form a double-layer trace structure using only the second power line VDD and the second auxiliary power line 507; in still other exemplary embodiments, the display substrate may form a double-layer trace structure using the first power line VSS and the first auxiliary power line 506, and the second power line VDD and the second auxiliary power line 507 may also form a double-layer trace structure, and this disclosure does not limit this.

[0160] In an exemplary embodiment, such as Figure 7h As shown, the second auxiliary power line 507 is disposed on the same layer as the first touch metal layer. A buffer layer 504 is disposed between the first touch metal layer and the source / drain metal layer. The second power line VDD and the second auxiliary power line 507 are electrically connected through a groove or via penetrating the buffer layer 504.

[0161] In an exemplary embodiment, such as Figure 7i As shown, the second auxiliary power line 507 is disposed on the same layer as the second touch metal layer. A buffer layer 504 and a touch insulation layer 505 are disposed between the second touch metal layer and the source / drain metal layer. The second power line VDD and the second auxiliary power line are electrically connected through a groove or via penetrating the buffer layer 504 and the touch insulation layer 505.

[0162] In an exemplary embodiment, such as Figure 7j As shown, the second auxiliary power line 507 includes a fifth sub-trace 5071 and a sixth sub-trace 5072. The fifth sub-trace 5071 is disposed on the same layer as the first touch metal layer, and the sixth sub-trace 5072 is disposed on the same layer as the second touch metal layer. A buffer layer 504 is disposed between the first touch metal layer and the source / drain metal layer. The second power line VDD and the fifth sub-trace 5071 are electrically connected through a groove or via penetrating the buffer layer 504. A touch insulation layer 505 is disposed between the second touch metal layer and the first touch metal layer. The fifth sub-trace 5071 and the sixth sub-trace 5072 are electrically connected through a groove or via penetrating the touch insulation layer 505.

[0163] In an exemplary embodiment, such as Figure 7a As shown, on the side of the bending area 212 away from the display area 100, the second power line VDD includes a first lateral connecting portion extending along the first direction D1 and a first longitudinal connecting portion extending along the second direction D2; the second auxiliary power line 507 includes a second lateral connecting portion extending along the first direction D1 and a second longitudinal connecting portion extending along the second direction D2.

[0164] Both the first lateral connecting portion and the second lateral connecting portion are disposed between the bending area 212 and the driving chip area 215. The orthographic projection of the first lateral connecting portion on the substrate 10 and the orthographic projection of the second lateral connecting portion on the substrate 10 have an overlapping area.

[0165] There is an overlapping area between the orthographic projection of the first longitudinal connecting part on the base 10 and the orthographic projection of the second longitudinal connecting part on the base 10.

[0166] In an exemplary embodiment, the first longitudinal connecting portion includes a plurality of first branches and a plurality of second branches. The first branches extend from the end of the first transverse connecting portion along the first direction D1 to the bonding pin area 216. The second branches extend from the first transverse connecting portion to the display area. The second longitudinal connecting portion extends from the end of the second transverse connecting portion along the first direction D1 to the bonding pin area 216. The orthographic projection of the first branch on the substrate 10 and the orthographic projection of the second longitudinal connecting portion on the substrate 10 have an overlapping area.

[0167] In an exemplary embodiment, the source / drain metal layer includes a first source / drain metal layer and a second source / drain metal layer;

[0168] The second power line VDD can be placed on the same layer as the first source / drain metal layer; or...

[0169] The second power line VDD can be placed on the same layer as the second source / drain metal layer; or...

[0170] The second power line VDD may include a seventh sub-trace and an eighth sub-trace. The seventh sub-trace is disposed on the same layer as the first source / drain metal layer, and the eighth sub-trace is disposed on the same layer as the second source / drain metal layer.

[0171] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0172] In an exemplary embodiment, the display substrate includes a display area 100 and a non-display area surrounding the display area 100. The non-display area may include a bonding area 200 on one side of the display area 100 and a border area 300 on other sides of the display area 100. The fabrication process of the display substrate may include the following operations.

[0173] (1) A driving structure layer and a light-emitting structure layer pattern are sequentially formed on a substrate. In an exemplary embodiment, the driving structure layer includes multiple gate lines and multiple data lines, which intersect vertically to define multiple matrix-arranged pixel units. Each pixel unit includes at least three sub-pixels, and each sub-pixel includes one or more thin-film transistors (TFTs). In this embodiment, a pixel unit may include three sub-pixels, namely a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Of course, this embodiment is also applicable to the case where a pixel unit includes four sub-pixels (red sub-pixel R, green sub-pixel G, blue sub-pixel B, and white sub-pixel W).

[0174] In an exemplary embodiment, the fabrication process of the driving structure layer may include:

[0175] A first insulating film and a semiconductor film are sequentially deposited on a substrate. The semiconductor film is patterned using a patterning process to form a first insulating layer covering the entire substrate, and a semiconductor layer pattern disposed on the first insulating layer. The semiconductor layer pattern includes at least a first active layer.

[0176] Subsequently, a second insulating film and a first metal film are deposited sequentially. The first metal film is patterned using a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first gate metal layer pattern disposed on the second insulating layer. The first gate metal layer pattern includes at least a first gate electrode and a first capacitor electrode.

[0177] Subsequently, a third insulating film and a second metal film are deposited sequentially. The second metal film is patterned using a patterning process to form a third insulating layer covering the first gate metal layer, and a second gate metal layer pattern disposed on the third insulating layer. The second gate metal layer pattern includes at least a second capacitor electrode, and the position of the second capacitor electrode corresponds to the position of the first capacitor electrode.

[0178] Subsequently, a fourth insulating film is deposited, and multiple first via patterns are formed through a patterning process. The fourth, third, and second insulating layers within the first vias are etched away, exposing the two ends of the first active layer.

[0179] Subsequently, a third metal thin film is deposited and patterned using a patterning process to form a source / drain metal layer pattern on the fourth insulating layer. This source / drain metal layer pattern may include a first source electrode and a first drain electrode, a first power line VSS, and a second power line VDD. The first power line VSS is located in the bezel area and surrounds the display area. The second power line VDD is located in the display area and is electrically connected to multiple sub-pixels. The first power line VSS and the second power line VDD are led to a bonding area and connected to corresponding bonding pins. The first power line VSS and the second power line VDD are configured to connect to a low-voltage signal and a high-voltage signal, respectively. The first source electrode and the first drain electrode are connected to the first active layer through first vias. In an exemplary embodiment, the source / drain metal layer may further include multiple bonding pins (FPC on PlasticPad, FOP Pad) located in the bonding pin region 216, multiple driver chip pins (Chip on Plastic Pad, COPPad) located in the driver chip region 215, and input / output traces located between the bonding pin region 216 and the driver chip region 215 (since these input / output traces are located in the Outer Lead Bonding (OLB) region on the display substrate, these input / output traces may also be referred to as OLB traces), etc. The multiple bonding pins include at least a first bonding power pin and a second bonding power pin. The first bonding power pin is electrically connected to a first power line VSS, and the second bonding power pin is electrically connected to a second power line VDD. In some other exemplary embodiments, both the bonding pins and the driver chip pins may be formed by multiple metal film layers. The multiple metal film layers may include a gate metal layer (a first gate metal layer and / or a second gate metal layer), a source / drain metal layer, etc. (a first source / drain metal layer and / or a second source / drain metal layer). The display substrate of this embodiment is illustrated by taking a structure in which the source and drain metal layers consist of only one layer as an example. In other exemplary embodiments, the source and drain metal layers may also include a two-layer structure of a first source and drain metal layer and a second source and drain metal layer. In this case, the first power line VSS and the second power line VDD may be located in the first source and drain metal layer, or in the second source and drain metal layer, or in both the first source and drain metal layer and the second source and drain metal layer, thus forming a double-layer trace.

[0180] Subsequently, a planarization film is coated and patterned using a patterning process to form a planarization layer PLN. A second via, a partition, and a first dam pattern are formed on the planarization layer. The planarization layer within the second via is removed, exposing the surface of the first drain electrode of the first transistor. The planarization layer within the partition is removed, exposing the surface of the first power line VSS. The first dam is formed on the first power line VSS within the partition.

[0181] At this point, the driving structure layer pattern is complete on the substrate. In an exemplary embodiment, the first active layer, the first gate electrode, the first source electrode, and the first drain electrode constitute a thin-film transistor, and the first capacitor electrode and the second capacitor electrode constitute a storage capacitor. The thin-film transistor can be a bottom-gate structure or a top-gate structure, and can be an amorphous silicon (a-Si) thin-film transistor, a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor; no limitation is made herein.

[0182] In an exemplary embodiment, the fabrication process of the light-emitting structure layer may include:

[0183] A transparent conductive film is deposited on the substrate on which the aforementioned pattern is formed. The transparent conductive film is then patterned using a patterning process to form an anode pattern. The anode of each sub-pixel is connected to the drain electrode of the thin-film transistor in that sub-pixel through a second via on the planarization layer.

[0184] Subsequently, a pixel definition film is coated on the substrate on which the aforementioned pattern is formed, and the pixel definition film is patterned by a patterning process to form a pixel definition (PDL) layer and a second dam foundation pattern.

[0185] Subsequently, an organic material film is coated on the substrate forming the aforementioned pattern, and a masking, exposure, and development process is used to form a PS (isolation pillar) pattern. The first dam base, the second dam base, and the PS form an isolation dam (DAM), which surrounds the display area. The isolation dam may include a first isolation dam 410 and a second isolation dam 420, wherein the distance between the first isolation dam 410 and the display area 100 is smaller than the distance between the second isolation dam 420 and the display area 100.

[0186] Subsequently, an organic light-emitting layer and a cathode are sequentially formed on the substrate forming the aforementioned pattern. The organic light-emitting layer is formed within the pixel opening of the display area, thereby connecting the organic light-emitting layer to the anode. The organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), wherein the hole transport layer (HTL), the emissive layer (EML), the electron transport layer (ETL), and the electron injection layer (EIL) are sequentially disposed on the hole injection layer.

[0187] At this point, the luminescent structure layer pattern has been successfully fabricated on the substrate, as follows: Figure 8a , Figure 8b and Figure 8c As shown, Figure 8b for Figure 8a A sectional view of region AA' in the middle. Figure 8c for Figure 8aA cross-sectional view of region BB', where 11 is a composite insulating layer, which may include a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer stacked on the substrate 10. Since the organic light-emitting layer is connected to the anode, and the anode is connected to the drain electrode of the thin-film transistor, the connection between the organic light-emitting layer and the drain electrode of the thin-film transistor is achieved.

[0188] (2) A pattern of encapsulation structure layer 503 is formed on the surface of the light-emitting structure layer away from the substrate, such as... Figure 9 As shown. In the circuit area of ​​the display area and the bezel area, the encapsulation structure layer 503 includes a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, forming an inorganic / organic / inorganic material stacked structure. In the isolation dam area of ​​the bezel area (i.e., the area where the first power line VSS is located), the encapsulation structure layer includes a first encapsulation layer and a third encapsulation layer stacked together, forming an inorganic / inorganic material stacked structure, which can further ensure the integrity of the encapsulation and effectively isolate external water and oxygen. The bonding area 200 does not have an encapsulation structure layer pattern.

[0189] In an exemplary embodiment, the first and third encapsulation layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers, ensuring that external water and oxygen cannot enter the light-emitting structure layer. The second encapsulation layer can be made of organic materials, such as resin, to encapsulate the various film layers of the display substrate, thereby improving structural stability and flatness.

[0190] (3) On the surface of the encapsulation structure layer 503 away from the substrate, a buffer layer 504 and a first touch metal layer pattern are formed in sequence. The material of the buffer layer 504 can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON). The first touch metal layer may include multiple spaced connecting bridges (not shown in the figure) and a first touch lead (not shown in the figure).

[0191] In an exemplary embodiment, forming the first touch metal layer pattern may include: depositing a first conductive film on a substrate, coating a layer of photoresist on the first conductive film, exposing and developing the photoresist using a mask, forming unexposed areas with photoresist at the locations of the connecting bridges and touch lead patterns, forming fully exposed areas at other locations, removing the photoresist, etching the conductive film in the fully exposed areas, and stripping off the remaining photoresist to form the first touch metal layer pattern. The first conductive film may be a metallic material or a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), carbon nanotubes, or graphene.

[0192] (3) A touch insulating layer (TLD) 505 pattern is formed on the surface of the first touch metal layer away from the substrate 10, such as... Figure 10a , Figure 10b and Figure 10c As shown, Figure 10b for Figure 10a A sectional view of region AA' in the middle. Figure 10c for Figure 10a In the cross-sectional view of the BB' region, the touch insulating layer 505 may include an eighth via (not shown in the figure) and a ninth via (not shown in the figure). The eighth via is located at both ends of the connecting bridge. The touch insulating layer in the eighth via is etched away to expose both ends of the connecting bridge. The first sub-electrode formed subsequently is electrically connected to the connecting bridge through this via. The ninth via is located in the region where the first touch lead is located. The touch insulating layer in the ninth via is etched away to expose the first touch lead, which is used to form a double-layer touch trace with the second touch lead formed subsequently.

[0193] In an exemplary embodiment, the touch insulating layer 505 may further include a first groove H1, which is located in the first fan-out area of ​​the border region 300 and the bonding region 200. The orthographic projection of the first groove H1 on the substrate overlaps with the orthographic projection of the first power line VSS on the substrate. The orthographic projection of the first groove H1 on the substrate does not overlap with the orthographic projections of the first isolation dam 410 and the second isolation dam 420 on the substrate. The distance between the first groove H1 and the display area is greater than the distance between the second isolation dam 420 and the display area. The touch insulating layer and the buffer layer within the first groove H1 are etched away, exposing the surface of the encapsulation structure layer (due to over-etching, a portion of the encapsulation structure layer may be etched away).

[0194] In other exemplary embodiments, the first groove H1 may also be replaced by a plurality of discontinuous third vias (not shown in the figure). That is, the third vias are located in the first fan-out area of ​​the border area 300 and the bonding area 200. The orthographic projection of the third via on the substrate overlaps with the orthographic projection of the first power line VSS on the substrate. The orthographic projection of the third via on the substrate does not overlap with the orthographic projections of the first isolation dam 410 and the second isolation dam 420 on the substrate. The distance between the third via and the display area is greater than the distance between the second isolation dam 420 and the display area. The touch insulating layer and buffer layer inside the third via are etched away, exposing the surface of the encapsulation structure layer (due to over-etching, a portion of the encapsulation structure layer may be etched away).

[0195] In an exemplary embodiment, the touch insulating layer 505 may further include a second groove H2, which is located in the bonding region 200 and on the side of the bending region 212 away from the display region 100. The orthographic projection of the second groove H2 on the substrate overlaps with the orthographic projection of the second power line VDD on the substrate. The touch insulating layer and buffer layer in the second groove H2 are etched away to expose the surface of the second power line VDD.

[0196] In some other exemplary embodiments, the second groove H2 may also be replaced by a plurality of discontinuous fourth vias (not shown in the figure), that is, the fourth vias are located in the bonding area 200, the fourth vias are located on the side of the bending area 212 away from the display area 100, the orthographic projection of the fourth vias on the substrate overlaps with the orthographic projection of the second power line VDD on the substrate, the touch insulating layer and buffer layer in the fourth vias are etched away, exposing the surface of the second power line VDD.

[0197] (4) A third groove H3 is formed on the packaging structure layer through a patterning process. The orthographic projection of the third groove H3 onto the substrate is within the range of the orthographic projection of the first groove H1 onto the substrate. The packaging structure layer within the third groove H3 is etched away, exposing the surface of the first power line VSS, such as... Figure 11a and Figure 11b As shown, Figure 11b for Figure 11a A cross-sectional view of region AA' in the middle.

[0198] In some other exemplary embodiments, the third groove H3 may also be replaced by a plurality of discontinuous fifth vias (not shown in the figure), that is, the fifth vias are located in the first fan-out area of ​​the border area 300 and the bonding area 200, the orthographic projection of the fifth vias on the substrate is within the range of the orthographic projection of the first groove H1 (or the third vias) on the substrate, and the packaging structure layer in the fifth vias is etched away to expose the surface of the first power line VSS.

[0199] (5) A second touch metal layer pattern is formed on the surface of the touch insulating layer 505 away from the substrate, such as... Figures 12a to 12d As shown, the second touch metal layer may include patterns such as a first electrode, a second electrode, and a second touch lead 603. The first electrode includes a plurality of first sub-electrodes 601 arranged along a first direction D1. Two adjacent first sub-electrodes 601 along the first direction D1 are electrically connected to a connecting bridge 600 through an eighth via. The second electrode includes a plurality of second sub-electrodes 602 arranged along a second direction D2. Two adjacent second sub-electrodes 602 are interconnected along the second direction D2. The first direction D1 and the second direction D2 intersect.

[0200] In this embodiment, both the first direction D1 and the second direction D2 are perpendicular to the thickness direction of the encapsulation structure layer. This application does not limit the size of the angle between the first direction D1 and the second direction D2; for example, they can be perpendicular.

[0201] In this embodiment, both the first sub-electrode 601 and the second sub-electrode 602 are in the form of a mesh structure, with at least one sub-pixel disposed within the mesh, and both the first sub-electrode 601 and the second sub-electrode 602 are made of metallic materials. Because metallic materials have low resistance, good conductivity, and high sensitivity, they can avoid transmission delays of electrical signals in the first sub-electrode 601 and the second sub-electrode 602, thus improving the touch response. The mesh structure can have a regular polygonal or an irregular polygonal shape.

[0202] In an exemplary embodiment, the second touch metal layer may further include a first auxiliary power line 506. The first auxiliary power line 506 is located in the first fan-out area of ​​the frame area 300 and the bonding area 200. The orthographic projection of the first auxiliary power line 506 on the substrate overlaps with the orthographic projection of the first power line VSS on the substrate. The orthographic projection of the first auxiliary power line 506 on the substrate does not overlap with the orthographic projections of the first isolation dam 410 and the second isolation dam 420 on the substrate. The distance between the first auxiliary power line 506 and the display area is greater than the distance between the second isolation dam 420 and the display area. The first auxiliary power line 506 is electrically connected to the first power line VSS through the first groove H1 (or the third via) and the third groove H3 (or the fifth via).

[0203] In an exemplary embodiment, the second touch metal layer may further include a second auxiliary power line 507. The second auxiliary power line 507 is located in the bonding area 200. The second auxiliary power line 507 is located on the side of the bending area 212 away from the display area 100. The orthographic projection of the second auxiliary power line 507 on the substrate overlaps with the orthographic projection of the second power line VDD on the substrate. The second auxiliary power line 507 is electrically connected to the second power line VDD through the second groove H2.

[0204] (5) A protective layer 508 pattern is formed on the surface of the second touch metal layer on the side away from the substrate, such as... Figure 7c and Figure 7i As shown. The protective layer can be made of materials such as polyimide (PI), and mainly serves to insulate and protect the touch electrodes and peripheral traces.

[0205] In an exemplary embodiment, the fabrication process of the flexible display substrate may further include processes such as peeling off the substrate, attaching the back film, and cutting, which are not limited herein.

[0206] As can be seen from the structure and fabrication process of the display substrate in the exemplary embodiments of this disclosure, by forming a first groove H1, a third groove H3, and a first auxiliary power line 506, the first power line VSS and the first auxiliary power line 506 form a double-layer wiring structure, reducing wiring resistance and thus reducing panel loading, thereby improving panel uniformity. Furthermore, by forming a second groove H2 and a second auxiliary power line 507, the second power line VDD and the second auxiliary power line 507 also form a double-layer wiring structure, further reducing wiring resistance and thus reducing panel loading, thereby improving panel uniformity. The fabrication process of the display substrate in the exemplary embodiments of this disclosure has good process compatibility, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0207] The structure of the display substrate and its fabrication process as described in this exemplary embodiment are merely illustrative. In the exemplary embodiments, the corresponding structure and the patterning process may be modified or reduced as needed, and this disclosure does not limit the scope of the invention.

[0208] Figure 13a This is a schematic diagram of the structure of another display substrate as an exemplary embodiment of the present disclosure. Figures 13b to 13e for Figure 13a Several cross-sectional views of the C-C' region are shown. In an exemplary embodiment, the display substrate includes a display area and a bonding area located on one side of the display area. The bonding area includes a driver chip area 215 and a bonding pin area 216, and an input / output trace 217 located between the driver chip area 215 and the bonding pin area 216. The driver chip area 215 includes a driver chip pin 2151, the bonding pin area 216 includes a bonding pin 2161, and the input / output trace 217 connects the driver chip pin 2151 and the bonding pin 2161.

[0209] The input / output trace 217 includes a first input / output trace 2171 and a second input / output trace 2172. The orthographic projection of the first input / output trace 2171 on the substrate 10 and the orthographic projection of the second input / output trace 2172 on the substrate 10 have an overlapping area.

[0210] On a plane perpendicular to the display substrate, the display substrate includes a source / drain metal layer and a touch metal layer located on the substrate 10. The first input / output trace 2171 is disposed on the same layer as the source / drain metal layer, and the second input / output trace 2172 is disposed on the same layer as the touch metal layer.

[0211] The exemplary embodiments of this disclosure reduce the trace resistance by forming a double-layer trace structure with the first input / output trace 2171 and the second input / output trace 2172, thereby reducing the panel load and improving panel uniformity.

[0212] In some exemplary implementations, such as Figure 13b As shown, the second input / output trace 2172 is disposed on the same layer as the first touch metal layer, and the first input / output trace 2171 and the second input / output trace 2172 are electrically connected through a groove or via penetrating the buffer layer 504.

[0213] In other exemplary embodiments, such as Figure 13c As shown, the second input / output trace 2172 is disposed on the same layer as the second touch metal layer, and the first input / output trace 2171 and the second input / output trace 2172 are electrically connected through a groove or via penetrating the buffer layer 504 and the touch insulating layer 505.

[0214] In some other exemplary embodiments, such as Figure 13d As shown, the second input / output trace 2172 includes a ninth sub-trace 21721 and a tenth sub-trace 21722. The ninth sub-trace 21721 is disposed on the same layer as the first touch metal layer, and the tenth sub-trace 21722 is disposed on the same layer as the second touch metal layer. The first input / output trace 2171 and the ninth sub-trace 21721 are electrically connected through a groove or via penetrating the buffer layer 504, and the ninth sub-trace 21721 and the tenth sub-trace 21722 are electrically connected through a groove or via penetrating the touch insulating layer 505.

[0215] In some other exemplary embodiments, such as Figure 13e As shown, an insulating layer is included between the source / drain metal layer and the touch metal layer. The first input / output trace 2171 and the second input / output trace 2172 are isolated by the insulating layer and electrically connected through the driver chip pin 2151 and the bonding pin 2161. Since both the driver chip pin 2151 and the bonding pin 2161 have touch metal layer films, the planarization layer PLN, buffer layer 504, touch insulating layer 505, and other films can be left on the first input / output trace 2171. That is, the first input / output trace 2171 and the second input / output trace 2172 are isolated by the insulating layer and electrically connected through the driver chip pin 2151 and the bonding pin 2161.

[0216] In some other exemplary embodiments, the source / drain metal layer includes a first source / drain metal layer and a second source / drain metal layer (not shown in the figure);

[0217] The first input / output traces are configured on the same layer as the first source / drain metal layer; or...

[0218] The first input / output traces are placed on the same layer as the second source / drain metal layer; or...

[0219] The first input / output trace includes an eleventh sub-trace and a twelfth sub-trace. The eleventh sub-trace is set on the same layer as the first source / drain metal layer, and the twelfth sub-trace is set on the same layer as the second source / drain metal layer.

[0220] This disclosure also provides an exemplary embodiment of a method for preparing a display substrate.

[0221] A source / drain metal layer is formed, the source / drain metal layer including a first trace;

[0222] An insulating layer is formed on the source / drain metal layer;

[0223] A touch metal layer is formed on the insulating layer. The touch metal layer includes a second trace. The orthographic projection of the first trace on the substrate and the orthographic projection of the second trace on the substrate have an overlapping area. The first trace and the second trace form a double-layer trace structure.

[0224] In an exemplary embodiment, the display substrate includes a display area, a bonding area located on one side of the display area, and a border area located on other sides of the display area. The bonding area includes a first fan-out area and a bonding pin area. The fabrication method includes:

[0225] A source / drain metal layer is formed, the source / drain metal layer including a first power line, the first power line being located in the border region and the first fan-out region, and extending from the first fan-out region to the bonding pin region;

[0226] An insulating layer is formed on the source / drain metal layer, and a groove or via is formed on the insulating layer that penetrates the insulating layer, the groove or via exposing the first power line;

[0227] A touch metal layer is formed on the insulating layer. The touch metal layer includes a first auxiliary power line located in the frame area and the first fan-out area. The orthographic projection of the first power line on the substrate overlaps with the orthographic projection of the first auxiliary power line on the substrate. The first power line and the first auxiliary power line are electrically connected through the groove or via.

[0228] In an exemplary embodiment, the display substrate includes a display area and a bonding area located on one side of the display area. The bonding area, along a direction away from the display area, sequentially includes a first fan-out area, a bending area, a driver chip area, and a bonding pin area. The fabrication method includes:

[0229] A source / drain metal layer is formed, the source / drain metal layer including a second power line, the second power line being located in the display area and the first fan-out area, and extending from the first fan-out area to the bonding pin area;

[0230] An insulating layer is formed on the source / drain metal layer, and a groove or via is formed on the insulating layer that penetrates the insulating layer, the groove or via exposing the second power line;

[0231] A touch metal layer is formed on the insulating layer. The touch metal layer includes a second auxiliary power line. The second auxiliary power line is located in the bonding area and on the side of the bending area away from the display area. The orthographic projection of the second power line on the substrate overlaps with the orthographic projection of the second auxiliary power line on the substrate. The second power line and the second auxiliary power line are electrically connected through the groove or via.

[0232] In an exemplary embodiment, the display substrate includes a display area and a bonding area located on one side of the display area; the bonding area includes a driver chip area and a bonding pin area; the driver chip area includes driver chip pins, and the bonding pin area includes bonding pins; the fabrication method includes:

[0233] A source / drain metal layer is formed, the source / drain metal layer includes a first input / output trace, the first input / output trace is located between the driver chip area and the bonding pin area, and the first input / output trace connects the driver chip pin and the bonding pin;

[0234] An insulating layer is formed on the source / drain metal layer;

[0235] A touch metal layer is formed on the insulating layer. The touch metal layer includes a second input / output trace. The orthographic projection of the first input / output trace on the substrate and the orthographic projection of the second input / output trace on the substrate have an overlapping area.

[0236] This disclosure also provides a display device, including the display panel of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0237] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit the invention. Any person skilled in the art may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope of this disclosure; however, the patent protection scope of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, the display substrate comprising a display area and a bonding area located on one side of the display area, the bonding area comprising, in sequence along a direction away from the display area, a first fan-out area, a bending area, a driver chip area, and a bonding pin area; on a plane perpendicular to the display substrate, the display substrate comprising a source / drain metal layer on a substrate, an insulating layer on the source / drain metal layer, and a touch metal layer on the insulating layer, the source / drain metal layer comprising a first trace, the touch metal layer comprising a second trace, the orthographic projection of the first trace on the substrate and the orthographic projection of the second trace on the substrate having an overlapping area, the first trace and the second trace forming a double-layer trace structure; in, The first trace includes a second power line, the second trace includes a second auxiliary power line, the second power line is located in the display area and the first fan-out area, and extends from the first fan-out area to the bonding pin area, the second auxiliary power line is located in the bonding area and is located on the side of the bending area away from the display area, and there is an overlapping area between the orthographic projection of the second power line on the substrate and the orthographic projection of the second auxiliary power line on the substrate; The touch metal layer includes a first touch metal layer and a second touch metal layer. The second auxiliary power line includes a fifth sub-trace and a sixth sub-trace. The fifth sub-trace is disposed in the same layer as the first touch metal layer, and the sixth sub-trace is disposed in the same layer as the second touch metal layer. A buffer layer is disposed between the first touch metal layer and the source / drain metal layer. The second power line and the fifth sub-trace are electrically connected through a groove or via penetrating the buffer layer. A touch insulating layer is disposed between the second touch metal layer and the first touch metal layer. The fifth sub-trace and the sixth sub-trace are electrically connected through a groove or via penetrating the touch insulating layer.

2. The display substrate according to claim 1, wherein, The display substrate also includes a border area located on other sides of the display area; The first trace includes a first power line, and the second trace includes a first auxiliary power line. The first power line is located in the frame area and the first fan-out area, and extends from the first fan-out area to the bonding pin area. The first auxiliary power line is located in the frame area and the first fan-out area. The orthographic projection of the first power line on the substrate and the orthographic projection of the first auxiliary power line on the substrate have an overlapping area. The first power line and the first auxiliary power line are electrically connected through a groove or through-hole penetrating the insulation layer.

3. The display substrate according to claim 2, wherein, The first auxiliary power line is disposed on the same layer as the first touch metal layer; or... The first auxiliary power line is disposed on the same layer as the second touch metal layer; or... The first auxiliary power line includes a first sub-trace and a second sub-trace. The first sub-trace is disposed on the same layer as the first touch metal layer, and the second sub-trace is disposed on the same layer as the second touch metal layer.

4. The display substrate according to claim 2, wherein, The border area includes at least one isolation dam, which is disposed around the display area; The orthographic projection of the first auxiliary power line on the substrate does not overlap with the orthographic projection of the isolation dam on the substrate, and the distance between the first auxiliary power line and the display area is greater than the distance between the isolation dam and the display area.

5. The display substrate according to claim 2, wherein, The border area includes at least one isolation dam, which is disposed around the display area; The orthographic projection of the first auxiliary power line on the substrate at least partially covers the orthographic projection of the isolation dam on the substrate.

6. The display substrate according to claim 2, wherein, The insulating layer includes an encapsulation structure layer, a buffer layer, and a touch insulating layer; the groove includes a first groove and a third groove, the first groove penetrating the touch insulating layer and the buffer layer, and the third groove penetrating the encapsulation structure layer.

7. The display substrate according to claim 6, wherein, The orthographic projection of the first groove on the substrate covers the orthographic projection of the third groove on the substrate.

8. The display substrate according to any one of claims 2 to 7, wherein, The source / drain metal layer includes a first source / drain metal layer and a second source / drain metal layer; The first power line is disposed on the same layer as the first source / drain metal layer; or... The first power line is disposed on the same layer as the second source / drain metal layer; or... The first power line includes a third sub-trace and a fourth sub-trace. The third sub-trace is disposed in the same layer as the first source / drain metal layer, and the fourth sub-trace is disposed in the same layer as the second source / drain metal layer.

9. The display substrate according to claim 1, wherein, In the bonding area, the second power cable includes a first lateral connecting portion extending along a first direction and a first longitudinal connecting portion extending along a second direction; the second auxiliary power cable includes a second lateral connecting portion extending along the first direction and a second longitudinal connecting portion extending along the second direction. Both the first lateral connecting portion and the second lateral connecting portion are disposed between the bending area and the driving chip area. The orthographic projection of the first lateral connecting portion on the substrate and the orthographic projection of the second lateral connecting portion on the substrate overlap in an area; the orthographic projection of the first longitudinal connecting portion on the substrate and the orthographic projection of the second longitudinal connecting portion on the substrate also overlap in an area.

10. The display substrate according to claim 9, wherein, The first vertical connecting portion includes a plurality of first branches and a plurality of second branches. The first branches extend from the end of the first horizontal connecting portion along the first direction to the bonding pin area. The second branches extend from the first horizontal connecting portion to the display area. The second vertical connecting portion extends from the end of the second horizontal connecting portion along the first direction to the bonding pin area. The orthographic projection of the first branch on the substrate and the orthographic projection of the second vertical connecting portion on the substrate have an overlapping area.

11. The display substrate according to claim 9 or 10, wherein, The source / drain metal layer includes a first source / drain metal layer and a second source / drain metal layer; The second power line is disposed in the same layer as the first source / drain metal layer; or, The second power line is disposed in the same layer as the second source / drain metal layer; or, The second power line includes a seventh sub-trace and an eighth sub-trace. The seventh sub-trace is disposed in the same layer as the first source / drain metal layer, and the eighth sub-trace is disposed in the same layer as the second source / drain metal layer.

12. The display substrate according to claim 1, wherein, The bonding area includes a driver chip area and a bonding pin area, as well as input / output traces located between the driver chip area and the bonding pin area; the driver chip area includes driver chip pins, the bonding pin area includes bonding pins, and the input / output traces connect the driver chip pins and the bonding pins. The first trace includes a first input / output trace, and the second trace includes a second input / output trace. The orthographic projections of the first input / output trace on the substrate and the orthographic projections of the second input / output trace on the substrate have an overlapping area.

13. The display substrate according to claim 12, wherein, The second input / output traces are disposed on the same layer as the first touch metal layer; or... The second input / output traces are disposed on the same layer as the second touch metal layer; or... The second input / output trace includes a ninth sub-trace and a tenth sub-trace. The ninth sub-trace is disposed on the same layer as the first touch metal layer, and the tenth sub-trace is disposed on the same layer as the second touch metal layer.

14. The display substrate according to claim 12, wherein, An insulating layer is included between the source / drain metal layer and the touch metal layer, and the first input / output trace and the second input / output trace are electrically connected through a groove or via penetrating the insulating layer.

15. The display substrate according to claim 12, wherein, An insulating layer is included between the source / drain metal layer and the touch metal layer. The first input / output trace and the second input / output trace are isolated by the insulating layer and electrically connected through the driver chip pin and the bonding pin.

16. The display substrate according to any one of claims 12 to 15, wherein, The source / drain metal layer includes a first source / drain metal layer and a second source / drain metal layer; The first input / output traces are disposed on the same layer as the first source / drain metal layer; or... The first input / output traces are disposed on the same layer as the second source / drain metal layer; or... The first input / output trace includes an eleventh sub-trace and a twelfth sub-trace. The eleventh sub-trace is disposed on the same layer as the first source / drain metal layer, and the twelfth sub-trace is disposed on the same layer as the second source / drain metal layer.

17. A display device comprising a display substrate as described in any one of claims 1 to 16.

18. A method for preparing a display substrate, used to prepare a display substrate as described in any one of claims 1 to 16, comprising: A source / drain metal layer is formed, the source / drain metal layer including a first trace; An insulating layer is formed on the source / drain metal layer; A touch metal layer is formed on the insulating layer. The touch metal layer includes a second trace. The orthographic projection of the first trace on the substrate and the orthographic projection of the second trace on the substrate have an overlapping area. The first trace and the second trace form a double-layer trace structure.

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