Galvanic isolation using isolation breaks between electrodes in the redistribution layer

Abstract

The present disclosure relates to current isolation using an isolation break between redistribution layer electrodes. A structure includes: current isolation including a horizontal portion, the horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer and a second RDL electrode in the first insulator layer that is laterally spaced apart from the first RDL electrode. The isolation break includes a trench in the first insulator layer defined between the first RDL electrode and the second RDL electrode and at least one second insulator layer located in the trench. The first insulator layer and the second insulator layer are located between the first RDL electrode and the second RDL electrode. The isolation can separate voltage domains having different voltage levels, for example. A related method is also disclosed. The isolation can also include a vertical portion using the first RDL electrode and another electrode in a metal layer, the other electrode being separated from the first RDL electrode by multiple interconnecting dielectric layers.

Description

Technical Field

[0001] The present disclosure relates to integrated circuits, and more particularly to structures having galvanic isolation including isolation breaks between redistribution layer electrodes and related methods. Background Art

[0002] Galvanic isolation is the process of preventing a first circuit from electrically communicating direct current (DC) and unwanted alternating current (AC) with a second circuit, but allowing the two circuits to communicate through other mechanisms such as optical devices, inductors, capacitors, or other means. The two circuits are typically at different voltages, for example, a high voltage and a low voltage. Galvanic isolation is created by forming a parallel plate capacitor using electrodes located in different metallization layers of an integrated circuit (for example, different metallization layers in the back-end of line (BEOL) interconnect layer). The dielectric of the BEOL layer separates the electrodes to form the capacitor. For higher voltage applications, the thickness of the BEOL dielectric layer or the number of BEOL dielectric layers is increased to provide a higher breakdown voltage. As device voltages increase, for example, into the kilovolt range, the space available to increase the dielectric thickness or increase the number of dielectric layers to create reliable and robust galvanic isolation becomes limited. Summary of the Invention

[0003] One aspect of the present disclosure relates to a structure comprising: current isolation including a horizontal portion, the horizontal portion comprising: a first redistribution layer (RDL) electrode in a first insulator layer; a second RDL electrode in the first insulator layer that is laterally spaced apart from the first RDL electrode; and an isolation break, which comprises a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode and at least one second insulator layer located in the trench, wherein the first insulator layer and the at least one second insulator layer are located between the first RDL electrode and the second RDL electrode.

[0004] Another aspect of the present disclosure includes a structure comprising: a high voltage domain located on a substrate; a low voltage domain located on the substrate, which operates at a voltage lower than the high voltage domain; and galvanic isolation, which isolates the high voltage domain from the low voltage domain, the galvanic isolation including a horizontal portion, the horizontal portion including: a first redistribution layer (RDL) electrode in a first insulator layer, which is located above one of the high voltage domain and the low voltage domain; a second RDL electrode in the first insulator layer, which is laterally separated from the first RDL electrode and is operably coupled to the other of the high voltage domain and the low voltage domain; and an isolation break, which includes a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode and at least one second insulator layer located in the trench, wherein the first insulator layer and the at least one second insulator layer are located between the first RDL electrode and the second RDL electrode.

[0005] One aspect of the present disclosure relates to a method comprising: forming a trench in a first insulator layer between a first redistribution layer (RDL) electrode and a second RDL electrode in the first insulator layer, the first RDL electrode and the second RDL electrode being laterally spaced apart; and filling the trench with at least one second insulator layer, wherein the first insulator layer and the at least one second insulator layer are located between the first RDL electrode and the second RDL electrode, wherein the first RDL electrode is located in a first voltage domain and the second RDL electrode is located in a different second voltage domain.

[0006] The foregoing and other features of the present disclosure will be apparent from the following more particular description of embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the present disclosure will be described in detail with reference to the following drawings, wherein like reference numerals represent like elements, and wherein:

[0008] Figure 1 A cross-sectional view of a structure including galvanic isolation according to an embodiment of the present disclosure is shown.

[0009] Figure 2 A top view of a structure including galvanic isolation according to an embodiment of the present disclosure is shown.

[0010] Figure 3 Cross-sectional views of structures including galvanic isolation according to other embodiments of the present disclosure are shown.

[0011] Figure 4 A cross-sectional view of an initial structure for forming current isolation including forming trenches according to an embodiment of the present disclosure is shown.

[0012] Figure 5 The embodiment according to the present disclosure is shown in Figure 4 A cross-sectional view of an insulator layer formed in a trench.

[0013] Figure 6 The embodiment according to the present disclosure is shown in Figure 4 A cross-sectional view of another insulator layer formed in the trench.

[0014] Please note that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of the present disclosure and therefore should not be considered to limit the scope of the present disclosure. In the drawings, the same reference numerals represent the same elements between the drawings. DETAILED DESCRIPTION

[0015] In the following description, reference is made to the accompanying drawings, which form a part thereof, and in which are shown by way of illustration certain exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is understood that other embodiments may be used and changes may be made without departing from the scope of the present teachings. Therefore, the following description is illustrative only.

[0016] It will be understood that when an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0017] References in the specification to "one embodiment" or "an embodiment" of the present disclosure, as well as other variations thereof, mean that the particular features, structures, characteristics, etc. described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment" or "in an embodiment" and any other variations appearing throughout the specification do not necessarily all refer to the same embodiment. It should be understood that the use of any of " / ", "and / or", and "at least one" in the context of, for example, "A / B", "A and / or B", and "at least one of A and B" is intended to include selecting only the first listed option (a), or only the second listed option (B), or both options (A and B) at the same time. As another example, in the case of "A, B, and / or C" and "at least one of A, B, and C," these phrases are intended to include selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be apparent to one of ordinary skill in the art, this scenario can be extended to many of the listed items.

[0018] Embodiments of the present disclosure include a structure comprising: current isolation including a horizontal portion, the horizontal portion comprising a first redistribution layer (RDL) electrode located in a first insulator layer, and a second RDL electrode located in the first insulator layer and laterally spaced apart from the first RDL electrode. The first insulator layer may include a polyimide located above a far back end of line interconnect layer in an integrated circuit structure. The isolation fracture includes a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode and at least one second insulator layer located in the trench. The first insulator layer and the second insulator layer are located between the first RDL electrode and the second RDL electrode. The isolation can separate voltage domains having different voltage levels, for example. A related method is also disclosed. The current isolation can also include a vertical portion using a first RDL electrode and a third electrode located in a metal layer and separated from the first RDL by multiple interconnect dielectric layers.

[0019] Galvanic isolation provides stronger (e.g., kilovolt-level) galvanic isolation by increasing capacitive coupling using isolation breaks and RDL electrodes in the horizontal portions of the far BEOL interconnect layers. This galvanic isolation provides stronger protection than available structures with more or thicker BEOL interconnect layers. The isolated horizontal (lateral) portions also prevent lateral spikes from high voltage contacts on the bond pads. Where desired, the first insulator layer (which may be a polyimide encapsulation layer) can be made thinner than conventionally used, or can be made thicker to achieve higher galvanic isolation. The formation process is compatible with complementary metal oxide semiconductor (CMOS) processes, but at a lower cost than increasing the thickness or number of BEOL interconnect layers.

[0020] Figure 1 shows a cross-sectional view of a structure 100 according to an embodiment of the present disclosure, Figure 2 FIG. 1 shows a top view of a structure 100 according to an embodiment of the present disclosure. The structure 100 includes a galvanic isolation 110 (hereinafter referred to as “isolation 110”), which includes a horizontal portion 111. Figure 1 As shown, isolation 110 is at least partially located in a galvanic isolation region 112 adjacent to a logic region 114 in an integrated circuit (IC) structure 116. Logic region 114 may include any now known or later developed integrated circuit functional elements (not shown) formed above substrate 118, such as, but not limited to, transistors (located below the M1 layer), resistors, capacitors, etc. Galvanic isolation region 112 may represent a first voltage domain 120, while logic region 114 may represent a second voltage domain 122. First voltage domain 120 and second voltage domain 122 have different operating voltages. For example, first voltage domain 120 may be a relatively high voltage domain on substrate 118, while second voltage domain 122 may be a relatively low voltage domain on substrate 118. In any case, second voltage domain 122 operates at a lower voltage than first voltage domain 120.

[0021] Any currently known or later developed back-end-of-the-line (BEOL) interconnect layer 130 may be provided within logic region 114 and galvanic isolation region 112. Note that BEOL interconnect layer 130 may include any currently known or later developed interlayer dielectric (ILD) layer 132, with conductive wiring 134 or vias 136 therein electrically interconnecting components, such as within logic region 114. ILD layer 132 may include, but is not limited to, silicon dioxide; silicon nitride; carbon-doped silicon dioxide materials; fluorinated silicate glass (FSG); organic polymer thermoset materials; silicon oxycarbide; SiCOH dielectrics; spin-on glass; silsesquioxane; and any silicon-containing low-k dielectric. Wiring 134 and vias 136 may include any suitable conductor, such as tungsten, cobalt, copper, aluminum, and the like, and any suitable liner, such as tantalum nitride, tantalum, and the like. While a number of BEOL interconnect layers 130 are shown, any number may be used, and they may have any thickness desired to accommodate the structures therein. BEOL interconnect layers 130 scale electrical interconnects, such as wires 134 and vias 136, until structures such as input / output pads 138 are large enough to interconnect to external structures of IC structure 116. BEOL interconnect layers 130 may also include an outermost BEOL interconnect layer 133, which may be referred to as a far BEOL (FBEOL) layer.

[0022] The structure 100 includes a redistribution layer (RDL) 140 located above an outermost ILD layer 142, which includes I / O pads 138 (only one of the I / O pads 138 is shown for clarity). The RDL 140 and ILD layer 142 can be part of the FBEOL layer 133, as they are the outermost interconnect layers in the IC structure 116. The RDL 140 is an additional metal layer on the IC die that makes the I / O pads 138 of the IC structure 116 available in other locations on the die when needed to better access the I / O pads 138. The RDL 140 distributes contact points around the IC structure 116, allowing solder balls 144 to be applied and distributing thermal stress. The RDL 140 includes a first insulator layer 146 that includes metal wiring 148 to move the contact points to a location other than the I / O pads 138. First insulator layer 146 can include any now known or later developed dielectric suitable for use in RDL 140. In one embodiment, first insulator layer 146 includes polyimide. First insulator layer 146 can therefore have a dielectric strength of, for example, approximately 300 Vrms / μm.

[0023] The structure 100 employing selective metal wiring 148 in the RDL 140 includes a first redistribution layer (RDL) electrode 150 located in a first insulator layer 146 and a second RDL electrode 152 located in the first insulator layer 146 and laterally spaced apart from the first RDL electrode 150. The first RDL electrode 150 and the second RDL electrode 152 are part of the RDL 140, which may include other metal wiring 148, not shown. As used herein, an "electrode" may include any conductor capable of providing a plate for a capacitor. The first RDL electrode 150 and the second RDL electrode 152 are at the same level in the first insulator layer 146. Therefore, the first RDL electrode 150 and the second RDL electrode 152 can be spaced apart horizontally or laterally by a distance S, which can be user-defined. As is conventional, other portions of the metal wiring 148 in the RDL 140 can be at different levels for interconnection purposes, for example, to an I / O pad 138 or other structures. The RDL electrodes 150, 152 can have any desired lateral layout. In the example shown, the second RDL electrode 152 can be electrically coupled to the second voltage domain 122 (e.g., in the logic region 114) via a plurality of (BEOL) interconnect layers 130. As described, the first voltage domain 120 and the second voltage domain 122 can have different operating voltages. For example, the first voltage domain 120 can be a relatively high voltage domain, while the second voltage domain 122 can be a relatively low voltage domain.

[0024] The structure 100 further includes an isolation break 160. The isolation break 160 electrically isolates the first RDL electrode 150 from the second RDL electrode 152. Figure 1 As shown, the isolation break 160 includes a trench 162 defined in the first insulator layer 146 between the first RDL electrode 150 and the second RDL electrode 152. At least one second insulator layer 166, 168 is located in the trench 162. Therefore, the first insulator layer 146 and the at least one second insulator layer 166, 168 are located between the first RDL electrode 150 and the second RDL electrode 152. Each second insulator layer 166, 168 has a higher dielectric constant than the first insulator layer 146. In one embodiment, the second insulator layer may include at least one nitride layer 166 and at least one oxide layer 168. In the example shown, the at least one nitride layer 166 lines the sidewalls 170 of the trench 162, and the at least one oxide layer 168 fills the remaining portion of the trench 162. However, other arrangements of nitrides and oxides are possible. In this way, as Figure 2As best shown in FIG, the isolation break 160 includes a nitride-oxide-nitride arrangement between the first RDL electrode 150 and the second RDL electrode 152, which increases the capacitive coupling generated by the isolation 110 compared to vertical current isolation using the BEOL interconnect layer 130. The nitride layer 166 may include, but is not limited to, silicon nitride, and the oxide layer 168 may include, but is not limited to, silicon oxide. Figure 2 As shown, the trench 162 and the isolation break 160 surround the first RDL electrode 150 .

[0025] Isolation break 160 provides additional dielectric strength, thereby increasing the capacitive coupling for isolation 110. The use of nitride layer 166 and oxide layer 168 allows the dielectric strength of isolation 110 to be further increased and / or customized. For example, silicon nitride has a dielectric strength of approximately 1100 Vrms / μm and silicon oxide (high temperature version) has a dielectric strength of approximately 500 Vrms / μm, compared to a dielectric strength of approximately 300 Vrms / μm for polyimide. The type of material, its thickness, and the width of trench 162 can be customized to provide the desired dielectric strength for isolation break 160 and the desired capacitive coupling for isolation 110. Other options for second insulator layers 166, 168 may include, but are not limited to, hydrogenated silicon oxycarbide (SiCOH) (~750 Vrms / μm) or porous SiCOH (750+ Vrms / μm). The type of silicon oxide may also vary and may include, for example, tetraethyl orthosilicate, Si(OC2H5)4 (TEOS) silicon oxide (-900 Vrms / μm), or low temperature silicon oxide (-500 Vrms / μm).

[0026] like Figure 1 As shown, the structure 100 and isolation 110 may also include a vertical portion 172. The vertical portion 172 may include a third electrode 170 located below the first RDL electrode 150 and in a metal layer (M1, M2, etc.) of the first voltage domain 120. Although the third electrode 170 is shown as being located in the first metal layer M1, it may be located in any metal layer in the BEOL interconnect layer 130. The third electrode 170 is vertically separated from the first RDL electrode 140 by a plurality of ILD layers 132 of the BEOL interconnect layer 130, thereby forming the vertical portion 172 of the galvanic isolation 110. Any number of ILD layers 132 may be used.

[0027] Figure 3 A cross-sectional view of a structure 100 is shown according to an alternative embodiment. Figure 3 The structure 100 in is basically similar to Figure 1The structure shown in FIG. 1 is shown in FIG. 2 , except that first insulator layer 146 includes at least one nitride layer 180 and at least one oxide layer 182, i.e., at least one nitride layer 180 and at least one oxide layer 182 are horizontally formed across regions 112 and 114. In other words, nitride layer 180 and oxide layer 182 replace polyimide. Isolation fracture 160 still extends into trench 162 in nitride layer 180 and oxide layer 182. The use of nitride layer 180 and oxide layer 182 allows the dielectric strength of isolation 110 to be further increased and / or customized.

[0028] refer to Figures 4 to 6 , showing a cross-sectional view of a method according to an embodiment of the present disclosure. Figure 4 An initial structure 200 is shown. The initial structure 200 includes the logic region 114, including any devices (not shown), and the BEOL interconnect layer 130 located thereover. At this stage, the I / O pads 138 have been formed, and the metal wiring 148 has been formed in the first insulator layer 146. In addition to other structures not shown, the metal wiring 148 includes a first RDL electrode 150 and a second RDL electrode 152 located in the first insulator layer 146. The first RDL electrode 150 and the second RDL electrode 152 are laterally spaced apart, for example, by a distance S( Figure 1 ). Any currently known or later developed process (e.g., conventional CMOS process) can be used to form the aforementioned structure. Compared with conventional processes, Figure 4 Also shown is a trench 162 formed into the first insulator layer 146 between the first RDL electrode 150 and the second RDL electrode 152 in the first insulator layer 146. The trench 162 can be formed using a patterned mask 202 and a suitable etching process (e.g., reactive ion etching) for the first insulator layer 146. The trench 162 does not expose the BEOL interconnect layer 130, but extends sufficiently below the RDL metal electrodes 150, 152 so that the isolation 160 ultimately formed therein provides the desired dielectric strength and electrical isolation. The mask 202 can be removed using any suitable ashing process.

[0029] Figures 5 and 6 The trench 162 is shown filled with at least one second insulator layer 166 , 168 . Figure 5At least one nitride layer 166 is shown formed. Each second insulator layer 166, 168 has a higher dielectric constant than the first insulator layer 146. In one embodiment, the first insulator layer 146 may include polyimide, and the second insulator layer may include at least one nitride layer 166 and at least one oxide layer 168. Although shown as not filling the trench 162, a single second insulator layer, for example composed of nitride or oxide, may fill the entire trench 162, so that the isolation break 160 includes only a single insulator layer. In the example shown, the nitride layer 166 only covers the sidewalls 170 of the trench 162, and Figure 6 At least one oxide layer 168 is shown formed over the nitride layer 166, filling the remaining portion of the trench 162 ( Figure 5 The filling step may comprise any suitable deposition technique for the material being formed. Any suitable planarization may thereafter be performed to remove excess material, such as chemical mechanical polishing (CMP).

[0030] The first insulator layer 146 and each second insulator layer 166, 168 are located between the first RDL electrode 150 and the second RDL electrode 152, forming a horizontal portion 111 of the current isolation 110 and a capacitor. The first RDL electrode 150 is located in a first voltage domain 120, and the second RDL electrode 122 is located in a different second voltage domain 122. Figure 1 As partially shown, any conventional packaging processes, such as formation of solder bumps 144 , wire bonding, etc., may be performed after the isolation 110 is formed.

[0031] Galvanic isolation 110 provides stronger (e.g., kilovolt-level) galvanic isolation by increasing capacitive coupling using isolation breaks 160 and RDL electrodes 150, 152 in the horizontal portion of FBEOL interconnect layer 133. Isolation 110 provides greater protection than available structures with more or thicker BEOL interconnect layers 132. Horizontal (lateral) portions 111 of isolation 110 also prevent lateral spikes from high-voltage contacts on I / O pads 138. If desired, first insulator layer 146 (which may be a polyimide encapsulation layer) can be made thinner than conventionally used, or can be made thicker to achieve higher galvanic isolation. Figures 4 to 6 The formation process shown is compatible with CMOS processing, but is less expensive than increasing the thickness or number of BEOL interconnect layers 132 .

[0032] The above-described method is used to manufacture integrated circuit chips. The resulting integrated circuit chip package can be integrated with other chip packages, discrete circuit components, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0033] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or groups thereof. "Optional" or "optionally" means that the event or situation described subsequently may or may not occur, and that the description includes situations where the event occurs and situations where the event does not occur.

[0034] Approximate language, as used throughout the specification and claims, may be used to modify any quantitative representation that is permissible to vary without resulting in a change in the basic function to which it relates. Accordingly, a value modified by one or more terms such as "about," "approximately," and "substantially" is not limited to the precise value specified. In at least some cases, approximate language may correspond to the precision of an instrument used to measure the value. Herein and throughout the specification and claims, range limitations may be combined and / or interchanged, such ranges are identified and include all subranges contained therein unless context or language dictates otherwise. "Approximately" applied to a particular value of a range applies to both values ​​and may indicate + / - 10% of the stated value unless otherwise dependent upon the precision of the instrument used to measure the value.

[0035] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been given for purposes of illustration and description, but is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others of ordinary skill in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular use contemplated.

Claims

1. A semiconductor structure comprising: Galvanic isolation comprising a horizontal portion comprising: a first redistribution layer (RDL) electrode in the first insulator layer; a second redistribution layer electrode in the first insulator layer laterally spaced from the first redistribution layer electrode; and an isolation break comprising a trench defined in the first insulator layer between the first redistribution layer electrode and the second redistribution layer electrode and at least one second insulator layer located in the trench, The first insulator layer and the at least one second insulator layer are located between the first redistribution layer electrode and the second redistribution layer electrode.

2. The structure according to claim 1, wherein Each second insulator layer has a higher dielectric constant than the first insulator layer.

3. The structure according to claim 1, wherein The at least one second insulator layer includes at least one nitride layer and at least one oxide layer.

4. The structure according to claim 3, wherein The at least one nitride layer lines sidewalls of the trench, and the at least one oxide layer fills a remaining portion of the trench.

5. The structure according to claim 1, wherein The first insulator layer includes polyimide.

6. The structure according to claim 1, wherein The isolation break surrounds the first redistribution layer electrode.

7. The structure according to claim 1, wherein The galvanic isolation includes a vertical portion comprising a third electrode located below the first redistribution layer electrode and in a metal layer of a first voltage domain, the third electrode being vertically separated from the first redistribution layer electrode by a plurality of interconnecting dielectric layers.

8. The structure according to claim 7, wherein The second redistribution layer electrode is electrically coupled to a second voltage domain through a plurality of interconnection layers, and the first voltage domain and the second voltage domain have different operating voltages.

9. The structure according to claim 1, wherein The first insulator layer includes at least one nitride layer and at least one oxide layer.

10. The structure according to claim 1, wherein The first redistribution layer electrode and the second redistribution layer electrode are at the same level in the first insulator layer.

11. A semiconductor structure comprising: a high voltage domain located on the substrate; a low voltage domain located on the substrate, operating at a voltage lower than that of the high voltage domain; as well as Galvanic isolation isolating the high voltage domain from the low voltage domain, the galvanic isolation comprising a horizontal portion, the horizontal portion comprising: a first redistribution layer (RDL) electrode in a first insulator layer over one of the high voltage domain and the low voltage domain; a second redistribution layer electrode in the first insulator layer, laterally spaced apart from the first redistribution layer electrode and operatively coupled to the other of the high voltage domain and the low voltage domain; and an isolation break comprising a trench defined in the first insulator layer between the first redistribution layer electrode and the second redistribution layer electrode and at least one second insulator layer located in the trench, The first insulator layer and the at least one second insulator layer are located between the first redistribution layer electrode and the second redistribution layer electrode.

12. The structure according to claim 11, wherein Each second insulator layer has a higher dielectric constant than the first insulator layer.

13. The structure according to claim 11, wherein The first insulator layer includes polyimide, and the at least one second insulator layer includes at least one nitride layer and at least one oxide layer.

14. The structure according to claim 11, wherein The isolation break surrounds the first redistribution layer electrode.

15. The structure according to claim 11, wherein The galvanic isolation includes a vertical portion comprising a third electrode located below the first redistribution layer electrode and in a metal layer of one of the high voltage domain and the low voltage domain, the third electrode being vertically separated from the first redistribution layer electrode by a plurality of interconnected dielectric layers.

16. The structure according to claim 11, wherein The first insulator layer includes at least one nitride layer and at least one oxide layer.

17. The structure according to claim 11, wherein The first redistribution layer electrode and the second redistribution layer electrode are at the same level in the first insulator layer.

18. A method of forming a semiconductor structure, comprising: forming a trench in a first insulator layer between a first redistribution layer (RDL) electrode and a second RDL electrode in the first insulator layer, the first RDL electrode and the second RDL electrode being laterally spaced apart; as well as filling the trench with at least one second insulator layer, wherein the first insulator layer and the at least one second insulator layer are located between the first redistribution layer electrode and the second redistribution layer electrode, The first redistribution layer electrode is located in a first voltage domain, and the second redistribution layer electrode is located in a different second voltage domain.

19. The method according to claim 18, wherein The at least one second insulator layer has a higher dielectric constant than the first insulator layer.

20. The method according to claim 18, wherein The first insulator layer includes polyimide, and the at least one second insulator layer includes at least one nitride layer and at least one oxide layer.

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