Multi-FPGA + Soc and Split Display Electronic Rearview Mirror CMS

Abstract

The present invention discloses an electronic rearview mirror CMS with multiple FPGAs + Soc and a segmented display screen. The electronic rearview mirror CMS with multiple FPGAs + Soc and a segmented display screen includes a COMS image sensor, a DDR3 image data memory, an ARM central controller, a MIPI video decoding and distribution unit - FPGA + Soc, an image algorithm compensation processing module, and an AMOLED display screen module; the overall AMOLED display screen is segmented into multiple groups of individual AMOLED display screens, enabling each individual AMOLED display screen to be independently scanned and displayed. This can save the scanning and display time, reduce the delay of the electronic rearview mirror CMS, and also improve the scanning frame rate of the display screen.

Description

Technical Field

[0001] The invention relates to an image distortion correction method for a CCD imaging system, and in particular to an electronic rearview mirror CMS with multiple FPGA+Soc and a split display screen. Technical Background

[0002] With the advent of intelligent transportation systems, the advancement of automobile intelligence is getting faster and faster. Many parts of automobiles have been electronicized. Among them, the electronic rearview mirror of automobiles, which has received a lot of public attention in recent years, has brought great convenience and safety to people's driving. The electronic rearview mirror of automobiles is a system composed of cameras and monitors. Compared with traditional physical rearview mirrors, the camera replaces the optical lens, which can bring drivers a wider field of view and a more flexible perspective, making it easier for drivers to judge the road conditions behind the vehicle more quickly. Even in severe weather conditions such as heavy rain and heavy snow, the electronic rearview mirror can provide better clarity. At present, the lenses used in most automotive electronic cameras are wide-angle lenses, which will cause image distortion. The distortion types are mainly radial distortion and tangential distortion. Radial distortion is an off-axis point imaging, and the light beam has aberration. Even if only the main light passes through the optical system, the light still cannot coincide with the ideal optical axis, mainly because of the spherical aberration factor. Therefore, the height of the intersection is not the same as the ideal image height. When the magnification is not constant, the image has no similarity to the object. This is the cause of distortion, which mainly manifests as fisheye distortion and barrel distortion. The distortion caused by non-axisymmetry in the optical system is tangential distortion, which is mainly caused by the fact that the camera lens is not completely parallel to the image plane. Summary of the invention

[0003] The present invention aims to address the deficiencies of the prior art and provides an electronic rearview mirror CMS with multiple FPGA+Soc and multiple independent display modes for an automobile electronic rearview mirror.

[0004] The purpose of the present invention is achieved by at least one of the following technical solutions.

[0005] An electronic rearview mirror CMS with multiple FPGA+Soc and split display screens, including a COMS image sensor, a DDR3 image data memory, an ARM central controller, a MIPI video decoding distributor-FPGA+Soc, an image algorithm compensation processing module and an AMOLED display screen module; the image algorithm compensation processing module includes n groups of image algorithm compensation processing FPGA+Soc; the AMOLED display screen module includes n separate AMOLED display screens;

[0006] The ARM central controller is respectively connected to a CMOS image sensor, a DDR3 image data memory, a MIPI video decoding and distribution unit - FPGA + Soc, and n groups of image algorithm compensation processing FPGA + Soc; the n groups of image algorithm compensation processing FPGA + Soc are respectively connected to n individual AMOLED displays one - to - one;

[0007] The ARM central controller sends a detection signal to the CMOS image sensor, and the CMOS image sensor outputs image information in MIPI format data;

[0008] After the MIPI video decoding and distribution unit - FPGA + Soc receives the image information output by the CMOS image sensor, it decodes the image data and divides the image information into n groups based on rows. After the image information processing of the n groups of image algorithm compensation processing FPGA + Soc is completed, the compensated image data is output and transmitted to the corresponding individual AMOLED displays respectively.

[0009] Furthermore, the MIPI video decoding and distribution unit - FPGA + Soc includes a video image information receiving module, a video image information decoding module, a VDMA image caching module, an image information pre - processing module, a video image RGB conversion module, an image information segmentation module, and n image information transmission interfaces connected in sequence;

[0010] The video image information receiving module receives the MIPI - format data transmitted by the COMS image sensor, converts the serial data in MIPI format into parallel data and sends it to the video image information decoding module;

[0011] The video image information decoding module analyzes different data packets according to the standard protocol, generates corresponding line and field synchronization signals, extracts the image data, converts the format of the image data, and transmits it to the VDMA image caching module;

[0012] The MIPI image information data realizes image caching through the VDMA image caching module; by ensuring that the image system has multiple frame buffers, the output data is not torn, the input and output rates of the image are coordinated, and the image is ensured to be stable;

[0013] The image information pre - processing module sorts out the image information cached in the VDMA image caching module, analyzes the image, performs processing before feature extraction, segmentation, and matching of the input image, eliminates irrelevant information in the image, restores useful real information, improves the reliability of feature extraction, image segmentation, matching, and recognition, and sends the pre - processed image data to the video image RGB conversion module;

[0014] The video image RGB conversion module converts the image data format into the corresponding video data for display on the display screen and sends it to the image information segmentation module;

[0015] The image information segmentation module divides the video data into n groups according to different resolutions and sends them to n groups of image algorithm compensation processing FPGA+Soc through n image information transmission interfaces respectively.

[0016] Furthermore, the image algorithm compensation processing FPGA+Soc includes an ARM controller, a DDR3 image data memory, an image information transmission interface, an image correction function coefficient setting module, an image correction function and algorithm module, and an output interface circuit;

[0017] In the image correction function coefficient setting module, two functions of image geometric distortion correction and image gray correction are adopted, including setting the known reference points of the image, that is, the corresponding relationship between the coordinates of some pixel points of the undistorted image and the corresponding pixels of the distorted image, setting and calculating the unknown coefficients in the mapping relationship, and establishing a mathematical model for geometric correction; performing a spatial coordinate transformation on the image, establishing the row coordinates and column coordinates of the image pixel points, calculating the corresponding parameters, and determining the gray values of each pixel;

[0018] In the image correction function and algorithm module, the image signal is converted into a digital signal, and then the digital signal is processed, including image filtering, image enhancement, image segmentation, image restoration and reconstruction, image feature extraction and image compression, to complete the color restoration of the image information, horizontal uniformity, vertical uniformity, brightness contrast reproduction, gray level reproduction and image geometric distortion correction;

[0019] The output interface circuit adopts the LVDS image transmission mode to realize the high-dynamic image transmission, connects to the corresponding separate AMOLED display screen, and can directly transmit the image output result to the pixel matrix of column×row of the AMOLED display screen for OLED direct display.

[0020] Furthermore, the separate AMOLED display screen includes a power management module, an input interface circuit, an address driving circuit, an image data driving circuit, and a column×row pixel matrix display OLED; among them, the image data driving circuit includes an R-gamma correction and gray voltage generation module, a G-gamma correction and gray voltage generation module, and a B-gamma correction and gray voltage generation module;

[0021] The power management module is respectively connected to the input interface circuit, the address driving circuit, the image data driving circuit, and the column×row pixel matrix display OLED;

[0022] The input interface circuit decodes the input image information and inputs the decoded image information into the address driving circuit and the image data driving circuit respectively;

[0023] According to the decoded image information, the image data driving circuit respectively corrects R pixels, G pixels, and B pixels through the R-GAMA correction and gray voltage generation module, the G-GAMA correction and gray voltage generation module, and the B-GAMA correction and gray voltage generation module to obtain the gray signal voltages required for R pixels, G pixels, and B pixels, and then outputs an image display signal to the column×row pixel matrix display OLED;

[0024] According to the decoded image information, the address driving circuit outputs an image control signal to the column×row pixel matrix display OLED;

[0025] The column×row pixel matrix display OLED displays the image information according to the received image display signal and image control signal.

[0026] Further, in the column×row pixel matrix display OLED, the RGB pixel driving circuits form an AMOLED display screen, including R pixels, G pixels, and B pixels. Each pixel includes a TFT device and a storage capacitor, respectively constituting an R red pixel driving circuit, a G green pixel driving circuit, and a B blue pixel driving circuit. The 2TC circuit composed of two thin film transistors and a capacitor is used to achieve continuous lighting of the screen. The external power supply provides voltage V DD to provide a continuous current, and the magnitude of this current value is controlled by the driving transistor T. That is, the gate voltage on the driving transistor T controls whether the current can flow through the channel of the first driving transistor T1 into the organic light-emitting diode OLED. When the gate voltage of the driving transistor is not sufficient to turn on the first driving transistor T1, the first driving transistor T1 is in the off state, and no current enters the organic light-emitting diode OLED, and this pixel point appears as an unlit state;

[0027] The gate voltage becomes an important switch, and this switch is determined by the signal stored in the capacitor C.

[0028] Further, the R red pixel driving circuit, the G green pixel driving circuit, and the B blue pixel driving circuit all include a first thin film transistor, a second thin film transistor, and a capacitor;

[0029] When the signal provided by the line scan signal Sn is at a low level, the first thin film transistor is turned on, and the voltage of the image data is transmitted to the gate of the second thin film transistor; when the signal provided by the line scan signal Sn is at a high level, the first thin film transistor is turned off, and the gate of the second thin film transistor maintains the data voltage unchanged until the next cycle when the first thin film transistor is turned on, and the image data voltage of the next frame changes, refreshing the gate voltage of the second thin film transistor. Among them, the on and off of the second thin film transistor are determined by the data voltage provided by the image data, and the on time and off time of the second thin film transistor are controlled by the pulse width modulation signal provided by the line scan signal Sn; the power supply is connected to the positive electrode of the corresponding OLED to control the on and off of the current of the corresponding OLED; the function of the capacitor is to keep the gate voltage of the second thin film transistor unchanged, that is, the voltage remains after the capacitor is charged until the next data voltage change;

[0030] The image data has two logical states, logic '0' and logic '1', and the working state of the second thin film transistor of the pixel is in the cut-off region and the saturation region of the transfer characteristic curve.

[0031] Further, in the column×row pixel matrix display OLED, according to the received image signal, each pixel driving circuit independently regulates a single pixel, and the image data driving circuit and the address driving circuit provide the image display signal and the control signal output to the pixel matrix;

[0032] The address driving circuit outputs a line scan signal, and the line scan signal is loaded onto the gates of the thin film transistors in each pixel driving circuit to sequentially turn on each pixel driving circuit in the pixel array;

[0033] The image data driving circuit outputs a column scan signal and simultaneously provides the gray scale signal voltage required for each pixel;

[0034] After the first thin film transistor is turned on, the gray scale signal of each sub-pixel is output by the source driver and flows into the second thin film transistor in the form of current. The OLED is a light-emitting diode, making the pixel emit light; the gray scale signal of each pixel will be stored in the capacitor C in the form of voltage, and the next frame of image display signal is refreshed. The light emission intensity and proportion of the OLED light-emitting diodes in the pixel driving circuits of R pixels, G pixels, and B pixels determine the color and brightness of each pixel.

[0035] Further, the output interface circuit of the image algorithm compensation processing FPGA+Soc is a direct scan driving circuit, including a column information image data module, a row information scan decoding module, an ARM controller, and a clock module;

[0036] The ARM controller realizes the image algorithm compensation processing of the FPGA+Soc direct scanning drive column×row pixel matrix display OLED through the column information image data module and the row information scanning decoding module.

[0037] Further, n is an integer multiple of the number of rows in the AMOLED display screen resolution.

[0038] Further, the parameters of the CMOS image sensor are as follows: image output format: YUV422; CMOS sensor resolution: 1920*1080; sensor frame rate ≥ 60fps. The display screen resolution is 1280*720; the display frame rate ≥ 60fps; the wide dynamic range ≥ 120dB; the display delay ≤ 45mS. The image information output interface is MIPI.

[0039] The advantages of the present invention are as follows:

[0040] (1) The CMS delay provided by the present invention avoids the delay formed by converting MIPI or LVDS again. For ordinary electronic rearview mirror CMS, the original delay is T1, the image algorithm compensation delay is T2, and the delay formed by converting MIPI or LVDS again is T3. The total CMS system delay is T = T 1+ T 2+ T3. The CMS delay provided by the present invention avoids the delay formed by converting MIPI or LVDS again, such as the delay of 60 frames per second or 30 frames per second, the T3 time.

[0041] (2) The AMOLED display screen provided by the present invention is divided into multiple groups of separate AMOLED display screens. Each separate AMOLED display screen is an independent part, specifically including the input interface, image column information D decoding, address information S gate information decoding, etc. When controlling the scanning and display of the separate AMOLED display screen, it saves and reduces the display delay of the CMS.

[0042] (3) The MIPI video decoding distributor FPGA+Soc provided by the present invention divides the received image information into multiple groups, corresponding to the module and the image information transmission interface, and the preprocessing steps of image information calculation and compensation.

[0043] (4) The image algorithm compensation processing FPGA+Soc is divided into multiple groups. The multiple groups of image algorithm compensation processing FPGA+Soc can simplify the image processing function, save the time of image processing, image algorithms, and image compensation, and convert the multi-functional image algorithm compensation processing into multiple groups of simplified operations and compensated images, while retaining the interface function, that is, selecting the FPGA+Soc with only operation and interface functions.

[0044] (5) The multi-group separate AMOLED displays provided by the present invention divide the overall AMOLED display into multiple groups of separate AMOLED displays, enabling each separate AMOLED display to be independently scanned and displayed. This can save scanning and display time, reduce the delay of the electronic rearview mirror CMS, and also increase the scanning frame rate of the display.

[0045] (6) In the method for directly driving an AMOLED display provided by the present invention, the output interface circuit of the image algorithm compensation processing FPGA+Soc is designed as a direct driving circuit. The direct scanning and driving of the AMOLED display is jointly composed of column information, image information D source driving circuit, row information, and address decoding S gate driving circuit. The output interface circuit of the image algorithm compensation processing FPGA+Soc is used to control a separate directly driven AMODLED display, reducing the link of converting image information into a video signal, that is, converting it into a MIPI or LVDS video mode, saving time and reducing the delay of the electronic rearview mirror CMS. Description of the Drawings

[0046] Figure 1 It is a schematic structural diagram of the electronic rearview mirror CMS with multiple FPGA+Soc and a segmented display in the embodiment of the present invention.

[0047] Figure 2 It is a schematic structural diagram of a common electronic rearview mirror CMS in the embodiment of the present invention.

[0048] Figure 3 It is a schematic structural diagram of the electronic rearview mirror CMS with multiple FPGA+Soc and a segmented display using direct driving in the embodiment of the present invention.

[0049] Figure 4 It is a schematic structural diagram of the MIPI video decoding and distributor FPGA+Soc in the embodiment of the present invention.

[0050] Figure 5 It is a schematic structural diagram of the image algorithm compensation processing FPGA+Soc in the embodiment of the present invention.

[0051] Figure 6 It is a schematic structural diagram of a separate AMOLED display in the embodiment of the present invention.

[0052] Figure 7 It is a schematic structural diagram of the direct scanning and driving AMOLED display in the embodiment of the present invention.

[0053] Figure 8 It is a flowchart of the working principle of the electronic rearview mirror CMS with multiple FPGA+Soc and a segmented display in the embodiment of the present invention.

[0054] Figure 9Schematic diagram of the driving circuit structure of RGB pixel points for a column×row pixel matrix display OLED in an embodiment of the present invention. Detailed implementation manners

[0055] To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the following will combine with the accompanying drawings and give embodiments to elaborate on the specific implementation of the present invention in detail.

[0056] Embodiment:

[0057] Under normal circumstances, a common electronic rearview mirror CMS, such as Figure 2 shown, consists of an ARM central controller, a COMS image sensor, an FPGA image algorithm and compensation module, a DDR3 image data memory, and a TFT display screen.

[0058] For a common electronic rearview mirror CMS, usually one FPGA image algorithm and compensation module is adopted. When the output of the COMS image sensor is 1920×1280, the image data is relatively large, and the operation time of the image algorithm and compensation is relatively long, resulting in an increase in system delay, seriously affecting the real-time performance of the electronic rearview mirror. The solution is to increase the FPGA function, that is, to increase the internal structure module processing function. In this way, the cost or price of the FPGA is increased, and the price of the electronic rearview mirror is increased significantly, which is not conducive to popularization and application.

[0059] The described common electronic rearview mirror CMS uses a display screen. In the working state, when the output of the COMS image sensor is 1920×1280, it needs to be decoded in the FPGA before the image algorithm and compensation operations can be performed, increasing the system delay of the electronic rearview mirror. After generating the image information, it is converted into video image information for output, and then 60 frames per second are formed again, that is, the display time is 1 / 60 second per second.

[0060] The delay T of the described common electronic rearview mirror CMS is T = T1 + T2 + T3, specifically: (1) The original adopted delay T1, with 60 frames per second required, the delay T1 = 1 / 60; (2) The delay T2 for the image algorithm and compensation operations; (3) Forming 60 frames per second again T3 and outputting to the display screen, the delay T3 = 1 / 60.

[0061] An electronic rearview mirror CMS with multiple FPGAs + Soc and a segmented display screen, such as Figure 1 shown, includes a COMS image sensor, a DDR3 image data memory, an ARM central controller, a MIPI video decoding and distribution - FPGA + Soc, an image algorithm compensation processing module, and an AMOLED display screen module; the image algorithm compensation processing module includes n groups of image algorithm compensation processing FPGAs + Soc; the AMOLED display screen module includes n individual AMOLED display screens;

[0062] The ARM central controller is respectively connected to a CMOS image sensor, a DDR3 image data memory, a MIPI video decoding and distribution unit - FPGA + Soc, and n groups of image algorithm compensation processing FPGA + Soc; the n groups of image algorithm compensation processing FPGA + Soc are respectively connected to n individual AMOLED displays one-to-one;

[0063] As Figure 8 shown, the ARM central controller sends a detection signal to the CMOS image sensor, and the CMOS image sensor outputs image information in MIPI format data;

[0064] After the MIPI video decoding and distribution unit - FPGA + Soc receives the image information output by the CMOS image sensor, it decodes the image data, and divides the image information into n groups based on rows. After the n groups of image algorithm compensation processing FPGA + Soc complete the image distortion compensation for the image information, the compensated image data is output and transmitted to the corresponding individual AMOLED displays respectively.

[0065] In this embodiment, n is an integer multiple of the number of rows in the AMOLED display resolution, and n = 6.

[0066] As Figure 4 shown, the MIPI video decoding and distribution unit - FPGA + Soc includes a video image information receiving module, a video image information decoding module, a VDMA image caching module, an image information preprocessing module, a video image RGB conversion module, an image information segmentation module, and n image information transmission interfaces connected in sequence;

[0067] The video image information receiving module receives the MIPI format data transmitted by the COMS image sensor, and converts the serial data in MIPI format into parallel data and sends it to the video image information decoding module;

[0068] The video image information decoding module analyzes different data packets according to the standard protocol, generates corresponding line and field synchronization signals, extracts the image data, converts the format of the image data, and transmits it to the VDMA image caching module;

[0069] The MIPI image information data realizes the caching of the image through the VDMA image caching module; by ensuring that the image system has multiple frame buffers, the output data is not torn, the input and output rates of the image are coordinated, and the image is ensured to be stable;

[0070] The image information preprocessing module sorts out the image information cached in the VDMA image cache module, analyzes the image, performs processing before feature extraction, segmentation, and matching of the input image, eliminates irrelevant information in the image, restores useful real information, improves the reliability of feature extraction, image segmentation, matching, and recognition, and sends the preprocessed image data to the video image RGB conversion module;

[0071] The video image RGB conversion module converts the image data format into the video data corresponding to the display of the display screen and sends it to the image information segmentation module;

[0072] The image information segmentation module divides the video data into n groups according to different resolutions and sends them to n groups of image algorithm compensation processing FPGA+Soc through n image information transmission interfaces respectively.

[0073] As Figure 5 shown, the image algorithm compensation processing FPGA+Soc includes an ARM controller, a DDR3 image data memory, an image information transmission interface, an image correction function coefficient setting module, an image correction function and algorithm module, and an output interface circuit;

[0074] The image algorithm compensation processing FPGA+Soc is divided into n groups, and each image algorithm compensation processing FPGA+Soc works independently. The amount of image data is reduced by n times, the operation speed is improved, and the operation accuracy can also be improved. The output interface LVDS is directly sent to the display screen.

[0075] In the image correction function coefficient setting module, two functions of image geometric distortion correction and image gray correction are adopted, including setting known reference points of the image, that is, the corresponding relationship between the coordinates of some pixel points of the undistorted image and the corresponding pixels of the distorted image, setting and calculating the unknown coefficients in the mapping relationship, and establishing a mathematical model for geometric correction; performing spatial coordinate transformation on the image, establishing the row coordinates and column coordinates of the image pixel points, calculating the corresponding parameters, and determining the gray values of each pixel;

[0076] In the image correction function and algorithm module, the image signal is converted into a digital signal, and then the digital signal is processed, including image filtering, image enhancement, image segmentation, image restoration and reconstruction, image feature extraction, and image compression, to complete the color restoration of image information, horizontal direction uniformity, vertical direction uniformity, brightness contrast reproduction, gray level reproduction, and image geometric distortion correction;

[0077] The output interface circuit adopts the LVDS image transmission mode to realize high-dynamic image transmission, connects to the corresponding separate AMOLED display screen, and can directly transmit the image output result to the pixel matrix of the column×row of the AMOLED display screen for OLED direct display.

[0078] As Figure 6 shown, the separate AMOLED display screen includes a power management module, an input interface circuit, an address driving circuit, an image data driving circuit, and a column × row pixel matrix display OLED; among them, the image data driving circuit includes an R-gamma correction and gray-scale voltage generation module, a G-gamma correction and gray-scale voltage generation module, and a B-gamma correction and gray-scale voltage generation module;

[0079] The power management module is respectively connected to the input interface circuit, the address driving circuit, the input interface circuit of the image data driving circuit, and the column × row pixel matrix display OLED;

[0080] The image information input by the input interface circuit is decoded, and the decoded image information is respectively input into the address driving circuit and the image data driving circuit;

[0081] According to the decoded image information, the image data driving circuit respectively performs R pixel, G pixel, and B pixel corrections through the R-GAMA correction and gray-scale voltage generation module, the G-GAMA correction and gray-scale voltage generation module, and the B-GAMA correction and gray-scale voltage generation module to obtain the gray-scale signal voltages required for the R pixel, G pixel, and B pixel, and then outputs an image display signal to the column × row pixel matrix display OLED;

[0082] The working principles of the R-gamma correction, G-gamma correction, and B-gamma correction: Gamma correction is suitable for application in display screens to improve the image display effect. It is a method of editing the gamma curve of an image to perform non-linear tone editing on the image, detecting the dark and light parts of the image signal, and increasing the ratio of the two to improve the contrast of the image, etc. The Gamma curve of the image is suitable for the AMOLED display screen. The corresponding gamma curve is usually a power function Y=(X + e)γ, where Y is the brightness, X is the output voltage, e is the compensation coefficient, and the power value γ is the gamma value. Changing the magnitude of the power value (V) can change the gamma curve of the AMOLED display screen. Since the luminous gray scale of the image signal is not a linear function but an exponential function, the image information must be corrected.

[0083] The address driving circuit outputs an image control signal to the column × row pixel matrix display OLED according to the decoded image information;

[0084] The column × row pixel matrix display OLED displays the image information according to the received image display signal and image control signal.

[0085] Furthermore, in a column×row pixel matrix display OLED, the RGB pixel driving circuits form an AMOLED display screen, including R pixels, G pixels, and B pixels. Each pixel includes a TFT device and a storage capacitor, respectively constituting an R red pixel driving circuit, a G green pixel driving circuit, and a B blue pixel driving circuit. A 2TC circuit composed of two thin film transistors and a capacitor is used to continuously light up the screen, and an external power supply provides voltage V DD to provide a continuous current, and the magnitude of this current value is controlled by the driving transistor T. That is, the gate voltage on the driving transistor T controls whether the current can flow through the channel of the first driving transistor T1 into the organic light-emitting diode OLED. When the gate voltage of the driving transistor is not sufficient to turn on the first driving transistor T1, the first driving transistor T1 is in the off state, and no current enters the organic light-emitting diode OLED, and this pixel point appears in the unlit state;

[0086] The gate voltage becomes an important switch, and this switch is determined by the signal stored in the capacitor C.

[0087] The R red pixel driving circuit, the G green pixel driving circuit, and the B blue pixel driving circuit all include a first thin film transistor, a second thin film transistor, and a capacitor;

[0088] Among them, when the signal provided by the row scan signal Sn is at a low level, the first thin film transistor is turned on, and the voltage of the image data is transmitted to the gate of the second thin film transistor; when the signal provided by the row scan signal Sn is at a high level, the first thin film transistor is cut off, and the gate of the second thin film transistor maintains the data voltage unchanged until the first thin film transistor is turned on in the next cycle, and the voltage of the next frame of image data changes to refresh the gate voltage of the second thin film transistor. Among them, the conduction and cutoff of the second thin film transistor are determined by the data voltage provided by the image data, and the conduction time and cutoff time of the second thin film transistor are controlled by the pulse width modulation signal provided by the row scan signal Sn; the power supply is connected to the positive electrode of the corresponding OLED to control the conduction and cutoff of the current of the corresponding OLED; the function of the capacitor is to keep the gate voltage of the second thin film transistor unchanged, that is, the voltage remains after the capacitor is charged until the next data voltage change;

[0089] The image data has two logic states, logic '0' and logic '1', and the working state of the second thin film transistor of the pixel point is in the cutoff region and saturation region of the transfer characteristic curve.

[0090] Furthermore, in a column×row pixel matrix display OLED, according to the received image signal, each pixel driving circuit independently regulates a single pixel, and the image data driving circuit and the address driving circuit provide the image display signal and control signal output to the pixel matrix;

[0091] The address driving circuit outputs a row scanning signal, and the row scanning signal is loaded onto the gates of the thin-film transistors in each pixel driving circuit to turn on each pixel driving circuit in the pixel array row by row;

[0092] The image data driving circuit outputs a column scanning signal and simultaneously provides the gray-scale signal voltage required for each pixel;

[0093] After the first thin-film transistor is turned on, the gray-scale signal of each sub-pixel is output through the source driver and flows into the second thin-film transistor in the form of current. Since the OLED is a light-emitting diode, the pixel emits light; the gray-scale signal of each pixel is stored in the capacitor C in the form of voltage, and the display signal of the next frame image is refreshed. The light emission intensity and proportion of the OLED light-emitting diodes in the pixel driving circuits of the R pixels, G pixels, and B pixels determine the color and brightness of each pixel.

[0094] As Figure 3 and Figure 7 shown, the output interface circuit of the image algorithm compensation processing FPGA+Soc is a direct scanning driving circuit, including a column information image data module, a row information scanning decoding module, an ARM controller, and a clock module;

[0095] The ARM controller realizes the direct scanning driving of the column×row pixel matrix to display the OLED through the column information image data module and the row information scanning decoding module of the image algorithm compensation processing FPGA+Soc.

[0096] In this embodiment, as Figure 9 shown, the working principle of the R red pixel point driving circuit is as follows:

[0097] When the signal provided by the row scanning signal Sn is at a low level, the thin-film transistor Q 1R conducts, and the image data D 1R provides a voltage and transmits it to the gate of the thin-film transistor Q 2R ; when the signal provided by the row scanning signal Sn is at a high level, the thin-film transistor Q 1R is cut off, and the gate of the thin-film transistor Q 2R keeps the data voltage unchanged until the next cycle when the thin-film transistor Q 1R conducts, and the image data voltage of the next frame changes to refresh the gate voltage of the thin-film transistor Q 2R . Among them, the conduction and cut-off of the thin-film transistor Q 2R are determined by the data voltage provided by the image data D 1R , and the conduction time and cut-off time of the thin-film transistor Q 2R are controlled by the pulse width modulation signal provided by the row scanning signal Sn. The power supply Vdd is connected to the positive electrode of the OLED 1R to control the OLED 1RThe conduction and cut-off of the current; capacitor C 1R functions to keep the gate voltage of Q 2R unchanged. That is, the voltage is maintained after the capacitor is charged until the next data voltage change. Image data D 1R has two logic states, logic "0" and logic "1". The pixel thin-film transistor Q 2R operates in the cut-off region and saturation region of the transfer characteristic curve.

[0098] As Figure 9 shown, the working principle of the G green pixel driving circuit is as follows:

[0099] When the signal provided by the row scanning signal Sn is at a low level, the thin-film transistor Q 1G conducts, and the image data D 1G provides a voltage that is transmitted to the gate of the thin-film transistor Q 2G ; when the signal provided by the row scanning signal Sn is at a high level, the thin-film transistor Q 1G cuts off, and the gate of the thin-film transistor Q 2G maintains the data voltage unchanged until the next cycle when the thin-film transistor Q 1G conducts, and the image data voltage of the next frame changes, refreshing the gate voltage of the thin-film transistor Q 2G . Among them, the conduction and cut-off of the thin-film transistor Q 2G are determined by the data voltage provided by the image data D 1G , and the conduction time and cut-off time of the thin-film transistor Q 2G are controlled by the pulse width modulation signal provided by the row scanning signal Sn. The power supply Vdd is connected to the positive electrode of the OLED 1G to control the conduction and cut-off of the current of the OLED 1G ; capacitor C 1G functions to keep the gate voltage of Q 2G unchanged. That is, the voltage is maintained after the capacitor is charged until the next data voltage change. Image data D 1G has two logic states, logic "0" and logic "1". The pixel thin-film transistor Q 2G operates in the cut-off region and saturation region of the transfer characteristic curve.

[0100] As Figure 9 shown, the working principle of the B blue pixel driving circuit is as follows:

[0101] When the signal provided by the row scanning signal Sn is at a low level, the thin-film transistor Q 1B conducts, and the image data D 1B provides a voltage that is transmitted to the gate of the thin-film transistor Q 2B ; when the signal provided by the row scanning signal Sn is at a high level, the thin-film transistor Q 1BAs of now, the gate of thin-film transistor Q 2B holds the data voltage constant until the next cycle when thin-film transistor Q 1B conducts. When the data voltage of the next frame image changes, the gate voltage of thin-film transistor Q 2B is refreshed. Among them, the conduction and cutoff of thin-film transistor Q 2B are determined by the data voltage provided by image data D 1B . The conduction time and cutoff time of thin-film transistor Q 2B are controlled by the pulse-width modulation signal provided by the line scan signal Sn. Power supply Vdd is connected to the positive electrode of the OLED 1B , controlling the current conduction and cutoff of the OLED 1B . The function of capacitor C 1B is to keep the gate voltage of Q 2B unchanged, that is, the voltage remains after the capacitor is charged until the next data voltage change. Image data D 1B has two logic states, logic "0" and logic "1". The working state of the pixel thin-film transistor Q 2B is in the cutoff region and saturation region of the transfer characteristic curve.

[0102] The pixel points of the AMOLED display screen will continue to emit light until they are addressed again, and will remain until the next data voltage change, that is, the display scan time, corresponding to the delay of the CMS system.

[0103] In this embodiment, when the AMOLED display screen is 1280 columns × 1080 rows, or 1280 columns × 720 rows, the rows of the AMOLED display screen satisfy that they are integer multiples of n.

[0104] In this embodiment, the parameters of the CMOS image sensor are: image output format: YUV422; CMOS sensor resolution: 1920*1080; sensor frame rate ≥ 60fps. Display screen resolution 1280*720; display frame rate ≥ 60fps; wide dynamic range ≥ 120dB; display delay ≤ 45mS. The image information output interface is MIPI.

[0105] In this embodiment, the AMOLED display screen module includes a first AMOLED display screen 1280×(1~120), a second AMOLED display screen 1280×(121~240), a third AMOLED display screen 1280×(241~360), a fourth AMOLED display screen 1280×(361~480), a fifth AMOLED display screen 1280×(481~600), and a sixth AMOLED display screen 1280×(601~720), that is, it is composed of seven groups of individual display screens, and each display screen is an independent part, and each individual display screen has an input interface.

[0106] The described AMOLED display module is composed of six groups of displays respectively, which reduces the image information data, facilitates the improvement of the display frame rate, and can increase the frame rate range from 60 to 120 frames, or set the display frame rate under the condition of meeting relevant standards.

[0107] The function of the video image RGB conversion module is to convert the image data format into the corresponding video data for display on the display screen, including image information such as RGB format, corresponding pixel points, and pixel matrices.

[0108] The function of the image information segmentation module is to segment the image information with a resolution of 1920×1280 into 6 groups: 1920×(2~214), 1920×(215~427), 1920×(428~640), 1920×(641~853), 1920×(854~1066), 1920×(1067~1279). Among them, in the original image information of 1920×1280, the first column of 1920×1 and 1920×1280 is removed. Because after image operation compensation, post-processing of the image is still required and the number of rows and columns of the image information is reduced, it will not affect the overall image display.

[0109] The function of n image information transmission interfaces is to send the segmented image information to n groups of image algorithm compensation processing FPGA+Soc.

Claims

1. An electronic rearview mirror CMS with multiple FPGAs + Soc and a segmented display screen, characterized in that It includes a COMS image sensor, a DDR3 image data memory, an ARM central controller, a MIPI video decoding and distribution unit - FPGA + Soc, an image algorithm compensation processing module, and an AMOLED display module; the image algorithm compensation processing module includes n sets of image algorithm compensation processing FPGA + Soc; the AMOLED display module includes n individual AMOLED displays; The ARM central controller is respectively connected to the CMOS image sensor, the DDR3 image data memory, the MIPI video decoding and distribution unit - FPGA + Soc, and n sets of image algorithm compensation processing FPGA + Soc; the n sets of image algorithm compensation processing FPGA + Soc are respectively connected to the n individual AMOLED displays in a one-to-one manner; The ARM central controller sends a detection signal to the CMOS image sensor, and the CMOS image sensor outputs image information in MIPI format data; After the MIPI video decoding and distribution unit - FPGA + Soc receives the image information output by the CMOS image sensor, it decodes the image data, and divides the image information into n groups based on rows. The n sets of image algorithm compensation processing FPGA + Soc perform image distortion compensation on the image information. After the image information processing of the n sets of image algorithm compensation processing FPGA + Soc is completed, the compensated image data is output and transmitted to the corresponding individual AMOLED displays respectively; The MIPI video decoding and distribution unit - FPGA + Soc includes a video image information receiving module, a video image information decoding module, a VDMA image caching module, an image information preprocessing module, a video image RGB conversion module, an image information segmentation module, and n image information transmission interfaces connected in sequence; The video image information receiving module receives the MIPI format data transmitted by the COMS image sensor, and converts the serial data in MIPI format into parallel data and sends it to the video image information decoding module; The video image information decoding module analyzes different data packets according to the standard protocol, generates corresponding line and field synchronization signals, extracts the image data, converts the format of the image data, and transmits it to the VDMA image caching module; The MIPI image information data realizes the caching of the image through the VDMA image caching module; by ensuring that the image system has multiple frame buffers, the output data is not torn, the input and output rates of the image are coordinated, and the image is ensured to be stable; The image information preprocessing module sorts out the image information cached in the VDMA image caching module, analyzes the image, performs processing before feature extraction, segmentation, and matching of the input image, eliminates irrelevant information in the image, restores useful real information, improves the reliability of feature extraction, image segmentation, matching, and recognition, and sends the preprocessed image data to the video image RGB conversion module; The video image RGB conversion module converts the format of the image data into video data corresponding to the display of the display screen, and sends it to the image information segmentation module; The image information segmentation module divides the video data into n groups according to different resolutions and sends them to n groups of image algorithm compensation processing FPGA+Soc through n image information transmission interfaces respectively; The image algorithm compensation processing FPGA+Soc includes an ARM controller, a DDR3 image data memory, an image information transmission interface, an image correction function coefficient setting module, an image correction function and algorithm module, and an output interface circuit; In the image correction function coefficient setting module, two functions of image geometric distortion correction and image gray correction are adopted, including setting known reference points of the image, that is, the corresponding relationship between the coordinates of some pixel points of the undistorted image and the corresponding pixels of the distorted image, setting and calculating the unknown coefficients in the mapping relationship, and establishing a mathematical model for geometric correction; performing a spatial coordinate transformation on the image, establishing the row coordinate and column coordinate of the image pixel point, calculating the corresponding parameters, and determining the gray value of each pixel; In the image correction function and algorithm module, the image signal is converted into a digital signal, and then the digital signal is processed, including image filtering, image enhancement, image segmentation, image restoration and reconstruction, image feature extraction and image compression, to complete the color restoration of the image information, the horizontal uniformity, the vertical uniformity, the reproduction of brightness contrast, the reproduction of gray levels, and the correction of image geometric distortion; The output interface circuit adopts the LVDS image transmission mode to realize the transmission of high-dynamic images, connects to the corresponding separate AMOLED display screen, and can directly transmit the image output result to the column×row pixel matrix display OLED of the AMOLED display screen for direct display.

2. The electronic rearview mirror CMS with multiple FPGAs + Soc and a segmented display screen according to claim 1, characterized in that, The separate AMOLED display screen includes a power management module, an input interface circuit, an address driving circuit, an image data driving circuit, and a column×row pixel matrix display OLED; among them, the image data driving circuit includes an R-gamma correction and gray voltage generation module, a G-gamma correction and gray voltage generation module, and a B-gamma correction and gray voltage generation module; The power management module is connected to the input interface circuit, the address driving circuit, the image data driving circuit, and the column×row pixel matrix display OLED respectively; The image information input by the input interface circuit is decoded, and the decoded image information is input into the address driving circuit and the image data driving circuit respectively; According to the decoded image information, the image data driving circuit performs R pixel, G pixel, and B pixel corrections respectively through the R-GAMA correction and gray voltage generation module, the G-GAMA correction and gray voltage generation module, and the B-GAMA correction and gray voltage generation module to obtain the gray signal voltages required for the R pixel, G pixel, and B pixel, and then outputs an image display signal to the column×row pixel matrix display OLED; According to the decoded image information, the address driving circuit outputs an image control signal to the column×row pixel matrix display OLED; The column×row pixel matrix display OLED displays the image information according to the received image display signal and image control signal.

3. The electronic rearview mirror CMS with multiple FPGAs + Soc and a segmented display screen according to claim 2, characterized in that, In a column×row pixel matrix display OLED, the RGB pixel driving circuits form an AMOLED display screen, including R pixels, G pixels, and B pixels. Each pixel includes a TFT device and a storage capacitor, respectively constituting an R red pixel driving circuit, a G green pixel driving circuit, and a B blue pixel driving circuit. The 2TC circuit composed of two thin film transistors and a capacitor is used to achieve continuous lighting of the screen, and an external power supply provides voltage V DD provides a continuous current, and the magnitude of this current is controlled by the driving transistor T. That is, the gate voltage on the driving transistor T controls whether the current can flow through the channel of the first driving transistor T1 into the organic light emitting diode OLED. When the gate voltage of the driving transistor is not sufficient to turn on the first driving transistor T1, the first driving transistor T1 is in the off state, and no current enters the organic light emitting diode OLED, and this pixel point appears as an unlit state; When the gate voltage becomes an important switch, this switch is determined by the signal stored in the capacitor C.

4. The electronic rearview mirror CMS with multiple FPGAs + Soc and a segmented display screen according to claim 3, characterized in that, The R red pixel driving circuit, the G green pixel driving circuit, and the B blue pixel driving circuit all include a first thin-film transistor, a second thin-film transistor, and a capacitor. Among them, when the signal provided by the row scanning signal Sn is at a low level, the first thin-film transistor is turned on, and the voltage provided by the image data is transmitted to the gate of the second thin-film transistor; when the signal provided by the row scanning signal Sn is at a high level, the first thin-film transistor is turned off, and the gate of the second thin-film transistor maintains the data voltage unchanged until the next cycle when the first thin-film transistor is turned on, and the image data voltage of the next frame changes, refreshing the gate voltage of the second thin-film transistor; among them, the on and off of the second thin-film transistor are determined by the data voltage provided by the image data, and the on time and off time of the second thin-film transistor are controlled by the pulse width modulation signal provided by the row scanning signal Sn; the power supply is connected to the positive electrode of the corresponding OLED to control the conduction and cutoff of the current of the corresponding OLED; the function of the capacitor is to keep the gate voltage of the second thin-film transistor unchanged, that is, the voltage remains after the capacitor is charged until the next data voltage change. The image data has two logical states, logic '0' and logic '1', and the working state of the second thin-film transistor of the pixel is in the cut-off region and the saturation region of the transfer characteristic curve.

5. The electronic rearview mirror CMS with multiple FPGAs + Soc and a segmented display screen according to claim 4, characterized in that, In the column×row pixel matrix display OLED, according to the received image signal, each pixel driving circuit independently regulates a single pixel, and the image data driving circuit and the address driving circuit provide the image display signal and the control signal output to the pixel matrix. The address driving circuit outputs a row scanning signal, and the row scanning signal is loaded onto the gates of the thin-film transistors in each pixel driving circuit to sequentially turn on each pixel driving circuit in the pixel array. The image data driving circuit outputs a column scanning signal and simultaneously provides the gray-scale signal voltage required for each pixel. After the first thin-film transistor is turned on, the gray-scale signal of each sub-pixel is output by the source driver and flows into the second thin-film transistor in the form of current. OLED is a light-emitting diode, causing the pixel to emit light. The gray-scale signal of each pixel is stored in the form of voltage in the capacitor C and then the display signal of the next frame image is refreshed; in the pixel driving circuits of R pixels, G pixels, and B pixels OLED the light emission intensity and ratio of the light-emitting diodes determine the color and brightness of each pixel.

6. The electronic rearview mirror CMS with multiple FPGAs + Soc and a segmented display screen according to claim 5, wherein The output interface circuit of the image algorithm compensation processing FPGA+Soc is a direct scanning driving circuit, including a column information image data module, a row information scanning decoding module, an ARM controller, and a clock module. The ARM controller realizes the direct scanning driving of the column×row pixel matrix display OLED by the image algorithm compensation processing FPGA+Soc through the column information image data module and the row information scanning decoding module.

7. The electronic rearview mirror CMS with multiple FPGAs + Soc and a segmented display screen according to claim 1, characterized in that, n is an integer multiple of the number of rows in the AMOLED display resolution.

8. The electronic rearview mirror CMS with multiple FPGAs + Soc and a segmented display screen according to claim 1, wherein The parameters of the CMOS image sensor are image output format: YUV422; CMOS sensor resolution: 1920*1080; sensor frame rate ≥ 60fps; display screen resolution 1280*720; display frame rate ≥ 60fps; wide dynamic range ≥ 120dB; display delay ≤ 45mS; image information output interface is MIPI.

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