A fully synthetic precision measurement unit for integrated circuit testing

Abstract

This invention discloses a fully synthesized precision measurement unit for integrated circuit testing. The unit comprises a fully digital DAC module, a fully synthesized ADC module, and a gain measurement module. The fully digital DAC module is synthesized from a DDR-DDPM and LPF and is used to provide excitation for the device under test (DUT). The fully synthesized ADC is synthesized from a fully digital sub-DAC, a voltage comparator, and SAR logic and is used to read DUT data. The gain measurement module, comprised of analog components, provides gain and conversion between test vectors. This invention addresses the high cost of imported PMU chips, reduces capacitor parasitic effects, and improves accuracy.

Description

Technical Field

[0001] The present invention relates to the fields of circuit design and integrated circuit testing, and in particular to a fully synthetic precision measurement unit for integrated circuit testing. Background Art

[0002] Integrated circuit testing technology not only provides a strong guarantee for the correct development of integrated circuits, but also provides a scientific basis for the continuous improvement and perfection of integrated circuit design. Traditional integrated circuit testing technology primarily uses oscilloscopes and multimeters to measure chip pin parameters. This measurement method is not only costly, complex, and inaccurate, but also difficult to perform in large quantities, which significantly reduces measurement efficiency.

[0003] Large-scale integrated circuit (LSI) chip testing requires the design of high-speed, low-power, multi-channel test solutions to meet the demands of mass production. While domestic integrated circuit DC test systems have made some progress, they still lag behind similar foreign products. This gap is primarily reflected in the precision measurement units (PMUs) used in the test set. Of the various models of domestic DC parameter test systems on the market, 80% are small and medium-sized, with only a few utilizing computer-aided testing. Large-scale integrated circuit test systems such as the ICT-2, BC3170, and 3190 still have significant room for improvement due to factors such as price, reliability, and practicality.

[0004] Therefore, large-scale / ultra-large-scale integrated circuit test systems mainly rely on imports to solve domestic scientific research, production and application testing. In view of the above situation, improving the accuracy of PMU and reducing costs are the key to improving the performance of domestic test systems. Summary of the Invention

[0005] Purpose of the invention: The purpose of the present invention is to provide a fully synthetic precision measurement unit for integrated circuit testing, which reduces the influence of capacitor parasitic effects, improves the accuracy of PMU and reduces costs.

[0006] The technical solution is as follows: a fully synthesized precision measurement unit for integrated circuit testing, including a gain measurement module composed of a fully digital digital-to-analog converter (DAC), a fully synthesized analog-to-digital converter (ADC), and analog components. The fully digital DAC and fully synthesized ADC are implemented using an FPGA.

[0007] The all-digital DAC module uses FPGA and LPF to synthesize the all-digital DAC module. The FPGA inputs pulses with different duty cycles to the low-pass filter (LPF). After filtering by the low-pass filter (LPF), a low-ripple DC voltage output is achieved, realizing the function of the DAC and providing excitation for the gain measurement module.

[0008] The fully synthesized ADC module is composed of a fully digital sub-DAC, a voltage comparator and SAR logic, and is used to collect measurement information of the DUT and realize the conversion of analog information to digital information;

[0009] The gain measurement module is composed of analog components and includes multiple gain amplifiers. It can convert voltage excitation into current excitation and provide clamping protection functions, and measure the DUT through FVMI and FIMV methods.

[0010] Furthermore, the all-digital DAC module is synthesized based on the DDR-DDPM method. The DDR-DDPM method interleaves the duty cycle of the traditional PWM method and uses a double-edge D flip-flop to implement a shift register to output pulse code. The output of the N-bit all-digital DAC module is expressed as:

[0011]

[0012] Among them, D i Indicates the enable status of the i-th group of pulse shift registers, which is 1 if enabled and 0 if not. V DD Indicates the high-level voltage value that the FPGA pin can output.

[0013] This invention improves upon the binary digital pulse modulator (DDPM) and proposes a double data rate binary digital pulse modulation (DDR-DDPM) method. This method utilizes double-edge-edged D-type flip-flops to form a binary pulse-encoded shift register, achieving faster pulse output. Furthermore, an external low-pass filter (LPF) removes the harmonic components of the rectangular pulse, preserving its DC component. This achieves a low-ripple DC voltage output, providing input voltage for the subsequent PMU module.

[0014] Furthermore, the fully digital sub-DAC has the same structure as the fully digital DAC module, but is not the same module. As a sub-DAC in the fully synthesized ADC module, the fully digital sub-DAC continuously provides different voltages to the voltage comparator according to the SAR ADC method.

[0015] The voltage comparator compares the output value of the fully digital sub-DAC with the analog input value, outputs a digital value of 0 or 1 as the comparison result to represent the magnitude relationship between the two voltage values, and inputs the comparison result into the SAR logic in binary code; the voltage comparator is the main channel for the fully synthesized ADC module to convert the analog domain into the digital domain.

[0016] The SAR logic receives a comparison result of the voltage comparator and controls the output value of the full-digital sub-DAC according to the comparison result.

[0017] The ultimate goal of the fully synthesized ADC module is to enable the output of the fully digital sub-DAC module to continuously approach the analog input voltage according to SAR logic through information interaction between the three sub-modules, and ultimately record the digital value feedback from the comparator, thereby realizing the analog-to-digital conversion function.

[0018] Furthermore, the SAR logic controls the output of the fully digital sub-DAC according to a binary search algorithm by receiving the digital value transmitted by the voltage comparator, wherein the output of the fully digital sub-DAC can be expressed as:

[0019]

[0020] Where k∈[1,N-1] represents the number of real-time comparisons of the fully synthesized ADC; N is the number of bits of the fully synthesized ADC; V k Represents the output voltage value of the fully digital sub-DAC module at the kth comparison, where

[0021]

[0022] b k is the output value of the voltage comparator during the kth comparison, V DD Indicates the high-level voltage value that the FPGA pin can output.

[0023] Furthermore, the gain measurement module uses the fully digital DAC module as the excitation control path and the fully synthesized ADC module as the precision measurement circuit, employing Kelvin connections to implement flow measurement by pressure (FVMI) and flow measurement by pressure (FIMV). Its resolution is determined by the resolution of the specifically designed fully digital DAC and fully synthesized ADC.

[0024] Beneficial effects: Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1. The present invention realizes a fully synthetic precision measurement unit for integrated circuit testing through a fully synthetic method without the need for an integrated process and without the need for imported PMU chips and AD / DA.

[0026] 2. The present invention realizes AD / DA and a digital auxiliary interface for the PMU unit by adopting a digital synthesis method, thereby eliminating the parasitic effect problem in the integration process, improving the PMU accuracy and reducing the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is the overall system architecture diagram of the fully synthetic precision measurement unit of the present invention;

[0028] Figure 2 This is the DDR-DDPM timing diagram;

[0029] Figure 3 This is the system structure diagram for a multi-channel test scenario. DETAILED DESCRIPTION

[0030] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0031] The fully synthetic precision measurement unit designed by the present invention utilizes a fully digital digital-to-analog converter (DAC) and a fully synthetic analog-to-digital converter (ADC) as well as analog components to form a PMU unit, wherein the fully digital DAC and the fully synthetic ADC are implemented using FPGA.

[0032] The present invention is mainly composed of three modules, including a full digital DAC module, a full synthesis ADC module and a gain measurement module. Its overall system architecture is as follows Figure 1 shown.

[0033] The all-digital DAC module of the present invention is improved on the basis of binary digital pulse modulation (Dyadic Digital Pulse Modulator, DDPM), and a DDR-DDPM (Double Data Rate-Dyadic Digital Pulse Modulator, DDR-DDPM) is proposed, which uses a double-edge D flip-flop to form a binary pulse coded shift register to achieve faster pulse output. Secondly, the external circuit is equipped with a low-pass filter (LPF) to filter out the harmonic components of the rectangular pulse and preserve its DC component to achieve a low-ripple DC voltage output function and provide input voltage for the subsequent PMU module. The timing diagram of DDR-DDPM taking N=4bit as an example is as follows Figure 2 As shown. Then the output of the N-bit all-digital DAC module can be expressed as:

[0034]

[0035] Among them, D i Indicates the enable status of the i-th group of pulse shift registers, which is 1 if enabled and 0 if not. V DD Indicates the high-level voltage value that the FPGA pin can output. Figure 2 In the specific embodiment, the final output only enables D1 and D3, so the final DAC output voltage value is:

[0036]

[0037] The fully synthesized ADC module includes three sub-modules, namely a fully digital sub-DAC module, a voltage comparator module and a successive approximation register (SAR) logic module.

[0038] The fully digital sub-DAC module in the fully synthesized ADC module is implemented in the same way as the aforementioned fully digital DAC module, but is not the same module. This module, as a sub-DAC in the fully synthesized ADC module, continuously provides different voltages to the voltage comparator according to the SAR ADC method.

[0039] The voltage comparator module compares the analog input voltage to be measured with the output voltage of the fully digital sub-DAC module, and outputs a digital value of 0 or 1 to represent the magnitude relationship between the two voltage values. This module is the main channel for the fully integrated ADC module to convert the analog domain into the digital domain.

[0040] The SAR logic module controls the output of the full-digital sub-DAC module according to the binary search algorithm by receiving the digital value transmitted by the voltage comparator module. The output of the full-digital sub-DAC module can be expressed as:

[0041]

[0042] Where k∈[1,N-1] represents the number of real-time comparisons of the fully synthesized ADC; N is the number of bits of the fully synthesized ADC; V k Represents the output voltage value of the fully digital sub-DAC module at the kth comparison, where b k is the output value of the voltage comparator during the kth comparison.

[0043] The ultimate goal of the fully synthesized ADC module is to make the output of the fully digital sub-DAC module continuously approach the analog input voltage according to the SAR logic through information interaction between the three sub-modules, and finally record the digital value result {b1, b2, ..., b N}, thereby realizing the analog to digital conversion function.

[0044] The resolution of the PMU of the present invention is determined by the resolution of the specifically designed all-digital DAC and fully synthesized ADC. In specific implementations, it is generally necessary to ensure that the all-digital DAC module and the fully synthesized ADC module have the same resolution, and this resolution is equal to the resolution of the PMU of the present invention.

[0045] The gain measurement module uses the all-digital DAC module as an excitation control path and the fully synthesized ADC module as a precision measurement circuit, and adopts the Kelvin connection method to realize the functions of flow measurement by pressure (FVMI) and flow measurement by pressure (FIMV).

[0046] The gain measurement module has multiple gain amplifiers inside, such as Figure 1 As shown in the figure, G1 is an input power amplifier with a gain of 4, which can amplify the voltage input by FIN by 4 times to achieve ±4V. DD The voltage excitation range is 100 nm. G2 is the current sense amplifier, and G3 is the voltage sense amplifier. CPL and CPH are voltage clamps responsible for preventing DUT overload. CLH > CLL must be satisfied. MEASOUT is the measured value output. This line information serves as the analog input value for the fully synthesized ADC module.

[0047] In a specific embodiment, if the gain measurement module works in the pressure measurement mode, S1 is closed, S2 is open, and S3 is connected to P2. In this mode, the voltage V DUT There are three situations:

[0048] Case 1: If V CLL DUT ×R s ×16 <V CLH , then V DUT =4×V DAC .

[0049] Case 2: If I DUT ×R s ×16>V CLH , then V DUT =4×V CLH .

[0050] Case 3: If I DUT ×R s ×16 <V CLL , then V DUT =4×V CLL .

[0051] Among them, the test can be carried out normally only under the condition of situation 1.

[0052] In a specific embodiment, if the gain measurement module works in the current-adding pressure measurement mode, S1 is open, S2 is closed, and S3 is connected to P1. At this time, the excitation current value is:

[0053]

[0054] In this mode, the voltage across the chip under test (DUT) is V DUT There are three situations:

[0055] Case 1: If V CLL <V DUT <V CLH , then I DUT ​=4×V DAC / R s .

[0056] Case 2: If V DUT >V CLH , then I DUT =4×V CLH / R s .

[0057] Case 3: If V DUT <V CLL , then I DUT =4×V CLL / R s .

[0058] Among them, the test can be carried out normally only under the condition of situation 1.

[0059] The present invention uses a fully digital DAC and a fully synthetic ADC based on the DDR-DDPM method to achieve a fully synthetic PMU. While replacing imported PMU chips, the circuit does not contain a capacitor array, which also reduces errors caused by capacitor parasitic effects. In addition, the present invention can fully utilize the pin resources and board area resources of the FPGA to perform multi-channel testing, and then rely on the PCI bus to interact with the host computer for data. Its multi-channel specific implementation is as follows: Figure 3 As shown, the connection between the FPGA and the double-headed arrow represents the all-digital DAC module and the fully synthesized ADC module.

[0060] The present invention provides a fully synthesized precision measurement unit for integrated circuit testing. This unit comprises a fully digital DAC module, a fully synthesized ADC module, and a gain measurement module. The fully digital DAC module, synthesized from a DDR-DDPM and LPF, provides excitation for the device under test (DUT). The fully synthesized ADC, synthesized from a fully digital sub-DAC, a voltage comparator, and SAR logic, reads DUT data. The gain measurement module, comprised of analog components, provides gain and conversion between test vectors. This invention addresses the high cost of imported PMU chips, reduces capacitor parasitics, and improves accuracy.

[0061] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A fully synthetic precision measurement unit for integrated circuit testing, characterized in that: include: Fully digital DAC module, fully synthesized ADC module, gain measurement module; The all-digital DAC module is synthesized by FPGA and low-pass filter LPF. The FPGA inputs pulses of different duty cycles to the low-pass filter LPF, and after filtering by the low-pass filter LPF, a low-ripple DC voltage output is achieved, thereby realizing the function of DAC and providing excitation for the gain measurement module. The fully synthesized ADC module is composed of a fully digital sub-DAC, a voltage comparator and SAR logic, and is used to collect measurement information of the DUT and realize the conversion of analog information to digital information; The gain measurement module is composed of analog components and includes multiple gain amplifiers. It can convert voltage excitation into current excitation and provide clamping protection functions, and measure the DUT through FVMI and FIMV methods.

2. A fully synthetic precision measurement unit for integrated circuit testing according to claim 1, characterized in that: The all-digital DAC module is synthesized based on the DDR-DDPM method. The DDR-DDPM method interleaves the duty cycle of the traditional PWM method and uses a double-edge D flip-flop to implement a shift register to output pulse codes. The output of the N-bit all-digital DAC module is expressed as: Among them, D i Indicates the enable status of the i-th group of pulse shift registers, which is 1 if enabled and 0 if not. V DD Indicates the high-level voltage value that the FPGA pin can output.

3. A fully synthetic precision measurement unit for integrated circuit testing according to claim 1, characterized in that: The fully digital sub-DAC has the same structure as the fully digital DAC module; The voltage comparator compares the output value of the fully digital sub-DAC with the analog input value, and inputs the comparison result into the SAR logic in binary code; The SAR logic receives a comparison result of the voltage comparator and controls the output value of the full-digital sub-DAC according to the comparison result.

4. A fully synthetic precision measurement unit for integrated circuit testing according to claim 3, characterized in that: The SAR logic controls the output of the fully digital sub-DAC according to a binary search algorithm by receiving the digital value transmitted by the voltage comparator, wherein the output of the fully digital sub-DAC can be expressed as: Where k∈[1,N-1] represents the number of real-time comparisons of the fully synthesized ADC; N is the number of bits of the fully synthesized ADC; V k Represents the output voltage value of the fully digital sub-DAC module at the kth comparison, where b k is the output value of the voltage comparator during the kth comparison, V DD Indicates the high-level voltage value that the FPGA pin can output.

5. The fully synthetic precision measurement unit for integrated circuit testing according to claim 1, characterized in that: The low-pass filter LPF filters out the harmonic components of the rectangular pulse, preserves its DC component, and realizes a low-ripple DC voltage output function.

6. A fully synthetic precision measurement unit for integrated circuit testing according to claim 1, characterized in that: The gain measurement module uses the all-digital DAC module as an excitation control path and the fully synthesized ADC module as a precision measurement circuit, and adopts the Kelvin connection method to realize the functions of pressure-added flow measurement FVMI and flow-added pressure measurement FIMV.

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