A nested delay locked loop circuit and vernier time-to-digital converter

Abstract

The present invention discloses a nested delay locked loop circuit and a vernier time digital converter, wherein the nested delay locked loop circuit comprises an M-level voltage-controlled delay chain, a first N-level voltage-controlled delay chain, a second N-level voltage-controlled delay chain, a first phase detector, a second phase detector, a third phase detector, a first charge pump, a second charge pump, a third charge pump, a first loop filter capacitor, a second loop filter capacitor, a third loop filter capacitor, and an M-to-1 selector. The present invention adopts a multi-level nested delay locked loop, which can not only suppress the delay of the delay unit from shifting with PVT, but also can efficiently realize the fast and slow delay units with a specific proportional relationship in delay, so that the vernier time digital converter does not need to perform redundant operations when merging multiple segments of data, thereby reducing the complexity and power consumption of data processing.

Description

Technical Field

[0001] The present invention relates to the technical field of time-to-digital converters, and more specifically, to a nested delay-locked loop circuit and a vernier-type time-to-digital converter. Background Art

[0002] The time-to-digital converter (TDC) based on the vernier ring delay chain is a vernier-type time-to-digital converter architecture that has the advantages of high resolution and large range, while occupying a small area, and is an important architecture for achieving high dynamic range TDC. This TDC is widely used in pulsed LiDAR systems for autonomous driving, assisting LiDAR systems to accurately detect and distinguish objects within a range of hundreds of meters centered on the vehicle.

[0003] like Figure 1 As shown, the TDC architecture based on the vernier ring delay chain includes: a preprocessing circuit detects the rising edge of the electrical signal (START / STOP) representing the laser pulse emission and reception time, and shapes it into a narrow pulse signal; the vernier ring delay chain quantifies the time difference of the START / STOP pulse; the data processing module includes a counter, a decoder, a segmented data merging circuit and a serial output interface circuit to generate the final quantized flight time; a double-delay-locked delay locking loop (also called a double-delay-locked loop) provides two delay control voltages for the vernier ring delay chain circuit.

[0004] The basic principle of TDC based on vernier ring delay chain is to make the two pulse signals representing the emission and reception time propagate in the slow and fast ring delay chains respectively, and catch up with the delay difference between the slow and fast delay units as the time resolution, and finally identify the catch-up time of the two pulse signals through the arbitrator. The flight time of the laser pulse will be determined by the count value of the slow and fast ring delay chains and the catch-up time of the pulse signal in the two chains.

[0005] The flight time of a single measurement of the vernier ring delay chain TDC can be expressed as

[0006] T=A1·(Bt SLOW )+A2·[B(t SLOW -V FAST )]+A3·(t SLOW -t FAST )

[0007] Among them, t SLOW ,t FAST are the delays of the slow and fast delay units respectively; A1 is the count value of the slow delay chain; A2 is the count value of the fast delay chain; A3 is the catch-up moment of the pulse signal output by the arbitrator in the two chains; B is the number of delay units on the ring delay chain (the number of delay units in the fast and slow delay chains is the same).

[0008] Ideally, the resolution of the TDC based on the vernier ring delay chain is the difference between the delays of the delay units of the two ring delay chains, and is not limited by the minimum gate delay of the process. However, the delay unit is easily affected by the process, power supply voltage, and temperature (PVT). Therefore, a delay-locked loop (DLL) is needed to perform closed-loop control of the delay unit to prevent the delay unit from shifting with PVT. The TDC based on the vernier ring delay chain requires two voltages to control the fast and slow delay chains.

[0009] like Figure 2 As shown in the figure, the double delay lock loop of the classic scheme is composed of a DLL of an M-level delay chain and a DLL of an N-level delay chain, and the fast and slow delays generated are At this time, the resolution of TDC is This structure generates t SLOW :t SLOW -t FAST The lack of a quadratic relationship means that after TDC segment quantization, multiplication, division, and summation circuits are required to normalize the resolution of each segment and merge the data, which increases the complexity of the implementation and occupies a larger area.

[0010] like Figure 3 As shown in Figure 1, a research team proposed a master-slave delay lock loop to replace the traditional solution, connecting two adjacent nodes on the master DLL delay chain as the reference clock of the slave DLL. The master DLL controls the slow delay to Controlling T from DLL P(x) +t SLOW N = T P(x+1) +t FAST N, the TDC resolution By setting N to a power of two, t SLOW :t SLOW -t FAST When merging the three quantized data, there is no need to use multiplication, division, and summation operations. Instead, the quantized values ​​only need to be latched into the register, which reduces the complexity of data processing. However, due to cost considerations, the high-quality reference clock T REF Use a lower frequency (less than 100 MHz) crystal oscillator to generate. In order to achieve a resolution below 10ps, the number of delays in each delay chain of the master-slave DLL must be at least dozens, which causes power consumption and area consumption to a certain extent, and it is difficult to match each delay unit with a longer delay chain. DLL locking can only ensure that the total delay of the delay chain is the reference clock cycle, but it is difficult to ensure that the delay of each delay unit is uniform, resulting in TDC quantization deviation. Summary of the invention

[0011] In order to solve the above shortcomings and defects in the prior art, the present invention provides a nested delay locked loop circuit and a vernier time-to-digital converter.

[0012] In order to achieve the above-mentioned purpose of the present invention, the technical scheme adopted is as follows:

[0013] A nested delay locked loop circuit comprises an M-level voltage-controlled delay chain, a first N-level voltage-controlled delay chain, a second N-level voltage-controlled delay chain, a first phase detector, a second phase detector, a third phase detector, a first charge pump, a second charge pump, a third charge pump, a first loop filter capacitor, a second loop filter capacitor, a third loop filter capacitor, and an M-to-1 selector;

[0014] The input end of the M-level voltage-controlled delay chain is used to input an off-chip low-frequency clock, the first input end of the first phase detector is electrically connected to the output end of the M-level voltage-controlled delay chain; the second input end of the first phase detector is used to input an off-chip low-frequency clock;

[0015] The output end of the first phase detector is electrically connected to the input end of the first charge pump; the output end of the first charge pump outputs a first voltage-controlled voltage; at the same time, the output end of the first charge pump is also electrically connected to each delay unit in the M-level voltage-controlled delay chain and one end of the first loop filter capacitor; the other end of the first loop filter capacitor is grounded;

[0016] The selection end of the M-to-1 selector is electrically connected to the output end of each delay unit in the M-level voltage-controlled delay chain; the control end of the M-to-1 selector is used to input the control word K; the output end of the M-to-1 selector is electrically connected to the first input end of the second phase detector;

[0017] The input end of the first N-stage voltage-controlled delay chain is used to input an off-chip low-frequency clock, and the output end of the first N-stage voltage-controlled delay chain is electrically connected to the second input end of the second phase detector;

[0018] The output end of the second phase detector is electrically connected to the output end of the second charge pump; the output end of the second charge pump is used to output a second voltage-controlled voltage; at the same time, the output end of the second charge pump is also electrically connected to each delay unit in the first N-stage voltage-controlled delay chain and one end of the second loop filter capacitor; the other end of the second loop filter capacitor is grounded;

[0019] The first input terminal of the third phase detector is electrically connected to the output terminal of the N-1th delay unit in the first N-stage voltage-controlled delay chain;

[0020] The input end of the second N-stage voltage-controlled delay chain is used to input an off-chip low-frequency clock, and the output end of the second N-stage voltage-controlled delay chain is electrically connected to the second input end of the third phase detector;

[0021] The output end of the third phase detector is electrically connected to the input end of the third charge pump; the output end of the third charge pump outputs a third voltage-controlled voltage; at the same time, the output end of the third charge pump is also electrically connected to each delay unit in the second N-stage voltage-controlled delay chain and one end of the third loop filter capacitor; the other end of the third loop filter capacitor is grounded.

[0022] Preferably, the M-stage voltage-controlled delay chain, the first phase detector, the first charge pump, and the first loop filter capacitor constitute a first-stage delay lock loop;

[0023] The first N-stage voltage-controlled delay chain, the second phase detector, the second charge pump, and the second loop filter capacitor constitute a second-stage delay locking loop;

[0024] The second N-stage voltage-controlled delay chain, the third phase detector, the third charge pump, and the third loop filter capacitor form a third-stage delay locking loop.

[0025] Furthermore, a fourth-stage delay locked loop may be nested after the third-stage delay locked loop.

[0026] Further, the fourth-stage delay locked loop includes a third N-stage voltage-controlled delay chain, a fourth phase detector, a fourth charge pump, and a fourth loop filter capacitor;

[0027] A first delay unit is added at the output end of the second N-stage voltage-controlled delay chain; and the output of the third charge pump is electrically connected to the first delay unit;

[0028] The input end of the third N-stage voltage-controlled delay chain is used to input an off-chip low-frequency clock; the output end of the third N-stage voltage-controlled delay chain is electrically connected to the first input end of the fourth phase detector;

[0029] The second input terminal of the fourth phase detector is electrically connected to the output terminal of the first delay unit;

[0030] The output end of the fourth phase detector is electrically connected to the input end of the fourth charge pump; the output end of the fourth charge pump outputs a fourth voltage-controlled voltage; at the same time, the output end of the fourth charge pump is also electrically connected to each delay unit in the third N-stage voltage-controlled delay chain and one end of the fourth loop filter capacitor; the other end of the fourth loop filter capacitor is grounded.

[0031] Furthermore, the first-stage delay locked loop realizes the off-chip low-frequency clock T REFPropagation in the M-stage voltage-controlled delay chain, comparing the phase of the clock signal propagated through the M-stage voltage-controlled delay chain with the phase of the original reference clock signal through a first phase detector, and outputting a first phase difference;

[0032] The first charge pump generates a corresponding current according to the first phase difference output by the first phase detector, and charges or discharges the first loop filter capacitor to adjust the voltage control voltage value of the M-level voltage-controlled delay chain and control the unit delay of the M-level voltage-controlled delay chain; the phase of the clock signal propagated through the M-level voltage-controlled delay chain changes until it is aligned with the phase of the original reference clock; after the phase is aligned, the first-level delay locking loop is locked, and at this time the unit delay of the M-level voltage-controlled delay chain is

[0033] Furthermore, the second-stage delay locked loop realizes the off-chip low-frequency clock T REF Propagation in the first N-stage voltage-controlled delay chain, comparing the phase of the clock signal propagated through the first N-stage voltage-controlled delay chain with the phase of the output signal of the M-to-1 selector through a second phase detector, and outputting a second phase difference;

[0034] The second charge pump generates a corresponding current according to the second phase difference to charge or discharge the second loop filter capacitor to adjust the voltage control voltage value of the first N-stage voltage-controlled delay chain to control the unit delay of the first N-stage voltage-controlled delay chain;

[0035] The phase of the clock signal propagated through the first N-stage voltage-controlled delay chain changes until it is aligned with the phase of the output signal of the M-to-1 selector; after the phase is aligned, the second-stage delay lock loop is locked, and the unit delay of the first N-stage voltage-controlled delay chain is The second voltage-controlled voltage V of the first N-stage voltage-controlled delay chain SLOW Acting on the slow chain delay unit of the time-to-digital converter, the slow delay is

[0036] Furthermore, the third-stage delay locked loop realizes the off-chip low-frequency clock T REF During propagation in the second N-stage voltage-controlled delay chain, the phase of the Nth delay unit of the clock signal propagating through the second N-stage voltage-controlled delay chain is compared with the phase of the N-1th delay unit in the first N-stage voltage-controlled delay chain through a third phase detector, and a third phase difference is outputted;

[0037] The third charge pump generates a corresponding current according to the third phase difference to charge or discharge the third loop filter capacitor to adjust the voltage control voltage value of the second N-stage voltage-controlled delay chain to control the unit delay of the second N-stage voltage-controlled delay chain;

[0038] The phase of the Nth delay unit of the clock signal propagated through the second N-stage voltage-controlled delay chain changes until it is aligned with the phase of the N-1th delay unit in the first N-stage voltage-controlled delay chain; after the phase is aligned, the third-stage delay lock loop is locked, and the unit delay of the second N-stage voltage-controlled delay chain is The third voltage-controlled voltage V of the second N-stage voltage-controlled delay chain FAST The fast chain delay unit that can be used for the time-to-digital converter is

[0039] Furthermore, the fourth-stage delay locked loop realizes the off-chip low-frequency clock T REF Propagation in the third N-stage voltage-controlled delay chain, comparing the phase of the clock signal propagated through the third N-stage voltage-controlled delay chain with the phase of the output signal of the first delay unit through a fourth phase detector, and outputting a fourth phase difference;

[0040] The fourth charge pump generates a corresponding current according to the fourth phase difference to charge or discharge the fourth loop filter capacitor to adjust the voltage control voltage value of the third N-stage voltage-controlled delay chain to control the unit delay of the third N-stage voltage-controlled delay chain;

[0041] The phase of the clock signal propagated through the third N-stage voltage-controlled delay chain changes until it is aligned with the phase of the output signal of the first delay unit; after the phase is aligned, the fourth-stage delay lock loop is locked, and the unit delay of the third N-stage voltage-controlled delay chain is The fourth voltage-controlled voltage V FAST2 The fast chain delay unit that can be used for the time-to-digital converter is

[0042] A vernier time-to-digital converter, comprising the nested delay-locked loop circuit, preprocessing circuit, vernier ring delay chain, data processing and output interface as described above;

[0043] The preprocessing circuit is used to detect the rising edge of the electrical signal pulse at the time of laser pulse emission and reception, and shape it into a narrow pulse signal;

[0044] The vernier annular delay chain quantifies the time difference of the electrical signal pulses;

[0045] The nested delay locked loop circuit provides two voltage-controlled voltages for the vernier ring delay chain circuit;

[0046] The data processing module generates the final quantized flight time from the electrical signal pulse output by the vernier ring delay chain circuit.

[0047] Preferably, the vernier ring delay chain circuit comprises a slow chain delay unit and a fast chain delay unit;

[0048] The second voltage-controlled voltage V of the first N-stage voltage-controlled delay chain SLOW The third voltage-controlled voltage V acting on the slow chain delay unit of the vernier ring delay chain circuit and the second N-stage voltage-controlled delay chain FAST A fast chain delay unit acting on a vernier ring delay chain circuit;

[0049] Or the second voltage-controlled voltage V of the first N-stage voltage-controlled delay chain SLOW The fourth voltage-controlled voltage V acting on the slow chain delay unit of the vernier ring delay chain circuit and the third N-stage voltage-controlled delay chain FAST2 Acting on the fast chain delay unit of the vernier ring delay chain circuit, the fast delay is

[0050] The beneficial effects of the present invention are as follows:

[0051] The present invention adopts a multi-level nested delay locking loop, which can not only suppress the delay of the delay unit from shifting with the PVT, but also can efficiently realize the fast and slow delay units with delays in a specific proportional relationship. No redundant calculations are required when merging data, thereby reducing the complexity and power consumption of data processing.

[0052] In addition, the present invention can achieve a time resolution of less than 10 ps when a relatively low frequency crystal oscillator clock signal is input without requiring a large number of delay units.

[0053] The present invention introduces a nested delay locking loop into a vernier time digital converter, which significantly reduces the number of required delay units while achieving controllable fast and slow delay ratios and high resolution, and reduces the complexity of data merging after segmented quantization of the vernier time digital converter. The resolution of the TDC can be configured by adjusting an external control word. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 It is based on the vernier ring delay chain TDC architecture.

[0055] Figure 2 It is a typical DLL architecture with a double delay locked loop.

[0056] Figure 3 It is a master-slave DLL architecture with dual delay locked loops.

[0057] Figure 4 4 is a circuit diagram of the nested delay locked loop circuit described in Example 1.

[0058] Figure 5 4 is a circuit diagram of the nested delay locked loop circuit described in Example 2.

[0059] Figure 6 is based on Figure 4 Circuit block diagram of the vernier time-to-digital converter of the nested delay locked loop circuit.

[0060] Figure 7 is based on Figure 4 Schematic diagram of the change of the delay chain voltage control value during the locking process of the nested delay locked loop circuit.

[0061] Figure 8 is based on Figure 4 A schematic diagram of the variation of the delay time during the locking process of the nested delay locked loop circuit.

[0062] Fig. 9 This is the Monte Carlo simulation result without delay locking loop.

[0063] Fig.10 This is the Monte Carlo simulation result of delay using the nested delay locked loop described in Example 1.

[0064] Fig.11 This is the Monte Carlo simulation result of the fast and slow delay differences using the nested delay locked loop described in Example 1.

[0065] In the figure, 1-M-level voltage-controlled delay chain, 2-first phase detector, 3-first charge pump, 4-first loop filter capacitor, 5-M-to-1 selector, 6-first N-level voltage-controlled delay chain, 7-second phase detector, 8-second charge pump, 9-second loop filter capacitor, 10-second N-level voltage-controlled delay chain, 11-third phase detector, 12-third charge pump, 13-third loop filter capacitor, 14-third N-level voltage-controlled delay chain, 15-fourth phase detector, 16-fourth charge pump, 17-fourth loop filter capacitor, 18-first delay unit. DETAILED DESCRIPTION

[0066] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0067] Example 1

[0068] The core component of the vernier time-to-digital converter is the delay lock loop. The delay lock loop is the time standard ruler of the TDC, and its performance directly affects the key indicators of the TDC linearity and resolution. Therefore, the core work of the vernier time-to-digital converter with controllable delay ratio is to realize the delay lock loop with controllable delay ratio.

[0069] like Figure 4As shown, a nested delay locked loop circuit includes an M-level voltage-controlled delay chain 1, a first N-level voltage-controlled delay chain 6, a second N-level voltage-controlled delay chain 10, a first phase detector 2, a second phase detector 7, a third phase detector 11, a first charge pump 3, a second charge pump 8, a third charge pump 12, a first loop filter capacitor 4, a second loop filter capacitor 9, a third loop filter capacitor 13, and an M-to-1 selector 5;

[0070] The input end of the M-level voltage-controlled delay chain 1 is used to input an off-chip low-frequency clock, the first input end of the first phase detector 2 is electrically connected to the output end of the M-level voltage-controlled delay chain 1; the second input end of the first phase detector 2 is used to input an off-chip low-frequency clock;

[0071] The output end of the first phase detector 2 is electrically connected to the input end of the first charge pump 3; the output end of the first charge pump 3 outputs a first voltage-controlled voltage; at the same time, the output end of the first charge pump 3 is also electrically connected to each delay unit in the M-level voltage-controlled delay chain 1 and one end of the first loop filter capacitor 4; the other end of the first loop filter capacitor 4 is grounded;

[0072] The selection end of the M-to-1 selector 5 is electrically connected to the output end of each delay unit in the M-level voltage-controlled delay chain 1; the control end of the M-to-1 selector 5 is used to input the control word K; the output end of the M-to-1 selector 5 is electrically connected to the first input end of the second phase detector 7;

[0073] The input end of the first N-stage voltage-controlled delay chain 6 is used to input an off-chip low-frequency clock, and the output end of the first N-stage voltage-controlled delay chain 6 is electrically connected to the second input end of the second phase detector 7;

[0074] The output end of the second phase detector 7 is electrically connected to the output end of the second charge pump 8; the output end of the second charge pump 8 is used to output the second voltage-controlled voltage; at the same time, the output end of the second charge pump 8 is also electrically connected to each delay unit in the first N-stage voltage-controlled delay chain 6 and one end of the second loop filter capacitor 9; the other end of the second loop filter capacitor 9 is grounded;

[0075] The first input terminal of the third phase detector 11 is electrically connected to the output terminal of the N-1th delay unit in the first N-stage voltage-controlled delay chain 6;

[0076] The input end of the second N-stage voltage-controlled delay chain 10 is used to input an off-chip low-frequency clock, and the output end of the second N-stage voltage-controlled delay chain 10 is electrically connected to the second input end of the third phase detector 11;

[0077] The output end of the third phase detector 11 is electrically connected to the input end of the third charge pump 12; the output end of the third charge pump 12 outputs a third voltage-controlled voltage; at the same time, the output end of the third charge pump 12 is also electrically connected to each delay unit in the second N-stage voltage-controlled delay chain 10 and one end of the third loop filter capacitor 13; the other end of the third loop filter capacitor 13 is grounded.

[0078] In this embodiment, the M-stage voltage-controlled delay chain 1, the first N-stage voltage-controlled delay chain 6, and the second N-stage voltage-controlled delay chain 10 all adopt 16-stage voltage-controlled delay chains.

[0079] In a specific embodiment, the M-level voltage-controlled delay chain 1, the first phase detector 2, the first charge pump 3, and the first loop filter capacitor 4 constitute a first-level delay lock loop;

[0080] The first N-stage voltage-controlled delay chain 6, the second phase detector 7, the second charge pump 8, and the second loop filter capacitor 9 constitute a second-stage delay lock loop;

[0081] The second N-stage voltage-controlled delay chain 10, the third phase detector 11, the third charge pump 12, and the third loop filter capacitor 13 form a third-stage delay locked loop.

[0082] The nested delay locked loop circuit described in this embodiment is a three-stage nested delay locked loop circuit.

[0083] In a specific embodiment, the first-stage delay locked loop implements an off-chip low-frequency clock T REF During propagation in the M-stage voltage-controlled delay chain 1, the phase of the clock signal propagated through the M-stage voltage-controlled delay chain 1 is compared with the phase of the original reference clock signal through the first phase detector 2, and a first phase difference is output;

[0084] The first charge pump 3 generates a corresponding current according to the first phase difference output by the first phase detector 2, and charges or discharges the first loop filter capacitor 4 to adjust the voltage control voltage value of the M-level voltage-controlled delay chain 1 and control the unit delay of the M-level voltage-controlled delay chain 1; the phase of the clock signal propagated through the M-level voltage-controlled delay chain 1 changes until it is aligned with the phase of the original reference clock; after the phase is aligned, the first-level delay locking loop is locked, and at this time the unit delay of the M-level voltage-controlled delay chain 1 is

[0085] In a specific embodiment, the second-stage delay locked loop implements an off-chip low-frequency clock T REF The phase of the clock signal propagated through the first N-stage voltage-controlled delay chain 6 is compared with the phase of the output signal of the M-to-1 selector 5 by the second phase detector 7, and a second phase difference is output;

[0086] The second charge pump 8 generates a corresponding current according to the second phase difference to charge or discharge the second loop filter capacitor 9 to adjust the voltage control value of the first N-stage voltage-controlled delay chain 6 to control the unit delay of the N-stage voltage-controlled delay chain;

[0087] The phase of the clock signal propagated through the first N-stage voltage-controlled delay chain 6 changes until it is aligned with the phase of the output signal of the M-to-1 selector 5; after the phase is aligned, the second-stage delay lock loop is locked, and the unit delay of the first N-stage voltage-controlled delay chain 6 is The second voltage-controlled voltage V of the first N-stage voltage-controlled delay chain 6 is SLOW Acting on the slow chain delay unit of the time-to-digital converter, the slow delay is

[0088] In a specific embodiment, the third-stage delay locked loop implements an off-chip low-frequency clock T REF During the propagation in the second N-stage voltage-controlled delay chain 10, the phase of the Nth delay unit of the clock signal propagated through the second N-stage voltage-controlled delay chain 10 is compared with the phase of the N-1th delay unit in the first N-stage voltage-controlled delay chain 6 by the third phase detector 11, and a third phase difference is output;

[0089] The third charge pump 12 generates a corresponding current according to the third phase difference, and charges or discharges the third loop filter capacitor 13 to adjust the voltage control voltage value of the second N-stage voltage-controlled delay chain 10, and control the unit delay of the second N-stage voltage-controlled delay chain 10;

[0090] The phase of the Nth delay unit of the clock signal propagated through the second N-stage voltage-controlled delay chain 10 changes until it is aligned with the phase of the N-1th delay unit in the first N-stage voltage-controlled delay chain 6; after the phase is aligned, the third-stage delay locking loop is locked, and at this time the unit delay of the second N-stage voltage-controlled delay chain 10 is The third voltage-controlled voltage V of the second N-stage voltage-controlled delay chain 10 is FAST The fast chain delay unit that can be used for the time-to-digital converter is

[0091] Example 2

[0092] Based on the nested delay locked loop circuit shown in Example 1, more specifically, a fourth-stage delay locked loop may be nested after the third-stage delay locked loop. That is, the nested delay locked loop circuit described in this embodiment is a four-stage nested delay locked loop circuit. Figure 5 shown.

[0093] In a specific embodiment, the fourth-stage delay locked loop includes a third N-stage voltage-controlled delay chain 14, a fourth phase detector 15, a fourth charge pump 16, and a fourth loop filter capacitor 17;

[0094] A first delay unit is added at the output end of the second N-stage voltage-controlled delay chain 10; and the output of the third charge pump 12 is electrically connected to the first delay unit 18;

[0095] The input end of the third N-stage voltage-controlled delay chain 14 is used to input an off-chip low-frequency clock; the output end of the third N-stage voltage-controlled delay chain 14 is electrically connected to the first input end of the fourth phase detector 15;

[0096] The second input terminal of the fourth phase detector 15 is electrically connected to the output terminal of the first delay unit 18;

[0097] The output end of the fourth phase detector 15 is electrically connected to the input end of the fourth charge pump 16; the output end of the fourth charge pump 16 outputs a fourth voltage-controlled voltage; at the same time, the output end of the fourth charge pump 16 is also electrically connected to each delay unit in the third N-stage voltage-controlled delay chain 14 and one end of the fourth loop filter capacitor 17; the other end of the fourth loop filter capacitor 17 is grounded.

[0098] In a specific embodiment, the fourth-stage delay locked loop implements an off-chip low-frequency clock T REF The clock signal propagates in the third N-stage voltage-controlled delay chain 14, and the phase of the clock signal propagated through the third N-stage voltage-controlled delay chain 14 is compared with the phase of the output signal of the first delay unit 18 by the fourth phase detector 15, and a fourth phase difference is output;

[0099] The fourth charge pump 16 generates a corresponding current according to the fourth phase difference to charge or discharge the fourth loop filter capacitor 17 to adjust the voltage control voltage value of the third N-stage voltage-controlled delay chain 14 and control the unit delay of the third N-stage voltage-controlled delay chain 14;

[0100] The phase of the clock signal propagated through the third N-stage voltage-controlled delay chain 14 changes until it is aligned with the phase of the output signal of the first delay unit 18; after the phase is aligned, the fourth-stage delay lock loop is locked, and the unit delay of the third N-stage voltage-controlled delay chain 14 is The fourth voltage-controlled voltage V of the third N-stage voltage-controlled delay chain 14 is FAST2 The fast chain delay unit that can be used for the time-to-digital converter is

[0101] Example 3

[0102] A vernier time-to-digital converter, comprising the nested delay-locked loop circuit, preprocessing circuit, vernier ring delay chain, data processing and output interface as described above;

[0103] The preprocessing circuit is used to detect the rising edge of the electrical signal (START / STOP) pulse at the time of laser pulse emission and reception, and shape it into a narrow pulse signal;

[0104] The vernier annular delay chain quantifies the time difference of the electrical signal pulses;

[0105] The nested delay locked loop circuit provides two voltage-controlled voltages for the vernier ring delay chain circuit;

[0106] The data processing module generates the final quantized flight time from the electrical signal pulse output by the vernier ring delay chain circuit.

[0107] like Figure 6 As shown, the vernier ring delay chain includes a slow ring delay chain, a fast ring delay chain, and an arbitrator;

[0108] The output end of the preprocessing circuit inputs the START pulse into the slow ring delay chain and inputs the STOP pulse into the fast ring delay chain.

[0109] The basic principle of the vernier ring delay chain is to make the two pulse signals representing the emission and reception time propagate in the slow and fast ring delay chains respectively, and catch up with the difference of the delay of the slow and fast delay units as the time resolution, and finally identify the catch-up time of the two pulse signals through the arbitrator. The flight time of the laser pulse will be determined by the count value of the slow and fast ring delay chains and the catch-up time of the pulse signal in the two chains.

[0110] The data processing module includes a counter, a decoder, a segmented data merging circuit and a serial output interface circuit to generate the final quantized flight time.

[0111] In a specific embodiment, the second voltage-controlled voltage V SLOW The third voltage-controlled voltage V acting on the slow chain delay unit of the vernier ring delay chain circuit and the second N-stage voltage-controlled delay chain 10 is FAST A fast chain delay unit acting on a vernier ring delay chain circuit;

[0112] like Figure 6 As shown, the three-stage nested delay locked loop provides a delay control voltage for the vernier ring delay chain circuit. At the same time, this embodiment can also adopt the nested delay locked loop described in Example 2, which is a four-stage nested delay locked loop. Since this example does not need to use the fourth-stage delay locked loop, the first delay unit 18 and the fourth-stage delay locked loop are omitted.

[0113] The flight time of a single measurement of a time-to-digital converter based on a vernier ring delay chain can be expressed as

[0114] T=A1·(16t SLOW )+A2·[16(t SLOW -t FAST )]+A3·(t SLOW -t FAST )

[0115] Among them, t SLOW ,t FAST are the delays of the slow and fast delay units respectively; A1 is the count value of the slow delay chain; A2 is the count value of the fast delay chain; A3 is the catch-up moment of the pulse signal output by the arbitrator in the two chains.

[0116] The input reference clock frequency of the three-stage nested delay locked loop is 32MHz. The delay chain level of the first-stage delay locked loop is M=16. After locking, its unit delay t MAIN The stable delay is 1.95ns. The delay chain of the second-stage delay lock loop has a number of N = 16. After locking, its unit delay t SLOW The third-stage delay lock loop has a delay chain number of N = 16. After locking, its unit delay t FAST The second voltage control voltage of the second-stage delay lock loop is connected to the slow chain voltage control voltage V of the vernier ring delay chain. SLOW , connect the third voltage control voltage of the third-stage delay lock loop to the fast chain voltage control voltage V of the vernier ring delay chain FAST , the resolution t of the TDC based on the vernier ring delay chain can be obtained SLOW -t FAST The stable speed is K·7.63ps, and the configurable range is 7.63ps to 122ps.

[0117] Figure 7 , Figure 8 Schematic diagram of the locking process of the three-stage nested delay locking loop of this embodiment. After a period of time after the three-stage nested delay locking loop is powered on, the voltage control voltage value tends to be stable, and the delay is stable at the set value.

[0118] The ratio of the three-stage quantization resolution of the delay lock loop based on the vernier ring delay chain is

[0119] 16t SLOW :16(t SLOW -t FAST ):(t SLOW -t FAST )=256:16:1=2 8 :2 4 :2 0

[0120] Therefore, the time-to-digital converter can use registers to merge data, latch the 4-bit decoder data A3 in register <3:0>, latch the 4-bit fast delay chain counter output in register <7:4>, and latch the 8-bit slow delay chain counter output value A1 in register <15:8>. Finally, 16-bit TDC quantization data is obtained. In order to save the number of pads on the chip, the 16-bit data is serially output through the SPI protocol.

[0121] Example 4

[0122] Based on the nested delay locked loop circuit described in Example 2, this embodiment is similar to Example 3, and the second voltage-controlled voltage V SLOW The fourth voltage-controlled voltage V acting on the slow chain delay unit of the vernier ring delay chain circuit and the third N-stage voltage-controlled delay chain 14 is FAST2 Acting on the fast chain delay unit of the vernier ring delay chain circuit, the fast delay is

[0123] Based on the nested delay locked loop circuit and the vernier time-to-digital converter described in the above embodiment, the simulation experimental data of this embodiment is as follows:

[0124] This embodiment introduces the nested delay locked loop circuit described in Embodiment 1 to enable the delay unit to resist PVT drift.

[0125] like Fig. 9 As shown in Figure 1, the delay unit without delay lock loop control has a delay deviation of 36ps in Monte Carlo simulation. Fig.10 As shown, in the Monte Carlo simulation, the delay unit controlled by the nested delay locked loop circuit has a delay deviation of 3ps, which indicates that the present invention can suppress the delay deviation of the delay unit due to process and mismatch, and can achieve a time resolution of less than 10ps.

[0126] The invention introduces a nested delay locked loop circuit to effectively control the fast and slow delay ratios, and reduce the complexity of data merging after segmented quantization based on a vernier annular delay chain TDC.

[0127] When the nested DLL is locked, t SLOW =121ps (such as Fig.10 As shown in Fig.11 As shown, It is similar to 16. It shows that the time data converter based on the vernier ring delay chain introduces a nested delay locked loop circuit to achieve t SLOW :t SLOW -t FASTWhen merging the three-segment quantized data of TDC, it is not necessary to use multiplication, division and summation operations, but only to latch the quantized value into the register, which reduces the complexity of data processing.

[0128] When the input reference clock frequency is low and the same TDC resolution is achieved, the number of delay chains required by the present invention is minimal.

[0129] As shown in Table 1, the three DLLs are summarized under the same reference clock T REF It can be seen that the master-slave DLL and the nested delay locked loop (K=1) of the present invention can both achieve t SLOW :t SLOW -t FAST It is in a quadratic relationship, which is more advantageous in the application of cursor-to-time digital converter.

[0130] Master-slave DLL can achieve TDC resolution The three-level nested DLL of the present invention can achieve TDC resolution when K is set to 1. The present invention only adds a set of phase detectors, charge pumps, and loop filter capacitors to reduce the TDC resolution by N times. The four-stage nested delay lock loop of the present invention, when K is set to 1, can achieve a TDC resolution of The present invention only adds two sets of phase detectors, charge pumps, and loop filter capacitors to reduce the TDC resolution by N. 2 times.

[0131] The master-slave DLL can achieve the same resolution as the three-stage nested delay lock loop of the present invention by increasing the delay chain units to M·N to achieve the delay. However, it is difficult to match each delay unit with a long delay chain, while the nested delay lock loop of the present invention only requires M+N delay units. Another way is that the master-slave DLL increases the reference clock frequency by N times, but this requires the introduction of an additional phase-locked loop circuit. At the same time, in order to ensure the loop stability of the phase-locked loop, the added loop filter is much larger than the loop filter capacitor of the present invention, and an additional N divider circuit is required. The above shows that the three-stage nested DLL of the present invention has a great advantage in achieving low resolution.

[0132] Table 1: Three DLLs with the same reference clock T REF Performance comparison under , M, and N parameters.

[0133]

[0134]

[0135] The nested delay locked loop of the present invention has a configurable TDC resolution function.

[0136] After the overall circuit design is determined, the numbers M and N cannot be changed. In addition, the frequency selection of the high-quality clock source outside the chip is limited, and the resolution of the TDC controlled by the classic dual DLL and master-slave DLL cannot be changed. However, the present invention can change the size of the control word K to change the resolution of the TDC to meet the resolution requirements of various TDC applications.

[0137] Obviously, the above embodiments of the present invention are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A nested delay locked loop circuit, characterized in that: It comprises an M-level voltage-controlled delay chain (1), a first N-level voltage-controlled delay chain (6), a second N-level voltage-controlled delay chain (10), a first phase detector (2), a second phase detector (7), a third phase detector (11), a first charge pump (3), a second charge pump (8), a third charge pump (12), a first loop filter capacitor (4), a second loop filter capacitor (9), a third loop filter capacitor (13), and an M-to-1 selector (5); The input end of the M-level voltage-controlled delay chain (1) is used to input an off-chip low-frequency clock, the first input end of the first phase detector (2) is electrically connected to the output end of the M-level voltage-controlled delay chain (1); the second input end of the first phase detector (2) is used to input an off-chip low-frequency clock; The output end of the first phase detector (2) is electrically connected to the input end of the first charge pump (3); the output end of the first charge pump (3) outputs a first voltage-controlled voltage; at the same time, the output end of the first charge pump (3) is also electrically connected to each delay unit in the M-level voltage-controlled delay chain (1) and one end of the first loop filter capacitor (4); the other end of the first loop filter capacitor (4) is grounded; The selection end of the M-to-1 selector (5) is electrically connected to the output end of each delay unit in the M-level voltage-controlled delay chain (1); the control end of the M-to-1 selector (5) is used to input the control word K; the output end of the M-to-1 selector (5) is electrically connected to the first input end of the second phase detector (7); The input end of the first N-stage voltage-controlled delay chain (6) is used to input an off-chip low-frequency clock, and the output end of the first N-stage voltage-controlled delay chain (6) is electrically connected to the second input end of the second phase detector (7); The output end of the second phase detector (7) is electrically connected to the output end of the second charge pump (8); the output end of the second charge pump (8) is used to output a second voltage-controlled voltage; at the same time, the output end of the second charge pump (8) is also electrically connected to each delay unit in the first N-stage voltage-controlled delay chain (6) and one end of the second loop filter capacitor (9); the other end of the second loop filter capacitor (9) is grounded; The first input end of the third phase detector (11) is electrically connected to the output end of the N-1th delay unit in the first N-stage voltage-controlled delay chain (6); The input end of the second N-stage voltage-controlled delay chain (10) is used to input an off-chip low-frequency clock, and the output end of the second N-stage voltage-controlled delay chain (10) is electrically connected to the second input end of the third phase detector (11); The output end of the third phase detector (11) is electrically connected to the input end of the third charge pump (12); the output end of the third charge pump (12) outputs a third voltage-controlled voltage; at the same time, the output end of the third charge pump (12) is also electrically connected to each delay unit in the second N-stage voltage-controlled delay chain (10) and one end of the third loop filter capacitor (13); the other end of the third loop filter capacitor (13) is grounded; The M-level voltage-controlled delay chain (1), the first phase detector (2), the first charge pump (3), and the first loop filter capacitor (4) form a first-level delay locking loop; The first N-stage voltage-controlled delay chain (6), the second phase detector (7), the second charge pump (8), and the second loop filter capacitor (9) form a second-stage delay locking loop; The second N-stage voltage-controlled delay chain (10), the third phase detector (11), the third charge pump (12), and the third loop filter capacitor (13) form a third-stage delay lock loop; The second-stage delay locked loop realizes the off-chip low-frequency clock The clock signal propagates in the first N-stage voltage-controlled delay chain (6), and the phase of the clock signal propagated through the first N-stage voltage-controlled delay chain (6) is compared with the phase of the output signal of the M-to-1 selector (5) through the second phase detector (7), and a second phase difference is output; The second charge pump (8) generates a corresponding current according to the second phase difference to charge or discharge the second loop filter capacitor (9) to adjust the voltage control voltage value of the first N-stage voltage-controlled delay chain (6) and control the unit delay of the first N-stage voltage-controlled delay chain (6); The phase of the clock signal propagated through the first N-stage voltage-controlled delay chain (6) changes until it is aligned with the phase of the output signal of the M-to-1 selector (5); after the phase is aligned, the second-stage delay lock loop is locked, and at this time the unit delay of the first N-stage voltage-controlled delay chain (6) is ; The second voltage-controlled voltage of the first N-stage voltage-controlled delay chain (6) Acting on the slow chain delay unit of the time-to-digital converter, the slow delay is ; The third-stage delay locked loop realizes the off-chip low-frequency clock During propagation in the second N-stage voltage-controlled delay chain, the phase of the Nth delay unit of the clock signal propagated through the second N-stage voltage-controlled delay chain (10) is compared with the phase of the N-1th delay unit in the first N-stage voltage-controlled delay chain (6) through a third phase detector (11), and a third phase difference is output; The third charge pump (12) generates a corresponding current according to the third phase difference, and charges or discharges the third loop filter capacitor (13) to adjust the voltage control voltage value of the second N-stage voltage-controlled delay chain (10) and control the unit delay of the second N-stage voltage-controlled delay chain (10); The phase of the Nth delay unit of the clock signal propagated through the second N-stage voltage-controlled delay chain (10) changes until it is aligned with the phase of the N-1th delay unit in the first N-stage voltage-controlled delay chain (6); after the phase is aligned, the third-stage delay locking loop is locked, and at this time the unit delay of the second N-stage voltage-controlled delay chain (10) is ; The third voltage-controlled voltage of the second N-stage voltage-controlled delay chain (10) The fast chain delay unit that can be used for the time-to-digital converter is .

2. The nested delay locked loop circuit according to claim 1, characterized in that: A fourth-stage delay locking loop may be nested after the third-stage delay locking loop.

3. The nested delay locked loop circuit according to claim 2, characterized in that: The fourth-stage delay locked loop comprises a third N-stage voltage-controlled delay chain (14), a fourth phase detector (15), a fourth charge pump (16), and a fourth loop filter capacitor (17); A first delay unit (18) is added to the output end of the second N-stage voltage-controlled delay chain (10); and the output of the third charge pump (12) is electrically connected to the first delay unit (18); The input end of the third N-stage voltage-controlled delay chain (14) is used to input an off-chip low-frequency clock; the output end of the third N-stage voltage-controlled delay chain (14) is electrically connected to the first input end of the fourth phase detector (15); The second input end of the fourth phase detector (15) is electrically connected to the output end of the first delay unit (18); The output end of the fourth phase detector (15) is electrically connected to the input end of the fourth charge pump (16); the output end of the fourth charge pump (16) outputs a fourth voltage-controlled voltage; at the same time, the output end of the fourth charge pump (16) is also electrically connected to each delay unit in the third N-stage voltage-controlled delay chain (14) and one end of the fourth loop filter capacitor (17); the other end of the fourth loop filter capacitor (17) is grounded.

4. The nested delay locked loop circuit according to claim 1, characterized in that: The first-stage delay locked loop realizes the off-chip low-frequency clock Propagation in the M-stage voltage-controlled delay chain (1), comparing the phase of the clock signal propagated through the M-stage voltage-controlled delay chain (1) with the phase of the original reference clock signal through a first phase detector (2), and outputting a first phase difference; The first charge pump (3) generates a corresponding current according to the first phase difference output by the first phase detector (2), and charges or discharges the first loop filter capacitor (4) to adjust the voltage control voltage value of the M-level voltage-controlled delay chain (1) and control the unit delay of the M-level voltage-controlled delay chain (1); the phase of the clock signal propagated through the M-level voltage-controlled delay chain (1) changes until it is aligned with the phase of the original reference clock; After phase alignment, the first-stage delay lock loop is locked. At this time, the unit delay of the M-stage voltage-controlled delay chain (1) is .

5. The nested delay locked loop circuit according to claim 3, characterized in that: The fourth-stage delay locked loop realizes the off-chip low-frequency clock propagates in the third N-stage voltage-controlled delay chain (14), compares the phase of the clock signal propagated through the third N-stage voltage-controlled delay chain (14) with the phase of the output signal of the first delay unit (18) through a fourth phase detector (15), and outputs a fourth phase difference; The fourth charge pump (16) generates a corresponding current according to the fourth phase difference, and charges or discharges the fourth loop filter capacitor (17) to adjust the voltage control voltage value of the third N-stage voltage-controlled delay chain (14), thereby controlling the unit delay of the third N-stage voltage-controlled delay chain (14); The phase of the clock signal propagated through the third N-stage voltage-controlled delay chain (14) changes until it is aligned with the phase of the output signal of the first delay unit (18); after the phase is aligned, the fourth-stage delay lock loop is locked, and at this time, the unit delay of the third N-stage voltage-controlled delay chain (14) is ; The fourth voltage-controlled voltage of the third N-stage voltage-controlled delay chain (14) The fast chain delay unit that can be used for the time-to-digital converter is .

6. A vernier time-to-digital converter, characterized in that: The method comprises a nested delay locked loop circuit, a preprocessing circuit, a vernier ring delay chain, a data processing module and an output interface as claimed in any one of claims 1 to 5; The preprocessing circuit is used to detect the rising edge of the electrical signal pulse at the time of laser pulse emission and reception, and shape it into a narrow pulse signal; The vernier annular delay chain quantifies the time difference of the electrical signal pulses; The nested delay locked loop circuit provides two voltage-controlled voltages for the vernier ring delay chain circuit; The data processing module generates the final quantized flight time from the electrical signal pulse output by the vernier ring delay chain circuit.

7. The vernier time-to-digital converter according to claim 6, characterized in that: The vernier ring delay chain circuit comprises a slow chain delay unit and a fast chain delay unit; The second voltage-controlled voltage of the first N-stage voltage-controlled delay chain (6) The third voltage-controlled voltage acting on the slow chain delay unit of the vernier ring delay chain circuit and the second N-stage voltage-controlled delay chain (10) A fast chain delay unit acting on a vernier ring delay chain circuit; Or the second voltage-controlled voltage of the first N-stage voltage-controlled delay chain (6) The fourth voltage-controlled voltage acting on the slow chain delay unit of the vernier ring delay chain circuit and the third N-stage voltage-controlled delay chain (14) Acting on the fast chain delay unit of the vernier ring delay chain circuit, the fast delay is .

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