A frequency adaptive time-to-digital conversion circuit

Abstract

A frequency adaptive time digital conversion circuit, including circuit includes phase detector, digital to analog converter, oscillator, 8 counters, 8 and gates, digital logic, the output end of each and gate is connected to the input end of a counter, the output end of all counters is connected to digital logic, the counters are divided into 4 groups, two by two, the oscillator outputs 4 signals, which are input into two and gates of the same group of counters, the phase detector has 2 input ends, which receive the input signals of the circuit respectively, the phase detector outputs 2 signals, which are input into two and gates of the same group of counters, the digital logic outputs 6 signals, 5 of which are output signals of the circuit, and 1 of which is input into the digital to analog converter, the digital to analog converter outputs current to the oscillator, which controls the frequency of the output signal of the oscillator.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and particularly relates to a design technique of a time-to-digital conversion circuit. BACKGROUND

[0002] Whether it is the sundial used in ancient times to roughly estimate time or the resonator used today to precisely define a second, it can be regarded as part of the timekeeping technology. Throughout the history of science, the timekeeping technology has been playing an important role in various fields. The electronic technology field is no exception: a stable clock is needed for the operation of a digital circuit, a strict timing control is needed for the coordinated division of labor of various modules of a circuit system, and various interface protocols also regard the requirement for timing as a key part.

[0003] A time-to-digital converter (TDC) is used to detect the delay difference between two clocks of the same frequency and different phases in an integrated circuit, and the working principle is as shown in FIG. 1. Figure 1 clk1 and clk2 are two clock signals of the same frequency, and there is a delay difference T between them, and the TDC detects T and generates a digital code Dout proportional to T. D D In many TDC documents, the clock signal clk1 with a phase lead is referred to as a start signal, and the clock signal clk2 with a phase lag is referred to as a stop signal, so as to reflect the phase relationship between the two signals.

[0004] Several indicators should be concerned in the application of the TDC: what is the interval range of the input clock frequency of the TDC? What is the minimum resolution LSB of the TDC? Whether does the LSB of the TDC change with the process angle, the power voltage and the temperature (collectively referred to as PVT)?

[0005] The design of the traditional TDC focuses on reducing the LSB, so as to obtain higher quantization accuracy. For example, the interpolation TDC and the vernier TDC can reduce the LSB to within one inverter delay, and their common point is that the internal oscillator always oscillates at the highest frequency and cannot be adjusted. Because the oscillation frequency of the oscillator changes greatly with the PVT, the LSB of the traditional TDC also changes with the PVT. The output values measured by the traditional TDC are different under different PVT conditions for the same input signal. SUMMARY

[0006] In order to solve the problems existing in the prior art, the present application provides a frequency adaptive time-to-digital conversion circuit for measuring the time interval between two working steps of other circuits, and in order to achieve the above purpose, the present application adopts the following technical scheme.

[0007] ​The circuit comprises a phase detector, a digital-to-analog converter, an oscillator, 8 counters, 8 AND gates, digital logic, the output of each AND gate is connected to the input of a counter, the outputs of all the counters are connected to the digital logic, the counters are divided into 4 groups, each group comprises two counters, the oscillator outputs 4 signals, which are input into two AND gates of the same group, the phase detector has 2 inputs, which receive input signals of the circuit, the phase detector outputs 2 signals, which are input into two AND gates of the same group, the digital logic outputs 6 signals, 5 of which are output signals of the circuit, and 1 of which is input into the digital-to-analog converter, the digital-to-analog converter outputs a current to the oscillator, which controls the frequency of the output signal of the oscillator.

[0008] The high-frequency oscillation signal generated by the oscillator serves as a time reference, and within a given delay difference, the number of oscillations of the oscillator is measured by the counters to obtain an accurate value of the delay difference.

[0009] The digital logic and the digital-to-analog converter constitute a loop, which operates on 8 measurement values, outputs a control signal, and adjusts the frequency of the oscillator in a closed loop to realize adaptive changes of the time-to-digital converter within a certain range, automatically adjusts the LSB to the optimal working state, and does not require human adjustment, thereby ensuring that the measurement results of the circuit have PVT stability.

[0010] The digital logic outputs 5 signals, which are a period measurement value, a delay difference measurement value, a lock state indication, an oscillator frequency too high indication, and an oscillator frequency too low indication, and outputs more information, which is beneficial to troubleshooting when the circuit is not working properly.

[0011] The two input signals are input into the phase detector to generate a delay difference and a period length of the two input signals, not only the delay difference but also the clock period is measured, the counters are paired with each other, and are associated with each other to ensure the accuracy of the measurement of the circuit, and in the case that the period of the input signal is known, the accurate value of the delay difference can be obtained by the proportional method.

[0012] The 8 counters and the AND gates constitute 4 identical modules, which work in parallel to cooperate with the multiple-phase signals generated by the oscillator, 4 measurements are averaged to reduce errors, and the measurement error of the TDC is reduced from the system level. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a working principle of the TDC, Figure 2 is a circuit structure principle, Figure 3 is an adaptive processing flow, Figure 4 is a test flow, Figure 5 is an input and output waveform. EMBODIMENT

[0014] The technical solutions of the present application will be described in detail below with reference to the drawings.

[0015] The structure principle of the circuit is shown as Figure 2 The input signal start and stop input phase detector, output clk_ref and clk_det, oscillator output osc0, osc1, osc2, osc3. osc0 corresponds to the first group of counter 0r and counter 0d, osc1 corresponds to the second group of counter 1r and counter 1d, osc2 corresponds to the third group of counter 2r and counter 2d, osc3 corresponds to the fourth group of counter 3r and counter 3d, clk_ref corresponds to counter 0r, counter 1r, counter 2r, counter 3r, clk_det corresponds to counter 0d, counter 1d, counter 2d, counter 3d, 4 groups of counters are driven by the oscillation signal osc0, osc1, osc2, osc3, osc0, the high level time of clk_ref and clk_det is measured, and 4 groups of measurement values ref_cnt0 <n:0>and det_cnt0 <n:0>, ref_cnt1 <n:0>and det_cnt1 <n:0>, ref_cnt2 <n:0>and det_cnt2 <n:0>, ref_cnt3 <n:0>and det_cnt3 <n:0>.

[0016] Digital logic calculates period measurement of start start_period from 4 measurements <m:0>, the measured value of the difference between the start and stop delays start2stop <m:0>, internal signal dac_code <x:0>, a lock state tdc_lock, an oscillator frequency too high over_high, an oscillator frequency too low over_low.

[0017] The processing flow of the digital logic is shown in Figure 3 Fig. 4 when start_period <m:0>reaching an upper limit, dac_code <x:0>Subtract 1, when start_period <m:0>reaching lower limit, dac_code <x:0>add 1, start_period <m:0>tdc_lock is set to 1 for other values, over_high is set to 1 when dac_code reaches the lower limit, over_low is set to 1 when dac_code reaches the upper limit, and dac_code is used to <x:0>Control the output current Ibias of the digital-to-analog converter to adjust the frequency of the oscillation signals osc0, osc1, osc2, and osc3.

[0018] Adaptive process such as Figure 4 As shown, if tdc_lock is not 1, then check over_high; if it is 1, manually decrease Ibias; if it is 0, check over_low; if it is 1, manually increase Ibias; if it is 0, wait for the circuit to adaptively adjust. If tdc_lock is 1, then read start_period. <m:0>and start2stop <m:0>with the start signal period x (start2stop <m:0>) / (start_period <m:0>) Calculate the rising edge time difference of start and stop, observe the waveform diagram corresponding to the input and output signals, as shown in Figure 5 The above process can be verified.

[0019] The above is an embodiment of the present application, and does not limit the present application. Any modification, equivalent replacement and improvement within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A frequency adaptive time-to-digital conversion circuit, characterized by Comprise: The circuit comprises a phase detector, a digital-to-analog converter, an oscillator, 8 counters, 8 AND gates, digital logic, the output of each AND gate is connected to the input of a counter, the outputs of all counters are connected to the digital logic, the counters are divided into 4 groups, each group has two counters, the oscillator outputs 4 signals, which are input into the two AND gates of the same group of counters, the phase detector has 2 inputs, which receive the input signals of the circuit, the phase detector outputs 2 signals, which are input into the two AND gates of the same group of counters, the digital logic outputs 6 signals, 5 of which are output signals of the circuit, 1 of which is input into the digital-to-analog converter, the digital-to-analog converter outputs a current to the oscillator, which controls the frequency of the oscillator output signal.

2. The frequency adaptive time-to-digital conversion circuit of claim 1, wherein, Also include: The input signals start and stop are input into the phase detector, and the output clk_ref and clk_det, the oscillator outputs osc0, osc1, osc2, osc3, osc0 corresponds to the first group of counter 0r and counter 0d, osc1 corresponds to the second group of counter 1r and counter 1d, osc2 corresponds to the third group of counter 2r and counter 2d, osc3 corresponds to the fourth group of counter 3r and counter 3d, clk_ref corresponds to counter 0r, counter 1r, counter 2r, counter 3r, clk_det corresponds to counter 0d, counter 1d, counter 2d, counter 3d, the four groups of counters are driven by the oscillation signals osc0, osc1, osc2, osc3, the high level time of clk_ref and clk_det is measured, and four groups of measurement values ref_cnt0 <n:0>and det_cnt0 <n:0>, ref_cnt1 <n:0>and det_cnt1 <n:0>, ref_cnt2 <n:0>and det_cnt2 <n:0>, ref_cnt3 <n:0>and det_cnt3 <n:0> 。< / n:0> 3. The frequency adaptive time-to-digital conversion circuit of claim 2, wherein, The digital logic calculates a period measurement start_period of start from 4 sets of measurements <m:0>, the measured value of the difference between the start and stop delays start2stop <m:0>, internal signal dac_code <x:0>, display lock state tdc_lock, oscillator frequency too high over_high, oscillator frequency too low over_low.< / x:0> 4. The frequency adaptive time-to-digital conversion circuit of claim 3, wherein, Also include: When start_period <m:0>reaching an upper limit, dac_code <x:0>-1, when start_period <m:0>reached lower limit, dac_code <x:0>add 1, start_period <m:0>tdc_lock is set to 1 for other values, over_high is set to 1 when dac_code reaches the lower limit, over_low is set to 1 when dac_code reaches the upper limit, and dac_code is used to <x:0>Control the output current Ibias of the digital-to-analog converter, adjust the frequencies of the oscillator signals osc0, osc1, osc2, osc3, osc0.< / x:0> 5. The frequency adaptive time-to-digital conversion circuit of claim 4, wherein, Also include: If tdc_lock is not 1, then check over_high, if 1, then manually decrease Ibias, if 0, then check over_low, if 1, then manually increase Ibias, if 0, then wait for circuit to adapt, if tdc_lock is 1, then read start_period <m:0>and start2stop <m:0>with the start signal period x (start2stop <m:0>) / (start_period <m:0>) Calculate the time difference between the rising edges of start and stop.< / m:0>

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